CN108233895B - Inverter and driving method thereof, shift register unit and display device - Google Patents
Inverter and driving method thereof, shift register unit and display device Download PDFInfo
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- CN108233895B CN108233895B CN201810117060.XA CN201810117060A CN108233895B CN 108233895 B CN108233895 B CN 108233895B CN 201810117060 A CN201810117060 A CN 201810117060A CN 108233895 B CN108233895 B CN 108233895B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
The invention discloses an inverter, a driving method thereof, a shift register unit and a display device, relates to the technical field of display, and aims to solve the problem that the working stability of the inverter is low in the prior art. The inverter includes: the first pull-up module is used for controlling whether the first level signal input end is connected with the signal output end or not under the control of the first clock signal input end; the second pull-up module is used for controlling whether the first level signal input end is connected with the signal output end or not under the control of the second clock signal input end; and the output pull-down module is used for controlling whether the signal output end is connected with the second level signal input end under the control of the input control end. The inverter provided by the invention is used for outputting the signal inverted with the input end.
Description
Technical Field
The invention relates to the technical field of display, in particular to an inverter, a driving method thereof, a shift register unit and a display device.
Background
In the display field, an inverter is often used in a display panel, and the main function of the inverter is to invert an input signal by 180 ° and output the inverted signal, where a binary value 1 represents a high level of the signal, and a binary value 0 represents a low level of the signal, for example, when a signal input to the inverter is 1, the signal output from the inverter is 0, and when a signal input to the inverter is 0, the signal output from the inverter is 1.
Because the inverter in the prior art generally includes two modules, namely a pull-up module and a pull-down module, in a normal operating state of the inverter, the pull-up module needs to be in an operating state for a long time, so that a problem of threshold voltage drift of a transistor in the pull-up module is easily caused, and further, the operating stability of the inverter is low.
Disclosure of Invention
The invention aims to provide an inverter, a driving method thereof, a shift register unit and a display device, which are used for solving the problem of low working stability of the inverter in the prior art.
In order to achieve the above purpose, the invention provides the following technical scheme:
a first aspect of the present invention provides an inverter comprising:
the first pull-up module is respectively connected with a first level signal input end, a first clock signal input end and a signal output end and is used for controlling whether the first level signal input end is connected with the signal output end or not under the control of the first clock signal input end;
the second pull-up module is respectively connected with the first level signal input end, the second clock signal input end and the signal output end, and is used for controlling whether the first level signal input end is connected with the signal output end or not under the control of the second clock signal input end;
and the output pull-down module is respectively connected with the input control end, the signal output end and the second level signal input end and is used for controlling whether the signal output end is connected with the second level signal input end or not under the control of the input control end.
Further, the first pull-up module comprises a first switch tube and a second switch tube; the grid electrode of the first switch tube is connected with the first clock signal input end, the first pole of the first switch tube is connected with the first level signal input end, and the second pole of the first switch tube is connected with the first node; a grid electrode of the second switch tube is connected with the first node, a first pole of the second switch tube is connected with the first level signal input end, and a second pole of the second switch tube is connected with the signal output end;
the second upward-pulling module comprises a third switch tube and a fourth switch tube; the grid electrode of the third switching tube is connected with the second clock signal input end, the first pole of the third switching tube is connected with the first level signal input end, and the second pole of the third switching tube is connected with the second node; a grid electrode of the fourth switching tube is connected with the second node, a first pole of the fourth switching tube is connected with the first level signal input end, and a second pole of the fourth switching tube is connected with the signal output end;
the output pull-down module comprises a fifth switch tube, the grid electrode of the fifth switch tube is connected with the input control end, the first pole of the fifth switch tube is connected with the signal output end, and the second pole of the fifth switch tube is connected with the second level signal input end.
Further, the first pull-up module further includes a first capacitor, a first end of the first capacitor is connected to the first node, and a second end of the first capacitor is connected to the signal output end; and/or the presence of a gas in the gas,
the second pull-up module further comprises a second capacitor, a first end of the second capacitor is connected with the second node, and a second end of the second capacitor is connected with the signal output end.
Further, the inverter further includes:
the first node control module is respectively connected with the second clock signal input end, the second level signal input end and the first node, and is used for controlling whether the first node is connected with the second level signal input end or not under the control of the second clock signal input end; and/or the presence of a gas in the gas,
and the second node control module is respectively connected with the first clock signal input end, the second level signal input end and the second node and is used for controlling whether the second node is connected with the second level signal input end or not under the control of the first clock signal input end.
Further, the first node control module includes a sixth switching tube, a gate of the sixth switching tube is connected to the second clock signal input terminal, a first pole of the sixth switching tube is connected to the first node, and a second pole of the sixth switching tube is connected to the second level signal input terminal;
the second node control module comprises a seventh switch tube, the grid electrode of the seventh switch tube is connected with the first clock signal input end, the first pole of the seventh switch tube is connected with the second node, and the second pole of the seventh switch tube is connected with the second level signal input end.
Further, the inverter further includes:
the first node pull-down module is respectively connected with the input control end, the first node and the second level signal input end, and is used for controlling whether the first node is connected with the second level signal input end or not under the control of the input control end; and/or the presence of a gas in the gas,
and the second node pull-down module is respectively connected with the input control end, the second node and the second level signal input end and is used for controlling whether the second node is connected with the second level signal input end or not under the control of the input control end.
Further, the first node pull-down module includes an eighth switching tube, a gate of the eighth switching tube is connected to the input control end, a first pole of the eighth switching tube is connected to the first node, and a second pole of the eighth switching tube is connected to the second level signal input end;
the second node pull-down module comprises a ninth switch tube, the grid electrode of the ninth switch tube is connected with the input control end, the first pole of the ninth switch tube is connected with the second node, and the second pole of the ninth switch tube is connected with the second level signal input end.
Based on the technical solution of the inverter, a second aspect of the present invention provides a shift register unit, including the inverter.
Based on the technical solution of the shift register unit, a third aspect of the present invention provides a display device, including the shift register unit.
Based on the technical solution of the inverter, a fourth aspect of the present invention provides a driving method for an inverter, for driving the inverter, the driving method including: performing a first inversion step in the first driving phase and a second inversion step in the second driving phase; the first driving phase comprises first driving periods and second driving periods which are alternately arranged;
the first inverting step includes:
in the first driving time period, the input control end inputs a second level, and the first pull-up module controls the first level signal input end to be connected with the signal output end under the control of the first clock signal input end;
in the second driving time period, the input control end inputs a second level, and the second pull-up module controls the first level signal input end to be connected with the signal output end under the control of a second clock signal input end;
the second inverting step includes:
the input control end inputs a first level, and the output pull-down module controls the signal output end to be connected with the second level signal input end under the control of the input control end.
In the technical scheme provided by the invention, the phase inverter comprises a first pull-up module, a second pull-up module and a pull-down module. In a first driving period, the second pull-up module is in a non-operating state, and the first level signal input end is controlled to be connected with the signal output end only through the first pull-up module, so that the signal output end can output a first level signal. And in a second driving time period, the first pull-up module is in a non-operating state, and the first level signal input end is controlled to be connected with the signal output end only through the second pull-up module, so that the signal output end can output the first level signal. It can be seen that the inverter provided by the embodiment of the invention can control the first pull-up module and the second pull-up module to work alternately, and the problem that a transistor in a module is easy to have threshold voltage drift due to the fact that only one pull-up module is in a working state for a long time is avoided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art inverter;
FIG. 2 is a schematic diagram of a first block of an inverter according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a second module of an inverter according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an inverter according to an embodiment of the present invention;
FIG. 5 is a timing diagram illustrating the operation of an inverter according to an embodiment of the present invention.
Reference numerals:
s1-pull-up module, S2-pull-down module,
1-a first pull-up module, 2-a second pull-up module,
3-output pull-down module, 4-first node control module,
5-a second node control module, 6-a first node pull-down module,
7-second node pull-down module, V1-first level signal input terminal,
CLKA-a first clock signal input terminal, VOUT-signal output terminal,
CLKB-a second clock signal input terminal, VIN-an input control terminal,
v2-second level signal input, N1-first node,
n2-second node, C1-first capacitor,
c2-second capacitor, T1-first switch tube,
t2-second switch tube, T3-third switch tube,
t4-a fourth switching tube, T5-a fifth switching tube,
t6-sixth switch tube, T7-seventh switch tube,
t8-eighth switch tube, T9-ninth switch tube,
p1-first driving phase, P11-first driving period,
p12-second driving period, P2-second driving phase.
Detailed Description
In order to further explain the inverter, the driving method thereof, the shift register unit and the display device provided by the embodiment of the invention, the following is described in detail with reference to the accompanying drawings.
As described in the background, referring to fig. 1, an inverter in the prior art generally includes a pull-up module S1 and a pull-down module S2, and in a normal operating state, a transistor included in the pull-up module S1 is always in an operating state, and when the transistor is an oxide thin film transistor, a problem of threshold voltage shift is easily caused, thereby resulting in a low operating stability of the inverter.
Based on the existence of the above problems, the inventor of the present invention has found through research that the above problems can be solved by arranging two pull-up modules to work alternately, and specifically, referring to fig. 2, an embodiment of the present invention provides an inverter, including:
the first pull-up module 1 is respectively connected with the first level signal input end V1, the first clock signal input end CLKA and the signal output end VOUT, and is used for controlling whether the first level signal input end V1 is connected with the signal output end VOUT or not under the control of the first clock signal input end CLKA;
the second pull-up module 2 is respectively connected with the first level signal input end V1, the second clock signal input end CLKB and the signal output end VOUT, and is used for controlling whether the first level signal input end V1 is connected with the signal output end VOUT or not under the control of the second clock signal input end CLKB;
the output pull-down module 3 is connected to the input control terminal VIN, the signal output terminal VOUT, and the second level signal input terminal V2, respectively, and is configured to control whether the signal output terminal VOUT is connected to the second level signal input terminal V2 under the control of the input control terminal VIN.
The inverter comprises two driving phases during specific operation, wherein a first inversion step is performed in the first driving phase P1, and a second inversion step is performed in the second driving phase P2; wherein the first driving phase P1 includes first driving periods P11 and second driving periods P12 alternately arranged.
In the first driving period P11: the input control terminal VIN inputs the second level, and the output pull-down module 3 controls the control signal output terminal VOUT to be disconnected from the second level signal input terminal V2 under the control of the input control terminal VIN. The first pull-up module 1 controls the first level signal input terminal V1 to be connected to the signal output terminal VOUT under the control of the first clock signal input terminal CLKA, thereby enabling the signal output terminal VOUT to output a first level signal. Meanwhile, in the first driving period P11, the second pull-up module 2 is in an inactive state under the control of the second clock signal input terminal CLKB, thereby realizing that the first level signal is output only by the first pull-up module 1 control signal output terminal VOUT in the first driving period P11.
In the second driving period P12: the input control terminal VIN continues to input the second level, and the output pull-down module 3 continues to control the signal output terminal VOUT to be disconnected from the second level signal input terminal V2 under the control of the input control terminal VIN. The second pull-up module 2 controls the first level signal input terminal V1 to be connected to the signal output terminal VOUT under the control of the second clock signal input terminal CLKB, so that the signal output terminal VOUT can output the first level signal. Meanwhile, in the second driving period P12, the first pull-up module 1 is in an inactive state under the control of the first clock signal input terminal CLKA, thereby realizing that the first level signal is output only by the second pull-up module 2 control signal output terminal VOUT in the second driving period P12.
In the second driving phase P2: first pull-up block 1 is in an inactive state under the control of first clock signal input terminal CLKA, and second pull-up block 2 is in an inactive state under the control of second clock signal input terminal CLKB. The input control terminal VIN inputs a first level, the output pull-down module 3 is controlled by the input control terminal VIN, and the control signal output terminal VOUT is connected to the second level signal input terminal V2, so that the signal output terminal VOUT outputs a second level signal.
According to the specific structure and operation process of the inverter provided in the above embodiment, the inverter provided in the embodiment of the present invention includes a first pull-up module 1, a second pull-up module 2, and an output pull-down module 3. In the first driving period P11, the second pull-up module 2 is in an inactive state, and the first level signal input terminal V1 is controlled to be connected to the signal output terminal VOUT only by the first pull-up module 1, so that the signal output terminal VOUT can output the first level signal. And in the second driving period P12, the first pull-up module 1 is in the inactive state, and the first level signal input terminal V1 is controlled to be connected to the signal output terminal VOUT only by the second pull-up module 2, so that the signal output terminal VOUT can output the first level signal. It can be seen that the inverter provided in the embodiment of the present invention can control the first pull-up module 1 and the second pull-up module 2 to alternately operate, and avoid a problem that a transistor in a module is prone to threshold voltage drift due to only one pull-up module being in an operating state for a long time.
The first pull-up module 1, the second pull-up module 2, and the output pull-down module 3 provided in the above embodiments have various specific structures, and a specific structure corresponding to each module is given below, and a detailed description is given to an operation process of the inverter in the specific structure.
As shown in fig. 4, the first upward drawing module 1 includes a first switching tube T1 and a second switching tube T2; a gate of the first switch transistor T1 is connected to the first clock signal input terminal CLKA, a first pole of the first switch transistor T1 is connected to the first level signal input terminal V1, and a second pole of the first switch transistor T1 is connected to the first node N1; the gate of the second switch transistor T2 is connected to the first node, the first pole of the second switch transistor T2 is connected to the first level signal input terminal V1, and the second pole of the second switch transistor T2 is connected to the signal output terminal VOUT.
The second pull-up module 2 comprises a third switching tube T3 and a fourth switching tube T4; a gate of the third switching tube T3 is connected to the second clock signal input terminal CLKB, a first pole of the third switching tube T3 is connected to the first level signal input terminal V1, and a second pole of the third switching tube T3 is connected to the second node N2; the gate of the fourth switch transistor T4 is connected to the second node, the first pole of the fourth switch transistor T4 is connected to the first level signal input terminal V1, and the second pole of the fourth switch transistor T4 is connected to the signal output terminal VOUT.
The output pull-down module 3 includes a fifth switch T5, a gate of the fifth switch T5 is connected to the input control terminal VIN, a first pole of the fifth switch T5 is connected to the signal output terminal VOUT, and a second pole of the fifth switch T5 is connected to the second level signal input terminal V2.
Specifically, in the first driving period P11 of the first driving phase P1, the first clock signal input terminal CLKA controls the first switch transistor T1 to be turned on, so that the first level signal input terminal V1 is connected to the first node N1, and the first level signal input from the first level signal input terminal V1 is transmitted to the first node N1. The first node N1 controls the second switch transistor T2 to be turned on, so that the first level signal input terminal V1 is connected to the signal output terminal VOUT, and the first level signal input by the first level signal input terminal V1 is transmitted to the signal output terminal VOUT, thereby enabling the signal output terminal VOUT to output the first level signal.
Meanwhile, in the first driving period P11, the second clock signal input terminal CLKB controls the third switching tube T3 to be turned off, so that the first level signal input terminal V1 is not connected to the second node N2, and further the fourth switching tube T4 is also in a turned-off state, thereby implementing the second pull-up module 2 in an inoperative state. In the first driving period P11, the input control terminal VIN controls the fifth switch transistor T5 to be turned off, so that the signal output terminal VOUT is not connected to the second level signal input terminal V2.
In the second driving period P12 of the first driving phase P1, the second clock signal input terminal CLKB controls the third switching transistor T3 to be turned on, so that the first level signal input terminal V1 is connected to the second node N2, and the first level signal input from the first level signal input terminal V1 is transmitted to the second node N2. The second node N2 controls the fourth switch tube T4 to be turned on, so that the first level signal input terminal V1 is connected to the signal output terminal VOUT, and the first level signal input by the first level signal input terminal V1 is transmitted to the signal output terminal VOUT, thereby enabling the signal output terminal VOUT to output the first level signal.
Meanwhile, in the second driving period P12, the first clock signal input terminal CLKA controls the first switch transistor T1 to be turned off, so that the first level signal input terminal V1 is not connected to the first node N1, and the second switch transistor T2 is also in a turned-off state, thereby implementing that the first pull-up module 1 is in an inoperative state. In the second driving period P12, the input control terminal VIN controls the fifth switch transistor T5 to be turned off, so that the signal output terminal VOUT is not connected to the second level signal input terminal V2.
In the second driving phase P2, the first switch transistor T1, the second switch transistor T2, the third switch transistor T3 and the fourth switch transistor T4 are all turned off, so that the first pull-up module 1 and the second pull-up module 2 are both in an inactive state. In the second driving phase P2, the input control terminal VIN controls the fifth switch T5 to be turned on, so that the signal output terminal VOUT is connected to the second level signal input terminal V2, and the second level signal input from the second level signal input terminal V2 is transmitted to the signal output terminal VOUT, so that the signal output terminal VOUT can output the second level signal.
With reference to fig. 4, the first pull-up module 1 of the above embodiment further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the first node N1, and a second end of the first capacitor C1 is connected to the signal output terminal VOUT; and/or, the second pull-up module 2 further includes a second capacitor C2, a first terminal of the second capacitor C2 is connected to the second node N2, and a second terminal of the second capacitor C2 is connected to the signal output terminal VOUT.
Specifically, when the first pull-up module 1 includes the first capacitor C1, in the first driving period P11, the first switch tube T1 and the second switch tube T2 are sequentially turned on, after the first switch tube T1 is turned on, the potential of the first node N1 becomes the first level, after the second switch tube T2 is turned on, the potential of the second end of the first capacitor C1 rises, and due to the coupling effect of the capacitors, the potential of the first end of the first capacitor C1 rises, so that the potential of the first node N1 is further raised, and after the potential of the first node N1 is raised, the second switch tube T2 can be in the fully-open state under the control of the first node N1, so that the threshold voltage of the second switch tube T2 is prevented from affecting the first level signal transmitted to the signal output terminal VOUT, and the inverter can better realize rail-to-rail output.
Similarly, when the second pull-up module 2 includes the second capacitor C2, in the second driving period P12, the third switch T3 and the fourth switch T4 are sequentially turned on, after the third switch T3 is turned on, the potential of the second node N2 becomes the first level, after the fourth switch T4 is turned on, the potential of the second end of the second capacitor C2 is raised, and due to the coupling effect of the capacitors, the potential of the first end of the second capacitor C2 is raised, so that the potential of the second node N2 is further raised, and after the potential of the second node N2 is raised, the fourth switch T4 can be in the fully-open state under the control of the second node N2, thereby preventing the threshold voltage of the fourth switch T4 from affecting the first level signal transmitted to the signal output terminal VOUT, and better implementing the rail-to-rail output of the inverter.
As shown in fig. 3, the inverter provided in the above embodiment further includes: the first node control module 4 is respectively connected to the second clock signal input terminal CLKB, the second level signal input terminal V2 and the first node N1, and is configured to control whether the first node N1 is connected to the second level signal input terminal V2 under the control of the second clock signal input terminal CLKB; and/or, the second node control module 5 is respectively connected to the first clock signal input terminal CLKA, the second level signal input terminal V2 and the second node N2, and is configured to control whether the second node N2 is connected to the second level signal input terminal V2 under the control of the first clock signal input terminal CLKA.
Specifically, in the first driving period P11 in the first driving phase P1, the first node control module 4 controls the first node N1 to be disconnected from the second level signal input terminal V2 under the control of the second clock signal input terminal CLKB; meanwhile, the second node control module 5 controls the second node N2 to be connected to the second level signal input terminal V2 under the control of the first clock signal input terminal CLKA.
In the second driving period P12 of the first driving stage P1, the first node control module 4 controls the first node N1 to be connected to the second level signal input terminal V2 under the control of the second clock signal input terminal CLKB; meanwhile, the second node control module 5 controls the second node N2 not to be connected to the second level signal input terminal V2 under the control of the first clock signal input terminal CLKA.
The inverter provided by the above embodiment includes the first node control module 4 and the second node control module 5, so that when the first pull-up module 1 is in an operating state and the second pull-up module 2 is in an inoperative state, the second node control module 5 can pull down the potential of the second node N2, thereby preventing the second node N2 from being in a floating state, and the signal output by the signal output terminal VOUT is influenced by the coupling effect of the second capacitor C2. Similarly, when the first pull-up module 1 is in an inoperative state and the second pull-up module 2 is in an operative state, the potential of the first node N1 can be pulled down through the first node control module 4, so that the first node N1 is prevented from being in a floating state, the second switch tube T2 is acted by the coupling action of the second capacitor C1, and further the signal output by the signal output terminal VOUT is influenced. Therefore, when the inverter provided in the above embodiment includes the first node control module 4 and the second node control module 5, the noise signal in the signal output from the signal output terminal VOUT can be avoided.
Further, with continued reference to fig. 4, the first node control module 4 provided in the above embodiment includes a sixth switch T6, a gate of the sixth switch T6 is connected to the second clock signal input terminal CLKB, a first pole of the sixth switch T6 is connected to the first node N1, and a second pole of the sixth switch T6 is connected to the second level signal input terminal V2; the second node control module 5 includes a seventh switch T7, a gate of the seventh switch T7 is connected to the first clock signal input terminal CLKA, a first pole of the seventh switch T7 is connected to the second node N2, and a second pole of the seventh switch T7 is connected to the second level signal input terminal V2.
Specifically, in the first driving period P11 in the first driving phase P1, the sixth switching tube T6 is turned off under the control of the second clock signal input terminal CLKB, so that the first node N1 is not connected to the second level signal input terminal V2; meanwhile, under the control of the first clock signal input terminal CLKA, the seventh switch transistor T7 is turned on, so that the second node N2 is connected to the second level signal input terminal V2.
In the second driving period P12 of the first driving phase P1, the sixth switching tube T6 is turned on under the control of the second clock signal input terminal CLKB, so that the first node N1 is connected to the second level signal input terminal V2; meanwhile, under the control of the first clock signal input terminal CLKA, the seventh switching tube T7 is turned off, so that the second node N2 is not connected to the second level signal input terminal V2.
As shown in fig. 3, the inverter provided in the above embodiment further includes: the first node pull-down module 6 is respectively connected to the input control terminal VIN, the first node N1 and the second level signal input terminal V2, and is configured to control whether the first node N1 is connected to the second level signal input terminal V2 under the control of the input control terminal VIN; and/or the second node pull-down module 7 is respectively connected to the input control terminal VIN, the second node N2 and the second level signal input terminal V2, and is configured to control whether the second node N2 is connected to the second level signal input terminal V2 under the control of the input control terminal VIN.
Specifically, in the first driving period P11 and the second driving period P12 of the first driving phase P1, the first node pull-down module 6 controls the first node N1 not to be connected to the second level signal input terminal V2 and the second node pull-down module 7 controls the second node N2 not to be connected to the second level signal input terminal V2 under the control of the input control terminal VIN. In the second driving phase P2, under the control of the input control terminal VIN, the first node pull-down module 6 controls the first node N1 to be connected to the second level signal input terminal V2, and the second node pull-down module 7 controls the second node N2 to be connected to the second level signal input terminal V2.
The inverter provided by the above embodiment includes the first node pull-down module 6 and the second node pull-down module 7, so that in the second driving phase P2, the first node pull-down module 6 can pull down the potential of the first node N1, and the second node pull-down module 7 can pull down the potential of the second node N2, thereby achieving that the inverter can pull down the potential of the signal output terminal VOUT more quickly in the second driving phase P2, and avoiding the problem that the potential of the signal output terminal VOUT is not pulled down completely because only the output pull-down module 3 pulls down the potential of the signal output terminal VOUT.
Further, with reference to fig. 4, the first node pull-down module 6 provided in the above embodiment includes an eighth switch T8, a gate of the eighth switch T8 is connected to the input control terminal VIN, a first pole of the eighth switch T8 is connected to the first node N1, and a second pole of the eighth switch T8 is connected to the second level signal input terminal V2;
the second node pull-down module 7 includes a ninth switch T9, a gate of the ninth switch T9 is connected to the input control terminal VIN, a first pole of the ninth switch T9 is connected to the second node N2, and a second pole of the ninth switch T9 is connected to the second level signal input terminal V2.
Specifically, in the first driving period P11 and the second driving period P12 in the first driving phase P1, under the control of the input control terminal VIN, the eighth switching tube T8 is turned off, so that the first node N1 is not connected to the second level signal input terminal V2, and the ninth switching tube T9 is turned off, so that the second node N2 is not connected to the second level signal input terminal V2. In the second driving phase P2, under the control of the input control terminal VIN, the eighth switch T8 is turned on, such that the first node N1 is connected to the second level signal input terminal V2, and the ninth switch T9 is turned on, such that the second node N2 is connected to the second level signal input terminal V2. It should be noted that, in the second driving phase P2, although T1 and T3 can be turned on alternately to affect the potentials of the first node N1 and the second node N2, since the eighth switch tube T8 and the ninth switch tube T9 are both turned on, the potentials of the first node N1 and the second node N2 can still be pulled down well, and the stability of the operation of the inverter can be ensured.
Further, the width-to-length ratio (W/L) of the eighth switching tube T8 and the ninth switching tube T9 may be set to be smaller than the width-to-length ratio (W/L) of the fifth switching tube T5, the sixth switching tube T6 and the seventh switching tube T7, so that the eighth switching tube T8 and the ninth switching tube T9 can have smaller leakage current, and the first node N1 and the second node N2 can be more stable, thereby further improving the stability of the inverter operation.
Each of the switching transistors may be a thin film transistor, a field effect transistor, or another device having the same characteristics. In the above embodiments, to distinguish the two poles of each switching tube except the gate, one of the two poles is referred to as a first pole, and the other pole is referred to as a second pole. In practical operation, the first pole may be a drain, and the second pole may be a source; alternatively, the first pole may be a source and the second pole may be a drain.
In the above embodiments, each switch is an N-type transistor, and the first electrode is a drain electrode and the second electrode is a source electrode. When the N-type transistors are used as the switches in the above embodiments, the first level signal input terminal V1 can be selected as a high level signal input terminal, the first level signal input by the high level signal input terminal is a high level signal (VGH), the second level signal input terminal V2 can be selected as a low level signal input terminal, and the second level signal input by the low level signal input terminal is a low level signal (VGL). The first level of the input control terminal VIN input mentioned in the above embodiments may be selected as a high level, and the second level of the input control terminal VIN input may be selected as a low level. Furthermore, when the inverter operates normally, the first level of the input control terminal VIN may be set to be the same as the high level signal input by the first level signal input terminal V1, and the second level of the input control terminal VIN may be set to be the same as the low level signal input by the second level signal input terminal V2.
In addition, each of the switch tubes may be a P-type transistor, and the circuit design in which each of the switch tubes is a P-type transistor is also within the protection scope of the present application, when each of the switch tubes is a P-type transistor, for the circuit diagram in fig. 4, it is only necessary to invert both the first clock signal input by the first clock signal input terminal CLKA and the second clock signal input by the second clock signal input terminal CLKB (it can be understood that the waveform corresponding to CLKA in fig. 5 is exchanged with the waveform corresponding to CLKB), output the low-level signal from the first level signal input terminal V1, and output the high-level signal from the second level signal input terminal V2.
The embodiment of the invention also provides a shift register unit which comprises the inverter provided by the embodiment.
Since the inverter provided in the above embodiment has stable working performance, can implement rail-to-rail output, and can reduce noise of the signal output by the signal output terminal, and the like, the shift register unit provided in the embodiment of the present invention also has the above advantages when including the above inverter, and details thereof are not described herein.
The embodiment of the invention also provides a display device which comprises the shift register unit provided by the embodiment.
Since the shift register unit includes the inverter provided in the above embodiments, the display device provided in the embodiments of the present invention also has the advantages of the shift register unit when the shift register unit is included, and details are not repeated herein.
The embodiment of the present invention further provides a driving method for an inverter, which is used for driving the inverter provided in the above embodiment, and the driving method includes: a first inversion step is performed at the first driving phase P1, and a second inversion step is performed at the second driving phase P2; the first driving phase P1 includes first driving periods P11 and second driving periods P12 alternately arranged.
The first inversion step includes:
in the first driving period P11, the input control terminal VIN inputs the second level, and the first pull-up module 1 controls the first level signal input terminal V1 to be connected to the signal output terminal VOUT under the control of the first clock signal input terminal CLKA;
specifically, in the first driving period P11, the input control terminal VIN inputs the second level, and the output pull-down module 3 is controlled by the input control terminal VIN, so that the control signal output terminal VOUT is not connected to the second level signal input terminal V2. The first pull-up module 1 controls the first level signal input terminal V1 to be connected to the signal output terminal VOUT under the control of the first clock signal input terminal CLKA, thereby enabling the signal output terminal VOUT to output a first level signal. Meanwhile, in the first driving period P11, the second pull-up module 2 is in an inactive state under the control of the second clock signal input terminal CLKB, thereby realizing that the first level signal is output only by the first pull-up module 1 control signal output terminal VOUT in the first driving period P11.
In the second driving period P12, the input control terminal VIN inputs the second level, and the second pull-up module 2 controls the first level signal input terminal V1 to be connected to the signal output terminal VOUT under the control of the second clock signal input terminal CLKB.
Specifically, the input control terminal VIN continues to input the second level, and the output pull-down module 3 continues to control the signal output terminal VOUT to be disconnected from the second level signal input terminal V2 under the control of the input control terminal VIN. The second pull-up module 2 controls the first level signal input terminal V1 to be connected to the signal output terminal VOUT under the control of the second clock signal input terminal CLKB, so that the signal output terminal VOUT can output the first level signal. Meanwhile, in the second driving period P11, the first pull-up module 1 is in an inactive state under the control of the first clock signal input terminal CLKA, thereby realizing that the signal output terminal VOUT outputs the first level signal only by the second pull-up module 2 in the first driving period P11.
The second inversion step includes:
the input control terminal VIN inputs a first level, the output pull-down module 3 is controlled by the input control terminal VIN, and the control signal output terminal VOUT is connected to the second level signal input terminal V2.
Specifically, the first pull-up module 1 is in an inactive state under the control of the first clock signal input terminal CLKA, and the second pull-up module 2 is in an inactive state under the control of the second clock signal input terminal CLKB. The input control terminal VIN inputs a first level, the output pull-down module 3 is controlled by the input control terminal VIN, and the control signal output terminal VOUT is connected to the second level signal input terminal V2, so that the signal output terminal VOUT outputs a second level signal.
When the inverter is driven by using the driving method of the inverter according to the embodiment of the present invention, in the first driving period P11, the second pull-up module 2 is in the inactive state, and the first level signal input terminal V1 is controlled to be connected to the signal output terminal VOUT only by the first pull-up module 1, so that the signal output terminal VOUT can output the first level signal. And in the second driving period P12, the first pull-up module 1 is in the inactive state, and the first level signal input terminal V1 is controlled to be connected to the signal output terminal VOUT only by the second pull-up module 2, so that the signal output terminal VOUT can output the first level signal. It can be seen that when the inverter is driven by using the driving method of the inverter provided by the embodiment of the present invention, the first pull-up module 1 and the second pull-up module 2 can be controlled to alternately operate, so as to avoid the problem that the transistor in the module is easy to have threshold voltage drift due to only one pull-up module being in an operating state for a long time, and enable the inverter to have higher operating stability.
In the foregoing description of embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (9)
1. An inverter, comprising:
the first pull-up module is respectively connected with a first level signal input end, a first clock signal input end and a signal output end and is used for controlling whether the first level signal input end is connected with the signal output end or not under the control of the first clock signal input end;
the second pull-up module is respectively connected with the first level signal input end, the second clock signal input end and the signal output end, and is used for controlling whether the first level signal input end is connected with the signal output end or not under the control of the second clock signal input end;
the output pull-down module is respectively connected with an input control end, the signal output end and a second level signal input end and is used for controlling whether the signal output end is connected with the second level signal input end or not under the control of the input control end;
when the inverter works, the inverter comprises two driving stages, wherein a first inversion step is executed in the first driving stage, and a second inversion step is executed in the second driving stage; wherein the first driving phase includes first driving periods and second driving periods alternately arranged;
in the first driving period: the input control end inputs a second level, the output pull-down module is controlled by the input control end, and the control signal output end is not connected with the second level signal input end; the first pull-up module controls the first level signal input end to be connected with the signal output end under the control of the first clock signal input end, so that the signal output end can output a first level signal; in the first driving period, the second pull-up module is in an idle state under the control of the second clock signal input end, and only the first pull-up module controls the signal output end to output a first level signal in the first driving period;
in the second driving period: the input control end continues to input a second level, and the output pull-down module continues to control the signal output end to be disconnected with the second level signal input end under the control of the input control end; the second pull-up module controls the first level signal input end to be connected with the signal output end under the control of the second clock signal input end, so that the signal output end can output a first level signal; in the second driving period, the first pull-up module is in a non-working state under the control of the first clock signal input end, and only the second pull-up module controls the signal output end to output a first level signal in the second driving period;
the first pull-up module comprises a first switch tube and a second switch tube; the grid electrode of the first switch tube is connected with the first clock signal input end, the first pole of the first switch tube is connected with the first level signal input end, and the second pole of the first switch tube is connected with the first node; a grid electrode of the second switch tube is connected with the first node, a first pole of the second switch tube is connected with the first level signal input end, and a second pole of the second switch tube is connected with the signal output end;
the second upward-pulling module comprises a third switch tube and a fourth switch tube; the grid electrode of the third switching tube is connected with the second clock signal input end, the first pole of the third switching tube is connected with the first level signal input end, and the second pole of the third switching tube is connected with the second node; a grid electrode of the fourth switching tube is connected with the second node, a first pole of the fourth switching tube is connected with the first level signal input end, and a second pole of the fourth switching tube is connected with the signal output end;
the output pull-down module comprises a fifth switch tube, the grid electrode of the fifth switch tube is connected with the input control end, the first pole of the fifth switch tube is connected with the signal output end, and the second pole of the fifth switch tube is connected with the second level signal input end.
2. The inverter according to claim 1,
the first pull-up module further comprises a first capacitor, a first end of the first capacitor is connected with the first node, and a second end of the first capacitor is connected with the signal output end; and/or the presence of a gas in the gas,
the second pull-up module further comprises a second capacitor, a first end of the second capacitor is connected with the second node, and a second end of the second capacitor is connected with the signal output end.
3. The inverter according to claim 1 or 2, further comprising:
the first node control module is respectively connected with the second clock signal input end, the second level signal input end and the first node, and is used for controlling whether the first node is connected with the second level signal input end or not under the control of the second clock signal input end; and/or the presence of a gas in the gas,
and the second node control module is respectively connected with the first clock signal input end, the second level signal input end and the second node and is used for controlling whether the second node is connected with the second level signal input end or not under the control of the first clock signal input end.
4. The inverter according to claim 3,
the first node control module comprises a sixth switching tube, the grid electrode of the sixth switching tube is connected with the second clock signal input end, the first pole of the sixth switching tube is connected with the first node, and the second pole of the sixth switching tube is connected with the second level signal input end;
the second node control module comprises a seventh switch tube, the grid electrode of the seventh switch tube is connected with the first clock signal input end, the first pole of the seventh switch tube is connected with the second node, and the second pole of the seventh switch tube is connected with the second level signal input end.
5. The inverter according to claim 1 or 2, further comprising:
the first node pull-down module is respectively connected with the input control end, the first node and the second level signal input end, and is used for controlling whether the first node is connected with the second level signal input end or not under the control of the input control end; and/or the presence of a gas in the gas,
and the second node pull-down module is respectively connected with the input control end, the second node and the second level signal input end and is used for controlling whether the second node is connected with the second level signal input end or not under the control of the input control end.
6. The inverter according to claim 5,
the first node pull-down module comprises an eighth switch tube, the grid electrode of the eighth switch tube is connected with the input control end, the first pole of the eighth switch tube is connected with the first node, and the second pole of the eighth switch tube is connected with the second level signal input end;
the second node pull-down module comprises a ninth switch tube, the grid electrode of the ninth switch tube is connected with the input control end, the first pole of the ninth switch tube is connected with the second node, and the second pole of the ninth switch tube is connected with the second level signal input end.
7. A shift register cell comprising the inverter according to any one of claims 1 to 6.
8. A display device comprising the shift register unit according to claim 7.
9. A driving method of an inverter, for driving the inverter according to any one of claims 1 to 6, the driving method comprising: two driving stages, a first inversion step being performed in a first driving stage, and a second inversion step being performed in a second driving stage; the first driving phase comprises first driving periods and second driving periods which are alternately arranged;
the first inverting step includes:
in the first driving time interval, the input control end inputs a second level, and the output pull-down module is controlled by the input control end, so that the control signal output end is not connected with the second level signal input end; the first pull-up module controls the first level signal input end to be connected with the signal output end under the control of a first clock signal input end, so that the signal output end can output a first level signal; in the first driving period, the second pull-up module is in an idle state under the control of the second clock signal input end, and only the first pull-up module controls the signal output end to output a first level signal in the first driving period;
in the second driving time period, the input control end inputs a second level, and the output pull-down module continues to control the signal output end to be disconnected with the second level signal input end under the control of the input control end; the second pull-up module controls the first level signal input end to be connected with the signal output end under the control of a second clock signal input end, so that the signal output end can output a first level signal; in the second driving period, the first pull-up module is in a non-working state under the control of the first clock signal input end, and only the second pull-up module controls the signal output end to output a first level signal in the second driving period;
the second inverting step includes:
the input control end inputs a first level, and the output pull-down module controls the signal output end to be connected with the second level signal input end under the control of the input control end;
the first pull-up module comprises a first switch tube and a second switch tube; the grid electrode of the first switch tube is connected with the first clock signal input end, the first pole of the first switch tube is connected with the first level signal input end, and the second pole of the first switch tube is connected with the first node; a grid electrode of the second switch tube is connected with the first node, a first pole of the second switch tube is connected with the first level signal input end, and a second pole of the second switch tube is connected with the signal output end;
the second upward-pulling module comprises a third switch tube and a fourth switch tube; the grid electrode of the third switching tube is connected with the second clock signal input end, the first pole of the third switching tube is connected with the first level signal input end, and the second pole of the third switching tube is connected with the second node; a grid electrode of the fourth switching tube is connected with the second node, a first pole of the fourth switching tube is connected with the first level signal input end, and a second pole of the fourth switching tube is connected with the signal output end;
the output pull-down module comprises a fifth switch tube, the grid electrode of the fifth switch tube is connected with the input control end, the first pole of the fifth switch tube is connected with the signal output end, and the second pole of the fifth switch tube is connected with the second level signal input end.
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| CN109064964B (en) * | 2018-09-18 | 2021-11-09 | 合肥鑫晟光电科技有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN109887467B (en) * | 2018-11-23 | 2021-05-18 | 北京大学深圳研究生院 | Shift register and gate driving device |
| CN112509513A (en) * | 2020-12-15 | 2021-03-16 | 云谷（固安）科技有限公司 | Shift register, display panel and display device |
| CN112785959B (en) * | 2021-02-05 | 2024-05-10 | 厦门天马微电子有限公司 | Inverter, driving method thereof, driving circuit and display panel |
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