CN105139794A - Shift register circuit and driving method thereof, scanning drive circuit and display device - Google Patents
Shift register circuit and driving method thereof, scanning drive circuit and display device Download PDFInfo
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- CN105139794A CN105139794A CN201510568458.1A CN201510568458A CN105139794A CN 105139794 A CN105139794 A CN 105139794A CN 201510568458 A CN201510568458 A CN 201510568458A CN 105139794 A CN105139794 A CN 105139794A
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Abstract
The invention provides a shift register circuit and a driving method thereof, a scanning drive circuit and a display device. The shift register circuit includes an input module used for pulling up the potential of a first node under control of a signal received by an input end, and pulling down the potential of the first node under control of a signal received by a reset end; an output module used for pulling up the potential of an output end when the first node is at a high level; a pull-down module used for pulling down the potential of the first node and the potential of the output end when a second node is at a high level; a first pull-up module used for utilizing a first clock signal to pull up the potential of the second node periodically when a third node is at a high level; and a second pull-up module used for utilizing a second clock signal to pull up the potential of the third node periodically when the first node is at a low level. The shift register circuit provided by the invention solves the problem that in an existing GOA circuit pull-up and pull-down of the second node increases the area that a circuit occupies and increases circuit power consumption.
Description
Technical field
The present invention relates to display technique field, be specifically related to a kind of shift register circuit and driving method, scan drive circuit, display device.
Background technology
Compared to traditional handicraft, GOA (GateDriveonArray, array base palte row cutting) technology not only can realize the design for aesthetic of display panel both sides symmetry, also eliminate the binding region of scanning drive chip and the wiring area of such as fanout area, be conducive to the realization of narrow frame design.Meanwhile, due to the chip bonding technique on line direction can be saved, also very favourable to the reduction of the production capacity of entirety, the lifting of yield and cost.
A kind of primarily of thin film transistor (TFT) (ThinFilmTransistor, TFT) in the GOA circuit formed, comprise a transistor for the drop-down Section Point place current potential when first node place is high level, and for another transistor of pull-up Section Point current potential under control of the clock signal.Thus, the Section Point under duty be made to be in sufficiently high current potential, last transistor will be made to have enough large breadth length ratio, inevitably can increase the area occupied of GOA circuit like this; The more important thing is, the relative very large electric current of a numerical value can be formed to the pull-up of Section Point with drop-down simultaneously, for GOA circuit brings the no small circuit power consumption of a numerical value, the properties of product that impact is overall.
Summary of the invention
For defect of the prior art, the invention provides shift register circuit and driving method, scan drive circuit, display device, can solve in existing GOA circuit the pull-up of Section Point and the drop-down problem that can increase circuit area occupied, increasing circuit power consumption.
First aspect, the invention provides a kind of shift register circuit, comprises input end, reset terminal and output terminal, also comprises:
Load module, at input end connect the current potential at pull-up first node place under the control of signal, and reset terminal connect the control of signal under the current potential at drop-down described first node place;
Output module, for the current potential at described first node place for output described in pull-up during high level;
Drop-down module, for the current potential of drop-down described first node place current potential and described output when Section Point place is high level;
First pull-up module, at the 3rd Nodes for utilizing the current potential at Section Point place described in the first clock signal period pull-up during high level;
Second pull-up module, at first node place for utilizing the current potential of the 3rd Nodes described in second clock signal period property pull-up during low level;
Wherein, the time period that described first clock signal and described second clock signal are in significant level staggers mutually.
Alternatively, described load module comprises the first transistor and transistor seconds, wherein:
The grid of described the first transistor connects described input end, and source electrode is connected the first bias voltage line with in drain electrode, and another connects described first node;
The grid of described transistor seconds connects described reset terminal, and source electrode is connected described first node with in drain electrode, and another connects the second bias voltage line.
Alternatively, described output module comprises third transistor and the first electric capacity, wherein:
The grid of described third transistor connects described first node, and source electrode is connected described second clock signal with in drain electrode, and another connects described output terminal;
The first end of described first electric capacity connects described first node, and the second end connects described output terminal.
Alternatively, described drop-down module comprises the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor and the second electric capacity, wherein:
The grid of described 4th transistor connects described Section Point, and source electrode is connected described output terminal with in drain electrode, and another connects low level voltage line;
The grid of described 5th transistor connects described first node, and source electrode is connected described Section Point with in drain electrode, and another connects low level voltage line;
The grid of described 6th transistor connects described Section Point, and source electrode is connected described first node with in drain electrode, and another connects low level voltage line;
The grid of described 7th transistor connects described output terminal, and source electrode is connected described Section Point with in drain electrode, and another connects low level voltage line;
The first end of described second electric capacity connects described Section Point, and the second end connects low level voltage line.
Alternatively, described first pull-up module comprises the 8th transistor and the 9th transistor, wherein:
The grid of described 8th transistor connects described 3rd node, and source electrode is connected described first clock signal with in drain electrode, and another connects described 9th transistor;
The grid of described 9th transistor connects described first clock signal, and source electrode is connected described 8th transistor with in drain electrode, and another connects described Section Point.
Alternatively, described second pull-up module comprises the tenth transistor and the 11 transistor, wherein:
The grid of described tenth transistor connects described second clock signal, and source electrode is connected described second clock signal with in drain electrode, and another connects described 3rd node;
The grid of described 11 transistor connects described first node, and source electrode is connected described 3rd node with in drain electrode, and another connects low level voltage line.
Second aspect, present invention also offers a kind of driving method of any one shift register circuit above-mentioned, comprising:
Within the first stage, apply input signal to described input end, to make the current potential at first node place described in described load module pull-up, and make the current potential of described output module output described in pull-up in the subordinate phase that described first node place is high level;
Within the phase III, apply reset signal to described reset terminal, to make the current potential at the drop-down described first node place of described load module, and make the current potential of described drop-down module drop-down described first node and described output when Section Point place is high level;
Wherein, described second pull-up module at first node place for utilizing the current potential of the 3rd Nodes described in second clock signal period property pull-up during low level; Described first pull-up module at the 3rd Nodes for utilizing the current potential at Section Point place described in the first clock signal period pull-up during high level.
The third aspect, present invention also offers a kind of scan drive circuit, comprises multi-stage shift register unit, and every one-level shift register cell all has the circuit structure of any one shift register circuit above-mentioned.
Fourth aspect, present invention also offers a kind of array base palte, any one scan drive circuit above-mentioned comprising substrate and formed on the substrate.
5th aspect, present invention also offers a kind of display device, comprises any one array base palte above-mentioned.
As shown from the above technical solution, the present invention is based on the setting of the first pull-up module and the second pull-up module, during first node place is high level, can not carry out pull-up to Section Point place current potential, thus drop-down module does not need very large pull-down capability Section Point now can be maintained enough low current potential yet.Thus, the present invention can solve the existence of existing GOA circuit and carry out pull-up and drop-down problem to Section Point simultaneously, contributes to reducing circuit area occupied, reducing circuit power consumption.
In instructions of the present invention, describe a large amount of detail.But can understand, embodiments of the invention can be put into practice when not having these details.In some instances, be not shown specifically known method, structure and technology, so that not fuzzy understanding of this description.
Similarly, be to be understood that, to disclose and to help to understand in each inventive aspect one or more to simplify the present invention, in the description above to exemplary embodiment of the present invention, each feature of the present invention is grouped together in single embodiment, figure or the description to it sometimes.But, the method for the disclosure should not explained the following intention in reflection: namely the present invention for required protection requires feature more more than the feature clearly recorded in each claim.Or rather, as the following claims reflect, all features of inventive aspect disclosed single embodiment before being to be less than.Therefore, the claims following embodiment are incorporated to this embodiment thus clearly, and wherein each claim itself is as independent embodiment of the present invention.
The present invention will be described instead of limit the invention to it should be noted above-described embodiment, and those skilled in the art can design alternative embodiment when not departing from the scope of claims.In the claims, any reference symbol between bracket should be configured to limitations on claims.Word " comprises " not to be got rid of existence and does not arrange element in the claims or step.Word "a" or "an" before being positioned at element is not got rid of and be there is multiple such element.The present invention can by means of including the hardware of some different elements and realizing by means of the computing machine of suitably programming.In the unit claim listing some devices, several in these devices can be carry out imbody by same hardware branch.Word first, second and third-class use do not represent any order.Can be title by these word explanations.
Last it is noted that above each embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme, it all should be encompassed in the middle of the scope of claim of the present invention and instructions.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, simply introduce doing one to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structured flowchart of a kind of shift register circuit in one embodiment of the invention;
Fig. 2 is the circuit structure diagram of a kind of shift register circuit in one embodiment of the invention;
Fig. 3 is the circuit simulation sequential chart of a kind of shift register circuit shown in Fig. 2;
Fig. 4 is a kind of circuit simulation sequential chart of shift register circuit of contrast;
Fig. 5 is the steps flow chart schematic diagram of the driving method of a kind of shift register circuit in one embodiment of the invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Fig. 1 is the structured flowchart of a kind of shift register circuit in one embodiment of the invention.See Fig. 1, this shift register circuit comprises input end IN, reset terminal RESET and output terminal OUT, also comprises:
Load module 11, at input end IN connect the current potential at pull-up first node PU place under the control of signal, and reset terminal RESET connect the control of signal under the current potential at drop-down described first node PU place;
Output module 12, for the current potential at described first node PU place for output terminal OUT place described in pull-up during high level;
Drop-down module 13, for the current potential at described first node PU place current potential drop-down when Section Point PD place is high level and described output terminal OUT place;
First pull-up module 14, at the 3rd node PM place for utilizing the current potential at the first clock signal C K periodically Section Point PD place described in pull-up during high level;
Second pull-up module 15, at first node PU place for utilizing the current potential at second clock signal CKB periodically the 3rd node PM place described in pull-up during low level;
Wherein, the time period that described first clock signal C K and described second clock signal CKB is in significant level staggers mutually.
It should be noted that, " high level " and " low level " herein refers to two kinds of logic states that a certain circuit node position is represented by potential level scope respectively.For example, the high level at first node PU place specifically can refer to the current potential higher than common port more than voltage 3V, and the low level of first node place PU specifically can refer to the current potential lower than common port more than voltage 3V; And the high level at Section Point PD place specifically can refer to the current potential higher than common port more than voltage 6V simultaneously, the low level of first node place PU specifically can refer to the current potential lower than common port more than voltage 6V.Be understandable that, concrete potential level scope can be arranged as required under embody rule scene, and the present invention does not limit this.
Corresponding with it, " pull-up " herein refers to and makes the level at corresponding circuit node place rise to high level, and " drop-down " herein refers to and make the level at corresponding circuit node place drop to low level.Be understandable that, above-mentioned " pull-up " and " drop-down " all can be realized by the displacement of electric charge, and therefore can specifically realize by the electronic devices and components or its combination with corresponding function, the present invention does not limit this.
In order to be illustrated more clearly in the structure and fuction of above-mentioned each module, a summary is done, see Fig. 1 to the principle of work of this shift register circuit below:
Under general state, first node PU and output terminal OUT place are low level, thus the second pull-up module 15 utilizes the current potential at the 3rd node PM place described in second clock signal CKB periodicity pull-up, makes the 3rd node PM place for high level.Thus the first pull-up module 14 utilizes the current potential at Section Point PD place described in the first clock signal C K periodicity pull-up, makes Section Point PD place for high level.Thus, drop-down module 13 can when Section Point PD place is high level the current potential at drop-down described first node PU place's current potential and described output terminal OUT place, keep the low level at first node PU and output terminal OUT place.
When input end signal that IN connects is converted to significant level, load module 11 can by the current potential pull-up at first node PU place.Now, output module 12 can under the high level effect at first node PU place the current potential at pull-up output terminal OUT place, the signal that output terminal is exported is high level.After this, when reset terminal signal that RESET connects transfers significant level to, load module 11 can by drop-down for the current potential at first node PU place.Now, first pull-up module 14, second pull-up module 15 and drop-down module 13 can according to the process same with under general state the current potential at drop-down described first node PU place's current potential and described output terminal OUT place, make first node PU and output terminal OUT place remain low level.
In addition under preferably condition, drop-down module 13 can also for the current potential at described Section Point PD place drop-down when first node PU place is high level, and when output terminal OUT place is high level the current potential at drop-down described Section Point PD place.Thus, the impact on the current potential at first node PU place and output terminal OUT place of drop-down module 13 in during first node PU place is pulled to high level can be reduced.
Can find out, the embodiment of the present invention is based on the setting of the first pull-up module 14 and the second pull-up module 15, can not carry out pull-up to Section Point PD place current potential at first node PU place for during high level, thus drop-down module 13 does not need very large pull-down capability Section Point PD now can be maintained enough low current potential yet.Thus, the present invention can solve the existence of existing GOA circuit and carry out pull-up and drop-down problem to Section Point simultaneously, contributes to reducing circuit area occupied, reducing circuit power consumption.
As one example more specifically, Fig. 2 is the circuit structure diagram of a kind of shift register circuit in one embodiment of the invention, see Fig. 2:
In the embodiment of the present invention, above-mentioned load module 11 comprises the first transistor T1 and transistor seconds T2, and the grid of the first transistor T1 wherein connects input end IN, and source electrode is connected the first bias voltage line CN with in drain electrode, and another connects first node PU; The grid of transistor seconds T2 connects reset terminal RESET, and source electrode is connected first node PU with in drain electrode, and another connects the second bias voltage line CNB.
It should be noted that, transistor shown in Fig. 2 is N-type transistor (when grid is high level source electrode and drain electrode conducting), but can replace the part or all of transistor in figure in other embodiments of the invention with P-type crystal pipe (when grid is low level source electrode and drain electrode conducting), the present invention is not restricted this.And, the connected mode of each transistor source and drain electrode can be determined according to the type of selected transistor, and at transistor, there are source electrode and source electrode during drain electrode symmetrical structure and two electrodes that can be considered as not doing to distinguish especially that drain, it is well-known to those skilled in the art, does not repeat them here.
Thus, first bias voltage line CN is applied with the bias voltage of the high level for providing first node PU, the high level of input end IN can make the first transistor T1 inside form the electric current being flowed to first node PU by the first bias voltage line CN, to realize the pull-up of first node PU.When the second bias voltage line CNB being applied with for providing the low level bias voltage of first node PU, the high level of reset terminal RESET can make transistor seconds T2 inside form the electric current being flowed to the second bias voltage line CNB by first node PU, to realize the drop-down of first node PU.Can find out, the embodiment of the present invention realizes the function of above-mentioned load module 11 by two transistors.
In the embodiment of the present invention, the grid that above-mentioned output module 12 comprises third transistor T3 and the first electric capacity C1, third transistor T3 wherein connects first node PU, and source electrode is connected second clock signal CKB with in drain electrode, and another connects output terminal OUT; The first end of the first electric capacity C1 connects first node PU, and the second end connects output terminal OUT.Thus, be high level at first node PU place, the first electric capacity C1 is when storing a certain amount of electric charge under the state that two ends have potential difference (PD), current potential on second clock signal wire CKB transfers high level to by low level and can make the current potential of output terminal OUT can by the electric current pull-up from the first clock cable CK, and the current potential at first node PU place by further lifting, can accelerate the speed that output terminal OUT place current potential is pulled up under the effect of the first electric capacity C1.Can find out, the embodiment of the present invention realizes the function of above-mentioned output module 12 by a transistor and electric capacity.
In the embodiment of the present invention, above-mentioned drop-down module 13 comprises the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the 7th transistor T7 and the second electric capacity C2.Wherein:
The grid of the 4th transistor T4 connects Section Point PD, and source electrode is connected output terminal OUT with in drain electrode, and another connects low level voltage line VGL;
The grid of the 5th transistor T5 connects first node PU, and source electrode is connected Section Point PD with in drain electrode, and another connects low level voltage line VGL;
The grid of the 6th transistor T6 connects Section Point PD, and source electrode is connected first node PU with in drain electrode, and another connects low level voltage line VGL;
The grid of the 7th transistor T7 connects output terminal OUT, and source electrode is connected Section Point PD with in drain electrode, and another connects low level voltage line VGL;
The first end of the second electric capacity C2 connects Section Point PD, and the second end connects low level voltage line VGL.
Thus, when Section Point PD place is high level, what the 4th transistor T4 was formed in inside flow to the electric current of low level voltage line VGL by first node PU can drop-down described first node PU current potential; And the 6th transistor T6 is formed in inside flow to the electric current of low level voltage line VGL by output terminal OUT can drop-down output terminal OUT current potential.In addition, after first node PU is pulled to high level, what the 5th transistor T5 was formed in inside flow to the electric current of low level voltage line VGL by Section Point PD can drop-down described Section Point PD current potential; After output terminal OUT is pulled to high level, what the 7th transistor T7 was formed in inside flow to the electric current of low level voltage line VGL by Section Point PD can drop-down described Section Point PD current potential.During this period, the second electric capacity C2 can play the effect of stable Section Point PD place current potential.Can find out, the embodiment of the present invention realizes the function of above-mentioned drop-down module 13 by four transistors and electric capacity.
In the embodiment of the present invention, first pull-up module 14 comprises the 8th transistor T8 and the 9th transistor T9, the grid of the 8th transistor T8 wherein connects the 3rd node PM, and source electrode is connected the first clock signal C K with in drain electrode, and another connects source electrode or the drain electrode of the 9th transistor T9; The grid of the 9th transistor T9 connects the first clock signal C K, and source electrode is connected drain electrode or the source electrode of the 8th transistor T8 with in drain electrode, and another connects Section Point PD.Thus, at the 3rd node PM place for high level and the first clock signal C K is also high level time, 8th transistor T8 and the 9th transistor T9 is all in opening, thus flow to the electric current of Section Point PD by the first clock signal C K can Section Point PD current potential described in pull-up.And when the first clock signal C K is low level, the closed condition of the 9th transistor can stop the pull-up to Section Point current potential.Thus, along with the conversion of the first clock signal C K between high level and low level, the periodicity pull-up to described Section Point PD place current potential can be realized.Visible, the embodiment of the present invention realizes the function of above-mentioned first pull-up module 14 by two transistors.
In the embodiment of the present invention, second pull-up module 15 comprises the tenth transistor T10 and the 11 transistor T11, the grid of the tenth transistor T10 wherein connects second clock signal CKB, and source electrode is connected second clock signal CKB with in drain electrode, and another connects the 3rd node PM; The grid of the 11 transistor T11 connects first node PU, and source electrode is connected the 3rd node PM with in drain electrode, and another connects low level voltage line VGL.Thus, when first node PU is low level, the tenth transistor T10 can along with the current potential at the transformation period property pull-up three node PM place of second clock signal CKB between high level and low level; In addition, during first node PU place is high level, the 11 transistor T11 can the tenth transistor T10 close time drop-down 3rd node PM place current potential.Can find out, the embodiment of the present invention realizes the function of above-mentioned second pull-up module 15 by two transistors.
In addition, during first node PU place is high level, the time period being in significant level due to the first clock signal C K and second clock signal CKB staggers mutually, thus always there is one to be in closed condition in the 8th transistor T8 and the 9th transistor T9, thus the periodicity pull-up of the first pull-up module 14 pairs of Section Point PD place current potentials can be stopped during this period.
Be understandable that, the high level at arbitrary circuit node place or low level can be provided by corresponding bias voltage line or other circuit nodes, one end that such as above-mentioned the first transistor T1 is connected with the first bias voltage line CN also can change into be connected with input end IN, one end that above-mentioned transistor seconds T2 is connected with the second bias voltage line CNB also can change into and being connected etc. with reset terminal RESET, it belongs to the equivalent replacement to foregoing circuit structure, and the present invention does not limit this.
Based on the circuit structure shown in Fig. 2, Fig. 3 is the circuit simulation sequential chart of a kind of shift register circuit shown in Fig. 2.Wherein, the signal that connects of reset terminal RESET does not illustrate in the drawings, is 8V, is-8V in all the other time periods during this signal 70us to 80us in the drawings.Be understandable that, the structure and fuction of each module in the circuit sequence shown in Fig. 3 and Fig. 2, and the principle of work of the shift register circuit shown in Fig. 1 is all consistent, does not repeat them here.The part of dashed circle mark can be found out in figure 3, during first node PU place is high level, the time period being in significant level due to the first clock signal C K and second clock signal CKB staggers mutually, thus one is always had to be in closed condition in the 8th transistor T8 and the 9th transistor T9, thus the periodicity pull-up of the first pull-up module 14 pairs of Section Point PD place current potentials can be stopped during this period, make Section Point PD place be stable low level.
As reference, Fig. 4 is a kind of circuit simulation sequential chart of shift register circuit of contrast.This shift register circuit, on the basis of the circuit structure shown in Fig. 2, eliminates the 8th transistor T8, the tenth transistor T10 and the 11 transistor T11.Wherein, the signal that connects of reset terminal RESET does not illustrate in the drawings, is 8V, is-8V in all the other time periods during this signal 70us to 80us in the drawings.The part of dashed circle mark can be found out in the diagram, due at input end IN to connect during signal is high level in (T=30 ~ 40us), the high level of the first clock signal C K can make the 9th transistor T9 open and carry out pull-up to Section Point PD, 5th transistor T5 opens and carries out drop-down to Section Point PD under the high level effect of first node PU simultaneously, both make Section Point PD maintain about-5V under interacting, and deviate from desired-8V voltage.Usually, in order to improve this phenomenon, the breadth length ratio of the 5th transistor T5 can be designed larger than the breadth length ratio of the 9th transistor T9, but such way inevitably can increase the area shared by shift register circuit.And the more important thing is, simultaneously to pull-up and the drop-down relative very large electric current of a numerical value that can be formed of Section Point PD, for shift register circuit brings the no small circuit power consumption of a numerical value.
Easily know after contrast, the embodiment of the present invention is based on the setting of the first pull-up module 14 and the second pull-up module 15, can not carry out pull-up to Section Point PD place current potential at first node PU place for during high level, thus drop-down module 13 does not need very large pull-down capability Section Point PD now can be maintained enough low current potential yet.Thus, the present invention can solve the existence of existing GOA circuit and carry out pull-up and drop-down problem to Section Point simultaneously, contributes to reducing circuit area occupied, reducing circuit power consumption.
Based on same inventive concept, Fig. 5 is the steps flow chart schematic diagram of the driving method of a kind of shift register circuit in one embodiment of the invention, and this shift register circuit can be any one shift register circuit above-mentioned.See Fig. 5, the method comprises:
Step 501: apply input signal to input end within the first stage, to make the current potential at load module pull-up first node place, and make output module be the current potential of pull-up output in the subordinate phase of high level at first node place;
Step 502: apply reset signal to reset terminal within the phase III, to make the current potential at the drop-down first node place of load module, and make the current potential of drop-down module drop-down first node and output when Section Point place is high level;
Wherein, above-mentioned second pull-up module utilizes the current potential of second clock signal period property pull-up the 3rd Nodes when first node place is low level; Above-mentioned first pull-up module utilizes the current potential at the first clock signal period pull-up Section Point place when the 3rd Nodes is high level.
Be understandable that, circuit sequence shown in Fig. 3 can be considered as the concrete example of one of the embodiment of the present invention, and the method step of the embodiment of the present invention is all corresponding with the work schedule of any one shift register circuit above-mentioned, thus specifically for the driving of any one shift register circuit above-mentioned, and the beneficial effect reducing circuit area occupied, reduce circuit power consumption can be obtained.
Based on same inventive concept, the embodiment of the present invention provides a kind of scan drive circuit, and this scan drive circuit comprises multi-stage shift register unit, and every one-level shift register cell all has the circuit structure of any one shift register circuit above-mentioned.In one embodiment of the invention, above-mentioned multi-stage shift register unit can connect in the following manner: except first order shift register cell, and the input end of arbitrary grade of shift register cell is all connected with the output terminal of upper level shift register cell; Except first order shift register cell, the output terminal of arbitrary grade of shift register cell is all connected with the reset terminal of upper level shift register cell.Be understandable that, this scan drive circuit can realize signal transmission step by step and output, and has the advantage that any one shift register circuit above-mentioned has.
Based on same inventive concept, the embodiment of the present invention provides a kind of array base palte, and this array base palte comprises any one scan drive circuit above-mentioned.Be understandable that, this scan drive circuit can be arranged on outside viewing area, to form GOA circuit structure, and has the advantage that any one scan drive circuit above-mentioned has.
Based on same inventive concept, embodiments provide a kind of display device, this display device comprises any one array base palte above-mentioned, thus has the advantage that any one array base palte above-mentioned has.It should be noted that, the display device in the present embodiment can be: any product or parts with Presentation Function such as Electronic Paper, mobile phone, panel computer, televisor, notebook computer, digital album (digital photo frame), navigating instrument.
It should be noted that in describing the invention, term " on ", the orientation of the instruction such as D score or position relationship be based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as limitation of the present invention.Unless otherwise clearly defined and limited, term " installation ", " being connected ", " connection " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
Claims (10)
1. a shift register circuit, is characterized in that, comprises input end, reset terminal and output terminal, also comprises:
Load module, at input end connect the current potential at pull-up first node place under the control of signal, and reset terminal connect the control of signal under the current potential at drop-down described first node place;
Output module, for the current potential at described first node place for output described in pull-up during high level;
Drop-down module, for the current potential of drop-down described first node place current potential and described output when Section Point place is high level;
First pull-up module, at the 3rd Nodes for utilizing the current potential at Section Point place described in the first clock signal period pull-up during high level;
Second pull-up module, at first node place for utilizing the current potential of the 3rd Nodes described in second clock signal period property pull-up during low level;
Wherein, the time period that described first clock signal and described second clock signal are in significant level staggers mutually.
2. shift register circuit according to claim 1, is characterized in that, described load module comprises the first transistor and transistor seconds, wherein:
The grid of described the first transistor connects described input end, and source electrode is connected the first bias voltage line with in drain electrode, and another connects described first node;
The grid of described transistor seconds connects described reset terminal, and source electrode is connected described first node with in drain electrode, and another connects the second bias voltage line.
3. shift register circuit according to claim 1, is characterized in that, described output module comprises third transistor and the first electric capacity, wherein:
The grid of described third transistor connects described first node, and source electrode is connected described second clock signal with in drain electrode, and another connects described output terminal;
The first end of described first electric capacity connects described first node, and the second end connects described output terminal.
4. shift register circuit according to claim 1, is characterized in that, described drop-down module comprises the 4th transistor, the 5th transistor, the 6th transistor, the 7th transistor and the second electric capacity, wherein:
The grid of described 4th transistor connects described Section Point, and source electrode is connected described output terminal with in drain electrode, and another connects low level voltage line;
The grid of described 5th transistor connects described first node, and source electrode is connected described Section Point with in drain electrode, and another connects low level voltage line;
The grid of described 6th transistor connects described Section Point, and source electrode is connected described first node with in drain electrode, and another connects low level voltage line;
The grid of described 7th transistor connects described output terminal, and source electrode is connected described Section Point with in drain electrode, and another connects low level voltage line;
The first end of described second electric capacity connects described Section Point, and the second end connects low level voltage line.
5. shift register circuit according to claim 1, is characterized in that, described first pull-up module comprises the 8th transistor and the 9th transistor, wherein:
The grid of described 8th transistor connects described 3rd node, and source electrode is connected described first clock signal with in drain electrode, and another connects described 9th transistor;
The grid of described 9th transistor connects described first clock signal, and source electrode is connected described 8th transistor with in drain electrode, and another connects described Section Point.
6. shift register circuit according to claim 1, is characterized in that, described second pull-up module comprises the tenth transistor and the 11 transistor, wherein:
The grid of described tenth transistor connects described second clock signal, and source electrode is connected described second clock signal with in drain electrode, and another connects described 3rd node;
The grid of described 11 transistor connects described first node, and source electrode is connected described 3rd node with in drain electrode, and another connects low level voltage line.
7. as a driving method for the shift register circuit of any one in claim 1 to 6, it is characterized in that, comprising:
Within the first stage, apply input signal to described input end, to make the current potential at first node place described in described load module pull-up, and make the current potential of described output module output described in pull-up in the subordinate phase that described first node place is high level;
Within the phase III, apply reset signal to described reset terminal, to make the current potential at the drop-down described first node place of described load module, and make the current potential of described drop-down module drop-down described first node and described output when Section Point place is high level;
Wherein, described second pull-up module at first node place for utilizing the current potential of the 3rd Nodes described in second clock signal period property pull-up during low level; Described first pull-up module at the 3rd Nodes for utilizing the current potential at Section Point place described in the first clock signal period pull-up during high level.
8. a scan drive circuit, is characterized in that, comprises multi-stage shift register unit, and every one-level shift register cell all has the circuit structure as the shift register circuit in claim 1 to 6 as described in any one.
9. an array base palte, is characterized in that, the scan drive circuit as claimed in claim 8 comprising substrate and formed on the substrate.
10. a display device, is characterized in that, comprises array base palte as claimed in claim 9.
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