CN103151013B - Gate driver circuit - Google Patents
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- CN103151013B CN103151013B CN201310072323.7A CN201310072323A CN103151013B CN 103151013 B CN103151013 B CN 103151013B CN 201310072323 A CN201310072323 A CN 201310072323A CN 103151013 B CN103151013 B CN 103151013B
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Abstract
The present invention proposes a kind of gate driver circuit, and it comprises multistage drive element of the grid, and wherein every grade of drive element of the grid comprises the first to the 6th on-off element.3rd on-off element, the 4th on-off element, the 5th on-off element and the 6th on-off element form latch.Latch is used for by receiving upper two-stage gate drive signal and upper level gate drive signal, the first order, second level pull-up are carried out respectively to the voltage of the control signal that its latch exports, to improve the voltage of described latch to the first control end output of the first on-off element.Gate driver circuit of the present invention can export in the time period of the voltage of gate drive signal at drive element of the grid, latch is made to export a very high voltage to the control end of the first on-off element, improve the fan-out capability of the first on-off element, therefore under the prerequisite ensureing the gate drive signal exporting enough voltage, the size of the first on-off element can also be reduced further, and reduce power consumption.
Description
Technical field
The present invention relates to a kind of driving circuit, particularly a kind of gate driver circuit being applicable to liquid crystal indicator.
Background technology
Liquid crystal indicator (LiquidCrystalDisplay, LCD) possesses the plurality of advantages such as frivolous, energy-conservation, radiationless, has therefore replaced traditional cathode ray tube (CRT) display gradually.Current liquid crystal display is widely used in the electronic equipments such as HD digital TV, desk-top computer, PDA(Personal Digital Assistant), notebook computer, mobile phone, digital camera.
With thin film transistor (TFT) (ThinFilmTransistor, TFT) liquid crystal indicator is example, it comprises: display panels and driving circuit, wherein, display panels comprises many gate lines and a plurality of data lines, and adjacent two gate lines and adjacent two data lines intersect to form a pixel cell, each pixel cell at least comprises a thin film transistor (TFT).And driving circuit comprises: gate driver circuit (gatedrivecircuit) and source electrode drive circuit (sourcedrivecircuit).Along with the cost degradation pursuit of the producer to liquid crystal indicator and the raising of manufacturing process, originally the glass substrate that the driving circuit integrated chip be arranged at beyond display panels is arranged at display panels becomes possibility, such as, grid-driving integrated circuit is arranged at array base palte (GateICinArray, GIA) upper thus simplify the manufacture process of liquid crystal indicator, and reduce production cost.
The basic functional principle of display panels and driving circuit is: gate driver circuit is by sending gate drive signal Gn with pulling up transistor to gate line of being electrically connected of gate line, sequentially the TFT of every a line is opened, then the pixel cell of a full line is charged to voltage required separately, to show different GTGs by source electrode drive circuit simultaneously.Namely first to be pulled up transistor by it by the gate driver circuit of the first row and the thin film transistor (TFT) of the first row opened, then charged by the pixel cell of source electrode drive circuit to the first row.When the pixel cell of the first row is charged, this row thin film transistor (TFT) just cuts out by gate driver circuit, then the gate driver circuit of the second row is pulled up transistor by it and to be opened by thin film transistor (TFT) of the second row, then carries out discharge and recharge by source electrode drive circuit to the pixel cell of the second row.So sequentially go down, when the pixel cell of substituting the bad for the good last column, just charge from the first row again.
But, due to narrow frame and high-res (i.e. resolution, the development of small size panel resolution), new challenge is proposed to the design of gate driver circuit: on the one hand, narrow frame limits the size of gate driver circuit, the size (channel width-over-length ratio) pulled up transistor of corresponding output stage is also restricted, because the driving force pulled up transistor is directly proportional to its size, (driving force of transistor is conducted electricity the factor with it and is represented, the value of the conduction factor is larger, its driving force is stronger, the factor of conducting electricity then is directly proportional to the channel width-over-length ratio of transistor), namely the size pulled up transistor if therefore reduce also reduces the driving force pulled up transistor, thus its fan-out capability may be caused to reduce, namely the voltage that gate driver circuit exports reduces, on the other hand, the panel of high-res makes the load of gate line larger, thus in order to the normal display that ensures liquid crystal indicator and display quality, even need pulling up transistor of stronger fan-out capability, but the undertension that the restriction of size but makes latch export to the gate terminal that pulls up transistor exports enough voltage to drive to pull up transistor to gate line, thus cause a contradiction in gate driver circuit design.
Therefore, be necessary to provide the technical scheme of improvement to overcome the above technical matters existed in prior art.
Summary of the invention
The main technical problem to be solved in the present invention is to provide a kind of gate driver circuit, to solve the problem of the fan-out capability deficiency that pulls up transistor of gate driver circuit in the miniaturization of available liquid crystal display device and high-res development.
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, comprise multistage drive element of the grid, wherein every grade of drive element of the grid is for driving on display panel a corresponding gate line respectively, and every grade of drive element of the grid comprises the first to the 6th on-off element.Described first on-off element comprises the first path terminal, alternate path end and the first control end, and described first path terminal receives the first clock signal, and described alternate path end is as the output terminal of described drive element of the grid.Described second switch element comprises third path end, the 4th path terminal and the second control end, described third path termination receives low reference voltage, described second control end receives the second clock signal, and described 4th path terminal is connected with the alternate path end of described first on-off element.Described 3rd on-off element comprises five-way terminal, the 6th path terminal and the 3rd control end and is electrically connected and receives the upper two-stage gate drive signal that the drive element of the grid that upwards differs two-stage exports.Described 4th on-off element it comprise the 7th path terminal, the 8th path terminal and the 4th control end, described 7th path terminal receives the upper level gate drive signal that the drive element of the grid that upwards differs one-level exports, described 4th control end is connected with described 6th path terminal, described 8th path terminal is connected with the 6th path terminal of described 3rd on-off element by the first electric capacity, described 4th control end is connected with described 6th path terminal, and described 8th path terminal is connected with described 6th path terminal by the first electric capacity.Described 5th on-off element it comprise the 9th path terminal, the tenth path terminal and the 5th control end, described 9th path terminal and described 5th control end are all connected with the 4th control end of described 4th on-off element, and described tenth path terminal is connected with described first control end of described first on-off element.Described 6th on-off element it comprise the 11 path terminal, the 12 path terminal and the 6th control end, described 11 path terminal receives described low reference voltage, the lower two-stage gate drive signal that the drive element of the grid that described 6th control end receives difference two-stage downwards exports, described 12 path terminal is connected with described tenth path terminal.
Pole of the present invention driving circuit can export in the time period of the voltage of gate drive signal at drive element of the grid, a very high voltage can be exported to the first control end of the first on-off element, thus improve the fan-out capability of the first on-off element, therefore under the prerequisite ensureing the gate drive signal exporting enough voltage, the size of the first on-off element can also be reduced further, and reduce power consumption.
By the detailed description below with reference to accompanying drawing, other side of the present invention and feature become obvious.But it should be known that accompanying drawing is only the object design of explanation, instead of as the restriction of scope of the present invention, this is because it should with reference to additional claim.Should also be appreciated that, unless otherwise noted, unnecessaryly draw accompanying drawing to scale, they only try hard to structure described herein and flow process are described conceptually.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 1 is the circuit structure diagram of the drive element of the grid in the embodiment of the present invention one.
Fig. 2 is the time diagram of drive element of the grid in embodiment one.
Fig. 3 is the circuit structure diagram of the level Four drive element of the grid of one embodiment of the invention.
Fig. 4 is the time diagram of level Four drive element of the grid as shown in Figure 3.
The gate drive signal voltage-contrast schematic diagram at different ambient temperatures that Fig. 5 exports for drive element of the grid of the present invention.
Fig. 6 is the control signal voltage-contrast schematic diagram at different ambient temperatures that the latch outputs in drive element of the grid of the present invention exports.
Fig. 7 is the level Four drive element of the grid output analog result at different ambient temperatures in the present invention.
Fig. 8 is the circuit diagram of drive element of the grid in prior art.
The voltage-contrast schematic diagram of the control signal that Fig. 9 exports for latch in drive element of the grid in the present invention and prior art.
Figure 10 is the voltage-contrast schematic diagram of exported the at different ambient temperatures gate drive signal of drive element of the grid in the present invention and prior art.
Figure 11 is that at varying environment temperature, in the present invention and prior art, drive element of the grid power consumption contrasts schematic diagram.
Figure 12 is the circuit structure diagram of the drive element of the grid of the embodiment of the present invention two.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Although the present invention uses first, second, third, etc. term to describe different elements, signal, port, assembly or part, these elements, signal, port, assembly or part be not by the restriction of these terms.These terms are only used to an element, signal, port, assembly or part and another element, signal, port, assembly or part to make a distinction.In the present invention, element, port, assembly or a part and another element, port, assembly or part " being connected ", " connection ", can be understood as direct electric connection, or also can be understood as the indirect electric connection that there is intermediary element.Unless otherwise defined, otherwise all terms used in the present invention (comprising technical term and scientific terminology) have the meaning usually understood with those skilled in the art.
Gate driver circuit of the present invention (also referred to as shift register) comprises multistage drive element of the grid (also referred to as shifting deposit unit), the drive element of the grid of every one-level is corresponding with the every a line gate line on display panel to be respectively electrically connected, thus gate drive signal is sequentially successively applied to often on row gate line, the annexation between drive element of the grid will elaborate hereinafter.
Embodiment one
Fig. 1 is the circuit structure diagram of the drive element of the grid in the embodiment of the present invention one.Refer to Fig. 1, the present embodiment gate driver circuit, comprise multistage drive element of the grid, drive element of the grid for exporting gate drive signal Gn, to drive on display panel corresponding gate line respectively.Every grade of drive element of the grid comprises the first on-off element T1, second switch elements T 2, the 3rd on-off element T3, the 4th on-off element T4, the 5th on-off element T5 and the 6th on-off element T6.Wherein, the first on-off element T1 is as pull-up on-off element, and second switch elements T 2 is as drop-down switching element, and the 3rd on-off element T3, the 4th on-off element T4, the 5th on-off element T5 and the 6th on-off element T6 form latch 10.
Particularly, the first on-off element T1 comprises the first path terminal, alternate path end and the first control end, the first path terminal for receiving the first clock signal clk D, alternate path end as the output terminal of drive element of the grid at the corresponding levels to export gate drive signal Gn.
Second switch elements T 2 comprises third path end, the 4th path terminal and the second control end, second control end is for receiving second clock signal CLKA, third path termination receives low reference voltage VGL, and the 4th path terminal is connected with the alternate path end of the first on-off element T1.In the present embodiment, the first on-off element T1 is pull-up on-off element, and second switch elements T 2 is the element that pulls down switch.3rd on-off element T3 comprises five-way terminal, the 6th path terminal and the 3rd control end, and five-way terminal and the 3rd control end are connected and for receiving the upper two-stage gate drive signal Gn-2 that the drive element of the grid that upwards differs two-stage exports.One end of first electric capacity C1 is connected with the 6th path terminal of the 3rd on-off element T3.4th on-off element T4 comprises the 7th path terminal, the 8th path terminal and the 4th control end, the upper level gate drive signal Gn-1 that 7th path terminal exports for receiving the drive element of the grid that upwards differs one-level, 4th control end is connected with the 6th path terminal of the 3rd on-off element T3, and the 8th path terminal is connected with the other end of the first electric capacity C1.Namely the two ends of the first electric capacity C1 are connected with the 6th path terminal of the 3rd on-off element T3 and the 8th path terminal of the 4th on-off element T4 respectively.5th on-off element T5 comprises the 9th path terminal, the 5th control end and the tenth path terminal, 9th path terminal and the 5th control end are all connected with the 4th control end of the 4th on-off element T4, and the tenth path terminal is connected with first control end of the first on-off element T1 and as the output terminal of latch 10.6th on-off element T6 comprises the 11 path terminal, the 6th control end and the 12 path terminal, 11 path terminal receives low reference voltage VGL, the lower two-stage gate drive signal Gn+2 that 6th control end exports for the drive element of the grid receiving difference two-stage downwards, and the 12 path terminal is connected with the tenth path terminal of the 5th on-off element T5.In the present embodiment, the upper two-stage gate drive signal Gn-2 that latch 10 exports according to the drive element of the grid upwards differing two-stage and the upper level gate drive signal Gn-1 that the drive element of the grid upwards differing one-level exports, carries out the first order and second level pull-up respectively with the control signal Q2 exported the output terminal of latch 10.
In addition, the drive element of the grid of the present embodiment can also comprise: the 7th on-off element T7, the 8th on-off element T8, the second electric capacity C2 and the 9th on-off element T9.
In the present embodiment, the 7th on-off element T7 comprises the tenth threeway terminal, the 7th control end and the 14 path terminal, and the 7th control end is connected with first control end of the first on-off element T1, and the tenth three-way termination receives low reference voltage VGL.8th on-off element T8 comprises the tenth five-way terminal, the 8th control end and the 16 path terminal, 16 path terminal is connected with first control end of the first on-off element T1,8th control end is connected with the 14 path terminal of the 7th on-off element T7, and the tenth five-way terminal receives low reference voltage VGL.Second electric capacity C2 is connected between first path terminal of the first on-off element T1 and the 8th control end of the 8th on-off element T8.9th on-off element T9 comprises the 17 path terminal, the 9th control end and the 18 path terminal, 17 path terminal receives low reference voltage VGL, 9th control end is connected with the 8th control end of the 8th on-off element T8, and the 18 path terminal is connected with the 4th path terminal of second switch elements T 2.
In the present embodiment, the first to the 9th on-off element all utilizes N-type transistor and realizes.Certainly, it will be appreciated by persons skilled in the art that the first to the 9th on-off element also can adopt other on-off element and realize, such as P-type crystal pipe.Principle of work of the present invention is introduced particularly below for N-type transistor.
Refer to Fig. 2, it is the time diagram of drive element of the grid in embodiment one, and the course of work of every one-level drive element of the grid is divided into 7 stages:
In the stage 1: when the second clock signal CLKA of input is high level, second switch elements T 2 conducting, the voltage of the gate drive signal Gn at the corresponding levels that drive element of the grid at the corresponding levels exports is pulled down to low reference voltage VGL by the second switch T2 of conducting.
Stage 2: when the level of the upper two-stage gate drive signal Gn-2 that the drive element of the grid upwards differing two-stage exports is by low uprising, the 3rd on-off element T3 conducting, node Q1 is charged, and its voltage raises; Along with the voltage of node Q1 raises, the 4th on-off element T4 and the 5th on-off element T5 starts conducting.Because the 5th on-off element T5 is in conducting state, node Q1 passes through the 5th on-off element T5 of conducting to the output terminal of latch 10, namely node Q2 point charges, thus the voltage of the control signal Q2 of the output of latch 10 is driven high, thus realizes the first time pull-up to the control signal Q2 that latch 10 exports.
Stage 3: when the upper level gate drive signal Gn-1 that the drive element of the grid upwards differing one-level exports level from low to high time, due to the 4th on-off element T4 conducting the stage 2 time, therefore, in the stage 3, the upper level gate drive signal Gn-1 being in high level is charged to node Q0 by the 4th on-off element T4 of conducting.Now due to the boot strap of the first electric capacity C1, along with the rising of node Q0 place voltage, it can make the voltage of Q1 point be drawn high further, drawing high further of node Q1 place's voltage, make the 5th on-off element T5 conductively more abundant, thus the voltage of node Q2 is drawn high again, realize the second time pull-up to node Q2.It should be noted that, in the present invention, can directly adopt the stray capacitance of the 4th on-off element T4 as the first electric capacity C1, or in order to promote pull-up effect, can also adopt one independently memory capacitance as the first electric capacity C1, wherein, the parasitic capacitance in parallel of this separate, stored electric capacity and the 4th on-off element T4 is also common as the first electric capacity C1, i.e. the first electric capacity C1 stray capacitance of equaling the 4th on-off element T4 and independently memory capacitance sum.
The level of stage 4: the first clock signal CLKD from low to high, draw high because node Q2 voltage when stage 2-3 have passed through twice, therefore the first on-off element T1 conducting, drawn high by the high level of the first clock signal CLKD by the voltage of the output terminal of drive element of the grid.In addition, stray capacitance is there is between first control end of the first on-off element T1 and the first path terminal, therefore, in the stage 4, due to the boot strap of stray capacitance formed between first control end and the first path terminal of the first on-off element T1, the voltage of node Q2 is drawn high for the third time, thus realizes the third time pull-up to the control signal Q2 of the output of latch 10, thus make the first on-off element T1 can conducting fully further, and possesses a higher fan-out capability.
The level of stage 5: the first clock signal CLKD by high step-down, the voltage step-down of the output terminal of drive element of the grid.The level of the second clock signal that the second clock signal input end CLKA exports is uprised by low, second switch elements T 2 conducting, the voltage of the gate drive signal Gn at the corresponding levels that drive element of the grid at the corresponding levels exports is pulled down to low reference voltage VGL, due to the boot strap of stray capacitance formed between first control end and the first path terminal of the first on-off element T1, Q2 point is dragged down a part.
Stage 6: from low to high, the 6th on-off element T6 conducting, Q2 point voltage is pulled down to low reference voltage VGL to the level of the signal that pulldown signal input end Gn+2 inputs.
Stage 7: be the low level maintenance stage after the stage 7.When stage 5-6, the gate drive signal Gn at the corresponding levels that drive element of the grid at the corresponding levels exports is pulled low to low level, therefore, within the follow-up time, be i.e. the stage 7, need to make gate drive signal Gn at the corresponding levels maintain low level, thus obtains desirable waveform.
But, because the first clock signal clk D is clock signal, its within the follow-up time (namely after stage 7) also ceaselessly can produce pulse, can have an impact to the gate drive signal Gn of the output of drive element of the grid at the corresponding levels, in order to eliminate these impacts, the embodiment of the present invention utilizes on-off element T7-T9 to improve.
Particularly, within the follow-up time, when the first clock signal CLKD is by (second shown in Fig. 2 and follow-up pulse in) during low uprising, the impact of the stray capacitance between first control end of cause the first on-off element T1 and the first path terminal, the voltage at node Q2 place is driven high, and due to the impact of the second electric capacity C2, the voltage at node QB place is also driven high.By the impact of node Q2 place voltage, the first on-off element T1 conducting, the output terminal of high level to drive element of the grid at the corresponding levels of the first clock signal CLKD charges, and draws high the voltage of gate drive signal Gn at the corresponding levels.
But, because the stray capacitance between first control end of the second electric capacity C2 and the first on-off element T1 and the first path terminal is larger by comparison, therefore the voltage at node QB place is higher than the voltage at node Q2 place, now the 7th switch T7, the 8th on-off element T8 and the 9th switch T9 conducting.9th on-off element T9 conducting, Gn point voltage promptly can be pulled down to low reference voltage VGL.And the conducting of the 8th on-off element T8, the voltage of node Q2 promptly can be pulled low to low reference voltage VGL, and because Q2 point is pulled down to VGL very soon, the 7th on-off element T7 closes, and QB point can maintain a relative high voltage.Therefore, although be subject to the impact of the first clock signal clk D high level, the voltage of the output of node Q2 and drive element of the grid at the corresponding levels can be drawn high; But due to the effect of on-off element T7-T9, it can the voltage of pulling down node Q2, thus drag down the voltage of the output terminal of drive element of the grid at the corresponding levels, and then enable gate drive signal Gn at the corresponding levels maintain low level.
In like manner, when the first clock signal CLKD second and pulse subsequently by principle during high step-down with when the first clock signal CLKD is when second and pulse are subsequently by low uprising, the principle that the voltage of node Q2 and gate drive signal Gn at the corresponding levels is pulled down to low reference voltage VGL is identical, does not repeat them here.
By seeing the description of the present embodiment sequential control, the voltage of drive element of the grid to the control signal Q2 that latch 10 exports of the present embodiment has carried out the pull-up of three times, and (Gn-2 signal and Gn-1 signal realize a pull-up respectively, stray capacitance between first control end of the first on-off element T1 and the first path terminal realizes a pull-up), thus export in the time period of the gate drive signal Gn of high level (stage 4) at drive element of the grid, the control signal Q2 that latch 10 is exported keeps a very high voltage, also the first on-off element T1 is made to have stronger fan-out capability.
The lower two-stage gate drive signal Gn+2 that the drive element of the grid of the upper level gate drive signal Gn-1 that the present embodiment drive element of the grid receives upper two-stage gate drive signal Gn-2 that the drive element of the grid that upwards differs two-stage exports, the drive element of the grid that upwards differs one-level exports and downwards difference two-stage exports.Namely suppose that the present embodiment drive element of the grid is n-th grade of drive element of the grid, wherein, n >=3, its gate drive signal exported is Gn, the upper two-stage gate drive signal that the drive element of the grid then upwards differing two-stage exports is Gn-2, and the lower two-stage gate drive signal that the upper level gate drive signal that the drive element of the grid upwards differing one-level exports exports for Gn-1 and the downward drive element of the grid differing two-stage is Gn+2.
It should be noted that, under this connected mode, because first order drive element of the grid does not upwards differ the drive element of the grid of one-level, the first to second level drive element of the grid does not upwards differ the drive element of the grid of secondary, last two-stage drive element of the grid does not differ the drive element of the grid of two-stage downwards, so the upper level gate drive signal Gn-1 of first order drive element of the grid, the upper two-stage gate drive signal Gn-2 of the first to second level drive element of the grid, the lower two-stage gate drive signal Gn+2 of last two-stage drive element of the grid all will be provided by external signal circuit.
For level Four drive element of the grid, as shown in Figure 3, which describe the drive principle of the first order, the second level and last two-stage drive element of the grid, wherein, the every one-level drive element of the grid shown in Fig. 3 comprises M port, N port and P port.For the drive element of the grid for exporting gate drive signal Gn as shown in Figure 1, M port is used to receive two-stage gate drive signal Gn-2, N port is used to receive upper level gate drive signal Gn-1, and P port is used to receive lower two-stage gate drive signal Gn+2.And as shown in Figure 3, first order drive element of the grid does not upwards differ the drive element of the grid of two-stage or one-level, therefore the M port of first order drive element of the grid receives the signal that the first outside source STV1 provides, the signal that the N port accepts second outside source STV2 of first order drive element of the grid provides.Second level drive element of the grid does not upwards differ the drive element of the grid of secondary, and therefore the M port of second level drive element of the grid receives the signal that the second outside source STV2 provides.Third level drive element of the grid and fourth stage drive element of the grid do not differ the drive element of the grid of two-stage downwards, therefore the signal that provides of P port accepts the 3rd outside source STV3 of third level drive element of the grid, the signal that P port accepts the 4th outside source STV4 of fourth stage drive element of the grid provides.
Wherein, the clock signal that first to fourth grade of drive element of the grid, two of receiving that timing sequence generating circuit exports respectively are adjacent, particularly, first order drive element of the grid receives the first clock signal CLKD and the second clock signal CLKA that timing sequence generating circuit provides.The second clock signal CLKA that second level drive element of the grid reception timing sequence generating circuit provides and the 3rd clock signal CLKB.The 3rd clock signal CLKB that third level drive element of the grid reception timing sequence generating circuit provides and the 4th clock signal CLKC.The first clock signal CLKD that fourth stage drive element of the grid reception timing sequence generating circuit provides and the 4th clock signal CLKC.
Fig. 4 is the time diagram of level Four drive element of the grid as shown in Figure 3.As shown in Figure 3, the second clock signal CLKA early than the 3rd clock signal CLKB, the 3rd clock signal CLKB early than the 4th clock signal CLKC, the 4th clock signal CLKC early than the first clock signal CLKD.
Refer to Fig. 5, its gate drive signal Gn voltage-contrast schematic diagram at different ambient temperatures exported for drive element of the grid of the present invention.As shown in Figure 3, at environment temperature is-25 DEG C, 27 DEG C and 80 DEG C, the figure of the voltage of gate drive signal Gn at the corresponding levels is basically identical.
Refer to Fig. 6, it is the contrast schematic diagram of the control signal Q2 voltage at different ambient temperatures that the latch 10 in drive element of the grid of the present invention exports.As shown in Figure 4, at environment temperature is-25 DEG C, 27 DEG C and 80 DEG C, the figure of the voltage of the control signal Q2 that latch 10 exports is basically identical.
Refer to Fig. 7, it is the voltage analog result of gate drive signal Gn+1, Gn+2 and Gn+3 that the level Four drive element of the grid in the present invention exports at different ambient temperatures.As shown in Figure 5, at environment temperature is-25 DEG C, 27 DEG C and 80 DEG C, the shape of the voltage of gate drive signal Gn, Gn+1, Gn+2 and Gn+3 of the output of level Four drive element of the grid is basically identical.Therefore, as in Figure 3-5, gate driver circuit thermal adaptability of the present invention is very good, and it normally can carry out work under low temperature and hot environment.That is, drive element of the grid of the present invention can adapt to wider temperature range.
Refer to Fig. 8, it is the circuit structure diagram of drive element of the grid in prior art, 10 ' is prior art latch, wherein, relative to conventional the first on-off element T1 ' being of a size of 5200 μm in prior art drive element of the grid, the size of drive element of the grid first on-off element T1 of the present invention can be reduced to 2250 μm.
Refer to Fig. 9, the contrast schematic diagram of the voltage of its control signal exported for latch in drive element of the grid in prior art shown in the present invention and Fig. 6, wherein Q2 for environment temperature at 27 DEG C time the latch 10 of the present invention control signal that exports, Q2 ' for environment temperature at 27 DEG C time the prior art latch 10 ' control signal that exports.Can see, owing to present invention employs three grades of pull-up (prior art only has two-stage pull-up), therefore make latch 10 can export higher voltage to first control end of the first on-off element T1, thus improve the fan-out capability of the first on-off element T1.
Refer to Figure 10, it is the voltage-contrast schematic diagram of drive element of the grid output terminal at different ambient temperatures in the present invention and prior art.Wherein, Gn to be environment temperature be-20 DEG C, 27 DEG C and 80 DEG C time, the gate drive signal at the corresponding levels that drive element of the grid of the present invention exports, Gn ' for environment temperature be-20 DEG C, 27 DEG C and 80 DEG C time, the gate drive signal at the corresponding levels of prior art drive element of the grid output.Can find out, drive element of the grid of the present invention is substantially identical with the fan-out capability of the drive element of the grid of prior art at different temperatures, only on output voltage slope of a curve, there is fine distinction, that is, under drive element of the grid of the present invention can ensure to export and have the gate drive signal Gn of enough voltage, the size of the first on-off element T1 is obviously reduced.Figure 10 is the circuit structure diagram of the drive element of the grid of the embodiment of the present invention two.
Refer to Figure 11, it is that under different temperatures, in the present invention and prior art, drive element of the grid power consumption contrasts schematic diagram.Wherein the resistance of hypothesis pull-up resistor Rload is the capacitance of 1400 Ω, load capacitance Cload is 85pf.A is the analog result of 480 grades of drive element of the grid power consumptions in the present invention under different temperatures.B is the analog result of drive element of the grid 480 grades of power consumptions in prior art under different temperatures.Can find out that in the present invention, 480 grades of drive element of the grid power consumptions are significantly less than 480 grades of drive element of the grid power consumptions in prior art.
The adjustment of local can also be done to drive element of the grid, to make its structure more succinct in the present invention.
Embodiment two
Refer to Figure 12, it is the circuit structure diagram of the gate driver circuit of the embodiment of the present invention two, and compared to Figure 1 difference is, eliminates the 7th on-off element T7 in Fig. 1, the 8th on-off element T8, and increases by the tenth on-off element T10.Tenth on-off element T10 comprises the 20 path terminal, the tenth control end and the 19 path terminal, wherein the 20 path terminal is connected with first path terminal of the first on-off element T1 by the second electric capacity C2, tenth control end is connected with the output terminal of drive element of the grid, and the 19 path terminal receives low reference voltage VGL.Can be seen by the oscillogram shown in Fig. 2, the present embodiment at same time (i.e. stage 7) conducting the 9th on-off element T9, can be pulled down to low reference voltage VGL to make Gn point voltage.And make circuit more succinct after saving the 7th on-off element T7, the 8th on-off element T8.Other circuit structure of the present embodiment and principle of work are all identical with the embodiment of Fig. 1, do not repeat them here.
In sum, pole of the present invention driving circuit can export in the time period of the voltage of gate drive signal Gn at drive element of the grid, latch 10 is made to export a very high voltage to the first on-off element T1, improve the fan-out capability of the first on-off element T1, therefore under the prerequisite ensureing the gate drive signal Gn exporting enough voltage, the size of the first on-off element T1 can also be reduced further, and reduce power consumption.
Apply specific case herein to set forth gate driver circuit of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention; all will change in specific embodiments and applications; to sum up, this description should not be construed as limitation of the present invention, and protection scope of the present invention should be as the criterion with appended claim.
Claims (8)
1. a gate driver circuit, is characterized in that, comprises multistage drive element of the grid, and wherein every grade of drive element of the grid is for driving one on display panel corresponding gate line respectively, and every grade of drive element of the grid comprises:
First on-off element, comprises the first path terminal, alternate path end and the first control end, and described first path terminal receives the first clock signal, and described alternate path end is as the output terminal of described drive element of the grid;
Second switch element, comprise third path end, the 4th path terminal and the second control end, described third path termination receives low reference voltage, and described second control end receives the second clock signal, and described 4th path terminal is connected with the alternate path end of described first on-off element;
3rd on-off element, comprises five-way terminal, the 6th path terminal and the 3rd control end, and described five-way terminal and described 3rd control end are electrically connected and receive the upper two-stage gate drive signal that the drive element of the grid that upwards differs two-stage exports;
4th on-off element, comprise the 7th path terminal, the 8th path terminal and the 4th control end, described 7th path terminal receives the upper level gate drive signal that the drive element of the grid that upwards differs one-level exports, described 4th control end is connected with described 6th path terminal, and described 8th path terminal is connected with the 6th path terminal of described 3rd on-off element by the first electric capacity;
5th on-off element, comprise the 9th path terminal, the tenth path terminal and the 5th control end, described 9th path terminal and described 5th control end are all connected with the 4th control end of described 4th on-off element, and described tenth path terminal is connected with described first control end of described first on-off element; And
6th on-off element, comprise the 11 path terminal, the 12 path terminal and the 6th control end, described 11 path terminal receives described low reference voltage, the lower two-stage gate drive signal that the drive element of the grid that described 6th control end receives difference two-stage downwards exports, described 12 path terminal is connected with the tenth path terminal of described 5th on-off element.
2. gate driver circuit as claimed in claim 1, it is characterized in that, described first electric capacity is the stray capacitance of described 4th on-off element.
3. gate driver circuit as claimed in claim 1, it is characterized in that, be provided with separate, stored electric capacity between 4th control end of described 4th on-off element and the 8th path terminal, described first electric capacity is the stray capacitance of described 4th on-off element and described separate, stored electric capacity sum.
4. gate driver circuit as claimed in claim 1, is characterized in that there is the stray capacitance of the first on-off element between described first path terminal of described first on-off element and described first control end.
5. gate driver circuit as claimed in claim 4, it is characterized in that, every grade of drive element of the grid also comprises:
7th on-off element, comprises the tenth threeway terminal, the 7th control end and the 14 path terminal, and described 7th control end is connected with described first control end of described first on-off element, and described tenth three-way termination receives described low reference voltage;
8th on-off element, comprise the tenth five-way terminal, the 8th control end and the 16 path terminal, described 16 path terminal is connected with described first control end of described first on-off element, described 8th control end is connected with described 14 path terminal, and described tenth five-way terminal receives described low reference voltage;
Second electric capacity, is connected between the first path terminal of described first on-off element and described 8th control end; And
9th on-off element, comprise the 17 path terminal, the 9th control end and the 18 path terminal, described 17 path terminal receives described low reference voltage, described 9th control end is connected with described 8th control end, and described 18 path terminal is connected with described 4th path terminal of described second switch element.
6. gate driver circuit as claimed in claim 4, it is characterized in that, every grade of drive element of the grid also comprises:
Second electric capacity, one end of described second electric capacity is connected with the first path terminal of described first on-off element;
9th on-off element, comprise the 17 path terminal, the 9th control end and the 18 path terminal, described 17 path terminal receives described low reference voltage, described 9th control end is connected with the other end of described second electric capacity, and described 18 path terminal is connected with described 4th path terminal of described second switch element; Tenth on-off element, it comprises the 19 path terminal, the tenth control end and the 20 path terminal, described 19 path terminal receives described low reference voltage, described tenth control end is connected with described 4th path terminal of described second switch element, and described 20 path terminal is connected with the other end of described second electric capacity.
7. the gate driver circuit as described in claim 5 or 6, is characterized in that, the capacitance of described second electric capacity is greater than the capacitance of the stray capacitance between the first control end of described first on-off element and the first path terminal.
8. gate driver circuit as claimed in claim 1, it is characterized in that, described gate driver circuit comprises at least level Four drive element of the grid.
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| CN201310072323.7A CN103151013B (en) | 2013-03-07 | 2013-03-07 | Gate driver circuit |
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| CN201310072323.7A CN103151013B (en) | 2013-03-07 | 2013-03-07 | Gate driver circuit |
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| CN103151013B true CN103151013B (en) | 2015-11-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104575409B (en) * | 2013-10-16 | 2017-08-18 | 瀚宇彩晶股份有限公司 | Liquid crystal display and its bi-directional shift apparatus for temporary storage |
| CN103680458B (en) * | 2014-01-02 | 2016-03-30 | 昆山龙腾光电有限公司 | Gate driver circuit |
| CN104599629B (en) * | 2014-12-16 | 2017-04-19 | 上海天马有机发光显示技术有限公司 | Driving circuit, lighting control circuit, display panel and display device |
| CN104715732B (en) * | 2015-03-17 | 2017-02-01 | 昆山龙腾光电有限公司 | Grid driving circuit and display device |
| CN105185292B (en) * | 2015-10-09 | 2017-11-07 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| KR102476721B1 (en) * | 2016-06-30 | 2022-12-15 | 삼성디스플레이 주식회사 | Stage and Organic Light Emitting Display Device Using The Same |
| CN112992042B (en) * | 2021-03-01 | 2022-12-06 | 中国科学院微电子研究所 | Light-emitting drive circuit, method and display drive circuit |
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Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |