CN104766573A - Gate drive circuit and display device - Google Patents
Gate drive circuit and display device Download PDFInfo
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- CN104766573A CN104766573A CN201510104519.9A CN201510104519A CN104766573A CN 104766573 A CN104766573 A CN 104766573A CN 201510104519 A CN201510104519 A CN 201510104519A CN 104766573 A CN104766573 A CN 104766573A
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Abstract
The invention discloses a gate drive circuit. The gate drive circuit comprises a plurality of levels of gate drive units. Each level of gate drive unit comprises a first switch element to a seventeenth switch element. Each level of gate drive unit receives a first clock signal. A first stabilizing unit is formed by the tenth switch element, the twelfth switch element, the fourteenth switch element and the sixteenth switch element. A second stabilizing unit is formed by the eleventh switch element, the thirteenth switch element, the fifteenth switch element and the seventeenth switch element. The invention further provides a display device. According to the gate drive circuit and the display device using the gate drive circuit, the switch elements playing a stable role and the switch elements playing a role in outputting gate drive signals receive different clock signals, the output capability of the gate drive circuit is higher, and the gate drive circuit comprises the two stabilizing units, so that stability is high.
Description
Technical field
The present invention relates to display technique field, particularly a kind of gate driver circuit and display device.
Background technology
Liquid crystal indicator (Liquid Crystal Display, LCD) possesses the plurality of advantages such as frivolous, energy-conservation, radiationless, has therefore replaced traditional cathode-ray tube (CRT) (CRT) display gradually.Current liquid crystal display is widely used in the electronic equipments such as HD digital TV, desk-top computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera.
With thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal indicator is example, it comprises: display panels and driving circuit, wherein, display panels comprises many gate lines and a plurality of data lines, and adjacent two gate lines and adjacent two data lines intersect to form a pixel cell, each pixel cell at least comprises a thin film transistor (TFT).Driving circuit comprises gate driver circuit (gate drive circuit) and source electrode drive circuit (source drivecircuit).Along with the cost degradation pursuit of the producer to liquid crystal indicator and the raising of manufacturing process, originally the glass substrate that the driving circuit integrated chip be arranged at beyond display panels is arranged at display panels becomes possibility, such as, grid-driving integrated circuit is arranged at array base palte (Gate IC in Array, GIA) upper thus simplify the manufacture process of liquid crystal indicator, and reduce production cost.
The basic functional principle of display panels and driving circuit is: gate driver circuit is by sending gate drive signal with pulling up transistor to gate line of being electrically connected of gate line, sequentially the TFT of every a line is opened, then the pixel cell of a full line is charged to voltage required separately, to show different GTGs by source electrode drive circuit simultaneously.Namely first to be pulled up transistor by it by the gate driver circuit of the first row and the thin film transistor (TFT) of the first row opened, then charged by the pixel cell of source electrode drive circuit to the first row.When the pixel cell of the first row is charged, this row thin film transistor (TFT) just cuts out by gate driver circuit, then the gate driver circuit of the second row is pulled up transistor by it and to be opened by thin film transistor (TFT) of the second row, then carries out discharge and recharge by source electrode drive circuit to the pixel cell of the second row.So sequentially go down, when the pixel cell of substituting the bad for the good last column, just charge from the first row again.
But, for large-sized display panels, the load that its gate driver circuit drives is very large, and it is higher to the uniformity requirements of display, so just require the gate drive signal that gate driver circuit output voltage values is larger and stable, prior art generally adopts the number of the on-off element increased in gate driver circuit, electric capacity and size to solve the problems referred to above, but said method is unfavorable for the design of the narrow frame of liquid crystal indicator, and power consumption is large.
Summary of the invention
The main technical problem to be solved in the present invention is to provide a kind of gate driver circuit, and it can, while the gate drive signal that output voltage values is larger and stable, be conducive to the design of narrow frame, and power consumption be little.
For solving the problems of the technologies described above, the invention provides a kind of gate driver circuit, it comprises multiple drive element of the grid, described every grade of drive element of the grid comprises the first on-off element, second switch element, 3rd on-off element, 4th on-off element, 5th on-off element, 6th on-off element, 7th on-off element, 8th on-off element, 9th on-off element, tenth on-off element, 11 on-off element, twelvemo closes element, 13 on-off element, 14 on-off element, 15 on-off element, sixteenmo closes element, 17 on-off element.
Wherein, the first on-off element comprises the first path terminal, the first control end, alternate path end, and described first path terminal receives with reference to high voltage, and described first control end receives the first pulse signal.Second switch element comprises third path end, the second control end, the 4th path terminal, described third path termination receives the first clock signal, described second control end is connected with the alternate path end of described first on-off element, and be connected with described 4th path terminal by the first electric capacity, described 4th path terminal is the output terminal of every grade of drive element of the grid.3rd on-off element comprises five-way terminal, the 3rd control end, the 6th path terminal, described five-way terminal is connected with the alternate path end of described first on-off element, described 3rd control end receives the second pulse signal, and the 6th path terminal receives the first low reference voltage.4th on-off element comprises the 7th path terminal, the 4th control end, the 8th path terminal, the second low reference voltage that described 7th path terminal receives, and described 4th control end receives described second pulse signal.5th on-off element comprises the 9th path terminal, the 5th control end, the tenth path terminal, and described 9th path terminal receives described second low reference voltage, and described 5th control end receives described second pulse signal.6th on-off element comprises the 11 path terminal, the 6th control end, the 12 path terminal, described 11 path terminal receives described second low reference voltage, described 6th control end is connected with the second control end of described first on-off element, and the 12 path terminal is connected with the 8th path terminal of described 4th on-off element.
7th on-off element comprises the tenth threeway terminal, the 7th control end, the 14 path terminal, described tenth three-way termination receives described second low reference voltage, described 7th control end is connected with the second control end of described first on-off element, and described 14 path terminal is connected with the tenth path terminal of described 5th on-off element.8th on-off element comprises the tenth five-way terminal, the 8th control end, the 16 path terminal, described tenth five-way terminal is connected with the 8th path terminal of described 4th on-off element, described 8th control end receives described first pulse signal, and described 16 path terminal receives described second low reference voltage.9th on-off element comprises the 17 path terminal, the 9th control end, the 18 path terminal, described 17 path terminal is connected with the tenth path terminal of described 5th on-off element, described 9th control end receives described first pulse signal, and described 18 path terminal receives described second low reference voltage.Tenth on-off element comprises the 19 path terminal, the tenth control end, the 20 path terminal, and described 19 path terminal and described tenth control end receive the first stabilization signal, and described 20 path terminal is connected with the 8th path terminal of described 4th on-off element.11 on-off element comprises the 21 path terminal, the 11 control end, the 22 path terminal, described 21 path terminal is connected with the tenth path terminal of described 5th on-off element, and described 11 control end and described 22 path terminal receive the second stabilization signal.Twelvemo is closed element and is comprised the 20 threeway terminal, the 12 control end, the 24 path terminal, described 20 three-way termination receives described second low reference voltage, described 12 control end receives described first stabilization signal, and described 24 path terminal is connected with the 21 path terminal of described 11 on-off element.And the 13 on-off element comprise the 20 five-way terminal, the 13 control end, the 26 path terminal, described 20 five-way terminal is connected with the 20 path terminal of described tenth on-off element, described 13 control end receives described second stabilization signal, and described 26 path terminal receives described second low reference voltage.14 on-off element comprises Twenty-seven lines go side, the 14 control end, the 28 path terminal, described 27 path terminal is connected with the alternate path end of described first on-off element, described 14 control end is connected with the 20 path terminal of described tenth on-off element, and described 28 path terminal receives described second low reference voltage.
15 on-off element comprises the 29 path terminal, the 15 control end, the 30 path terminal, described 29 path terminal receives described second low reference voltage, described 15 control end is connected with the 21 path terminal of described 11 on-off element, and described 30 path terminal is connected with the alternate path end of described first on-off element.Sixteenmo closes element and comprises the 31 path terminal, the 16 control end, the 32 path terminal, described 31 path terminal is connected with the 4th path terminal of described second switch element, described 16 control end is connected with the 20 path terminal of described tenth on-off element, and described 32 path terminal receives described second low reference voltage.17 on-off element comprises the 30 threeway terminal, the 17 control end, the 34 path terminal, described 30 three-way termination receives described second low reference voltage, described 17 control end is connected with the 21 path terminal of described 11 on-off element, and described 34 path terminal is connected with the 4th path terminal of described second switch element.
Preferably, described first electric capacity is the stray capacitance between the 4th path terminal of described second switch element and the second control end.
Preferably, be provided with separate, stored electric capacity between second control end of described second switch element and the 4th path terminal, described first electric capacity is stray capacitance between the 4th path terminal of described second switch element and the second control end and described separate, stored electric capacity sum.
Preferably, if described drive element of the grid is n-th grade of drive element of the grid, the first pulse signal that then the first control end of described first on-off element receives is upper three grades of gate drive signals that the drive element of the grid upwards differing three grades with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=4.
Preferably, if described gate driver circuit comprises N level drive element of the grid, the second pulse signal that then the 3rd control end of described 3rd on-off element of n-th grade of drive element of the grid receives is lower three grades of gate drive signals that the drive element of the grid differing three grades with n-th grade of drive element of the grid downwards exports, wherein, n is integer, and 0≤n≤N-3.
Preferably, described first stabilization signal and described second stabilization signal are alternately high level.
Preferably, described first stabilization signal and described second stabilization signal are clock signal, and the dutycycle of described first stabilization signal and described second stabilization signal is 50 percent.
Preferably, the dutycycle of described first clock signal is 1/3rd, and the high level time of described first clock signal is 1/2nd of the high level time of described first stabilization signal and described second stabilization signal.
Preferably, described first on-off element to described 17 on-off element is N-type transistor.
The present invention also provides a kind of display device, described display device comprises gate driver circuit, gate driver circuit comprises multiple drive element of the grid, described every grade of drive element of the grid comprises the first on-off element, second switch element, 3rd on-off element, 4th on-off element, 5th on-off element, 6th on-off element, 7th on-off element, 8th on-off element, 9th on-off element, tenth on-off element, 11 on-off element, twelvemo closes element, 13 on-off element, 14 on-off element, 15 on-off element, sixteenmo closes element, 17 on-off element.
Wherein, the first on-off element comprises the first path terminal, the first control end, alternate path end, and described first path terminal receives with reference to high voltage, and described first control end receives the first pulse signal.Second switch element comprises third path end, the second control end, the 4th path terminal, described third path termination receives the first clock signal, described second control end is connected with the alternate path end of described first on-off element, and is connected with described 4th path terminal by the first electric capacity.3rd on-off element comprises five-way terminal, the 3rd control end, the 6th path terminal, described five-way terminal is connected with the alternate path end of described first on-off element, described 3rd control end receives the second pulse signal, and the 6th path terminal receives the first low reference voltage.4th on-off element comprises the 7th path terminal, the 4th control end, the 8th path terminal, the second low reference voltage that described 7th path terminal receives, and described 4th control end receives described second pulse signal.5th on-off element comprises the 9th path terminal, the 5th control end, the tenth path terminal, and described 9th path terminal receives described second low reference voltage, and described 5th control end receives described second pulse signal.6th on-off element comprises the 11 path terminal, the 6th control end, the 12 path terminal, described 11 path terminal receives described second low reference voltage, described 6th control end is connected with the second control end of described first on-off element, and the 12 path terminal is connected with the 8th path terminal of described 4th on-off element.
7th on-off element comprises the tenth threeway terminal, the 7th control end, the 14 path terminal, described tenth three-way termination receives described second low reference voltage, described 7th control end is connected with the second control end of described first on-off element, and described 14 path terminal is connected with the tenth path terminal of described 5th on-off element.8th on-off element comprises the tenth five-way terminal, the 8th control end, the 16 path terminal, described tenth five-way terminal is connected with the 8th path terminal of described 4th on-off element, described 8th control end receives described first pulse signal, and described 16 path terminal receives described second low reference voltage.9th on-off element comprises the 17 path terminal, the 9th control end, the 18 path terminal, described 17 path terminal is connected with the tenth path terminal of described 5th on-off element, described 9th control end receives described first pulse signal, and described 18 path terminal receives described second low reference voltage.Tenth on-off element comprises the 19 path terminal, the tenth control end, the 20 path terminal, and described 19 path terminal and described tenth control end receive the first stabilization signal, and described 20 path terminal is connected with the 8th path terminal of described 4th on-off element.11 on-off element comprises the 21 path terminal, the 11 control end, the 22 path terminal, described 21 path terminal is connected with the tenth path terminal of described 5th on-off element, and described 11 control end and described 22 path terminal receive the second stabilization signal.Twelvemo is closed element and is comprised the 20 threeway terminal, the 12 control end, the 24 path terminal, described 20 three-way termination receives described second low reference voltage, described 12 control end receives described first stabilization signal, and described 24 path terminal is connected with the 21 path terminal of described 11 on-off element.13 on-off element comprises the 20 five-way terminal, the 13 control end, the 26 path terminal, described 20 five-way terminal is connected with the 20 path terminal of described tenth on-off element, described 13 control end receives described second stabilization signal, and described 26 path terminal receives described second low reference voltage.14 on-off element comprises Twenty-seven lines go side, the 14 control end, the 28 path terminal, described 27 path terminal is connected with the alternate path end of described first on-off element, described 14 control end is connected with the 20 path terminal of described tenth on-off element, and described 28 path terminal receives described second low reference voltage.
15 on-off element comprises the 29 path terminal, the 15 control end, the 30 path terminal, described 29 path terminal receives described second low reference voltage, described 15 control end is connected with the 21 path terminal of described 11 on-off element, and described 30 path terminal is connected with the alternate path end of described first on-off element.Sixteenmo closes element and comprises the 31 path terminal, the 16 control end, the 32 path terminal, described 31 path terminal is connected with the 4th path terminal of described second switch element, described 16 control end is connected with the 20 path terminal of described tenth on-off element, and described 32 path terminal receives described second low reference voltage.17 on-off element comprises the 30 threeway terminal, the 17 control end, the 34 path terminal, described 30 three-way termination receives described second low reference voltage, described 17 control end is connected with the 21 path terminal of described 11 on-off element, and described 34 path terminal is connected with the 4th path terminal of described second switch element.
Preferably, described first electric capacity is the stray capacitance between the 4th path terminal of described second switch element and the second control end.
Preferably, be provided with separate, stored electric capacity between second control end of described second switch element and the 4th path terminal, described first electric capacity is stray capacitance between the 4th path terminal of described second switch element and the second control end and described separate, stored electric capacity sum.
Preferably, if described drive element of the grid is n-th grade of drive element of the grid, the first pulse signal that then the first control end of described first on-off element receives is upper three grades of gate drive signals that the drive element of the grid upwards differing three grades with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=4.
Preferably, if described gate driver circuit comprises N level drive element of the grid, the second pulse signal that then the 3rd control end of described 3rd on-off element of n-th grade of drive element of the grid receives is lower three grades of gate drive signals that the drive element of the grid differing three grades with n-th grade of drive element of the grid downwards exports, wherein, n is integer, and 0≤n≤N-3.
Preferably, described first stabilization signal and described second stabilization signal are alternately high level.
Preferably, described first stabilization signal and described second stabilization signal are clock signal, and the dutycycle of described first stabilization signal and described second stabilization signal is 50 percent.
Preferably, the dutycycle of described first clock signal is 1/3rd, and the high level time of described first clock signal is 1/2nd of the high level time of described first stabilization signal and described second stabilization signal.
Preferably, described first on-off element to described 17 on-off element is N-type transistor.
Gate driver circuit of the present invention and use its display device, and the on-off element (the tenth on-off element is to the 17 on-off element) playing stabilization receives different signals with the on-off element (second switch element) exporting gate drive signal, make the fan-out capability of gate driver circuit strong, and gate driver circuit comprises two stabilization elements (the tenth on-off element, twelvemo closes element, 14 on-off element, sixteenmo closes element and forms the first stabilization element, 11 on-off element, 13 on-off element, 15 on-off element, 17 on-off element forms the second stabilization element), good stability.
By the detailed description below with reference to accompanying drawing, other side of the present invention and feature become obvious.But it should be known that accompanying drawing is only the object design of explanation, instead of as the restriction of scope of the present invention, this is because it should with reference to additional claim.Should also be appreciated that, unless otherwise noted, unnecessaryly draw accompanying drawing to scale, they only try hard to structure described herein and flow process are described conceptually.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 2 is the time diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 3 is the electrical block diagram of six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 4 is the time diagram that six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention realize forward scan.
Fig. 5 is the time diagram that six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention realize reverse scan.
Fig. 6 is the analog result schematic diagram of the first order drive element of the grid output signal at three temperatures in the gate driver circuit of first embodiment of the invention.
Fig. 7 is the analog result schematic diagram of the output signal of the 120 grade of drive element of the grid under three kinds of environment temperatures in the gate driver circuit of first embodiment of the invention.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to its embodiment of display panels proposed according to the present invention, method, step, structure, feature and effect, be described in detail as follows.
Aforementioned and other technology contents, feature and effect for the present invention, can clearly present in the detailed description of following cooperation with reference to graphic preferred embodiment.By the explanation of embodiment, when can to the present invention for the technological means reaching predetermined object and take and effect be able to more deeply and concrete understanding, however institute's accompanying drawings be only to provide with reference to and the use of explanation, be not used for being limited the present invention.
Although the present invention uses first, second, third, etc. term to describe different elements, signal, port, assembly or part, these elements, signal, port, assembly or part be not by the restriction of these terms.These terms are only used to an element, signal, port, assembly or part and another element, signal, port, assembly or part to make a distinction.In the present invention, element, port, assembly or a part and another element, port, assembly or part " being connected ", " connection ", can be understood as direct electric connection, or also can be understood as the indirect electric connection that there is intermediary element.Unless otherwise defined, otherwise all terms used in the present invention (comprising technical term and scientific terminology) have the meaning usually understood with those skilled in the art.
Gate driver circuit of the present invention (also referred to as shift register) comprises multistage drive element of the grid (also referred to as shifting deposit unit), the drive element of the grid of every one-level is corresponding with the every a line gate line on display panel to be respectively electrically connected, thus gate drive signal is sequentially successively applied to often on row gate line, the annexation between drive element of the grid will elaborate hereinafter.
Fig. 1 is the electrical block diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.The present embodiment gate driver circuit, comprises multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid for exporting gate drive signal Gn, to drive on display panel corresponding gate line respectively.As shown in Figure 1, every grade of drive element of the grid comprises the first on-off element M1, second switch element M2, the 3rd on-off element M3, the 4th on-off element M4, the 5th on-off element M5, the 6th on-off element M6, the 7th on-off element M7, the 8th on-off element M8, the 9th on-off element M9, the tenth on-off element M10, the 11 on-off element M11, twelvemo pass element M12, the 13 on-off element M13, the 14 on-off element M14, the 15 on-off element M15, sixteenmo pass element M16 and the 17 on-off element M17.
Wherein, the first on-off element M1 comprises the first path terminal, the first control end, alternate path end, and the first path terminal receives with reference to high voltage VDD, and the first control end receives the first pulse signal.Second switch element M2 comprises third path end, the second control end, the 4th path terminal, third path termination receives the first clock signal clk, second control end is connected with the alternate path end of the first on-off element M1, and be connected with the 4th path terminal by the first electric capacity, the 4th path terminal is for exporting gate drive signal Gn at the corresponding levels.3rd on-off element M3 comprises five-way terminal, the 3rd control end, the 6th path terminal, and five-way terminal is connected with the alternate path end of the first on-off element M1, and the 3rd control end receives the second pulse signal, and the 6th path terminal receives the first low reference voltage VSS.4th on-off element M4 comprises the 7th path terminal, the 4th control end, the 8th path terminal, the second low reference voltage VGL that the 7th path terminal receives, and the 4th control end receives the second pulse signal.5th on-off element M5 comprises the 9th path terminal, the 5th control end, the tenth path terminal, and the 9th path terminal receives the second low reference voltage VGL, and the 5th control end receives the second pulse signal.6th on-off element M6 comprises the 11 path terminal, the 6th control end, the 12 path terminal, 11 path terminal receives the second low reference voltage VGL, 6th control end is connected with second control end of the first on-off element M1, and the 12 path terminal is connected with the 8th path terminal of the 4th on-off element M4.
7th on-off element M7 comprises the tenth threeway terminal, the 7th control end, the 14 path terminal, tenth three-way termination receives the second low reference voltage VGL, 7th control end is connected with second control end of the first on-off element M1, and the 14 path terminal is connected with the tenth path terminal of the 5th on-off element M5.8th on-off element M8 comprises the tenth five-way terminal, the 8th control end, the 16 path terminal, tenth five-way terminal is connected with the 8th path terminal of the 4th on-off element M4,8th control end receives the first pulse signal, and the 16 path terminal receives the second low reference voltage VGL.9th on-off element M9 comprises the 17 path terminal, the 9th control end, the 18 path terminal, 17 path terminal is connected with the tenth path terminal of the 5th on-off element M5,9th control end receives the first pulse signal, and the 18 path terminal receives the second low reference voltage VGL.Tenth on-off element M10 comprises the 19 path terminal, the tenth control end, the 20 path terminal, and the 19 path terminal and the tenth control end receive the first stabilization signal V1, and the 20 path terminal is connected with the 8th path terminal of the 4th on-off element M4.11 on-off element M11 comprises the 21 path terminal, the 11 control end, the 22 path terminal, 21 path terminal is connected with the tenth path terminal of the 5th on-off element M5, and the 11 control end and the 22 path terminal receive the second stabilization signal V2.Twelvemo is closed element M12 and is comprised the 20 threeway terminal, the 12 control end, the 24 path terminal, 20 three-way termination receives the second low reference voltage VGL, 12 control end receives the first stabilization signal V1, and the 24 path terminal is connected with the 21 path terminal of the 11 on-off element M11.13 on-off element M13 comprises the 20 five-way terminal, the 13 control end, the 26 path terminal, 20 five-way terminal is connected with the 20 path terminal of the tenth on-off element M10,13 control end receives the second stabilization signal V2, and the 26 path terminal receives the second low reference voltage VGL.14 on-off element M14 comprises Twenty-seven lines go side, the 14 control end, the 28 path terminal, 27 path terminal is connected with the alternate path end of the first on-off element M1,14 control end is connected with the 20 path terminal of the tenth on-off element M10, and the 28 path terminal receives the second low reference voltage VGL.
15 on-off element M15 comprises the 29 path terminal, the 15 control end, the 30 path terminal, 29 path terminal receives the second low reference voltage VGL, 15 control end is connected with the 21 path terminal of the 11 on-off element M11, and the 30 path terminal is connected with the alternate path end of the first on-off element M1.Sixteenmo closes element M16 and comprises the 31 path terminal, the 16 control end, the 32 path terminal, 31 path terminal is connected with the 4th path terminal of second switch element M2,16 control end is connected with the 20 path terminal of the tenth on-off element M10, and the 32 path terminal receives the second low reference voltage VGL.17 on-off element M17 comprises the 30 threeway terminal, the 17 control end, the 34 path terminal, 30 three-way termination receives the second low reference voltage VGL, 17 control end is connected with the 21 path terminal of the 11 on-off element M11, and the 34 path terminal is connected with the 4th path terminal of second switch element M2.
Wherein, tenth on-off element M10, twelvemo close element M12, the 14 on-off element M14, sixteenmo closes element M16 and forms the first stabilization element, and the 11 on-off element M11, the 13 on-off element M13, the 15 on-off element M15, the 17 on-off element M17 form the second stabilization element.
Wherein, the first electric capacity C1 is the stray capacitance between the 4th path terminal of second switch element M2 and the second control end.What certainly it will be appreciated by those skilled in the art that is, also separate, stored electric capacity can be set between second control end of second switch element M2 and the 4th path terminal, now, the first electric capacity C1 is stray capacitance between the 4th path terminal of second switch element M2 and the second control end and separate, stored electric capacity sum.
In an embodiment of the present invention, if drive element of the grid is n-th grade of drive element of the grid, and its gate drive signal exported is Gn, the first pulse signal that then first control end of the first on-off element M1 receives is upper three grades of gate drive signal Gn-3 that drive element of the grid i.e. the n-th-3 grades drive element of the grid upwards differing three grades with n-th grade of drive element of the grid export, wherein, n is integer, and n >=4.
In an embodiment of the present invention, if gate driver circuit comprises N level drive element of the grid, the second pulse signal that then the 5th control end of the 3rd control end of the 3rd on-off element M3 of n-th grade of drive element of the grid, the 4th control end of the 4th on-off element M4 and the 5th on-off element receives is lower three grades of gate drive signal Gn+3 that drive element of the grid i.e. the n-th+3 grades drive element of the grid of differing three grades downwards with n-th grade of drive element of the grid export, wherein, n is integer, and 0≤n≤N-3.
It should be noted that, because first order drive element of the grid, second level drive element of the grid and third level drive element of the grid upwards do not differ the drive element of the grid of three grades, last three grades of drive element of the grid do not differ the drive element of the grid of three grades downwards, so the first pulse signal that first order drive element of the grid, second level drive element of the grid and third level drive element of the grid receive, the second pulse signal that last three grades of drive element of the grid receive all will be provided by external signal circuit.
In the present embodiment, the first on-off element is N-type transistor to the 17 on-off element M1 ~ M17.First control end is grid to the 13 control end.First path terminal of the first on-off element M1, the third path end of second switch element M2, the five-way terminal of the 3rd on-off element M3, 7th path terminal of the 4th on-off element M4, 9th path terminal of the 5th on-off element M5, 11 path terminal of the 6th on-off element M6, the tenth threeway terminal of the 7th on-off element M7, the tenth five-way terminal of the 8th on-off element M8, 17 path terminal of the 9th on-off element M9, 19 path terminal of the tenth on-off element M10, 21 path terminal of the 11 on-off element M11, twelvemo closes the 20 threeway terminal of element M12, the 20 five-way terminal of the 13 on-off element M13, 27 path terminal of the 14 on-off element M14, 29 path terminal of the 15 on-off element M15, sixteenmo closes the 31 path terminal of element M16, the 30 threeway terminal of the 17 on-off element M17 is drain electrode.The alternate path end of the first on-off element M1, 4th path terminal of second switch element M2, 6th path terminal of the 3rd on-off element M3, 8th path terminal of the 4th on-off element M4, tenth path terminal of the 5th on-off element M5, 12 path terminal of the 6th on-off element M6, 14 path terminal of the 7th on-off element M7, 16 path terminal of the 8th on-off element M8, 18 path terminal of the 9th on-off element M9, 20 path terminal of the tenth on-off element M10, 22 path terminal of the 11 on-off element M11, twelvemo closes the 24 path terminal of element M12, 26 path terminal of the 13 on-off element M13, 28 path terminal of the 14 on-off element M14, 30 path terminal of the 15 on-off element M15, sixteenmo closes the 32 path terminal of element M16, 34 path terminal of the 17 on-off element M17 is source electrode.
Certainly, it will be appreciated by persons skilled in the art that the first on-off element can adopt the on-off elements such as such as non-crystalline silicon tft, oxide TFT or low temperature polycrystalline silicon N-TFT to the 17 on-off element M1 ~ M17 and realize.Below for the first on-off element M1 to the 17 on-off element M1 ~ M17 for N-type transistor introduces the specific embodiment of the present invention and principle of work thereof particularly.
Refer to Fig. 2, it is the time diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.As shown in Figure 2, the first stabilization signal V1 and the second stabilization signal V2 is alternately high level, that is, when the first stabilization signal V1 is high level, second stabilization signal V2 is low level, and when the first stabilization signal V1 is low level, the second stabilization signal V2 is high level.
In an embodiment of the present invention, the first stabilization signal V1 and the second stabilization signal V2 is clock signal, and the dutycycle of the first stabilization signal V1 and the second stabilization signal V2 is 50 percent.
In an embodiment of the present invention, the dutycycle of the first clock signal clk is 1/3rd, and the high level time of the first clock signal clk is 1/2nd of the high level time of the first stabilization signal V1 and the second stabilization signal V2.
The course of work of every one-level drive element of the grid is divided into pre-charging stage, pull-up stage, drop-down stage, 4 stages of stabilization sub stage:
Pre-charging stage and first stage: first control end of the first on-off element M1, upper three grades of gate drive signal Gn-3 that the drive element of the grid that namely the first pulse signal that 8th control end of the 8th on-off element M8 and the 9th control end of the 9th on-off element M9 receive upwards differs three grades exports are high level, first on-off element M1, 8th on-off element M8 and the 9th on-off element M9 conducting, the voltage at node Q place passes through the first on-off element M1 referenced high voltage VDD precharge of conducting, the voltage at node QB1 place is pulled low to the second low reference voltage VGL by the 8th on-off element M8 of conducting, the voltage at node QB2 place is pulled low to the second low reference voltage VGL by the 9th on-off element M9 of conducting, in addition, because the voltage at node Q place is precharged, 6th on-off element M6 and the 7th on-off element M7 conducting, the voltage at node QB1 and node QB2 place is pulled low to the second low reference voltage VGL respectively by the 6th on-off element M6 of conducting and the 7th on-off element M7.
Pull-up stage and subordinate phase: when the level of the first clock signal clk is by low uprising, owing to being precharged at pre-charging stage node Q, therefore, second switch element M2 conducting, due to the conducting of second switch element M2, and due to the boot strap of the first electric capacity C1, the voltage at node Q place is drawn high further, and the drawing high further of node Q place's voltage, make second switch element M2 conductively more abundant, thus the gate drive signal Gn at the corresponding levels making the output terminal of drive element of the grid at the corresponding levels export is drawn high by the first clock signal clk by the second switch element M2 of conducting.
It should be noted that, in the present invention, can directly adopt stray capacitance between the 4th path terminal of second switch element M2 and the second control end as the first electric capacity C1, or in order to promote pull-up effect, separate, stored electric capacity can also be set between second control end of second switch element M2 and the 4th path terminal, wherein, the parasitic capacitance in parallel of this separate, stored electric capacity and second switch element M2 is also common as the first electric capacity C1, namely the first electric capacity C1 equals stray capacitance between the 4th path terminal of second switch element M2 and the second control end and separate, stored electric capacity sum.
Drop-down stage and phase III: the first clock signal clk becomes low level from high level, due to being drawn high further at pull-up stage node Q place's voltage, second switch element M2 is in conducting state, and the gate drive signal Gn that the output terminal of drive element of the grid at the corresponding levels exports is dragged down by the first clock signal clk by the second switch element M2 of conducting; Meanwhile, due to the boot strap of the first electric capacity C1, the voltage at node Q place is also dragged down; In addition, when the gate drive signal Gn+3 of lower three grades of the drive element of the grid output of difference three grades downwards becomes high level from low level, 3rd on-off element M3 conducting, the voltage at node Q place is pulled low to the first low reference voltage VSS by the 3rd on-off element M3 of conducting.
Stabilization sub stage and fourth stage: because the first stabilization signal V1 and the second stabilization signal V2 is alternately high level, therefore, node QB1 and node QB2 is alternately high level, therefore, 4th on-off element M4 and the 5th on-off element M5 alternate conduction, thus make the voltage at node Q place be pulled low to the second low reference voltage VGL by the 14 on-off element M14 of conducting or the 15 on-off element M15 of conducting, in addition, sixteenmo closes element M16 and the 17 on-off element M17 also alternate conduction, thus the 17 on-off element M17 making gate drive signal Gn close element M16 or conducting by the sixteenmo of conducting is pulled low to the second low reference voltage VGL.
For six grades of drive element of the grid, as shown in Figure 3, which describe the drive principle of first order drive element of the grid R1, second level drive element of the grid R2, third level drive element of the grid R3, fourth stage drive element of the grid R4, level V drive element of the grid R5, the 6th grade of drive element of the grid R6, wherein, every one-level drive element of the grid shown in Fig. 3 is for receiving the upper two-stage gate drive signal Gn-3 of the drive element of the grid output upwards differing three grades, and the lower two-stage gate drive signal Gn+3 of the drive element of the grid output of difference three grades downwards.And as shown in Figure 3, first order drive element of the grid R1, second level drive element of the grid R2 and third level drive element of the grid R3 upwards do not differ the drive element of the grid of three grades, therefore, first order drive element of the grid R1 receives signal that the first outside source STV1 provides as the first pulse signal, second grid driver element R2 receive signal that the second outside source STV2 provides as the first pulse signal, the 3rd drive element of the grid R3 receives signal that the 3rd outside source STV3 provides as the first pulse signal.Fourth stage drive element of the grid R4, level V drive element of the grid R5 and the 6th grade of drive element of the grid R6 differ the drive element of the grid of three grades downwards, therefore, the signal that 4th drive element of the grid R4 reception the 4th outside source STV4 provides is as the second pulse signal, the signal that level V drive element of the grid R5 reception the 5th outside source STV5 provides is as the second pulse signal, and the signal that the 6th drive element of the grid R6 reception the 6th outside source STV6 provides is as the second pulse signal.
Fig. 4 is the time diagram that six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention realize forward scan.Please also refer to Fig. 3 and Fig. 4, first order drive element of the grid R1, second level drive element of the grid R2, third level drive element of the grid R3, fourth stage drive element of the grid R4, level V drive element of the grid R5, first pulse signal and first clock signal clk of the 6th grade of drive element of the grid R6 reception become high level from low level successively, therefore first order drive element of the grid R1, second level drive element of the grid R2, third level drive element of the grid R3, fourth stage drive element of the grid R4, level V drive element of the grid R5, 6th grade of drive element of the grid R6 exports gate drive signal Gn successively, thus drive corresponding gate line successively, to realize forward scan.
Fig. 5 is the time diagram that six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention realize reverse scan.Please also refer to Fig. 3 and as Fig. 5, 6th grade of drive element of the grid R6, level V drive element of the grid R5, fourth stage drive element of the grid R4, third level drive element of the grid R3, second level drive element of the grid R2, the first pulse signal that first order drive element of the grid R1 receives and the first clock signal clk become high level from low level successively, therefore the 6th grade of drive element of the grid R6, level V drive element of the grid R5, fourth stage drive element of the grid R4, third level drive element of the grid R3, second level drive element of the grid R2, first order drive element of the grid R1 exports gate drive signal Gn successively, thus realize reverse scan.
Fig. 6 is the analog result schematic diagram of the first order drive element of the grid output signal at three temperatures in the gate driver circuit of first embodiment of the invention.Fig. 7 is the analog result schematic diagram of the output signal of the 120 grade of drive element of the grid under three kinds of environment temperatures in the gate driver circuit of first embodiment of the invention.As shown in Figure 6,1., 2., 3. represent that first order drive element of the grid is at subzero 20 degrees Celsius, the gate drive signal that exports under normal temperature and under 70 degrees Celsius respectively, as shown in Figure 7,4., 5., 6. represent that the 120 grade of drive element of the grid is at subzero 20 degrees Celsius, the gate drive signal that exports under normal temperature and under 70 degrees Celsius respectively.Please also refer to Fig. 6 and Fig. 7, the first order drive element of the grid of gate driver circuit of the present invention subzero 20 degrees Celsius, all can the gate drive signal of stable output under normal temperature and under 70 degrees Celsius, 120 grade of drive element of the grid subzero 20 degrees Celsius, all can the gate drive signal of stable output under normal temperature and under 70 degrees Celsius, therefore gate driver circuit of the present invention can all can the gate drive signal of stable output under different environment temperatures.
The present invention also provides a kind of display device, it comprises gate driver circuit, gate driver circuit comprises multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid for exporting gate drive signal Gn, to drive on display panel corresponding gate line respectively.As shown in Figure 1, every grade of drive element of the grid comprises the first on-off element M1, second switch element M2, the 3rd on-off element M3, the 4th on-off element M4, the 5th on-off element M5, the 6th on-off element M6, the 7th on-off element M7, the 8th on-off element M8, the 9th on-off element M9, the tenth on-off element M10, the 11 on-off element M11, twelvemo pass element M12, the 13 on-off element M13, the 14 on-off element M14, the 15 on-off element M15, sixteenmo pass element M16 and the 17 on-off element M17.
Wherein, the first on-off element M1 comprises the first path terminal, the first control end, alternate path end, and the first path terminal receives with reference to high voltage VDD, and the first control end receives the first pulse signal.Second switch element M2 comprises third path end, the second control end, the 4th path terminal, third path termination receives the first clock signal clk, second control end is connected with the alternate path end of the first on-off element M1, and be connected with the 4th path terminal by the first electric capacity, the 4th path terminal is for exporting gate drive signal Gn at the corresponding levels.3rd on-off element M3 comprises five-way terminal, the 3rd control end, the 6th path terminal, and five-way terminal is connected with the alternate path end of the first on-off element M1, and the 3rd control end receives the second pulse signal, and the 6th path terminal receives the first low reference voltage VSS.4th on-off element M4 comprises the 7th path terminal, the 4th control end, the 8th path terminal, the second low reference voltage VGL that the 7th path terminal receives, and the 4th control end receives the second pulse signal.5th on-off element M5 comprises the 9th path terminal, the 5th control end, the tenth path terminal, and the 9th path terminal receives the second low reference voltage VGL, and the 5th control end receives the second pulse signal.6th on-off element M6 comprises the 11 path terminal, the 6th control end, the 12 path terminal, 11 path terminal receives the second low reference voltage VGL, 6th control end is connected with second control end of the first on-off element M1, and the 12 path terminal is connected with the 8th path terminal of the 4th on-off element M4.
7th on-off element M7 comprises the tenth threeway terminal, the 7th control end, the 14 path terminal, tenth three-way termination receives the second low reference voltage VGL, 7th control end is connected with second control end of the first on-off element M1, and the 14 path terminal is connected with the tenth path terminal of the 5th on-off element M5.8th on-off element M8 comprises the tenth five-way terminal, the 8th control end, the 16 path terminal, tenth five-way terminal is connected with the 8th path terminal of the 4th on-off element M4,8th control end receives the first pulse signal, and the 16 path terminal receives the second low reference voltage VGL.9th on-off element M9 comprises the 17 path terminal, the 9th control end, the 18 path terminal, 17 path terminal is connected with the tenth path terminal of the 5th on-off element M5,9th control end receives the first pulse signal, and the 18 path terminal receives the second low reference voltage VGL.Tenth on-off element M10 comprises the 19 path terminal, the tenth control end, the 20 path terminal, and the 19 path terminal and the tenth control end receive the first stabilization signal V1, and the 20 path terminal is connected with the 8th path terminal of the 4th on-off element M4.11 on-off element M11 comprises the 21 path terminal, the 11 control end, the 22 path terminal, 21 path terminal is connected with the tenth path terminal of the 5th on-off element M5, and the 11 control end and the 22 path terminal receive the second stabilization signal V2.Twelvemo is closed element M12 and is comprised the 20 threeway terminal, the 12 control end, the 24 path terminal, 20 three-way termination receives the second low reference voltage VGL, 12 control end receives the first stabilization signal V1, and the 24 path terminal is connected with the 21 path terminal of the 11 on-off element M11.13 on-off element M13 comprises the 20 five-way terminal, the 13 control end, the 26 path terminal, 20 five-way terminal is connected with the 20 path terminal of the tenth on-off element M10,13 control end receives the second stabilization signal V2, and the 26 path terminal receives the second low reference voltage VGL.14 on-off element M14 comprises Twenty-seven lines go side, the 14 control end, the 28 path terminal, 27 path terminal is connected with the alternate path end of the first on-off element M1,14 control end is connected with the 20 path terminal of the tenth on-off element M10, and the 28 path terminal receives the second low reference voltage VGL.
15 on-off element M15 comprises the 29 path terminal, the 15 control end, the 30 path terminal, 29 path terminal receives the second low reference voltage VGL, 15 control end is connected with the 21 path terminal of the 11 on-off element M11, and the 30 path terminal is connected with the alternate path end of the first on-off element M1.Sixteenmo closes element M16 and comprises the 31 path terminal, the 16 control end, the 32 path terminal, 31 path terminal is connected with the 4th path terminal of second switch element M2,16 control end is connected with the 20 path terminal of the tenth on-off element M10, and the 32 path terminal receives the second low reference voltage VGL.17 on-off element M17 comprises the 30 threeway terminal, the 17 control end, the 34 path terminal, 30 three-way termination receives the second low reference voltage VGL, 17 control end is connected with the 21 path terminal of the 11 on-off element M11, and the 34 path terminal is connected with the 4th path terminal of second switch element M2.
Wherein, tenth on-off element M10, twelvemo close element M12, the 14 on-off element M14, sixteenmo closes element M16 and forms the first stabilization element, and the 11 on-off element M11, the 13 on-off element M13, the 15 on-off element M15, the 17 on-off element M17 form the second stabilization element.
Gate driver circuit of the present invention and use its display device, and the on-off element (the tenth on-off element is to the 17 on-off element M10 ~ M17) playing stabilization receives different signals with the on-off element (second switch element M2) exporting gate drive signal, make the fan-out capability of gate driver circuit strong, and gate driver circuit comprises two stabilization elements (the tenth on-off element M10, twelvemo closes element M12, 14 on-off element M14, sixteenmo closes element M16 and forms the first stabilization element, 11 on-off element M11, 13 on-off element M13, 15 on-off element M15, 17 on-off element M17 forms the second stabilization element), good stability.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (10)
1. a gate driver circuit, comprises multiple drive element of the grid, and wherein every grade of drive element of the grid is for driving a gate line corresponding on display panel respectively, and it is characterized in that, described every grade of drive element of the grid comprises:
First on-off element, comprises the first path terminal, the first control end, alternate path end, and described first path terminal receives with reference to high voltage, and described first control end receives the first pulse signal;
Second switch element, comprise third path end, the second control end, the 4th path terminal, described third path termination receives the first clock signal, described second control end is connected with the alternate path end of described first on-off element, and be connected with described 4th path terminal by the first electric capacity, described 4th path terminal is the output terminal of every grade of drive element of the grid;
3rd on-off element, comprise five-way terminal, the 3rd control end, the 6th path terminal, described five-way terminal is connected with the alternate path end of described first on-off element, and described 3rd control end receives the second pulse signal, and the 6th path terminal receives the first low reference voltage;
4th on-off element, comprises the 7th path terminal, the 4th control end, the 8th path terminal, the second low reference voltage that described 7th path terminal receives, and described 4th control end receives described second pulse signal;
5th on-off element, comprises the 9th path terminal, the 5th control end, the tenth path terminal, and described 9th path terminal receives described second low reference voltage, and described 5th control end receives described second pulse signal;
6th on-off element, comprise the 11 path terminal, the 6th control end, the 12 path terminal, described 11 path terminal receives described second low reference voltage, described 6th control end is connected with the second control end of described first on-off element, and the 12 path terminal is connected with the 8th path terminal of described 4th on-off element;
7th on-off element, comprise the tenth threeway terminal, the 7th control end, the 14 path terminal, described tenth three-way termination receives described second low reference voltage, described 7th control end is connected with the second control end of described first on-off element, and described 14 path terminal is connected with the tenth path terminal of described 5th on-off element;
8th on-off element, comprise the tenth five-way terminal, the 8th control end, the 16 path terminal, described tenth five-way terminal is connected with the 8th path terminal of described 4th on-off element, described 8th control end receives described first pulse signal, and described 16 path terminal receives described second low reference voltage;
9th on-off element, comprise the 17 path terminal, the 9th control end, the 18 path terminal, described 17 path terminal is connected with the tenth path terminal of described 5th on-off element, described 9th control end receives described first pulse signal, and described 18 path terminal receives described second low reference voltage;
Tenth on-off element, comprises the 19 path terminal, the tenth control end, the 20 path terminal, and described 19 path terminal and described tenth control end receive the first stabilization signal, and described 20 path terminal is connected with the 8th path terminal of described 4th on-off element;
11 on-off element, comprise the 21 path terminal, the 11 control end, the 22 path terminal, described 21 path terminal is connected with the tenth path terminal of described 5th on-off element, and described 11 control end and described 22 path terminal receive the second stabilization signal;
Twelvemo closes element, comprise the 20 threeway terminal, the 12 control end, the 24 path terminal, described 20 three-way termination receives described second low reference voltage, described 12 control end receives described first stabilization signal, and described 24 path terminal is connected with the 21 path terminal of described 11 on-off element;
13 on-off element, comprise the 20 five-way terminal, the 13 control end, the 26 path terminal, described 20 five-way terminal is connected with the 20 path terminal of described tenth on-off element, described 13 control end receives described second stabilization signal, and described 26 path terminal receives described second low reference voltage;
14 on-off element, comprise Twenty-seven lines go side, the 14 control end, the 28 path terminal, described 27 path terminal is connected with the alternate path end of described first on-off element, described 14 control end is connected with the 20 path terminal of described tenth on-off element, and described 28 path terminal receives described second low reference voltage;
15 on-off element, comprise the 29 path terminal, the 15 control end, the 30 path terminal, described 29 path terminal receives described second low reference voltage, described 15 control end is connected with the 21 path terminal of described 11 on-off element, and described 30 path terminal is connected with the alternate path end of described first on-off element;
Sixteenmo closes element, comprise the 31 path terminal, the 16 control end, the 32 path terminal, described 31 path terminal is connected with the 4th path terminal of described second switch element, described 16 control end is connected with the 20 path terminal of described tenth on-off element, and described 32 path terminal receives described second low reference voltage; And
17 on-off element, comprise the 30 threeway terminal, the 17 control end, the 34 path terminal, described 30 three-way termination receives described second low reference voltage, described 17 control end is connected with the 21 path terminal of described 11 on-off element, and described 34 path terminal is connected with the 4th path terminal of described second switch element.
2. gate driver circuit as claimed in claim 1, it is characterized in that, described first electric capacity is the stray capacitance between the 4th path terminal of described second switch element and the second control end.
3. gate driver circuit as claimed in claim 1, it is characterized in that, be provided with separate, stored electric capacity between second control end of described second switch element and the 4th path terminal, described first electric capacity is stray capacitance between the 4th path terminal of described second switch element and the second control end and described separate, stored electric capacity sum.
4. gate driver circuit as claimed in claim 1, it is characterized in that, if described drive element of the grid is n-th grade of drive element of the grid, the first pulse signal that then the first control end of described first on-off element receives is upper three grades of gate drive signals that the drive element of the grid upwards differing three grades with n-th grade of drive element of the grid exports, wherein, n is integer, and n >=4.
5. gate driver circuit as claimed in claim 1, it is characterized in that, if described gate driver circuit comprises N level drive element of the grid, the second pulse signal that then the 3rd control end of described 3rd on-off element of n-th grade of drive element of the grid receives is lower three grades of gate drive signals that the drive element of the grid differing three grades with n-th grade of drive element of the grid downwards exports, wherein, n is integer, and 0≤n≤N-3.
6. gate driver circuit as claimed in claim 1, is characterized in that, described first stabilization signal and described second stabilization signal are alternately high level.
7. gate driver circuit as claimed in claim 6, it is characterized in that, described first stabilization signal and described second stabilization signal are clock signal, and the dutycycle of described first stabilization signal and described second stabilization signal is 50 percent.
8. gate driver circuit as claimed in claim 7, it is characterized in that, the dutycycle of described first clock signal is 1/3rd, and the high level time of described first clock signal is 1/2nd of the high level time of described first stabilization signal and described second stabilization signal.
9. gate driver circuit as claimed in claim 1, is characterized in that, described first on-off element to described 17 on-off element is N-type transistor.
10. a display device, is characterized in that, comprises gate driver circuit as claimed in any one of claims 1 to 9 wherein.
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