CN104766573B - Gate drive circuit and display device - Google Patents
Gate drive circuit and display device Download PDFInfo
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- CN104766573B CN104766573B CN201510104519.9A CN201510104519A CN104766573B CN 104766573 B CN104766573 B CN 104766573B CN 201510104519 A CN201510104519 A CN 201510104519A CN 104766573 B CN104766573 B CN 104766573B
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Abstract
The invention discloses a gate drive circuit. The gate drive circuit comprises a plurality of levels of gate drive units. Each level of gate drive unit comprises a first switch element to a seventeenth switch element. Each level of gate drive unit receives a first clock signal. A first stabilizing unit is formed by the tenth switch element, the twelfth switch element, the fourteenth switch element and the sixteenth switch element. A second stabilizing unit is formed by the eleventh switch element, the thirteenth switch element, the fifteenth switch element and the seventeenth switch element. The invention further provides a display device. According to the gate drive circuit and the display device using the gate drive circuit, the switch elements playing a stable role and the switch elements playing a role in outputting gate drive signals receive different clock signals, the output capability of the gate drive circuit is higher, and the gate drive circuit comprises the two stabilizing units, so that stability is high.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of gate driver circuit and display device.
Background technology
It is many excellent that liquid crystal indicator (Liquid Crystal Display, LCD) possesses frivolous, energy-conservation, radiationless etc.
Point, therefore gradually replaced traditional cathode-ray tube (CRT) display.At present liquid crystal display is widely used in height
The electronics such as clear DTV, desktop computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera
In equipment.
As a example by with thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal indicator, it includes：Liquid crystal
Show panel and drive circuit, wherein, display panels include a plurality of gate line and a plurality of data lines, and two adjacent grids
Line intersects to form a pixel cell with two adjacent data lines, and each pixel cell at least includes a thin film transistor (TFT).
Drive circuit includes gate driver circuit (gate drive circuit) and source electrode drive circuit (source drive
circuit).With cost degradation pursuit and the raising of manufacturing process of the producer to liquid crystal indicator, it is arranged at originally
Drive circuit integrated chip beyond display panels is arranged on the glass substrate of display panels and becomes possibility,
For example, grid-driving integrated circuit is arranged on array base palte (Gate IC in Array, GIA) so as to simplify liquid crystal display
The manufacture process of device, and reduce production cost.
Display panels are with the basic functional principle of drive circuit：Gate driver circuit with gate line by electrically connecting
Pulling up transistor for connecing send gate drive signal to gate line, sequentially opens the TFT of every a line, then by source drive electricity
The pixel cell of one full line is charged to each required voltage by road simultaneously, to show different GTGs.I.e. first by the first row
Gate driver circuit pulled up transistor by it and open the thin film transistor (TFT) of the first row, then by source electrode drive circuit to the
The pixel cell of a line is charged.When the pixel cell of the first row is charged, gate driver circuit is just by the row film crystal
Pipe is closed, and then the gate driver circuit of the second row is pulled up transistor by it and opens the thin film transistor (TFT) of the second row, then by
Source electrode drive circuit carries out discharge and recharge to the pixel cell of the second row.So sequentially go down, when the pixel of last column of having substituted the bad for the good
Unit, just starts to charge up from the first row again.
But, for large-sized display panels, the load that its gate driver circuit drives is very big, and to showing
Uniformity requirements it is higher, the gate drive signal for so requiring gate driver circuit output voltage values larger and stable is existing
There is technology typically to solve the above problems using the switch element, the number of electric capacity and size that increase in gate driver circuit, but
Said method is unfavorable for the design of the narrow frame of liquid crystal indicator, and power consumption is big.
The content of the invention
The main technical problem to be solved in the present invention is to provide a kind of gate driver circuit, and it can be larger in output voltage values
And while stable gate drive signal, be conducive to the design of narrow frame, and small power consumption.
To solve above-mentioned technical problem, the invention provides a kind of gate driver circuit, it includes multiple raster data model lists
Unit, every grade of drive element of the grid includes first switch element, second switch element, the 3rd switch element, the 4th switch unit
Part, the 5th switch element, the 6th switch element, the 7th switch element, the 8th switch element, the 9th switch element, the tenth switch
Element, the 11st switch element, twelvemo close element, the 13rd switch element, the 14th switch element, the 15th switch unit
Part, sixteenmo close element, the 17th switch element.
Wherein, first switch element includes the first path terminal, the first control end, alternate path end, first path terminal
Reception refers to high voltage, and first control end receives the first pulse signal.Second switch element include third path end, second
Control end, fourth passage end, the third path end receives the first clock signal, second control end and the first switch
The alternate path end of element is connected, and is connected with the fourth passage end by the first electric capacity, and the fourth passage end is per grade
The output end of drive element of the grid.3rd switch element includes fifth passage end, the 3rd control end, the 6th path terminal, described the
Five path terminals are connected with the alternate path end of the first switch element, and the 3rd control end receives the second pulse signal, the
Six path terminals receive the first low reference voltage.4th switch element includes the 7th path terminal, the 4th control end, the 8th path terminal,
The second low reference voltage that 7th path terminal is received, the 4th control end receives second pulse signal.5th opens
Closing element includes the 9th path terminal, the 5th control end, the tenth path terminal, and the 9th path terminal receives described second and refers to low electricity
Pressure, the 5th control end receives second pulse signal.6th switch element includes the 11st path terminal, the 6th control
End, the 12nd path terminal, the 11st path terminal receives second low reference voltage, the 6th control end and described the
Second control end of one switch element is connected, and the 12nd path terminal is connected with the 8th path terminal of the 4th switch element.
7th switch element includes the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth threeway terminal
Second low reference voltage is received, the 7th control end is connected with the second control end of the first switch element, described
14th path terminal is connected with the tenth path terminal of the 5th switch element.8th switch element include the 15th path terminal,
8th control end, the 16th path terminal, the 15th path terminal is connected with the 8th path terminal of the 4th switch element, institute
State the 8th control end and receive first pulse signal, the 16th path terminal receives second low reference voltage.9th
Switch element includes the 17th path terminal, the 9th control end, the 18th path terminal, and the 17th path terminal is opened with the described 5th
The tenth path terminal for closing element is connected, and the 9th control end receives first pulse signal, the 18th path termination
Receive second low reference voltage.Tenth switch element includes the 19th path terminal, the tenth control end, the 20th path terminal, institute
State the 19th path terminal and the tenth control end receives the first stabilization signal, the 20th path terminal and the described 4th switch
8th path terminal of element is connected.11st switch element includes the 21st path terminal, the 11st control end, the 20th two-way
Terminal, the 21st path terminal is connected with the tenth path terminal of the 5th switch element, the 11st control end and
22nd path terminal receives the second stabilization signal.Twelvemo closes element includes the 20th threeway terminal, the 12nd control
End processed, the 24th path terminal, the 20th three-way end receives second low reference voltage, the 12nd control end
Receive first stabilization signal, the 21st path terminal phase of the 24th path terminal and the 11st switch element
Even.And the 13rd switch element include the 25th path terminal, the 13rd control end, the 26th path terminal, the described 20th
Five path terminals are connected with the 20th path terminal of the tenth switch element, and the 13rd control end receives described second and stablizes
Signal, the 26th path terminal receives second low reference voltage.14th switch element is logical including Twenty-seven lines
End, the 14th control end, the 28th path terminal, the alternate path of the 27th path terminal and the first switch element
End is connected, and the 14th control end is connected with the 20th path terminal of the tenth switch element, the 28th path
End receives second low reference voltage.
15th switch element include the 29th path terminal, the 15th control end, the 30th path terminal, the described 20th
Nine path terminals receive second low reference voltage, the 15th control end and the 21st of the 11st switch element
Path terminal is connected, and the 30th path terminal is connected with the alternate path end of the first switch element.Sixteenmo closes element
Including the 31st path terminal, the 16th control end, the 32nd path terminal, the 31st path terminal is opened with described second
The fourth passage end for closing element is connected, and the 16th control end is connected with the 20th path terminal of the tenth switch element,
32nd path terminal receives second low reference voltage.17th switch element include the 30th threeway terminal, the
17 control ends, the 34th path terminal, the 30th three-way end receives second low reference voltage, and the described 17th
Control end is connected with the 21st path terminal of the 11st switch element, and the 34th path terminal is opened with described second
The fourth passage end for closing element is connected.
Preferably, first electric capacity is posting between the fourth passage end of the second switch element and the second control end
Raw electric capacity.
Preferably, separate storage electricity is provided between the second control end of the second switch element and fourth passage end
Hold, first electric capacity be parasitic capacitance between the fourth passage end of the second switch element and the second control end with it is described
Separate storage electric capacity sum.
Preferably, if the drive element of the grid is n-th grade of drive element of the grid, the first of the first switch element
The first pulse signal that control end is received is to differ the drive element of the grid output of three-level upwards with n-th grade of drive element of the grid
Upper three-level gate drive signal, wherein, n is integer, and n >=4.
Preferably, if the gate driver circuit includes N level drive element of the grid, the institute of n-th grade of drive element of the grid
The second pulse signal for stating the 3rd control end reception of the 3rd switch element is to differ three-level downwards with n-th grade of drive element of the grid
Drive element of the grid output lower three-level gate drive signal, wherein, n is integer, and 0≤n≤N-3.
Preferably, first stabilization signal replaces as high level with second stabilization signal.
Preferably, first stabilization signal is clock signal, the described first stable letter with second stabilization signal
Number it is 50 percent with the dutycycle of second stabilization signal.
Preferably, the dutycycle of first clock signal is 1/3rd, and the high level of first clock signal
Time is 1/2nd of the high level time of first stabilization signal and second stabilization signal.
Preferably, the first switch element is N-type transistor to the 17th switch element.
The present invention also provides a kind of display device, and the display device includes gate driver circuit, gate driver circuit bag
Multiple drive element of the grid are included, every grade of drive element of the grid includes first switch element, second switch element, the 3rd switch
Element, the 4th switch element, the 5th switch element, the 6th switch element, the 7th switch element, the 8th switch element, the 9th open
Close element, the tenth switch element, the 11st switch element, twelvemo and close element, the 13rd switch element, the 14th switch unit
Part, the 15th switch element, sixteenmo close element, the 17th switch element.
Wherein, first switch element includes the first path terminal, the first control end, alternate path end, first path terminal
Reception refers to high voltage, and first control end receives the first pulse signal.Second switch element include third path end, second
Control end, fourth passage end, the third path end receives the first clock signal, second control end and the first switch
The alternate path end of element is connected, and is connected with the fourth passage end by the first electric capacity.3rd switch element includes the 5th
Path terminal, the 3rd control end, the 6th path terminal, the alternate path end phase of the fifth passage end and the first switch element
Even, the 3rd control end receives the second pulse signal, and the 6th path terminal receives the first low reference voltage.4th switch element bag
Include the 7th path terminal, the 4th control end, the 8th path terminal, the second low reference voltage that the 7th path terminal is received, described the
Four control ends receive second pulse signal.5th switch element includes the 9th path terminal, the 5th control end, the tenth path
End, the 9th path terminal receives second low reference voltage, and the 5th control end receives second pulse signal.The
Six switch elements include the 11st path terminal, the 6th control end, the 12nd path terminal, and the 11st path terminal receives described the
Two low reference voltages, the 6th control end is connected with the second control end of the first switch element, the 12nd path terminal with
8th path terminal of the 4th switch element is connected.
7th switch element includes the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth threeway terminal
Second low reference voltage is received, the 7th control end is connected with the second control end of the first switch element, described
14th path terminal is connected with the tenth path terminal of the 5th switch element.8th switch element include the 15th path terminal,
8th control end, the 16th path terminal, the 15th path terminal is connected with the 8th path terminal of the 4th switch element, institute
State the 8th control end and receive first pulse signal, the 16th path terminal receives second low reference voltage.9th
Switch element includes the 17th path terminal, the 9th control end, the 18th path terminal, and the 17th path terminal is opened with the described 5th
The tenth path terminal for closing element is connected, and the 9th control end receives first pulse signal, the 18th path termination
Receive second low reference voltage.Tenth switch element includes the 19th path terminal, the tenth control end, the 20th path terminal, institute
State the 19th path terminal and the tenth control end receives the first stabilization signal, the 20th path terminal and the described 4th switch
8th path terminal of element is connected.11st switch element includes the 21st path terminal, the 11st control end, the 20th two-way
Terminal, the 21st path terminal is connected with the tenth path terminal of the 5th switch element, the 11st control end and
22nd path terminal receives the second stabilization signal.Twelvemo closes element includes the 20th threeway terminal, the 12nd control
End processed, the 24th path terminal, the 20th three-way end receives second low reference voltage, the 12nd control end
Receive first stabilization signal, the 21st path terminal phase of the 24th path terminal and the 11st switch element
Even.13rd switch element include the 25th path terminal, the 13rd control end, the 26th path terminal, the described 25th
Path terminal is connected with the 20th path terminal of the tenth switch element, and the 13rd control end receives the described second stable letter
Number, the 26th path terminal receives second low reference voltage.14th switch element include Twenty-seven lines go side,
14th control end, the 28th path terminal, the alternate path end of the 27th path terminal and the first switch element
It is connected, the 14th control end is connected with the 20th path terminal of the tenth switch element, the 28th path terminal
Receive second low reference voltage.
15th switch element include the 29th path terminal, the 15th control end, the 30th path terminal, the described 20th
Nine path terminals receive second low reference voltage, the 15th control end and the 21st of the 11st switch element
Path terminal is connected, and the 30th path terminal is connected with the alternate path end of the first switch element.Sixteenmo closes element
Including the 31st path terminal, the 16th control end, the 32nd path terminal, the 31st path terminal is opened with described second
The fourth passage end for closing element is connected, and the 16th control end is connected with the 20th path terminal of the tenth switch element,
32nd path terminal receives second low reference voltage.17th switch element include the 30th threeway terminal, the
17 control ends, the 34th path terminal, the 30th three-way end receives second low reference voltage, and the described 17th
Control end is connected with the 21st path terminal of the 11st switch element, and the 34th path terminal is opened with described second
The fourth passage end for closing element is connected.
Preferably, first electric capacity is posting between the fourth passage end of the second switch element and the second control end
Raw electric capacity.
Preferably, separate storage electricity is provided between the second control end of the second switch element and fourth passage end
Hold, first electric capacity be parasitic capacitance between the fourth passage end of the second switch element and the second control end with it is described
Separate storage electric capacity sum.
Preferably, if the drive element of the grid is n-th grade of drive element of the grid, the first of the first switch element
The first pulse signal that control end is received is to differ the drive element of the grid output of three-level upwards with n-th grade of drive element of the grid
Upper three-level gate drive signal, wherein, n is integer, and n >=4.
Preferably, if the gate driver circuit includes N level drive element of the grid, the institute of n-th grade of drive element of the grid
The second pulse signal for stating the 3rd control end reception of the 3rd switch element is to differ three-level downwards with n-th grade of drive element of the grid
Drive element of the grid output lower three-level gate drive signal, wherein, n is integer, and 0≤n≤N-3.
Preferably, first stabilization signal replaces as high level with second stabilization signal.
Preferably, first stabilization signal is clock signal, the described first stable letter with second stabilization signal
Number it is 50 percent with the dutycycle of second stabilization signal.
Preferably, the dutycycle of first clock signal is 1/3rd, and the high level of first clock signal
Time is 1/2nd of the high level time of first stabilization signal and second stabilization signal.
Preferably, the first switch element is N-type transistor to the 17th switch element.
The present invention gate driver circuit and the display device using it, and rise stabilization switch element (the tenth opens
Element is closed to the 17th switch element) receive different from the switch element (second switch element) for playing output gate drive signal
Signal so that the fan-out capability of gate driver circuit is strong, and gate driver circuit includes two stable unit (the tenth switch units
Part, twelvemo are closed element, the 14th switch element, sixteenmo and close the stable unit of element composition first, the 11st switch unit
Part, the 13rd switch element, the 15th switch element, the 17th switch element constitute the second stable unit), good stability.
Become obvious by the other side and feature below with reference to the detailed description of accompanying drawing, the present invention.But should know
Road, accompanying drawing be only explain purpose design, not as the restriction of the scope of the present invention, this is because its should refer to it is attached
Plus claim.It should also be noted that unless otherwise noted, it is not necessary to scale accompanying drawing, they only try hard to conceptually
Illustrate structure described herein and flow process.
Description of the drawings
Fig. 1 shows for the circuit structure of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention
It is intended to.
Fig. 2 is the time diagram of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 3 illustrates for the circuit structure of six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Figure.
Fig. 4 realizes forward scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.
Fig. 5 realizes reverse scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.
Fig. 6 for first embodiment of the invention gate driver circuit in first order drive element of the grid at three temperatures
Output signal analog result schematic diagram.
Fig. 7 is the 120th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention at three kinds
The analog result schematic diagram of the output signal under environment temperature.
Specific embodiment
Further to illustrate the present invention to reach technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to display panels proposed by the present invention its specific embodiments, method, step, structure,
Feature and effect, describe in detail as after.
For the present invention aforementioned and other technology contents, feature and effect, in the following preferable reality coordinated with reference to schema
Applying in the detailed description of example to be clearly presented.By the explanation of specific embodiment, when can be to the present invention to reach predetermined
The technological means and effect that purpose is taken be able to more deeply and it is specific understand, but institute's accompanying drawings be only to provide with reference to
Purposes of discussion, not for being any limitation as to the present invention.
Although the present invention describes different elements, signal, port, component or portion using first, second, third, etc. term
Point, but these elements, signal, port, component or part are not limited by these terms.These terms are intended merely to one
Individual element, signal, port, component or part make a distinction with another element, signal, port, component or part.In the present invention
In, element, port, component or part and another element, port, component or part " connected ", " connection ", it is possible to understand that
To be directly electrically connected with, or it can be appreciated that there is the indirect electric connection of intermediary element.Unless otherwise defined, otherwise originally
All terms (including technical term and scientific terminology) that invention is used have and ordinary skill people of the art
The meaning that member is generally understood that.
The gate driver circuit (also referred to as shift register) of the present invention (is also referred to as shifted including multistage drive element of the grid
Deposit unit), the drive element of the grid per one-level is corresponding with the every a line gate line on display floater respectively to be electrically connected with, so as to
Gate drive signal is sequentially gradually applied on every row gate line, the annexation between drive element of the grid will hereinafter
Elaborate.
Fig. 1 shows for the circuit structure of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention
It is intended to.The present embodiment gate driver circuit, including multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid is used
In output gate drive signal Gn, to drive a corresponding gate line on display floater respectively.As shown in figure 1, every grade of grid
Pole driver element include first switch element M1, second switch element M2, the 3rd switch element M3, the 4th switch element M4, the
Five switch element M5, the 6th switch element M6, the 7th switch element M7, the 8th switch element M8, the 9th switch element M9, the tenth
Switch element M10, the 11st switch element M11, twelvemo close element M12, the 13rd switch element M13, the 14th switch
Element M14, the 15th switch element M15, sixteenmo close element M16 and the 17th switch element M17.
Wherein, first switch element M1 includes the first path terminal, the first control end, alternate path end, the first path termination
Receive and refer to high voltage VDD, the first control end receives the first pulse signal.Second switch element M2 include third path end, second
Control end, fourth passage end, third path end receives the first clock signal clk, and the second control end is with first switch element M1's
Alternate path end is connected, and is connected with fourth passage end by the first electric capacity, and fourth passage end is used to export this grade of raster data model
Signal Gn.3rd switch element M3 includes fifth passage end, the 3rd control end, the 6th path terminal, and fifth passage end is opened with first
The alternate path end for closing element M1 is connected, and the 3rd control end receives the second pulse signal, and the 6th path terminal receives first with reference to low
Voltage VSS.4th switch element M4 includes the 7th path terminal, the 4th control end, the 8th path terminal, the 7th path terminal receive the
Two low reference voltages VGL, the 4th control end receives the second pulse signal.5th switch element M5 include the 9th path terminal, the 5th
Control end, the tenth path terminal, the 9th path terminal receives the second low reference voltage VGL, and the 5th control end receives the second pulse signal.
6th switch element M6 includes the 11st path terminal, the 6th control end, the 12nd path terminal, and the 11st path terminal receives second and joins
Low-voltage VGL is examined, the 6th control end is connected with second control end of first switch element M1, the 12nd path terminal is switched with the 4th
8th path terminal of element M4 is connected.
7th switch element M7 includes the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth three-way termination
Receive the second low reference voltage VGL, the 7th control end is connected with second control end of first switch element M1, the 14th path terminal with
Tenth path terminal of the 5th switch element M5 is connected.8th switch element M8 include the 15th path terminal, the 8th control end, the tenth
Six path terminals, the 15th path terminal is connected with the 8th path terminal of the 4th switch element M4, and the 8th control end receives the first pulse
Signal, the 16th path terminal receives the second low reference voltage VGL.9th switch element M9 includes the 17th path terminal, the 9th control
End processed, the 18th path terminal, the 17th path terminal is connected with the tenth path terminal of the 5th switch element M5, and the 9th control end is received
First pulse signal, the 18th path terminal receives the second low reference voltage VGL.Tenth switch element M10 includes the 19th path
End, the tenth control end, the 20th path terminal, the 19th path terminal and the tenth control end the first stabilization signal V1 of reception, the 20th
Path terminal is connected with the 8th path terminal of the 4th switch element M4.11st switch element M11 include the 21st path terminal, the
11 control ends, the 22nd path terminal, the 21st path terminal is connected with the tenth path terminal of the 5th switch element M5, and the tenth
One control end and the 22nd path terminal receive the second stabilization signal V2.Twelvemo closes element M12 includes the 20th three-way
End, the 12nd control end, the 24th path terminal, the 20th three-way end receives the second low reference voltage VGL, the 12nd control
End receives the first stabilization signal V1, and the 24th path terminal is connected with the 21st path terminal of the 11st switch element M11.The
13 switch element M13 include the 25th path terminal, the 13rd control end, the 26th path terminal, the 25th path terminal
It is connected with the 20th path terminal of the tenth switch element M10, the 13rd control end receives the second stabilization signal V2, the 26th leads to
Terminal receives the second low reference voltage VGL.14th switch element M14 include Twenty-seven lines go side, the 14th control end, the
28 path terminals, the 27th path terminal is connected with the alternate path end of first switch element M1, the 14th control end and the
20th path terminal of ten switch element M10 is connected, and the 28th path terminal receives the second low reference voltage VGL.
15th switch element M15 include the 29th path terminal, the 15th control end, the 30th path terminal, the 20th
Nine path terminals receive the 21st path terminal of the second low reference voltage VGL, the 15th control end and the 11st switch element M11
It is connected, the 30th path terminal is connected with the alternate path end of first switch element M1.Sixteenmo closes element M16 includes the 30th
The fourth passage of one path terminal, the 16th control end, the 32nd path terminal, the 31st path terminal and second switch element M2
End is connected, and the 16th control end is connected with the 20th path terminal of the tenth switch element M10, and the 32nd path terminal receives second
Low reference voltage VGL.17th switch element M17 includes the 30th threeway terminal, the 17th control end, the 34th path
End, the 30th three-way end receives the second low reference voltage VGL, the 17th control end and the second of the 11st switch element M11
11 path terminals are connected, and the 34th path terminal is connected with the fourth passage end of second switch element M2.
Wherein, the tenth switch element M10, twelvemo are closed element M12, the 14th switch element M14, sixteenmo and close unit
Part M16 constitutes the first stable unit, the 11st switch element M11, the 13rd switch element M13, the 15th switch element M15,
17th switch element M17 constitutes the second stable unit.
Wherein, the first electric capacity C1 is the parasitism electricity between the fourth passage end of second switch element M2 and the second control end
Hold.Certainly it will be appreciated by those skilled in the art that be, it is also possible in second control end and the 4th of second switch element M2
Separate storage electric capacity is set between path terminal, and now, the first electric capacity C1 is the fourth passage end and second of second switch element M2
Parasitic capacitance between control end and separate storage electric capacity sum.
In an embodiment of the present invention, if drive element of the grid is n-th grade of drive element of the grid, and the grid of its output
Drive signal is Gn, then the first pulse signal that first control end of first switch element M1 is received is and n-th grade of raster data model
Unit differs upwards the upper three-level gate drive signal of i.e. the n-th -3 grades drive element of the grid output of drive element of the grid of three-level
Gn-3, wherein, n is integer, and n >=4.
In an embodiment of the present invention, if gate driver circuit includes N level drive element of the grid, n-th grade of grid drives
3rd control end of the 3rd switch element M3 of moving cell, the 4th control end of the 4th switch element M4 and the 5th switch element
The second pulse signal that 5th control end is received is the drive element of the grid for differing three-level downwards with n-th grade of drive element of the grid
The lower three-level gate drive signal Gn+3 of i.e. the n-th+3 grades drive element of the grid output, wherein, n is integer, and 0≤n≤N-3.
It should be noted that because first order drive element of the grid, second level drive element of the grid and third level grid drive
Moving cell is without the drive element of the grid for differing three-level upwards, grid of the last three-level drive element of the grid without difference three-level downwards
Pole driver element, so first order drive element of the grid, second level drive element of the grid and third level drive element of the grid are received
The first pulse signal, the second pulse signal that last three-level drive element of the grid is received is intended to be provided by external signal circuit.
In the present embodiment, first switch element is N-type transistor to the 17th switch element M1～M17.First control
It is grid to hold to the 13rd control end.First path terminal of first switch element M1, the third path end of second switch element M2,
The fifth passage end of the 3rd switch element M3, the 7th path terminal of the 4th switch element M4, the 9th of the 5th switch element M5 the are led to
11st path terminal, the tenth threeway terminal, the 8th switch element M8 of the 7th switch element M7 of terminal, the 6th switch element M6
The 15th path terminal, the 17th path terminal of the 9th switch element M9, the 19th path terminal of the tenth switch element M10,
21st path terminal of 11 switch element M11, twelvemo close the 20th threeway terminal of element M12, the 13rd switch
25th path terminal of element M13, the 27th path terminal of the 14th switch element M14, the 15th switch element M15
29th path terminal, sixteenmo close element M16 the 31st path terminal, the 33rd of the 17th switch element M17 the
Path terminal is drain electrode.The alternate path end of first switch element M1, the fourth passage end of second switch element M2, the 3rd switch
6th path terminal of element M3, the 8th path terminal of the 4th switch element M4, the tenth path terminal of the 5th switch element M5, the 6th
12nd path terminal of switch element M6, the 14th path terminal of the 7th switch element M7, the 16th of the 8th switch element M8 the
Path terminal, the 18th path terminal of the 9th switch element M9, the 20th path terminal of the tenth switch element M10, the 11st switch
22nd path terminal of element M11, twelvemo close the 24th path terminal of element M12, the 13rd switch element M13
26th path terminal, the 28th path terminal of the 14th switch element M14, the 30th of the 15th switch element M15 the lead to
Terminal, sixteenmo close the 32nd path terminal of element M16, the 34th path terminal of the 17th switch element M17 and are
Source electrode.
Certainly, it will be appreciated by persons skilled in the art that first switch element switch element M1～M17 can to the 17th
To be realized using such as switch element such as non-crystalline silicon tft, oxide TFT or low temperature polycrystalline silicon N-TFT.Open with first below
The switch element M1 of element M1 to the 17th～M17 is closed specifically to introduce the specific embodiment party of the present invention as a example by N-type transistor
Formula and its operation principle.
Refer to Fig. 2, its be n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention when
Sequence schematic diagram.As shown in Fig. 2 the first stabilization signal V1 replaces as high level with the second stabilization signal V2, that is to say, that when first
When stabilization signal V1 is high level, the second stabilization signal V2 is low level, and when the first stabilization signal V1 is low level, second is steady
Signal V2 is determined for high level.
In an embodiment of the present invention, the first stabilization signal V1 and the second stabilization signal V2 is clock signal, and first
The dutycycle of stabilization signal V1 and the second stabilization signal V2 is 50 percent.
In an embodiment of the present invention, the dutycycle of the first clock signal clk is 1/3rd, and the first clock signal
The high level time of CLK be the first stabilization signal V1 and the high level time of the second stabilization signal V2 1/2nd.
It is divided into pre-charging stage, pull-up stage, drop-down stage, stabilization sub stage per the course of work of one-level drive element of the grid
4 stages：
Pre-charging stage is the first stage：First control end of first switch element M1, the 8th of the 8th switch element M8 the
The first pulse signal that 9th control end of control end and the 9th switch element M9 is received differs upwards the raster data model of three-level
Unit output upper three-level gate drive signal Gn-3 be high level, first switch element M1, the 8th switch element M8 and the 9th
Switch element M9 is turned on, and the voltage at node Q is referenced high voltage VDD precharge, section by the first switch element M1 for turning on
Voltage at point QB1 is pulled low to the second low reference voltage VGL, the electricity at node QB2 by the 8th switch element M8 for turning on
The 9th switch element M9 by turning on is pressed to be pulled low to the second low reference voltage VGL；Further, since the voltage quilt at node Q
Precharge, the 6th switch element M6 and the 7th switch element M7 are turned on, and the voltage at node QB1 and node QB2 is respectively by leading
Logical the 6th switch element M6 and the 7th switch element M7 is pulled low to the second low reference voltage VGL.
The pull-up stage is second stage：When the level of the first clock signal clk is by low uprising, due in pre-charging stage section
Point Q has been precharged, therefore, second switch element M2 conductings, due to the conducting of second switch element M2, and due to first electric
Hold the boot strap of C1, the voltage at node Q is further pulled up, and voltage is further pulled up at node Q so that second opens
Element M2 is closed conductively more fully, so that this grade of gate drive signal of the output end output of this grade of drive element of the grid
Gn is drawn high by the second switch element M2 for turning on by the first clock signal clk.
It should be noted that in the present invention, can directly using the fourth passage end and second of second switch element M2
Parasitic capacitance between control end as the first electric capacity C1, or in order to lift pull-up effect, can be with second switch element
Separate storage electric capacity is set between second control end of M2 and fourth passage end, wherein, the separate storage electric capacity and second switch
The parasitic capacitance in parallel of element M2 is simultaneously equal to the 4th of second switch element M2 the collectively as the first electric capacity C1, i.e. the first electric capacity C1
Parasitic capacitance between path terminal and the second control end and separate storage electric capacity sum.
The drop-down stage is the phase III：First clock signal clk is changed into low level from high level, due in the pull-up stage
Voltage is further pulled up at point Q, and element M2 is in the conduction state for second switch, the output end of this grade of drive element of the grid is defeated
The gate drive signal Gn for going out is dragged down by the second switch element M2 for turning on by the first clock signal clk；Simultaneously as first
The boot strap of electric capacity C1, the voltage at node Q is also pulled low；Additionally, the drive element of the grid output of three-level ought be differed downwards
Lower three-level gate drive signal Gn+3 when low level is changed into high level, the 3rd switch element M3 conducting, the electricity at node Q
The 3rd switch element M3 by turning on is pressed to be pulled low to the first low reference voltage VSS.
Stabilization sub stage is fourth stage：Because the first stabilization signal V1 and the second stabilization signal V2 is alternately high level, because
This, node QB1 and node QB2 are alternately high level, therefore, the 4th switch element M4 and the 5th switch element M5 alternate conductions, from
And the voltage at node Q is pulled low by the 14th switch element M14 of conducting or the 15th switch element M15 of conducting
To the second low reference voltage VGL, additionally, sixteenmo closes element M16 and the 17th switch element M17 also alternate conductions, so as to
So that gate drive signal Gn is pulled low by the 17th switch element M17 that the sixteenmo for turning on closes element M16 or conducting
To the second low reference voltage VGL.
By taking six grades of drive element of the grid as an example, as shown in figure 3, which describing first order drive element of the grid R1, the second level
Drive element of the grid R2, third level drive element of the grid R3, fourth stage drive element of the grid R4, level V drive element of the grid
The driving principle of R5, the 6th grade of drive element of the grid R6, wherein, the every one-level drive element of the grid shown in Fig. 3 be used to receiving to
The upper two-stage gate drive signal Gn-3 of the drive element of the grid output of upper difference three-level, and downwards the grid of difference three-level drives
The lower two-stage gate drive signal Gn+3 of moving cell output.And as shown in figure 3, first order drive element of the grid R1, second level grid
Drive element of the grid of the pole driver element R2 and third level drive element of the grid R3 without difference three-level upwards, therefore, the first order
Drive element of the grid R1 receives the signal of the first outside source STV1 offers as the first pulse signal, and second grid drives single
First R2 receive signal that the second outside source STV2 provides as the first pulse signal, the 3rd drive element of the grid R3 receives
The signal that 3rd outside source STV3 is provided is used as the first pulse signal.Fourth stage drive element of the grid R4, level V grid
Drive element of the grid of driver element R5 and the 6th grade of drive element of the grid R6 without difference three-level downwards, therefore, the 4th grid
Driver element R4 receives the signal of the 4th outside source STV4 offers as the second pulse signal, level V drive element of the grid
R5 receives the signal of the 5th outside source STV5 offers as the second pulse signal, and the 6th drive element of the grid R6 receives the 6th
The signal that outside source STV6 is provided is used as the second pulse signal.
Fig. 4 realizes forward scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.Please also refer to Fig. 3 and Fig. 4, first order drive element of the grid R1, second level drive element of the grid R2, the 3rd
Level drive element of the grid R3, fourth stage drive element of the grid R4, level V drive element of the grid R5, the 6th grade of drive element of the grid
The first pulse signal and the first clock signal clk that R6 is received is changed into high level from low level successively, therefore first order grid drives
Moving cell R1, second level drive element of the grid R2, third level drive element of the grid R3, fourth stage drive element of the grid R4, the 5th
Level drive element of the grid R5, the 6th grade of drive element of the grid R6 are sequentially output gate drive signal Gn, so as to drive correspondence successively
Gate line, to realize forward scan.
Fig. 5 realizes reverse scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.Please also refer to Fig. 3 and such as Fig. 5, the 6th grade of drive element of the grid R6, level V drive element of the grid R5, the
Level Four drive element of the grid R4, third level drive element of the grid R3, second level drive element of the grid R2, first order raster data model list
The first pulse signal and the first clock signal clk that first R1 is received is changed into high level, therefore the 6th grade of grid from low level successively
Driver element R6, level V drive element of the grid R5, fourth stage drive element of the grid R4, third level drive element of the grid R3,
Two grades of drive element of the grid R2, first order drive element of the grid R1 are sequentially output gate drive signal Gn, so as to realize reversely sweeping
Retouch.
Fig. 6 for first embodiment of the invention gate driver circuit in first order drive element of the grid at three temperatures
Output signal analog result schematic diagram.Fig. 7 is the 120th in the gate driver circuit of first embodiment of the invention
The analog result schematic diagram of output signal of the level drive element of the grid under three kinds of environment temperatures.As shown in fig. 6,1., 2., 3. dividing
Not Biao Shi first order drive element of the grid export under subzero 20 degrees Celsius, normal temperature and under 70 degrees Celsius raster data model letter
Number, as shown in fig. 7,4., 5., 6. representing the 120th grade of drive element of the grid under subzero 20 degrees Celsius, normal temperature respectively
And the gate drive signal exported under 70 degrees Celsius.Please also refer to Fig. 6 and Fig. 7, the of the gate driver circuit of the present invention
One-level drive element of the grid can export stable raster data model letter under subzero 20 degrees Celsius, normal temperature and under 70 degrees Celsius
Number, the 120th grade of drive element of the grid can export stable under subzero 20 degrees Celsius, normal temperature and under 70 degrees Celsius
Gate drive signal, therefore the gate driver circuit of the present invention can export stable grid under different environment temperatures and drive
Dynamic signal.
The present invention also provides a kind of display device, and it includes gate driver circuit, and gate driver circuit includes multistage such as Fig. 1
Shown drive element of the grid, n-th grade of drive element of the grid is used to export gate drive signal Gn, to drive display floater respectively
On a corresponding gate line.As shown in figure 1, every grade of drive element of the grid includes first switch element M1, second switch unit
Part M2, the 3rd switch element M3, the 4th switch element M4, the 5th switch element M5, the 6th switch element M6, the 7th switch element
M7, the 8th switch element M8, the 9th switch element M9, the tenth switch element M10, the 11st switch element M11, twelvemo are closed
Element M12, the 13rd switch element M13, the 14th switch element M14, the 15th switch element M15, sixteenmo close element
M16 and the 17th switch element M17.
Wherein, first switch element M1 includes the first path terminal, the first control end, alternate path end, the first path termination
Receive and refer to high voltage VDD, the first control end receives the first pulse signal.Second switch element M2 include third path end, second
Control end, fourth passage end, third path end receives the first clock signal clk, and the second control end is with first switch element M1's
Alternate path end is connected, and is connected with fourth passage end by the first electric capacity, and fourth passage end is used to export this grade of raster data model
Signal Gn.3rd switch element M3 includes fifth passage end, the 3rd control end, the 6th path terminal, and fifth passage end is opened with first
The alternate path end for closing element M1 is connected, and the 3rd control end receives the second pulse signal, and the 6th path terminal receives first with reference to low
Voltage VSS.4th switch element M4 includes the 7th path terminal, the 4th control end, the 8th path terminal, the 7th path terminal receive the
Two low reference voltages VGL, the 4th control end receives the second pulse signal.5th switch element M5 include the 9th path terminal, the 5th
Control end, the tenth path terminal, the 9th path terminal receives the second low reference voltage VGL, and the 5th control end receives the second pulse signal.
6th switch element M6 includes the 11st path terminal, the 6th control end, the 12nd path terminal, and the 11st path terminal receives second and joins
Low-voltage VGL is examined, the 6th control end is connected with second control end of first switch element M1, the 12nd path terminal is switched with the 4th
8th path terminal of element M4 is connected.
7th switch element M7 includes the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth three-way termination
Receive the second low reference voltage VGL, the 7th control end is connected with second control end of first switch element M1, the 14th path terminal with
Tenth path terminal of the 5th switch element M5 is connected.8th switch element M8 include the 15th path terminal, the 8th control end, the tenth
Six path terminals, the 15th path terminal is connected with the 8th path terminal of the 4th switch element M4, and the 8th control end receives the first pulse
Signal, the 16th path terminal receives the second low reference voltage VGL.9th switch element M9 includes the 17th path terminal, the 9th control
End processed, the 18th path terminal, the 17th path terminal is connected with the tenth path terminal of the 5th switch element M5, and the 9th control end is received
First pulse signal, the 18th path terminal receives the second low reference voltage VGL.Tenth switch element M10 includes the 19th path
End, the tenth control end, the 20th path terminal, the 19th path terminal and the tenth control end the first stabilization signal V1 of reception, the 20th
Path terminal is connected with the 8th path terminal of the 4th switch element M4.11st switch element M11 include the 21st path terminal, the
11 control ends, the 22nd path terminal, the 21st path terminal is connected with the tenth path terminal of the 5th switch element M5, and the tenth
One control end and the 22nd path terminal receive the second stabilization signal V2.Twelvemo closes element M12 includes the 20th three-way
End, the 12nd control end, the 24th path terminal, the 20th three-way end receives the second low reference voltage VGL, the 12nd control
End receives the first stabilization signal V1, and the 24th path terminal is connected with the 21st path terminal of the 11st switch element M11.The
13 switch element M13 include the 25th path terminal, the 13rd control end, the 26th path terminal, the 25th path terminal
It is connected with the 20th path terminal of the tenth switch element M10, the 13rd control end receives the second stabilization signal V2, the 26th leads to
Terminal receives the second low reference voltage VGL.14th switch element M14 include Twenty-seven lines go side, the 14th control end, the
28 path terminals, the 27th path terminal is connected with the alternate path end of first switch element M1, the 14th control end and the
20th path terminal of ten switch element M10 is connected, and the 28th path terminal receives the second low reference voltage VGL.
15th switch element M15 include the 29th path terminal, the 15th control end, the 30th path terminal, the 20th
Nine path terminals receive the 21st path terminal of the second low reference voltage VGL, the 15th control end and the 11st switch element M11
It is connected, the 30th path terminal is connected with the alternate path end of first switch element M1.Sixteenmo closes element M16 includes the 30th
The fourth passage of one path terminal, the 16th control end, the 32nd path terminal, the 31st path terminal and second switch element M2
End is connected, and the 16th control end is connected with the 20th path terminal of the tenth switch element M10, and the 32nd path terminal receives second
Low reference voltage VGL.17th switch element M17 includes the 30th threeway terminal, the 17th control end, the 34th path
End, the 30th three-way end receives the second low reference voltage VGL, the 17th control end and the second of the 11st switch element M11
11 path terminals are connected, and the 34th path terminal is connected with the fourth passage end of second switch element M2.
Wherein, the tenth switch element M10, twelvemo are closed element M12, the 14th switch element M14, sixteenmo and close unit
Part M16 constitutes the first stable unit, the 11st switch element M11, the 13rd switch element M13, the 15th switch element M15,
17th switch element M17 constitutes the second stable unit.
The present invention gate driver circuit and the display device using it, and rise stabilization switch element (the tenth opens
Element is closed to the 17th switch element M10～M17) and act the switch element (second switch element M2) for exporting gate drive signal
Receive different signals so that the fan-out capability of gate driver circuit is strong, and gate driver circuit includes two stable units (the
It is steady that ten switch element M10, twelvemo close element M12, the 14th switch element M14, sixteenmo pass element M16 compositions first
Order unit, the 11st switch element M11, the 13rd switch element M13, the 15th switch element M15, the 17th switch element
M17 constitutes the second stable unit), good stability.
The above, is only presently preferred embodiments of the present invention, and any pro forma restriction is not made to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any to be familiar with this professional technology people
Member, in the range of without departing from technical solution of the present invention, when making a little change or modification using the technology contents of the disclosure above
For the Equivalent embodiments of equivalent variations, as long as being without departing from technical solution of the present invention content, according to the technical spirit pair of the present invention
Any simple modification, equivalent variations and modification that above example is made, still fall within the range of technical solution of the present invention.
Claims (10)
1. a kind of gate driver circuit, including multiple drive element of the grid, wherein every grade of drive element of the grid is used to drive respectively
A corresponding gate line on display floater, it is characterised in that every grade of drive element of the grid includes：
First switch element, including the first path terminal, the first control end, alternate path end, first path terminal receives reference
High voltage, first control end receives the first pulse signal；
Second switch element, including third path end, the second control end, fourth passage end, the third path end receives first
Clock signal, second control end is connected with the alternate path end of the first switch element, and by the first electric capacity and institute
State fourth passage end to be connected, the fourth passage end is the output end of every grade of drive element of the grid；
3rd switch element, including fifth passage end, the 3rd control end, the 6th path terminal, the fifth passage end and described
The alternate path end of one switch element is connected, and the 3rd control end receives the second pulse signal, and the 6th path terminal receives first
Low reference voltage；
4th switch element, including the 7th path terminal, the 4th control end, the 8th path terminal, the 7th path terminal receive the
Two low reference voltages, the 4th control end receives second pulse signal；
5th switch element, including the 9th path terminal, the 5th control end, the tenth path terminal, the 9th path terminal receives described
Second low reference voltage, the 5th control end receives second pulse signal；
6th switch element, including the 11st path terminal, the 6th control end, the 12nd path terminal, the 11st path termination
Second low reference voltage is received, the 6th control end is connected with the second control end of the first switch element, the 12nd
Path terminal is connected with the 8th path terminal of the 4th switch element；
7th switch element, including the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth three-way termination
Second low reference voltage is received, the 7th control end is connected with the second control end of the first switch element, described
14 path terminals are connected with the tenth path terminal of the 5th switch element；
8th switch element, including the 15th path terminal, the 8th control end, the 16th path terminal, the 15th path terminal with
8th path terminal of the 4th switch element is connected, and the 8th control end receives first pulse signal, and the described tenth
Six path terminals receive second low reference voltage；
9th switch element, including the 17th path terminal, the 9th control end, the 18th path terminal, the 17th path terminal with
Tenth path terminal of the 5th switch element is connected, and the 9th control end receives first pulse signal, and the described tenth
Eight path terminals receive second low reference voltage；
Tenth switch element, including the 19th path terminal, the tenth control end, the 20th path terminal, the 19th path terminal and
Tenth control end receives the first stabilization signal, the 8th path terminal of the 20th path terminal and the 4th switch element
It is connected；
11st switch element, including the 21st path terminal, the 11st control end, the 22nd path terminal, the described 20th
One path terminal is connected with the tenth path terminal of the 5th switch element, the 11st control end and the 22nd path
End receives the second stabilization signal；
Twelvemo pass element, including the 20th threeway terminal, the 12nd control end, the 24th path terminal, the described 20th
Three-way end receives second low reference voltage, and the 12nd control end receives first stabilization signal, and described second
14 path terminals are connected with the 21st path terminal of the 11st switch element；
13rd switch element, including the 25th path terminal, the 13rd control end, the 26th path terminal, the described 20th
Five path terminals are connected with the 20th path terminal of the tenth switch element, and the 13rd control end receives described second and stablizes
Signal, the 26th path terminal receives second low reference voltage；
14th switch element, including the 27th path terminal, the 14th control end, the 28th path terminal, the described 20th
Seven path terminals are connected with the alternate path end of the first switch element, the 14th control end and the tenth switch element
The 20th path terminal be connected, the 28th path terminal receives second low reference voltage；
15th switch element, including the 29th path terminal, the 15th control end, the 30th path terminal, the described 29th
Path terminal receives second low reference voltage, and the 15th control end is led to the 21st of the 11st switch element the
Terminal is connected, and the 30th path terminal is connected with the alternate path end of the first switch element；
Sixteenmo pass element, including the 31st path terminal, the 16th control end, the 32nd path terminal, the described 30th
One path terminal is connected with the fourth passage end of the second switch element, the 16th control end and the tenth switch element
The 20th path terminal be connected, the 32nd path terminal receives second low reference voltage；And
17th switch element, including the 30th threeway terminal, the 17th control end, the 34th path terminal, the described 30th
Three-way end receives second low reference voltage, the 17th control end and the 21st of the 11st switch element
Path terminal is connected, and the 34th path terminal is connected with the fourth passage end of the second switch element.
2. gate driver circuit as claimed in claim 1, it is characterised in that first electric capacity is the second switch element
Fourth passage end and the second control end between parasitic capacitance.
3. gate driver circuit as claimed in claim 1, it is characterised in that the second control end of the second switch element with
Be provided with separate storage electric capacity between fourth passage end, first electric capacity be the second switch element fourth passage end with
Parasitic capacitance between second control end and the separate storage electric capacity sum.
4. gate driver circuit as claimed in claim 1, it is characterised in that if the drive element of the grid is n-th grade of grid
Driver element, then the first switch element the first control end receive the first pulse signal be and n-th grade of raster data model list
Unit differs upwards the upper three-level gate drive signal of the drive element of the grid output of three-level, wherein, n is integer, and n >=4.
5. gate driver circuit as claimed in claim 1, it is characterised in that if the gate driver circuit includes N level grids
Driver element, then the second pulse signal that the 3rd control end of the 3rd switch element of n-th grade of drive element of the grid is received
It is the lower three-level gate drive signal of the drive element of the grid output for differing three-level downwards with n-th grade of drive element of the grid, wherein,
N is integer, and 0≤n≤N-3.
6. gate driver circuit as claimed in claim 1, it is characterised in that first stabilization signal is stable with described second
Signal is alternately high level.
7. gate driver circuit as claimed in claim 6, it is characterised in that first stabilization signal is stable with described second
Signal is clock signal, and first stabilization signal is 50 percent with the dutycycle of second stabilization signal.
8. gate driver circuit as claimed in claim 7, it is characterised in that the dutycycle of first clock signal is three points
One of, and the high level time of first clock signal is the height electricity of first stabilization signal and second stabilization signal
Between at ordinary times 1/2nd.
9. gate driver circuit as claimed in claim 1, it is characterised in that the first switch element is opened to the described 17th
Close element and be N-type transistor.
10. a kind of display device, it is characterised in that including gate driver circuit as claimed in any one of claims 1 to 9 wherein.
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| CN105185341B (en) * | 2015-10-09 | 2017-12-15 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and use its display device |
| CN105261341B (en) * | 2015-11-11 | 2017-11-03 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and display device |
| CN105374331B (en) * | 2015-12-01 | 2017-11-17 | 武汉华星光电技术有限公司 | Gate driving circuit and the display using gate driving circuit |
| CN108109575B (en) * | 2017-12-21 | 2021-04-20 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
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| CN103021309A (en) * | 2011-09-23 | 2013-04-03 | 海蒂斯技术有限公司 | Shift register and driving circuit using the same |
| CN103137061A (en) * | 2013-02-18 | 2013-06-05 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode driving circuit and display device |
| CN103236273A (en) * | 2013-04-16 | 2013-08-07 | 北京京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit, and display device |
| CN104112421A (en) * | 2014-04-10 | 2014-10-22 | 友达光电股份有限公司 | Gate drive circuit and shift register |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103021309A (en) * | 2011-09-23 | 2013-04-03 | 海蒂斯技术有限公司 | Shift register and driving circuit using the same |
| CN103137061A (en) * | 2013-02-18 | 2013-06-05 | 京东方科技集团股份有限公司 | Shifting register unit, grid electrode driving circuit and display device |
| CN103236273A (en) * | 2013-04-16 | 2013-08-07 | 北京京东方光电科技有限公司 | Shift register unit and driving method thereof, gate drive circuit, and display device |
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