CN104637461B - A kind of gate driver circuit and display device - Google Patents
A kind of gate driver circuit and display device Download PDFInfo
- Publication number
- CN104637461B CN104637461B CN201510075980.6A CN201510075980A CN104637461B CN 104637461 B CN104637461 B CN 104637461B CN 201510075980 A CN201510075980 A CN 201510075980A CN 104637461 B CN104637461 B CN 104637461B
- Authority
- CN
- China
- Prior art keywords
- switch element
- control end
- path
- terminal
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a kind of gate driver circuit, which includes that multistage drive element of the grid, every grade of drive element of the grid include first switch element to the 13rd switch element.Every grade of drive element of the grid receives the first clock signal, second clock signal, the 3rd clock signal, the first clock signal and the second clock signal, wherein, 4th switch element, the 6th switch element, the 8th switch element, the tenth switch element and twelvemo are closed element and constitute the first stable unit, and the 5th switch element, the 7th switch element, the 9th switch element, the 11st switch element and the 13rd switch element constitute the second stable unit.The present invention also provides a kind of display device.The present invention gate driver circuit and using its display device, play the switch element of the Stabilization signal different from the switch element reception for playing output gate drive signal effect, so that the fan-out capability of gate driver circuit is strong, and gate driver circuit includes two stable units, good stability.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of gate driver circuit and display device.
Background technology
Liquid crystal indicator (Liquid Crystal Display, LCD) possesses frivolous, energy-conservation, radiationless etc. many excellent
Point, has therefore gradually replaced traditional cathode ray tube (CRT) display.Liquid crystal display is widely used in height at present
The electronics such as clear DTV, desk computer, personal digital assistant (PDA), notebook computer, mobile phone, digital camera
In equipment.
As a example by with thin film transistor (TFT) (Thin Film Transistor, TFT) liquid crystal indicator, which includes：Liquid crystal
Show panel and drive circuit, wherein, display panels include a plurality of gate line and a plurality of data lines, and two adjacent grids
Line intersects to form a pixel cell with two adjacent data lines, and each pixel cell at least includes a thin film transistor (TFT).
Drive circuit includes gate driver circuit (gate drive circuit) and source electrode drive circuit (source drive
circuit).With cost degradation pursuit and the raising of manufacturing process of the Producer to liquid crystal indicator, it is arranged at originally
Drive circuit integrated chip beyond display panels is arranged on the glass substrate of display panels and becomes possibility,
For example, grid-driving integrated circuit is arranged on array base palte (Gate IC in Array, GIA), so as to simplify liquid crystal
The manufacture process of showing device, and reduce production cost.
Display panels with the basic functional principle of drive circuit are：Gate driver circuit is by electrically connecting with gate line
Pulling up transistor for connecing send gate drive signal to gate line, sequentially opens the TFT of every a line, then by source drive electricity
The pixel cell of one full line is charged to each required voltage by road simultaneously, to show different GTGs.I.e. first by the first row
Gate driver circuit pulled up transistor by which thin film transistor (TFT) of the first row opened, then by source electrode drive circuit to the
The pixel cell of a line is charged.When the pixel cell of the first row is charged, gate driver circuit is just by the row film crystal
Pipe is closed, and then the gate driver circuit of the second row is pulled up transistor by which and opens the thin film transistor (TFT) of the second row, then by
Source electrode drive circuit carries out discharge and recharge to the pixel cell of the second row.So sequentially go down, when the pixel of last column of having substituted the bad for the good
Unit, is just started to charge up from the first row again.
But, for large-sized display panels, the load that its gate driver circuit drives is very big, and to showing
Uniformity requirements higher, the gate drive signal that so requires gate driver circuit output voltage values larger and stable is existing
There is technology typically to solve the above problems using the switch element, the number of electric capacity and size increased in gate driver circuit, but
Said method is unfavorable for the design of the narrow frame of liquid crystal indicator, and power consumption is big.
Content of the invention
The main technical problem to be solved in the present invention is to provide a kind of gate driver circuit, and which can be larger in output voltage values
And while stable gate drive signal, be conducive to the design of narrow frame, and small power consumption.
For solving above-mentioned technical problem, the invention provides a kind of gate driver circuit, which includes multiple raster data model lists
Unit, per grade of drive element of the grid include first switch element, second switch element, the 3rd switch element, the 4th switch unit
Part, the 5th switch element, the 6th switch element, the 7th switch element, the 8th switch element, the 9th switch element, the tenth switch
Element, the 11st switch element, twelvemo close element, the 13rd switch element.The first switch element includes that first leads to
Terminal, the first control end, alternate path end, first path terminal receive the first clock signal, and first control end is received
First pulse signal.The second switch element includes third path end, the second control end, fourth passage end, the threeway
Terminal receives second clock signal, and second control end is connected with the alternate path end of the first switch element, and
It is connected with the fourth passage end by the first electric capacity.3rd switch element include fifth passage end, the 3rd control end,
Clematis stem terminal, the fifth passage end are connected with the alternate path end of the first switch element, the 3rd control end
The second pulse signal is received, the clematis stem terminal receives the 3rd clock signal.4th switch element includes the 7th path
End, the 4th control end, the 8th path terminal, the alternate path end phase of the 7th path terminal and the first switch element
Even, the 8th path terminal receives low reference voltage.
5th switch element includes the 9th path terminal, the 5th control end, the tenth path terminal, the 9th path termination
The low reference voltage is received, the tenth path terminal is connected with the alternate path end of the first switch element.Described
Six switch elements include the 11st path terminal, the 6th control end, the 12nd path terminal, the 11st path terminal and described second
The fourth passage end of switch element is connected, the 4th control end of the 6th control end and the 4th switch element
It is connected, the 12nd path terminal receives the low reference voltage.7th switch element includes the tenth threeway terminal, the 7th control
End, the 14th path terminal, the tenth three-way end receive the low reference voltage, and the 7th control end is opened with the described 5th
The 5th control end for closing element is connected, the fourth passage end of the 14th path terminal and the second switch element
It is connected.8th switch element includes the 15th path terminal, the 8th control end, the tenth clematis stem terminal, the 15th path
End receives the first clock signal, and the 8th control end is connected with the 15th path terminal, the tenth clematis stem terminal and institute
The 4th control end for stating the 4th switch element is connected.9th switch element includes the 17th path terminal, the 9th control
End, the 18th path terminal, the 17th path terminal is connected with the 5th control end of the 5th switch element, and described the
Nine control ends receive the second clock signal, and the 18th path terminal is connected with the 9th control end.The tenth switch unit
Part includes that the 19th path terminal, the tenth control end, the 20th path terminal, the 19th path terminal receive described with reference to low electricity
Pressure, the tenth control end receive first clock signal, the institute of the 20th path terminal and the 5th switch element
State the 5th control end to be connected.
11st switch element includes the 21st path terminal, the 11st control end, the 22nd path terminal, described
21st path terminal is connected with the 4th control end of the 4th switch element, and the 11st control end receives described
Second clock signal, the 22nd path terminal receive the low reference voltage.The twelvemo closes element includes the 23rd
Path terminal, the 12nd control end, the 24th path terminal, the 20th three-way end receive the low reference voltage, described
12nd control end is connected with the alternate path end of the first switch element, the 24th path terminal and described
4th control end of four switch elements is connected.13rd switch element includes the 25th path terminal, the 13rd control
End processed, the 20th clematis stem terminal, the 25th path terminal receive the low reference voltage, the 13rd control end and institute
State first switch element the alternate path end be connected, the 20th clematis stem terminal with described in the 5th switch element
5th control end is connected.
Preferably, first electric capacity is the fourth passage end of the second switch element and second control end
Between parasitic capacitance.
Preferably, independence is provided between second control end of the second switch element and the fourth passage end
Storage capacitance, first electric capacity are described between the fourth passage end of the second switch element and the second control end
Parasitic capacitance and the separate storage electric capacity sum.
Preferably, if the drive element of the grid includes N level drive element of the grid, the institute of n-th grade of drive element of the grid
The first pulse signal for stating the first control end reception of first switch element is to be differed with n-th grade of drive element of the grid upwards
The upper two-stage gate drive signal of the drive element of the grid output of two-stage, wherein, n is integer, and n >=3.
Preferably, if the drive element of the grid includes N level drive element of the grid, the institute of n-th grade of drive element of the grid
The second pulse signal for stating the 3rd control end reception of the 3rd switch element is to be differed with n-th grade of drive element of the grid downwards
The lower two-stage gate drive signal of the drive element of the grid output of two-stage, wherein, n is integer, and 0≤n≤N-2.
Preferably, when first clock signal is high level, second clock signal is low level, when described the
When one clock signal is low level, second clock signal is high level.
Preferably, first clock signal and the time that the time that second clock signal is high level is a frame.
Preferably, the dutycycle phase of first clock signal, the second clock signal and the 3rd clock signal
With.
Preferably, the first switch element is N-type transistor to the 13rd switch element.
The present invention also provides a kind of display device, and the display device includes gate driver circuit, the raster data model electricity
Road includes multiple drive element of the grid, per grade of drive element of the grid include first switch element, second switch element, the 3rd
Switch element, the 4th switch element, the 5th switch element, the 6th switch element, the 7th switch element, the 8th switch element,
Nine switch elements, the tenth switch element, the 11st switch element, twelvemo close element, the 13rd switch element.Described first
Switch element includes that the first path terminal, the first control end, alternate path end, first path terminal receive the first clock signal,
First control end receives the first pulse signal.The second switch element include third path end, the second control end, the 4th
Path terminal, the third path end receive second clock signal, second control end with described in the first switch element
Alternate path end is connected, and is connected with the fourth passage end by the first electric capacity.3rd switch element includes that the 5th leads to
Terminal, the 3rd control end, clematis stem terminal, the alternate path end phase of the fifth passage end and the first switch element
Even, the 3rd control end receives the second pulse signal, and clematis stem terminal receives the 3rd clock signal.4th switch element
Including the 7th path terminal, the 4th control end, the 8th path terminal, the 7th path terminal and described the of the first switch element
Two path terminals are connected, and the 8th path terminal receives low reference voltage.
5th switch element includes the 9th path terminal, the 5th control end, the tenth path terminal, the 9th path termination
The low reference voltage is received, the tenth path terminal is connected with the alternate path end of the first switch element.Described
Six switch elements include the 11st path terminal, the 6th control end, the 12nd path terminal, the 11st path terminal and described second
The fourth passage end of switch element is connected, the 4th control end of the 6th control end and the 4th switch element
It is connected, the 12nd path terminal receives the low reference voltage.7th switch element includes the tenth threeway terminal, the 7th control
End, the 14th path terminal, the tenth three-way end receive the low reference voltage, and the 7th control end is opened with the described 5th
The 5th control end for closing element is connected, the fourth passage end of the 14th path terminal and the second switch element
It is connected.8th switch element includes the 15th path terminal, the 8th control end, the tenth clematis stem terminal, the 15th path
End receives the first clock signal, and the 8th control end is connected with the 15th path terminal, the tenth clematis stem terminal and institute
The 4th control end for stating the 4th switch element is connected.9th switch element includes the 17th path terminal, the 9th control
End, the 18th path terminal, the 17th path terminal is connected with the 5th control end of the 5th switch element, and described the
Nine control ends receive the second clock signal, and the 18th path terminal is connected with the 9th control end.The tenth switch unit
Part includes that the 19th path terminal, the tenth control end, the 20th path terminal, the 19th path terminal receive described with reference to low electricity
Pressure, the tenth control end receive first clock signal, the institute of the 20th path terminal and the 5th switch element
State the 5th control end to be connected.
11st switch element includes the 21st path terminal, the 11st control end, the 22nd path terminal, described
21st path terminal is connected with the 4th control end of the 4th switch element, and the 11st control end receives described
Second clock signal, the 22nd path terminal receive the low reference voltage.The twelvemo closes element includes the 23rd
Path terminal, the 12nd control end, the 24th path terminal, the 20th three-way end receive the low reference voltage, described
12nd control end is connected with the alternate path end of the first switch element, the 24th path terminal and described
4th control end of four switch elements is connected.13rd switch element includes the 25th path terminal, the 13rd control
End processed, the 20th clematis stem terminal, the 25th path terminal receive the low reference voltage, the 13rd control end and institute
State first switch element the alternate path end be connected, the 20th clematis stem terminal with described in the 5th switch element
5th control end is connected.
Preferably, first electric capacity is the fourth passage end of the second switch element and second control end
Between parasitic capacitance.
Preferably, separate storage is provided between the second control end of the second switch element and the fourth passage end
Electric capacity, first electric capacity are described between the fourth passage end of the second switch element and second control end
Parasitic capacitance and the separate storage electric capacity sum.
Preferably, if the drive element of the grid includes N level drive element of the grid, n-th grade of drive element of the grid
First pulse signal that receives of first control end of the first switch element be with n-th grade of drive element of the grid upwards
The upper two-stage gate drive signal of the drive element of the grid output of difference two-stage, wherein, n is integer, and n >=3.
Preferably, if the drive element of the grid includes N level drive element of the grid, the institute of n-th grade of drive element of the grid
The second pulse signal for stating the 3rd control end reception of the 3rd switch element is to be differed with n-th grade of drive element of the grid downwards
The lower two-stage gate drive signal of the drive element of the grid output of two-stage, wherein, n is integer, and 0≤n≤N-2.
Preferably, when first clock signal is high level, second clock signal is low level, when described the
When one clock signal is low level, second clock signal is high level.
Preferably, first clock signal and the time that the time that second clock signal is high level is a frame.
Preferably, the dutycycle phase of first clock signal, the second clock signal and the 3rd clock signal
With.
Preferably, the first switch element is N-type transistor to the 13rd switch element.
The present invention gate driver circuit and using its display device in, rise Stabilization switch element (the 4th opens
Close element element is closed to twelvemo) receive not with the switch element (second switch element) for playing output gate drive signal effect
Same signal so that the fan-out capability of gate driver circuit is strong, and gate driver circuit includes two stable units (the 4th switches
Element, the 6th switch element, the 8th switch element, the tenth switch element and twelvemo are closed element and constitute the first stable unit,
5th switch element, the 7th switch element, the 9th switch element, the 11st switch element and the 13rd switch element constitute second
Stable unit), good stability.
By the detailed description below with reference to accompanying drawing, the other side and feature of the present invention become obvious.But should know
Road, accompanying drawing be only explain purpose design, not as the restriction of the scope of the present invention, this is because its should refer to attached
Plus claim.It should also be noted that unless otherwise noted, it is not necessary to which scale accompanying drawing, they are only tried hard to conceptually
Structure described herein and flow process are described.
Description of the drawings
Fig. 1 shows for the circuit structure of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention
It is intended to.
Time diagrams of the Fig. 2 for n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention.
Fig. 3 illustrates for the circuit structure of six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Figure.
Fig. 4 realizes forward scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.
Fig. 5 realizes reverse scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.
Fig. 6 is for the first order in the gate driver circuit of first embodiment of the invention to the 6th grade of drive element of the grid in height
The analog result schematic diagram of the output signal under ambient temperature.
Fig. 7 for first embodiment of the invention gate driver circuit in first order drive element of the grid in high environment temperature
Under output signal noise simulation result schematic diagram.
Fig. 8 for first embodiment of the invention gate driver circuit in the 740th one-level to the 720th grade of grid
The analog result schematic diagram of pole driver element output signal at a high ambient temperature.
Fig. 9 for first embodiment of the invention gate driver circuit in the 720th grade of drive element of the grid in epipodium
The noise simulation result schematic diagram of the output signal at a temperature of border.
Figure 10 exists to the 6th grade of drive element of the grid for the first order in the gate driver circuit of first embodiment of the invention
The analog result schematic diagram of the output signal under low ambient temperature.
Figure 11 for first embodiment of the invention gate driver circuit in the 740th one-level to the 720th grade
The analog result schematic diagram of drive element of the grid output signal at low ambient temperatures.
Specific embodiment
For further illustrating the present invention for reaching technological means and effect that predetermined goal of the invention is taken, below in conjunction with
Accompanying drawing and preferred embodiment, to according to display panels proposed by the present invention its specific embodiments, method, step, structure,
Feature and effect, describe in detail as after.
For the present invention aforementioned and other technology contents, feature and effect, in the following preferable reality coordinated with reference to schema
Apply in the detailed description of example and clearly can present.By the explanation of specific embodiment, when can be predetermined for reaching to the present invention
The technological means and effect taken by purpose be able to more deeply and specific understand, but institute's accompanying drawings be only to provide with reference to
Purposes of discussion, is not used for being any limitation as the present invention.
Although the present invention describes different elements, signal, port, component or portion using first, second, third, etc. term
Point, but these elements, signal, port, component or part are not limited by these terms.These terms are intended merely to one
Individual element, signal, port, component or part are made a distinction with another element, signal, port, component or part.In the present invention
In, element, port, component or part and another element, port, component or part " being connected ", " connection ", it is possible to understand that
For being directly electrically connected with, or it can be appreciated that there is the indirect electric connection of intermediary element.Unless otherwise defined, otherwise originally
All terms (including technical term and scientific terminology) that invention is used have and ordinary skill people of the art
The meaning is generally understood that by member.
The gate driver circuit (also referred to as shift register) of the present invention (is also referred to as shifted including multistage drive element of the grid
Deposit unit), the drive element of the grid per one-level is corresponding with the every a line gate line on display floater respectively to be electrically connected with, so as to
Gate drive signal is sequentially gradually applied on every row gate line, the annexation between drive element of the grid will hereinafter
Elaborate.
Fig. 1 shows for the circuit structure of n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention
It is intended to.The present embodiment gate driver circuit, including multistage drive element of the grid as shown in Figure 1, n-th grade of drive element of the grid is used
In output gate drive signal Gn, to drive a corresponding gate line on display floater respectively.As shown in figure 1, every grade of grid
Pole driver element include first switch element M1, second switch element M2, the 3rd switch element M3, the 4th switch element M4,
Five switch element M5, the 6th switch element M6, the 7th switch element M7, the 8th switch element M8, the 9th switch element M9, the tenth
Switch element M10, the 11st switch element M11, twelvemo close element M12, the 13rd switch element M13.
Wherein, the 4th switch element M4, the 6th switch element M6, the 8th switch element M8, the tenth switch element M10 and
Twelvemo is closed element M12 and constitutes the first stable unit, the 5th switch element M5, the 7th switch element M7, the 9th switch element M9,
11st switch element M11 and the 13rd switch element M13 constitutes the second stable unit.
Specifically, first switch element M1 includes the first path terminal, the first control end, alternate path end, the first path terminal
The first clock signal clk 1 is received, the first control end receives the first pulse signal Gn-2.Second switch element M2 includes threeway
Terminal, the second control end, fourth passage end, third path end receive second clock signal CLK2, and the second control end is opened with first
The alternate path end for closing element M1 is connected, and is connected with fourth passage end by the first electric capacity C1.3rd switch element M3 includes
Fifth passage end, the 3rd control end, clematis stem terminal, fifth passage end are connected with the alternate path end of first switch element M1,
3rd control end receives the second pulse signal Gn+2, and clematis stem terminal receives the 3rd clock signal clk 3.4th switch element M4
Including the 7th path terminal, the 4th control end, the 8th path terminal, the alternate path end phase of the 7th path terminal and first switch element M1
Even, the 8th path terminal receives low reference voltage VGL.
5th switch element M5 includes the 9th path terminal, the 5th control end, the tenth path terminal, and the 9th path terminal receives reference
Low-voltage VGL, the tenth path terminal are connected with the alternate path end of first switch element M1.6th switch element M6 includes the 11st
Path terminal, the 6th control end, the 12nd path terminal, the 11st path terminal are connected with the fourth passage end of second switch element M2,
6th control end is connected with the 4th control end of the 4th switch element M4, and the 12nd path terminal receives low reference voltage VGL.7th
Switch element M7 includes that the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth three-way end receive low reference voltage
VGL, the 7th control end are connected with the 5th control end of the 5th switch element M5, and the 14th path terminal is with second switch element M2's
Fourth passage end is connected.8th switch element M8 includes the 15th path terminal, the 8th control end, the tenth clematis stem terminal, the 15th
Path terminal receives the first clock signal V1, and the 8th control end is connected with the 15th path terminal, and the tenth clematis stem terminal is switched with the 4th
4th control end of element M4 is connected.9th switch element M9 includes the 17th path terminal, the 9th control end, the 18th path
End, the 17th path terminal are connected with the 5th control end of the 5th switch element M5, and the 9th control end receives the second clock signal V2,
18th path terminal is connected with the 9th control end.Tenth switch element M10 include the 19th path terminal, the tenth control end, second
Ten path terminals, the 19th path terminal receive low reference voltage VGL, and the tenth control end receives the first clock signal V1, and the 20th leads to
Terminal is connected with the 5th control end of the 5th switch element M5.
11st switch element M11 includes the 21st path terminal, the 11st control end, the 22nd path terminal, second
11 path terminals are connected with the 4th control end of the 4th switch element M4, and the 11st control end receives the second clock signal V2, the
22 path terminals receive low reference voltage VGL.Twelvemo closes element M12 includes the 20th threeway terminal, the 12nd control
End, the 24th path terminal, the 20th three-way end receive low reference voltage VGL, the 12nd control end and first switch element
The alternate path end of M1 is connected, and the 24th path terminal is connected with the 4th control end of the 4th switch element M4.13rd switch
Element M13 includes that the 25th path terminal, the 13rd control end, the 20th clematis stem terminal, the 25th path terminal receive reference
Low-voltage VGL, the 13rd control end are connected with the alternate path end of first switch element M1, and the 20th clematis stem terminal is opened with the 5th
The 5th control end for closing element M5 is connected.
Wherein, the first electric capacity C1 is the parasitism electricity between the fourth passage end of second switch element M2 and the second control end
Hold.Certainly it will be appreciated by those skilled in the art that be, it is also possible in second control end and the 4th of second switch element M2
Separate storage electric capacity is set between path terminal, now, fourth passage ends and second of the first electric capacity C1 for second switch element M2
Parasitic capacitance between control end and separate storage electric capacity sum.
In an embodiment of the present invention, if drive element of the grid includes N level drive element of the grid, and n-th grade of grid drives
The gate drive signal of moving cell output is Gn, then first control end of the first switch element M1 of n-th grade of drive element of the grid
The first pulse signal for receiving is i.e. the n-th -2 grades grid of drive element of the grid for differing two-stage with n-th grade of drive element of the grid upwards
The upper two-stage gate drive signal Gn-2 of pole driver element output, wherein, n is integer, and n >=3.
In an embodiment of the present invention, if drive element of the grid includes that N level drive element of the grid, n-th grade of grid drive
The second pulse signal that 3rd control end of the 3rd switch element M3 of moving cell is received is downward with n-th grade of drive element of the grid
The lower two-stage gate drive signal Gn+2 of i.e. the n-th+2 grades drive element of the grid outputs of drive element of the grid of difference two-stage, wherein,
N is integer, and 0≤n≤N-2.
It should be noted that due to first order drive element of the grid and second level drive element of the grid upwards differ two
The drive element of the grid of level, last two-stage drive element of the grid do not differ downwards the drive element of the grid of two-stage, so first
The of first pulse signal and the last two-stage drive element of the grid of level drive element of the grid level and second level drive element of the grid
Two pulse signals are intended to be provided by external signal circuit.
In the present embodiment, first switch element is N-type transistor to the 13rd switch element M1～M13.First control
It is grid to hold to the 13rd control end.First path terminal of first switch element M1, the third path end of second switch element M2,
The fifth passage end of the 3rd switch element M3, the 7th path terminal of the 4th switch element M4, the tenth of the 5th switch element M5 the are led to
Terminal, the 11st path terminal of the 6th switch element M6, the 14th path terminal of the 7th switch element M7, the 8th switch element M8
The 15th path terminal, the 18th path terminal of the 9th switch element M9, the 20th path terminal of the tenth switch element M10,
21st path terminal of 11 switch element M11, twelvemo close the 24th path terminal of element M12, the 13rd switch
The 20th clematis stem terminal of element M13 is drain electrode.The alternate path end of first switch element M1, the of second switch element M2
Four path terminals, the clematis stem terminal of the 3rd switch element M3, the 8th path terminal of the 4th switch element M4, the 5th switch element M5
The 9th path terminal, the 12nd path terminal of the 6th switch element M6, the tenth threeway terminal of the 7th switch element M7, the 8th open
The tenth clematis stem terminal of pass element M8, the 17th path terminal of the 9th switch element M9, the 19th of the tenth switch element M10 the lead to
Terminal, the 22nd path terminal of the 11st switch element M11, twelvemo close the 20th threeway terminal of element M12 and the
25th path terminal of 13 switch element M13 is source electrode.
Certainly, it will be appreciated by persons skilled in the art that first switch element is to the 13rd switch element M1～M13
Can be realized, such as P-type transistor using other switch elements.Below with first switch element M1 to the 13rd switches unit
Part M1～M13 specifically introduces the specific embodiment and its operation principle of the present invention for as a example by N-type transistor.
Refer to Fig. 2, its be n-th grade of drive element of the grid in the gate driver circuit of first embodiment of the invention when
Sequence schematic diagram.As shown in Fig. 2 the first clock signal clk 1 and second clock signal CLK2 and the duty of the 3rd clock signal clk 3
Than identical, its dutycycle is 1/3rd.
In an embodiment of the present invention, the first clock signal V1 and the second clock signal V2 is one for the time of high level
The time of frame, and the first clock signal V1 replaced with the second clock signal V2 as high level, that is to say, that in the time of this frame
In the first clock signal V1 be high level, then in the time of next frame, the second clock signal V2 is high level, and when first
When sequential signal V1 is high level, the second clock signal V2 is low level, when the first clock signal V1 is low level, the second sequential
Signal V2 is high level.
In an embodiment of the present invention, as the load that the first clock signal V1 drives is larger, therefore, the first sequential is believed
The moment of the trailing edge of the rising edge and the second clock signal of number V1 differs the grid of two-stage upwards early than n-th grade of drive element of the grid
The moment of the rising edge of the upper two-stage gate drive signal Gn-2 of i.e. the n-th -2 grades drive element of the grid outputs of pole driver element.
It is divided into pre-charging stage, pull-up stage, drop-down stage, stabilization sub stage per the course of work of one-level drive element of the grid
4 stages：
Pre-charging stage is the first stage：The first pulse signal that first control end of first switch element M1 is received i.e. to
The upper two-stage gate drive signal Gn-2 of the drive element of the grid output of upper difference two-stage is high level, and first switch element M1 leads
Logical, when the first clock signal clk 1 is high level, the voltage at node Q is by the first switch element M1 of conducting by preliminary filling
Electricity；As the voltage at node Q is precharged, twelvemo closes element M12 and the 13rd switch element M13 conductings, node Qb1
And the 13rd switch element M13 that node Qb2 closes element M12 and conducting by the twelvemo for turning on respectively is pulled low to reference
Low-voltage VGL.
The pull-up stage is second stage：When the level of second clock signal CLK2 is by low uprising, due in pre-charging stage
Node Q has been precharged, and therefore, second switch element M2 is turned on, due to the conducting of second switch element M2, and due to first
The boot strap of electric capacity C1, the voltage at node Q are further pulled up so that second switch element M2 is conductively more abundant,
So that the gate drive signal Gn of this grade of drive element of the grid outfan by the second switch element M2 of conducting by second
Clock signal clk 2 is drawn high.
It should be noted that in the present invention, can directly using the fourth passage end and second of second switch element M2
Parasitic capacitance between control end as the first electric capacity C1, or in order to lift pull-up effect, can be with second switch element
Separate storage electric capacity, wherein, the separate storage electric capacity and second switch are set between second control end of M2 and fourth passage end
The parasitic capacitance in parallel of element M2 and collectively as the first electric capacity C1, i.e. the first electric capacity C1 be equal to second switch element M2 the 4th
Parasitic capacitance between path terminal and the second control end and separate storage electric capacity sum.
The drop-down stage is the phase III：Second clock signal CLK2 is changed into low level from high level, due in the pull-up stage
At node Q, voltage is further pulled up, and element M2 is in the conduction state for second switch, this grade of drive element of the grid outfan is defeated
The gate drive signal Gn for going out is pulled low by the second switch element M2 for turning on；Meanwhile, the second pulse signal is differed downwards
The gate drive signal Gn+2 of the lower two-stage of the drive element of the grid output of two-stage is changed into high level from low level, the 3rd switch unit
Part M3 is turned on, therefore, when the 3rd clock signal clk 3 is that the voltage at node Q is by conducting when high level is changed into low level
The 3rd switch element M3 be pulled low.
Stabilization sub stage is fourth stage：As the first clock signal V1 and the second clock signal V2 is alternately high level, because
This, node Qb1 and node Qb2 are alternately high level, therefore, the 4th switch element M4 and the 5th switch element M5 alternate conductions, from
And cause the voltage at node Q to be pulled low to reference by the 4th switch element M4 of conducting or the 5th switch element M5 of conducting
Low-voltage VGL, additionally, the 6th switch element M6 and the 7th switch element M7 alternate conductions, so that gate drive signal Gn
Low reference voltage VGL is pulled low to by the 6th switch element M6 of conducting or the 7th switch element M7 of conducting.
By taking six grades of drive element of the grid as an example, as shown in figure 3, which describing first order drive element of the grid R1, the second level
Drive element of the grid R2, third level drive element of the grid R3, fourth stage drive element of the grid R4, level V drive element of the grid
R5, the driving principle of the 6th grade of drive element of the grid R6, wherein, every one-level drive element of the grid shown in Fig. 3 be used for receiving to
The upper two-stage gate drive signal Gn-2 of the drive element of the grid output of upper difference two-stage, and the raster data model of difference two-stage downwards
The lower two-stage gate drive signal Gn+2 of unit output.And as shown in figure 3, first order drive element of the grid R1 and second level grid
Driver element R2 does not differ the drive element of the grid of two-stage upwards, and therefore, first order drive element of the grid R1 is received outside first
The signal that portion's signal source STV1 is provided receives the second outside source as the first pulse signal, second grid driver element R2
STV2 provide signal as the first pulse signal.Level V drive element of the grid R5 and the 6th grade of drive element of the grid not to
The drive element of the grid of lower difference two-stage, therefore, level V drive element of the grid R5 receives the 3rd outside source STV3 and provides
Signal as the second pulse signal, the 6th drive element of the grid R6 receives the signal conduct that the 4th outside source STV4 is provided
Second pulse signal.
Fig. 4 realizes forward scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.As shown in figure 4, first order drive element of the grid R1, second level drive element of the grid R2, third level raster data model
Unit R 3, fourth stage drive element of the grid R4, level V drive element of the grid R5, the 6th grade of drive element of the grid R6 receive the
One pulse signal is changed into high level from low level successively, therefore first order drive element of the grid R1, second level drive element of the grid
R2, third level drive element of the grid R3, fourth stage drive element of the grid R4, level V drive element of the grid R5, the 6th grade of grid
Driver element R6 is sequentially output gate drive signal Gn, so as to drive corresponding gate line successively, to realize forward scan.
Fig. 5 realizes reverse scan for six grades of drive element of the grid in the gate driver circuit of first embodiment of the invention
Time diagram.As shown in figure 5, the 6th grade of drive element of the grid R6, level V drive element of the grid R5, fourth stage raster data model
Unit R 4, third level drive element of the grid R3, second level drive element of the grid R2, first order drive element of the grid R1 receive the
One pulse signal is changed into high level from low level successively, therefore the 6th grade of drive element of the grid R6, level V drive element of the grid
R5, fourth stage drive element of the grid R4, third level drive element of the grid R3, second level drive element of the grid R2, first order grid
Driver element R1 is sequentially output gate drive signal Gn, so as to realize reverse scan.
Fig. 6 is for the first order in the gate driver circuit of first embodiment of the invention to the 6th grade of drive element of the grid in height
The analog result schematic diagram of the output signal under ambient temperature.During Fig. 8 is for the gate driver circuit of first embodiment of the invention
740th one-level is shown to the analog result of the 720th grade of drive element of the grid output signal at a high ambient temperature
It is intended to.Fig. 6 and Fig. 8 is please also refer to, the drive element of the grid of the gate driver circuit of the present invention still can be exported at high temperature
Stable gate drive signal such as first order drive element of the grid exports stable first order gate drive signal G1, the second level
Drive element of the grid exports stable second level gate drive signal G2, third level drive element of the grid and exports the stable third level
Gate drive signal G3, fourth stage drive element of the grid export stable fourth stage gate drive signal G4, level V grid and drive
Moving cell exports stable level V gate drive signal G5, the 6th grade of drive element of the grid and exports the 6th grade of stable grid and drive
Dynamic signal G6, good stability.
Fig. 7 for first embodiment of the invention gate driver circuit in first order drive element of the grid in high environment temperature
Under output signal noise simulation result schematic diagram.Fig. 9 is the 7th in the gate driver circuit of first embodiment of the invention
The noise simulation result schematic diagram of 120 grades of drive element of the grid output signal at a high ambient temperature.Please also refer to figure
7 and Fig. 9, the noise of gate driver circuit of the invention gate drive signal stable at high temperature is less, and the such as the 702nd
The noise negative sense of ten grades of drive element of the grid output gate drive signal at a high ambient temperature is poor with the maximum of positive-going noise
Only about 0.17019 volt of value dY.
Figure 10 exists to the 6th grade of drive element of the grid for the first order in the gate driver circuit of first embodiment of the invention
The analog result schematic diagram of the output signal under low ambient temperature.During Figure 11 is for the gate driver circuit of first embodiment of the invention
The 740th one-level to the 720th grade of drive element of the grid output signal at low ambient temperatures analog result
Schematic diagram.Figure 10 and Figure 11 is please also refer to, the gate driver circuit of the present invention still can export stable grid at low temperature
Drive signal, good stability.
The present invention also provides a kind of display device, and which includes that gate driver circuit, gate driver circuit include multistage such as Fig. 1
Shown drive element of the grid, n-th grade of drive element of the grid are used for exporting gate drive signal Gn, to drive display floater respectively
On a corresponding gate line.As shown in figure 1, every grade of drive element of the grid includes first switch element M1, second switch unit
Part M2, the 3rd switch element M3, the 4th switch element M4, the 5th switch element M5, the 6th switch element M6, the 7th switch element
M7, the 8th switch element M8, the 9th switch element M9, the tenth switch element M10, the 11st switch element M11, twelvemo are closed
Element M12, the 13rd switch element M13.
Wherein, the 4th switch element M4, the 6th switch element M6, the 8th switch element M8, the tenth switch element M10 and
Twelvemo is closed element M12 and constitutes the first stable unit, the 5th switch element M5, the 7th switch element M7, the 9th switch element M9,
11st switch element M11 and the 13rd switch element M13 constitutes the second stable unit.
Specifically, first switch element M1 includes the first path terminal, the first control end, alternate path end, the first path terminal
The first clock signal clk 1 is received, the first control end receives the first pulse signal Gn-2.Second switch element M2 includes threeway
Terminal, the second control end, fourth passage end, third path end receive second clock signal CLK2, and the second control end is opened with first
The alternate path end for closing element M1 is connected, and is connected with fourth passage end by the first electric capacity C1.3rd switch element M3 includes
Fifth passage end, the 3rd control end, clematis stem terminal, fifth passage end are connected with the alternate path end of first switch element M1,
3rd control end receives the second pulse signal Gn+2, and clematis stem terminal receives the 3rd clock signal clk 3.4th switch element M4
Including the 7th path terminal, the 4th control end, the 8th path terminal, the alternate path end phase of the 7th path terminal and first switch element M1
Even, the 8th path terminal receives low reference voltage VGL.
5th switch element M5 includes the 9th path terminal, the 5th control end, the tenth path terminal, and the 9th path terminal receives reference
Low-voltage VGL, the tenth path terminal are connected with the alternate path end of first switch element M1.6th switch element M6 includes the 11st
Path terminal, the 6th control end, the 12nd path terminal, the 11st path terminal are connected with the fourth passage end of second switch element M2,
6th control end is connected with the 4th control end of the 4th switch element M4, and the 12nd path terminal receives low reference voltage VGL.7th
Switch element M7 includes that the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth three-way end receive low reference voltage
VGL, the 7th control end are connected with the 5th control end of the 5th switch element M5, and the 14th path terminal is with second switch element M2's
Fourth passage end is connected.8th switch element M8 includes the 15th path terminal, the 8th control end, the tenth clematis stem terminal, the 15th
Path terminal receives the first clock signal V1, and the 8th control end is connected with the 15th path terminal, and the tenth clematis stem terminal is switched with the 4th
4th control end of element M4 is connected.9th switch element M9 includes the 17th path terminal, the 9th control end, the 18th path
End, the 17th path terminal are connected with the 5th control end of the 5th switch element M5, and the 9th control end receives the second clock signal V2,
18th path terminal is connected with the 9th control end.Tenth switch element M10 include the 19th path terminal, the tenth control end, second
Ten path terminals, the 19th path terminal receive low reference voltage VGL, and the tenth control end receives the first clock signal V1, and the 20th leads to
Terminal is connected with the 5th control end of the 5th switch element M5.
11st switch element M11 includes the 21st path terminal, the 11st control end, the 22nd path terminal, second
11 path terminals are connected with the 4th control end of the 4th switch element M4, and the 11st control end receives the second clock signal V2, the
22 path terminals receive low reference voltage VGL.Twelvemo closes element M12 includes the 20th threeway terminal, the 12nd control
End, the 24th path terminal, the 20th three-way end receive low reference voltage VGL, the 12nd control end and first switch element
The alternate path end of M1 is connected, and the 24th path terminal is connected with the 4th control end of the 4th switch element M4.13rd switch
Element M13 includes that the 25th path terminal, the 13rd control end, the 20th clematis stem terminal, the 25th path terminal receive reference
Low-voltage VGL, the 13rd control end are connected with the alternate path end of first switch element M1, and the 20th clematis stem terminal is opened with the 5th
The 5th control end for closing element M5 is connected.
The present invention gate driver circuit and using its display device in, rise Stabilization switch element (the 4th opens
Close element element M4～M12 is closed to twelvemo) and play switch element (the second switch element that output gate drive signal is acted on
M2 different signals are received) so that the fan-out capability of gate driver circuit is strong, and gate driver circuit includes two stable units
(the 4th switch element M4, the 6th switch element M6, the 8th switch element M8, the tenth switch element M10 and twelvemo close element
M12 constitutes the first stable unit, the 5th switch element M5, the 7th switch element M7, the 9th switch element M9, the 11st switch unit
Part, the 11 and the 13rd switch element M13 constitute the second stable unit), good stability.
The above, is only presently preferred embodiments of the present invention, not makees any pro forma restriction to the present invention, though
So the present invention is disclosed above with preferred embodiment, but is not limited to the present invention, any is familiar with this professional technology people
Member, in the range of without departing from technical solution of the present invention, when the technology contents using the disclosure above make a little change or modification
For the Equivalent embodiments of equivalent variations, as long as being without departing from technical solution of the present invention content, according to the technical spirit pair of the present invention
Any simple modification, equivalent variations and modification that above example is made, still fall within the range of technical solution of the present invention.
Claims (8)
1. a kind of gate driver circuit, including multiple drive element of the grid, wherein every grade drive element of the grid is used for driving respectively
A corresponding gate line on display floater, it is characterised in that every grade of drive element of the grid includes：
First switch element, including the first path terminal, the first control end, alternate path end, first path terminal receives first
Clock signal, first control end receive the first pulse signal；
Second switch element, including third path end, the second control end, fourth passage end, the third path end receives second
Clock signal, second control end are connected with the alternate path end of the first switch element, and pass through the first electric capacity
It is connected with the fourth passage end；
3rd switch element, including fifth passage end, the 3rd control end, clematis stem terminal, the fifth passage end and described
The alternate path end of one switch element is connected, and the 3rd control end receives the second pulse signal, and clematis stem terminal is received
3rd clock signal；
4th switch element, including the 7th path terminal, the 4th control end, the 8th path terminal, the 7th path terminal and described
The alternate path end of one switch element is connected, and the 8th path terminal receives low reference voltage；
5th switch element, including the 9th path terminal, the 5th control end, the tenth path terminal, the 9th path terminal receives described
Low reference voltage, the tenth path terminal are connected with the alternate path end of the first switch element；
6th switch element, including the 11st path terminal, the 6th control end, the 12nd path terminal, the 11st path terminal with
The fourth passage end of the second switch element is connected, and described the of the 6th control end and the 4th switch element
Four control ends are connected, and the 12nd path terminal receives the low reference voltage；
7th switch element, including the tenth threeway terminal, the 7th control end, the 14th path terminal, the tenth three-way termination
The low reference voltage is received, the 7th control end is connected with the 5th control end of the 5th switch element, described
14 path terminals are connected with the fourth passage end of the second switch element；
8th switch element, including the 15th path terminal, the 8th control end, the tenth clematis stem terminal, the 15th path termination
The first clock signal is received, the 8th control end is connected with the 15th path terminal, the tenth clematis stem terminal and described
4th control end of four switch elements is connected；
9th switch element, including the 17th path terminal, the 9th control end, the 18th path terminal, the 17th path terminal with
5th control end of the 5th switch element is connected, the second clock signal of the 9th control end reception, and the described tenth
Eight path terminals are connected with the 9th control end；
Tenth switch element, including the 19th path terminal, the tenth control end, the 20th path terminal, the 19th path termination
Receive the low reference voltage, the tenth control end receives first clock signal, the 20th path terminal and described the
5th control end of five switch elements is connected；
11st switch element, including the 21st path terminal, the 11st control end, the 22nd path terminal, the described 20th
One path terminal is connected with the 4th control end of the 4th switch element, when the 11st control end receives described second
Sequential signal, the 22nd path terminal receive the low reference voltage；
Twelvemo closes element, including the 20th threeway terminal, the 12nd control end, the 24th path terminal, the described 20th
Three-way end receives the low reference voltage, the alternate path end of the 12nd control end and the first switch element
It is connected, the 24th path terminal is connected with the 4th control end of the 4th switch element；And
13rd switch element, including the 25th path terminal, the 13rd control end, the 20th clematis stem terminal, the described 20th
Five path terminals receive the low reference voltage, the alternate path end of the 13rd control end and the first switch element
It is connected, the 20th clematis stem terminal is connected with the 5th control end of the 5th switch element；
Wherein, if the drive element of the grid includes N level drive element of the grid, described the first of n-th grade of drive element of the grid
The first pulse signal that first control end of switch element is received is to differ two-stage upwards with n-th grade of drive element of the grid
The upper two-stage gate drive signal of drive element of the grid output, the of the 3rd switch element of n-th grade of drive element of the grid
The second pulse signal that three control ends are received is the drive element of the grid output for differing downwards two-stage with n-th grade of drive element of the grid
Lower two-stage gate drive signal, wherein, n is integer, and 3≤n≤N-2.
2. gate driver circuit as claimed in claim 1, it is characterised in that first electric capacity is the second switch element
The fourth passage end and second control end between parasitic capacitance.
3. gate driver circuit as claimed in claim 1, it is characterised in that second control of the second switch element
Separate storage electric capacity is provided between end and the fourth passage end, first electric capacity is the described of the second switch element
The parasitic capacitance between fourth passage end and second control end and the separate storage electric capacity sum.
4. gate driver circuit as claimed in claim 1, it is characterised in that when first clock signal is high level,
Second clock signal is low level, and when first clock signal is low level, second clock signal is high electricity
Flat.
5. gate driver circuit as claimed in claim 4, it is characterised in that first clock signal and second sequential
Signal is the time that the time of high level is a frame.
6. gate driver circuit as claimed in claim 1, it is characterised in that first clock signal, the second clock
The dutycycle of signal and the 3rd clock signal is identical.
7. gate driver circuit as claimed in claim 1, it is characterised in that the first switch element is opened to the described 13rd
Close element and be N-type transistor.
8. a kind of display device, it is characterised in that include the gate driver circuit as described in claim 1～7 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510075980.6A CN104637461B (en) | 2015-02-12 | 2015-02-12 | A kind of gate driver circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510075980.6A CN104637461B (en) | 2015-02-12 | 2015-02-12 | A kind of gate driver circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104637461A CN104637461A (en) | 2015-05-20 |
| CN104637461B true CN104637461B (en) | 2017-03-15 |
Family
ID=53216135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510075980.6A Active CN104637461B (en) | 2015-02-12 | 2015-02-12 | A kind of gate driver circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104637461B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118456B (en) * | 2015-08-31 | 2017-11-03 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and the display device with the gate driving circuit |
| CN105185341B (en) * | 2015-10-09 | 2017-12-15 | 昆山龙腾光电有限公司 | A kind of gate driving circuit and use its display device |
| CN105469756B (en) * | 2015-12-07 | 2018-01-30 | 武汉华星光电技术有限公司 | GOA circuits based on LTPS semiconductor thin-film transistors |
| CN106601201B (en) * | 2016-12-09 | 2019-06-11 | 昆山龙腾光电有限公司 | Gate driving circuit |
| CN107564449B (en) * | 2017-09-13 | 2020-12-01 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
| CN109326256B (en) * | 2018-11-20 | 2021-11-02 | 昆山龙腾光电股份有限公司 | Gate drive circuit and display device |
| CN109448657A (en) * | 2018-12-26 | 2019-03-08 | 惠科股份有限公司 | Shift registor and gate driving circuit |
| CN110599955B (en) * | 2019-09-19 | 2021-02-09 | 昆山工研院新型平板显示技术中心有限公司 | Display panel and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9153341B2 (en) * | 2005-10-18 | 2015-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Shift register, semiconductor device, display device, and electronic device |
| CN103646636B (en) * | 2013-12-18 | 2015-11-25 | 合肥京东方光电科技有限公司 | Shift register, gate driver circuit and display device |
| TWI517117B (en) * | 2014-01-20 | 2016-01-11 | 友達光電股份有限公司 | Shift register and control method thereof |
| CN104299594B (en) * | 2014-11-07 | 2017-02-15 | 京东方科技集团股份有限公司 | Shifting register unit, gate driving circuit and display device |
-
2015
- 2015-02-12 CN CN201510075980.6A patent/CN104637461B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104637461A (en) | 2015-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104637461B (en) | A kind of gate driver circuit and display device | |
| CN104867472B (en) | A kind of shift register cell, gate driving circuit and display device | |
| CN104715732B (en) | Grid driving circuit and display device | |
| CN105632441B (en) | Gate driving circuit | |
| CN105261341B (en) | A kind of gate driving circuit and display device | |
| CN103208251B (en) | A kind of shift register cell, gate driver circuit and display device | |
| CN104715730B (en) | A kind of gate driving circuit and display device | |
| CN107633833A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN105788553B (en) | GOA circuits based on LTPS semiconductor thin-film transistors | |
| CN105225635B (en) | Array base palte horizontal drive circuit, shift register, array base palte and display | |
| CN103489422B (en) | Gate driver circuit | |
| CN103151013B (en) | Gate driver circuit | |
| CN103996390B (en) | A kind of gate driver circuit and the display device using which | |
| CN107358906A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN110211547A (en) | A kind of display panel, its driving method and display device | |
| CN103854622A (en) | Gate drive circuit | |
| CN104766573B (en) | Gate drive circuit and display device | |
| CN105321491B (en) | Gate driving circuit and the liquid crystal display using gate driving circuit | |
| CN103617784B (en) | A kind of gate driver circuit and use its display device | |
| CN103680458B (en) | Gate driver circuit | |
| CN106601178A (en) | Shift register unit and driving method thereof, grid driving circuit and display apparatus | |
| CN112673417B (en) | Display panel, display device and driving method | |
| CN105185341B (en) | A kind of gate driving circuit and use its display device | |
| CN208834749U (en) | A kind of shift register, gate driving circuit and display device | |
| CN104732935B (en) | Gate driving unit and display device with gate drive unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee after: Kunshan Longteng Au Optronics Co Address before: 215301, 1, Longteng Road, Kunshan, Jiangsu, Suzhou Patentee before: Kunshan Longteng Optronics Co., Ltd. |