CN109448657A - Shift registor and gate driving circuit - Google Patents
Shift registor and gate driving circuit Download PDFInfo
- Publication number
- CN109448657A CN109448657A CN201811600792.0A CN201811600792A CN109448657A CN 109448657 A CN109448657 A CN 109448657A CN 201811600792 A CN201811600792 A CN 201811600792A CN 109448657 A CN109448657 A CN 109448657A
- Authority
- CN
- China
- Prior art keywords
- pull
- node
- signal
- connect
- shift registor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
This application involves a kind of shift registor and gate driving circuits.Shift registor includes pull-up circuit, output circuit, pull-down circuit, the first pull-down control circuit and the second pull-down control circuit.First pull-down control circuit responds high level signal, high level signal is supplied to drop-down control node, in response to pulling down the voltage signal of control node, high level signal is supplied to pull-down node, and the voltage signal in response to switching signal and pull-up node, and low level signal is respectively supplied to pull-down node and drop-down control node.Low level signal is supplied to pull-down circuit in response to the voltage signal of pull-up node by the second pull-down control circuit.Low level signal is respectively supplied to the pull-up node and the first output end of the shift registor, in response to the voltage signal of the first pulldown signal, the second pulldown signal and the pull-down node to improve noise reduction effect by pull-down circuit.
Description
Technical field
This application involves display field more particularly to a kind of shift registors and gate driving circuit.
Background technique
Thin film transistor liquid crystal display (Thin Film Transistor Liquid Crystal Display, TFT-
LCD) driver mainly includes gate driving circuit and data drive circuit, wherein gate driving circuit believes the clock of input
Number by shift registor convert after be added on the grid line of liquid crystal display panel, gate driving circuit can with TFT formed have
Same process is simultaneously simultaneously formed together on the lcd panel with TFT.Gate driving circuit includes the shift registor with multistage,
Every grade of shift registor is all connected to corresponding grid line to export gate drive signal.The phases each other at different levels of gate driving circuit
Even, initial signal is input to the exporting gate drive signal to grid line of the first order at different levels and sequence, wherein current n-th
The input terminal of grade is connected to the n-th -2 grades of output end, and the first pulldown signal input terminal is connected to the n-th+4 grades of output end, and second
Pulldown signal input terminal is connected to the pull-down node of bottom n-1, and first switch signal input part connects (n-1)th grade of pull-up node,
Second switch signal input part connects (n+1)th grade of pull-up node.
In the gate driving circuit of LCD panel setting above structure, at present gate driving circuit design, when clock signal
A cycle signal, within the non-output period, when the clock signal is high level, due to the coupling of output end switching tube
Effect can generate noise in output end, influence signal output quality.
Summary of the invention
Based on this, this application provides a kind of shift registor and gate driving circuits, to improve noise reduction effect.
The embodiment of the present application provides a kind of shift registor, comprising:
Pull-up circuit connects the input signal end of the shift registor, to respond input signal, and by the input
Signal is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, to respond the electricity of the pull-up node
Signal is pressed, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit, the first pulldown signal input terminal of connection, the second pulldown signal input terminal and pull-down node, to sound
The voltage signal of the first pulldown signal, the second pulldown signal and the pull-down node is answered, and low level signal is provided respectively
First output end of pull-up node and the shift registor to the shift registor；
First pull-down control circuit, connection high level signal input terminal, switch signal input end, drop-down control node, institute
Pull-down node and the pull-up node are stated, to respond the high level signal, the high level signal is supplied to described
Control node is pulled down, the voltage signal of the drop-down control node is responded, the high level signal is supplied to the drop-down and is saved
The voltage signal of point and responding to switch signal and the pull-up node, and the low level signal is respectively supplied to described
Pull-down node and the drop-down control node；And
Second pull-down control circuit, the pull-up node and the second pulldown signal input terminal, to respond on described
The voltage signal for drawing node, is supplied to the second pulldown signal input terminal for the low level signal.
Second pull-down control circuit includes: in one of the embodiments,
Sixteenmo closes pipe, and grid connects the pull-up node, and drain electrode connects the second pulldown signal input terminal, source electrode
It is connect with the low level voltage signal input part.
First pull-down control circuit includes: in one of the embodiments,
First switch branch, connection switch signal input part, the drop-down control node and the pull-down node, to sound
The switching signal is answered, and the low level signal is respectively supplied to the pull-down node and the drop-down control node；
Second switch branch connects the pull-up node, the drop-down control node and the pull-down node, to respond
The voltage signal of the pull-up node, and the low level signal is respectively supplied to the pull-down node and drop-down control
Node；And
Drop-down input branch, connects the high level signal input terminal, the drop-down control node and the pull-down node,
To respond the high level signal, the high level signal is supplied to the drop-down control node, and under response is described
The voltage signal for drawing control node, is supplied to the pull-down node for the high level signal.
The pull-down circuit includes: in one of the embodiments,
First drop-down branch, connects the first pulldown signal input terminal, to respond first pulldown signal, and will
Low level signal is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；
Second drop-down branch, connects the second pulldown signal input terminal, to respond second pulldown signal, and will
Low level signal is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；And
Third pulls down branch, connects the pull-down node, to respond the voltage signal of the pull-down node, and by low electricity
Ordinary mail number is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor.
The pull-up circuit includes: in one of the embodiments,
First switch tube T1, grid and drain electrode are connect with the input signal end, and source electrode is connect with the pull-up node.
The output circuit includes: in one of the embodiments,
Second switch, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and institute
State the first output end connection of shift registor；
Third switching tube, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and institute
State the second output terminal connection of shift registor；And
Capacitor, one end are connect with the pull-up node, and the other end is connect with the first output end of the shift registor.
The first drop-down branch includes: in one of the embodiments,
4th switching tube, grid are connect with the first pulldown signal input terminal, drain electrode and the of the shift registor
One output end and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
5th switching tube, grid are connect with the first pulldown signal input terminal, and drain electrode is connect with the pull-up node, source
Pole is connect with the low level voltage signal input part；
Described second, which pulls down branch, includes:
6th switching tube, grid are connect with the second pulldown signal input terminal, drain electrode and the of the shift registor
One output end and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
7th switching tube, grid are connect with the second pulldown signal input terminal, and drain electrode is connect with the pull-up node, source
Pole is connect with the low level voltage signal input part；
The third pulls down branch
8th switching tube, grid are connect with the pull-down node, drain electrode and the first output end of the shift registor with
And the capacitance connection, source electrode are connect with the low level voltage signal input part；And
9th switching tube, grid are connect with the pull-down node, drain electrode connect with the pull-up node, source electrode with it is described low
The connection of level voltage signal input terminal.
The drop-down input branch includes: in one of the embodiments,
Tenth switching tube, grid and drain electrode are connect with the high level signal input terminal, and source electrode and the drop-down control
Node connection；And
11st switching tube, grid are connect with the drop-down control node, and drain electrode connects with the high level signal input terminal
It connects, source electrode is connect with the pull-down node；
The first switch branch includes:
12nd switching tube, grid are connect with the switch signal input end, and drain electrode is connect with the drop-down control node,
Source electrode is connect with the low level signal input terminal；And
13rd switching tube, grid are connect with the switch signal input end, and drain electrode is connect with pull-down node, source electrode and institute
State the connection of low level signal input terminal；
The second switch branch includes:
14th switching tube, grid are connect with the pull-up node, drain electrode connect with the drop-down control node, source electrode and
The low level signal input terminal connection；And
15th switching tube, grid are connect with the pull-up node, and drain electrode is connect with pull-down node, source electrode and the low electricity
Flat signal input part connection.
The switching tube is field-effect tube or is triode in one of the embodiments,.
Based on the same inventive concept, present invention also provides a kind of gate driving circuit, including cascade displacement at different levels are temporary
Storage, the shift registor include:
Pull-up circuit connects the second output terminal of the n-th -2 grades shift registors, temporary to respond the n-th -2 grades displacements
The output signal of storage, and the output signal of the n-th -2 grades shift registors is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, to respond the electricity of the pull-up node
Signal is pressed, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit connects the clock signal input terminal of (n-1)th grade of shift registor, the drop-down section of the shift registor
First output end of point and the n-th+2 grades shift registors, it is defeated to respond the n-th+2 grades shift registors, first output end
Voltage signal out, and by low level signal be respectively supplied to the shift registor pull-up node and the shift registor the
One output end；
First pull-down control circuit, connection high level signal input terminal, the pull-up node of (n-1)th grade of shift registor, institute
The pull-up node, drop-down control node and the pull-down node for stating shift registor, to respond the high level signal, by institute
It states high level signal and is supplied to the drop-down control node, respond the voltage signal of the drop-down control node, by the high electricity
Ordinary mail number is supplied to the pull-down node, and the voltage signal of pull-up node of (n-1)th grade of shift registor of response and described
The voltage signal of the pull-up node of shift registor, by the low level signal be respectively supplied to the pull-down node and it is described under
Draw control node；And
Second pull-down control circuit, connect the shift registor pull-up node and (n-1)th grade of buffer when
The low level signal is supplied to described (n-1)th grade to respond the voltage signal of the pull-up node by clock signal input part
The clock signal input terminal of buffer；
Wherein, 2 < n < N-2, N is grid line quantity, and n and N are positive integer.
To sum up, this application provides a kind of shift registor and gate driving circuits.The shift registor includes pull-up
Circuit, output circuit, pull-down circuit, the first pull-down control circuit and the second pull-down control circuit.The pull-up circuit connects institute
The input signal end for stating shift registor is supplied to pull-up node to respond input signal, and by the input signal.It is described
Output circuit connects the pull-up node and clock signal input terminal, to respond the voltage signal of the pull-up node, and
Clock signal is supplied to the first output end and second output terminal of the shift registor.Under the pull-down circuit connection first
Signal input part, the second pulldown signal input terminal and pull-down node are drawn, to respond the first pulldown signal, the second pulldown signal
And the voltage signal of the pull-down node, and low level signal is respectively supplied to the pull-up node of the shift registor and is somebody's turn to do
First output end of shift registor.First pull-down control circuit, connection high level signal input terminal, switching signal input
End, drop-down control node, the pull-down node and the pull-up node, to respond the high level signal, by the height
Level signal is supplied to the drop-down control node, responds the voltage signal of the drop-down control node, the high level is believed
Number it is supplied to the voltage signal of the pull-down node and responding to switch signal and the pull-up node, and by the low level
Signal is respectively supplied to the pull-down node and the drop-down control node.Second pull-down control circuit connects the pull-up
Node and the second pulldown signal input terminal, to respond the voltage signal of the pull-up node, by the low level signal
It is supplied to the second pulldown signal input terminal.In the application, in output stage, by second pull-down control circuit to
Second pulldown signal input terminal of two drop-down branches discharges, and guarantees the first output end normal output signal；Non- defeated
Stage out, when the clock signal of input is high level, by the second drop-down branch to the pull-up node and the first output
End is discharged, to improve noise reduction effect.
Detailed description of the invention
Fig. 1 is the electrical structure schematic diagram of exemplary display panel；
Fig. 2 is thompson electrical block diagram；
Fig. 3 is the charging process schematic diagram of pull-up node in thompson circuit；
Fig. 4 is the electrical block diagram of illustrative shift registor；
Fig. 5 is the electrical block diagram of the shift registor of another exemplary；
Fig. 6 is the timing diagram of each signal end of the shift registor in Fig. 5；
Fig. 7 is a kind of electrical block diagram of shift registor provided by the embodiments of the present application；
Fig. 8 is a kind of cascade structure schematic diagram of gate driving circuit provided by the present application；
Fig. 9 is the timing diagram of each signal end of the shift registor in Fig. 7.
Specific embodiment
In order to make the above objects, features, and advantages of the present application more apparent, with reference to the accompanying drawing to the application
Specific embodiment be described in detail.Many details are explained in the following description in order to fully understand this Shen
Please.But the application can be implemented with being much different from other way described herein, those skilled in the art can be not
Similar improvement is done in the case where violating the application intension, therefore the application is not limited by following public specific implementation.
Referring to Figure 1, shift registor is an important technology in panel design, and major advantage is can to replace
Grid drive chip (Gate driver IC), reduces production cost, is mainly exactly to generate logic by exposure development technology
Circuit is to drive grid signal.
Fig. 2 and Fig. 3 are referred to, gate driving circuit is developed on the basis of thompson circuit at present,
In scanning process, can all there be a preliminary filling signal to carry out preliminary filling to the point at pull-up node Q (boost point), so that the point
Voltage signal increase lofty perch position, and then be connected respective switch pipe export clock signal.
Fig. 4 and Fig. 5 are referred to, general shift registor includes main circuit, secondary pull-down circuit and secondary drop-down control electricity
Road.By taking the fourth stage shift registor during the gate driving circuit being made of 8 cascade shift registors is as an example, the 4th
The shift registor that grade moves gate driving circuit is only high electricity in the voltage signal and its clock signal CK4 when its pull-up node
Scanning signal is usually exported, to realize grid line turntable driving function.But in non-output stage, when in the shift registor
When clock signal CK (n) is high level signal, Fig. 6 is referred to, since the coupling of output end switching tube is occasionally used, may result in
Node and output end is drawn to generate noise, and then the signal quality exported.
To reduce noise to improve signal quality, this application provides a kind of shift registors, refer to Fig. 7.The shifting
Position buffer includes pull-up circuit 100, output circuit 200, pull-down circuit 300, the first pull-down control circuit 400 and the second drop-down
Control circuit 500.
The pull-up circuit 100 connects the input signal end F (n-2) of the shift registor, to respond input signal,
And the input signal is supplied to pull-up node Q (n).
The output circuit 200 connects the pull-up node Q (n) and clock signal CK (n) input terminal, to respond
It states the voltage signal of pull-up node Q (n), and clock signal is supplied to the first output end G (n) and the of the shift registor
Two output end F (n).
The pull-down circuit 300 connects the first pulldown signal input terminal G (n+2), the second pulldown signal input terminal CK (n-1)
And pull-down node P (n), to respond the voltage signal of the first pulldown signal, the second pulldown signal and the pull-down node,
And low level signal is respectively supplied to the pull-up node Q (n) of the shift registor and the first output end G of the shift registor
(n)。
First pull-down control circuit 400 connect high level signal VDD input terminal, switch signal input end Q (n-1),
Control node H (n), the pull-down node p (n) and the pull-up node Q (n) are pulled down, to respond the high level signal,
The high level signal is supplied to the drop-down control node H (n), responds the voltage letter of drop-down control node H (n)
Number, the high level signal VDD is supplied to the pull-down node P (n) and responding to switch signal and the pull-up node Q
(n) voltage signal, and the low level signal is respectively supplied to the pull-down node and the drop-down control node.
Second pull-down control circuit 500 connects the pull-up node Q (n) and the second pulldown signal input terminal CK
(n-1), to respond the voltage signal of the pull-up node Q (n), the low level signal is supplied to second drop-down and is believed
Number input terminal CK (n-1).
It is appreciated that in output stage, under pull down branch to second by second pull-down control circuit 500 second
It draws signal input part to discharge, guarantees the first output end normal output signal.In non-output stage, when the clock of input
Signal is high level, is discharged by the second drop-down branch the pull-up node and the first output end, to reduce height
Level signal input end is in the time of direct current high level working condition, so that reducing the pull-down node P (n) is in direct current height
The time of level active state, and then a possibility that the threshold voltage for reducing relevant thin film transistor (TFT) drifts about, it improves and drops
It makes an uproar effect.
First pull-down control circuit 400 is opened including first switch branch 410, second in one of the embodiments,
Close branch 420 and drop-down input branch 440.
The first switch branch 410 connects first switch signal Q (n-1) input terminal, the drop-down control node H (n)
With the pull-down node P (n), to respond the first switch signal Q (n-1), and the low level signal is provided respectively
To the pull-down node P (n) and the drop-down control node H (n).
The second switch branch 420 connect the pull-up node Q (n), the drop-down control node H (n) and it is described under
It draws node P (n), is respectively supplied to respond the voltage signal of the pull-up node Q (n), and by the low level signal VSS
The pull-down node P (n) and the drop-down control node H (n).
Drop-down input branch 430 connect the high level signal VDD input terminal, the drop-down control node H (n) with
The high level signal VDD is supplied to the drop-down to respond the high level signal VDD by the pull-down node P (n)
Control node H (n), and the voltage signal of response drop-down control node H (n), the high level signal VDD is supplied to
The pull-down node P (n).
In the present embodiment, believed using the voltage signal of the pull-up node of rear stage shift registor as the first switch
Number to control first switch branch 410, using the voltage signal of the pull-up node of current shift buffer as controlling described the
Two switching branches 420 do not carry out first output end so that the pull-down node described in output stage keeps low level signal
Electric discharge.
Second pull-down control circuit 500 includes: in one of the embodiments,
Sixteenmo closes pipe T16, and grid connects the pull-up node Q (n), and drain electrode connects the second pulldown signal input
It holds CK (n-1), source electrode is connect with the low level voltage signal VSS input terminal.
In this implementation, in output stage, pipe T16 is closed by the sixteenmo, the second drop-down of the second drop-down branch is believed
Number input terminal CK (n-1) discharges, and guarantees the first output end normal output signal.
The pull-down circuit 300 includes that the first drop-down branch 310, second pulls down branch 320 in one of the embodiments,
Branch 330 is pulled down with third.
The first drop-down branch 310 connects the first pulldown signal Q (n+2) input terminal, to respond described first
Pulldown signal Q (n+2), and by low level signal VSS be respectively supplied to the shift registor pull-up node Q (n) and the displacement
First output end G (n) of buffer；
The second drop-down branch 320 connects the second pulldown signal input terminal CK (n-1), to respond described second
Pulldown signal, and by low level signal VSS be respectively supplied to the shift registor pull-up node Q (n) and the shift registor
The first output end G (n)；And
The third drop-down branch 330 connects the pull-down node P (n), to respond the electricity of the pull-down node P (n)
Signal is pressed, and low level signal VSS is respectively supplied to the pull-up node Q (n) and the shift registor of the shift registor
First output end G (n).
In the present embodiment, using the n-th+2 grades of output signal Q (n+2) as first pulldown signal, described in control
First drop-down branch 310.Using (n-1)th grade of clock signal CK (n-1) as second pulldown signal, to control described second
Pull down branch 320.The third, which is controlled, using the voltage signal as prime pull-down node P (n) pulls down branch 330.It is appreciated that
By pulling down branch 320 and third drop-down branch 330 to pull-up node Q (n) and institute to the first drop-down branch 310, second
It states the first output end G (n) and carries out continual electric discharge, the noise reduction effect of the shift registor can be improved.
The pull-up circuit 100 includes first switch tube T1 in one of the embodiments,.The first switch tube T1's
Grid and drain electrode are connected with the input signal F (n-2) end, and source electrode is connect with the pull-up node Q (n).
In the present embodiment, as the input signal for working as prime, described first opens described the n-th -2 grades of output signal F (n-2)
It closes pipe T1 grid and drain electrode is connect with described the n-th -2 grades of second output terminal.
The output circuit 200 includes second switch T2, third switch transistor T 3 and capacitor in one of the embodiments,
C。
The grid of the second switch T2 is connect with the pull-up node Q (n), drain electrode and the clock signal CK (n)
Input terminal connection, source electrode connect G (n) with the first output end of the shift registor.
The grid of the third switch transistor T 3 is connect with the pull-up node Q (n), drain electrode and the clock signal input terminal
Connection, source electrode are connect with the second output terminal F (n) of the shift registor.
The one end the capacitor C is connect with the pull-up node Q (n), the first output of the other end and the shift registor
G (n) connection is held, for keeping the current potential of pull-up node Q (n).
In the present embodiment, first output end is connect with scan line, provides scanning signal for display panel, and described second
The output signal of output end is as the n-th+2 grades of input signal, to realize continuous scanning.
The first drop-down branch 310 includes the 4th switch transistor T 4 and the 5th switch transistor T 5 in one of the embodiments,.
The grid of 4th switch transistor T 4 is connect with the first pulldown signal input terminal G (n+4) input terminal, drain electrode with
First output end of the shift registor and the capacitor C connection, source electrode and the low level voltage signal VSS input terminal
Connection.
The grid of 5th switch transistor T 5 is connect with the first pulldown signal input terminal G (n+4) input terminal, drain electrode with
Pull-up node Q (n) connection, source electrode are connect with the low level voltage signal VSS input terminal.
The second drop-down branch 320 includes the 6th switch transistor T 6 and the 7th switch transistor T 7.
The grid of 6th switch transistor T 6 is connect with the second pulldown signal CK (n-1) input terminal, drain electrode with it is described
First output end G (n) of shift registor and the capacitor C connection, source electrode and the low level voltage signal VSS input terminal
Connection.
The grid of 7th switch transistor T 7 is connect with the second pulldown signal CK (n-1) input terminal, drain electrode with it is described
Pull-up node Q (n) connection, source electrode are connect with the low level voltage signal VSS input terminal.
The third drop-down branch 330 includes the 8th switch transistor T 8 and the 9th switch transistor T 9.
The grid of 8th switch transistor T 8 is connect with the pull-down node P (n), drain electrode and the of the shift registor
One output end G (n) and the capacitor C connection, source electrode are connect with the low level voltage signal VSS input terminal.
The grid of 9th switch transistor T 9 is connect with the pull-down node P (n), and drain electrode connects with the pull-up node Q (n)
It connects, source electrode is connect with the low level voltage signal VSS input terminal.
The drop-down input branch 440 includes the tenth switch transistor T 10, the 11st switching tube in one of the embodiments,
T11。
The grid of tenth switch transistor T 10 and drain electrode are connect with the high level signal VDD input terminal, source electrode and institute
State drop-down control node H (n) connection.
The grid of 11st switch transistor T 11 is connect with the drop-down control node H (n), drain electrode and the high level
The connection of signal VDD input terminal, source electrode are connect with the pull-down node P (n).
The first switch branch 410 includes the 12nd switch transistor T 12 and the 13rd switch transistor T 13.
The grid of 12nd switch transistor T 12 is connect with switching signal Q (n-1) input terminal, under draining and being described
Control node H (n) connection is drawn, source electrode is connect with the low level signal VSS input terminal；And
The grid of 13rd switch transistor T 13 is connect with switching signal Q (n-1) input terminal, and drain electrode is saved with drop-down
Point P (n) connection, source electrode are connect with the low level signal VSS input terminal.
The second switch branch 420 includes the 14th switch transistor T 14 and the 15th switch transistor T 15.
The grid of 14th switch transistor T 14 is connect with the pull-up node Q (n), and drain electrode is saved with drop-down control
Point H (n) connection, source electrode are connect with the low level signal VSS input terminal.
The grid of 15th switch transistor T 15 is connect with the pull-up node Q (n), and drain electrode connects with pull-down node P (n)
It connects, source electrode is connect with the low level signal VSS input terminal.
In the present embodiment, the grid of the 12nd switch transistor T 12 and the 13rd switch transistor T 13 with (n-1)th grade
Pull-up node Q (n-1) connection, respond the voltage signal of (n+1)th grade of the pull-up node Q (n-1).14th switch
Pipe T14 and the grid of the 15th switch transistor T 15 are connect with the pull-up node Q (n) when prime (i.e. n-th grade), and response is worked as
The voltage signal of the pull-up node Q (n) of prime.Therefore pass through the control signal, it is ensured that in the pull-down node P for working as prime
(n) working as prime and persistently keeping low level in (n-1)th grade of output period.
Switching tube all in the application example is N type switch tube in one of the embodiments,.
The switching tube is field-effect tube or is triode in one of the embodiments,.When the switching tube is equal
When using field-effect tube or being all made of triode, it is convenient for circuit design.Further, it is also possible to according to actual design needs, portion
Divide and use field-effect tube, another uses triode.
Based on the same inventive concept, present invention also provides a kind of gate driving circuit, grid provided by the embodiments of the present application
Pole driving circuit includes cascade shift registor at different levels, and the cascade shift registor is in any of the above-described embodiment
Shift registor.Specifically, which includes N grades, and N is grid line quantity, and 2 < n < N-6.
In the present embodiment, the shift registor includes pull-up circuit 100, output circuit 200, pull-down circuit 300, first
Pull-down control circuit 400 and the second pull-down control circuit 500.
The pull-up circuit 100 connects the second output terminal of the n-th -2 grades shift registors, to respond described the n-th -2 grades
The output signal of shift registor, and the output signal of the n-th -2 grades shift registors is supplied to pull-up node Q (n).
The output circuit 200 connects the pull-up node Q (n) and clock signal input terminal, to respond on described
The voltage signal of node Q (n) is drawn, and clock signal is supplied to the first output end and second output terminal of the shift registor.
The pull-down circuit 300 connects clock signal CK (n-1) input terminal of (n-1)th grade of shift registor, the displacement
First output end G (n+1) of pull-down node P (n) and (n+1)th grade of shift registor of buffer, to respond the clock
Signal CK (n-1), the voltage signal of the pull-down node P (n) and the output of the first output end of (n+1)th grade of shift registor
Voltage signal, and by low level signal VSS be respectively supplied to the shift registor pull-up node Q (n) and the shift register
First output end of device.
First pull-down control circuit 400 connects the pull-up section of high level signal VDD output end, (n-1)th grade of buffer
Point Q (n-1), the pull-up node Q (n) of the shift registor, drop-down control node H (n) and the pull-down node P (n), to
The high level signal VDD is responded, the high level signal VDD is supplied to the drop-down control node H (n), described in response
The high level signal VDD is supplied to the pull-down node P (n), and response by the voltage signal for pulling down control node H (n)
The voltage of the pull-up node Q (n) of the voltage signal and shift registor of the pull-up node Q (n-1) of (n-1)th grade of buffer is believed
Number, the low level signal VSS is respectively supplied to the pull-down node P (n) and the drop-down control node H (n).
Second pull-down control circuit 500 connect the shift registor pull-up node Q (n) and described (n-1)th grade
Clock signal CK (n-1) input terminal of buffer, to respond the voltage signal of the pull-up node Q (n), by the low level
Signal VSS is supplied to the clock signal input terminal of (n-1)th grade of buffer；
Wherein, 2 < n < N-6, N are the number of cascade shift registor, and n and N are positive integer.
In addition, in the present embodiment, the first pull-down circuit 300 of signal input part and last level Four for preceding two-stage with
The connection of initial signal input terminal.
Fig. 8 is the cascade structure schematic diagram of gate driving circuit, and Fig. 9 is the timing of each signal end of the shift registor
Figure, the work below with reference to Fig. 8 and Fig. 9 to n-th grade of shift registor in gate driving circuit provided by the embodiments of the present application
Method is illustrated, specifically with the 4th grade of shift registor in the gate driving circuit that is made of 8 shift registors
Working method is illustrated.
First stage S1, clock signal CK4 be low level signal, clock signal CK2 and CK8 be high level signal, second
The high level signal of the output of grade shift registor, the first switch tube T1 are opened, and are charged for pull-up node Q (4), pull-up section
Point Q (4) rises to high level, the second switch T2 and the third switch transistor T 3 conducting, but because CK4 is still low level,
Therefore the first output end G (4) and second output terminal F (4) keeps low level.
Second stage S2, clock signal CK4 be high level signal, clock signal CK2 and CK8 be low level signal, second
The low level signal of the output of grade shift registor, the first switch tube T1 are disconnected, but due to the presence of capacitor C, pull-up section
Point Q (4) still keeps high potential；Clock signal CK4 is high level simultaneously, due to the bootstrap effect of capacitor C
(Bootstrapping), the current potential of pull-up node Q (4) continues to increase, in response to the voltage signal of the pull-up node Q (4)
Second switch T2 and third switch transistor T 3 are connected.
Meanwhile the 14th switch transistor T 14 and the 15th switching tube of the voltage signal in response to the pull-up node Q (4)
T15 is also switched on, and low level signal VSS is supplied to pull-down node P (4) and drop-down control node H (4), therefore drop-down section at this time
Point P (4) keeps low potential, and the 8th switch transistor T 8 and the 9th switch transistor T 9 disconnect.In response to the voltage signal of (4) pull-up node Q
Sixteenmo close pipe T16 conducting, low level signal VSS is supplied to clock signal CK (3) output end, in response to clock signal
The 6th switch transistor T 6 and the 7th switch transistor T 7 of number CK (3) disconnects.Clock signal CK8 is low level, the 8th grade of shift registor
The output signal of the first output end G (8) be low level signal, the 4th switch transistor T 4 and the 5th switch transistor T 5 disconnect, to prevent
It discharges pull-up node Q (4).
Therefore, the output signal of the first output end G (4) and second output terminal F (4) is high level signal at this time.
Phase III S3, clock signal CK2, CK3, CK4 and CK8 are low level signal, and clock signal CK6 is high level.
It is connected in response to the 6th switch transistor T 6 of clock signal CK6 and the 7th switch transistor T 7, pull-up node Q (4) is carried out
Electric discharge, when the presence due to capacitor C, the pull-up node Q (4) still keeps high potential.
The pull-up node Q (4) is high potential simultaneously, the 12nd switch transistor T 12 in response to pull-up node Q (4) and the
Low level signal VSS is supplied to pull-down node P (4) and drop-down control node H (4), therefore this by the conducting of 13 switch transistor Ts 13
Shi Suoshu pull-down node P (4) keeps low level.
But clock signal CK4 is low level signal, therefore the first output end G (4) is low level.
Fourth stage S4, within the first half period of fourth stage, clock signal CK1, CK2, CK3, CK4, CK5 and CK6 are equal
For low level signal, clock signal CK7 and CK8 are high level signal.
Since clock signal CK4 is low level signal, the first output end G (4) is low level.
5th stage S5, within the first half period in the 5th stage, clock signal CK3, CK4, CK5, CK6, CK7 and CK8 are
Low level signal, clock signal CK1 and CK2 are high level signal.
The voltage signal of pull-up node Q (3) and pull-up node Q (4) are low level signal, in response to pull-up node Q (3)
It is disconnected with the switching tube in the first drop-down controlling brancher of pull-up node Q (4), the pull-down node P (4) is high level letter
Number, to first output end G (4) continuous discharge, the first output end G (4) keeps low level.
To sum up, this application provides a kind of shift registor and gate driving circuits.The shift registor includes pull-up
Circuit 100, output circuit 200, pull-down circuit 300, the first pull-down control circuit 400 and the second pull-down control circuit 500.It is described
Pull-up circuit 100 connects the input signal end of the shift registor, mentions to respond input signal, and by the input signal
It supplies pull-up node Q (n).The output circuit 200 connects the pull-up node Q (n) and clock signal input terminal, to sound
The voltage signal of the pull-up node Q (n) is answered, and clock signal is supplied to the first output end and of the shift registor
Two output ends.The pull-down circuit 300 connects first pulldown signal input terminal G (n+2) input terminal, the second pulldown signal input terminal
CK (n-1) and pull-down node P (n), to respond the first pulldown signal input terminal G (n+2), the second pulldown signal input terminal CK
(n-1) and the voltage signal of the pull-down node P (n), and low level signal VSS is respectively supplied to the shift registor
The first output end of pull-up node Q (n) and the shift registor.First pull-down control circuit 400 connects high level signal
VDD output end, switching signal Q (n-1) input terminal, drop-down control node H (n), the pull-down node P (n) and the pull-up
The high level signal VDD is supplied to the drop-down control node H to respond the high level signal VDD by node Q (n)
(n), the voltage signal for responding drop-down control node H (n), is supplied to the pull-down node P for the high level signal VDD
(n) and the voltage signal of responding to switch signal Q (n-1) and the pull-down node P (n), and by the low level signal VSS
It is respectively supplied to the pull-down node P (n) and the drop-down control node H (n).Described in the second pull-down control circuit connection
Pull-up node and the second pulldown signal input terminal, to respond the voltage signal of the pull-up node, by the low level
Signal is supplied to the second pulldown signal input terminal.In the application, in output stage, pass through second pull-down control circuit
It discharges the second pulldown signal input terminal of the second drop-down branch, guarantees the first output end normal output signal；?
Non- output stage, when the clock signal of input is high level, by drop-down branch to the pull-up node and the first output end into
Row electric discharge, to improve noise reduction effect.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
The limitation to claim therefore cannot be interpreted as.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of shift registor characterized by comprising
Pull-up circuit connects the input signal end of the shift registor, to respond input signal, and by the input signal
It is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, and the voltage to respond the pull-up node is believed
Number, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit, the first pulldown signal input terminal of connection, the second pulldown signal input terminal and pull-down node, to respond the
The voltage signal of one pulldown signal, the second pulldown signal and the pull-down node, and low level signal is respectively supplied to this
The pull-up node of shift registor and the first output end of the shift registor；
First pull-down control circuit, connection high level signal input terminal, switch signal input end, drop-down control node, it is described under
Draw node and the pull-up node that the high level signal is supplied to the drop-down to respond the high level signal
Control node responds the voltage signal of the drop-down control node, the high level signal is supplied to the pull-down node, with
And the voltage signal of responding to switch signal and the pull-up node, and the low level signal is respectively supplied to the drop-down and is saved
Point and the drop-down control node；And
Second pull-down control circuit connects the pull-up node and the second pulldown signal input terminal, to respond on described
The voltage signal for drawing node, is supplied to the second pulldown signal input terminal for the low level signal.
2. shift registor as described in claim 1, which is characterized in that second pull-down control circuit includes:
Sixteenmo closes pipe, and grid connects the pull-up node, and drain electrode connects the second pulldown signal input terminal, source electrode and institute
State the connection of low level voltage signal input part.
3. shift registor as claimed in claim 2, which is characterized in that first pull-down control circuit includes:
First switch branch, connection switch signal input part, the drop-down control node and the pull-down node, to respond
Switching signal is stated, and the low level signal is respectively supplied to the pull-down node and the drop-down control node；
Second switch branch connects the pull-up node, the drop-down control node and the pull-down node, described to respond
The voltage signal of pull-up node, and the low level signal is respectively supplied to the pull-down node and drop-down control section
Point；And
Drop-down input branch, connects the high level signal input terminal, the drop-down control node and the pull-down node, to
The high level signal is responded, the high level signal is supplied to the drop-down control node, and the response drop-down control
The high level signal is supplied to the pull-down node by the voltage signal of node processed.
4. shift registor as claimed in claim 3, which is characterized in that the pull-down circuit includes:
First drop-down branch, connects the first pulldown signal input terminal, to respond first pulldown signal, and by low electricity
Ordinary mail number is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；
Second drop-down branch, connects the second pulldown signal input terminal, to respond second pulldown signal, and by low electricity
Ordinary mail number is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor；And
Third pulls down branch, connects the pull-down node, believes to respond the voltage signal of the pull-down node, and by low level
Number it is respectively supplied to the pull-up node of the shift registor and the first output end of the shift registor.
5. shift registor as claimed in claim 4, which is characterized in that the pull-up circuit includes:
First switch tube T1, grid and drain electrode are connect with the input signal end, and source electrode is connect with the pull-up node.
6. shift registor as claimed in claim 5, which is characterized in that the output circuit includes:
Second switch, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and the shifting
The first output end connection of position buffer；
Third switching tube, grid are connect with the upper node, and drain electrode is connect with the clock signal input terminal, source electrode and the shifting
The second output terminal connection of position buffer；And
Capacitor, one end are connect with the pull-up node, and the other end is connect with the first output end of the shift registor.
7. shift registor as claimed in claim 6, which is characterized in that
Described first, which pulls down branch, includes:
4th switching tube, grid are connect with the first pulldown signal input terminal, drain with it is the first of the shift registor defeated
Outlet and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
5th switching tube, grid are connect with the first pulldown signal input terminal, drain electrode connect with the pull-up node, source electrode and
The low level voltage signal input part connection；
Described second, which pulls down branch, includes:
6th switching tube, grid are connect with the second pulldown signal input terminal, drain with it is the first of the shift registor defeated
Outlet and the capacitance connection, source electrode are connect with the low level voltage signal input part；And
7th switching tube, grid are connect with the second pulldown signal input terminal, drain electrode connect with the pull-up node, source electrode and
The low level voltage signal input part connection；
The third pulls down branch
8th switching tube, grid are connect with the pull-down node, first output end and institute of the drain electrode with the shift registor
Capacitance connection is stated, source electrode is connect with the low level voltage signal input part；And
9th switching tube, grid are connect with the pull-down node, and drain electrode is connect with the pull-up node, source electrode and the low level
Voltage signal inputs connection.
8. shift registor as claimed in claim 7, which is characterized in that
The drop-down inputs branch
Tenth switching tube, grid and drain electrode are connect with the high level signal input terminal, source electrode and the drop-down control node
Connection；And
11st switching tube, grid are connect with the drop-down control node, and drain electrode is connect with the high level signal input terminal, source
Pole is connect with the pull-down node；
The first switch branch includes:
12nd switching tube, grid are connect with the switch signal input end, and drain electrode is connect with the drop-down control node, source electrode
It is connect with the low level signal input terminal；And
13rd switching tube, grid are connect with the switch signal input end, drain electrode connect with pull-down node, source electrode with it is described low
The connection of level signal input terminal；
The second switch branch includes:
14th switching tube, grid are connect with the pull-up node, drain electrode connect with the drop-down control node, source electrode with it is described
The connection of low level signal input terminal；And
15th switching tube, grid are connect with the pull-up node, and drain electrode is connect with pull-down node, and source electrode and the low level are believed
The connection of number input terminal.
9. the shift registor as described in any claim of claim 1-8, which is characterized in that the switching tube is field-effect tube
It or is triode.
10. a kind of gate driving circuit, including cascade shift registor at different levels, which is characterized in that the shift registor packet
It includes:
Pull-up circuit connects the second output terminal of the n-th -2 grades shift registors, to respond the n-th -2 grades shift registors
Output signal, and the output signal of the n-th -2 grades shift registors is supplied to pull-up node；
Output circuit connects the pull-up node and clock signal input terminal, and the voltage to respond the pull-up node is believed
Number, and clock signal is supplied to the first output end and second output terminal of the shift registor；
Pull-down circuit, connect the clock signal input terminal of (n-1)th grade of shift registor, the shift registor pull-down node with
And the first output end of the n-th+2 grades shift registors, to respond the first output end of the n-th+2 grades shift registors output
Voltage signal, and by low level signal be respectively supplied to the shift registor pull-up node and the shift registor it is first defeated
Outlet；
First pull-down control circuit, connection high level signal input terminal, the pull-up node of (n-1)th grade of shift registor, the shifting
Pull-up node, drop-down control node and the pull-down node of position buffer, to respond the high level signal, by the height
Level signal is supplied to the drop-down control node, responds the voltage signal of the drop-down control node, the high level is believed
Number be supplied to the pull-down node, and (n-1)th grade of shift registor of response pull-up node voltage signal and the displacement
The low level signal is respectively supplied to the pull-down node and the drop-down is controlled by the voltage signal of the pull-up node of buffer
Node processed；And
Second pull-down control circuit connects the pull-up node of the shift registor and the clock letter of (n-1)th grade of buffer
Number input terminal, to respond the voltage signal of the pull-up node, by the low level signal be supplied to described (n-1)th grade it is temporary
The clock signal input terminal of device；
Wherein, 2 < n < N-2, N is grid line quantity, and n and N are positive integer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811600792.0A CN109448657A (en) | 2018-12-26 | 2018-12-26 | Shift registor and gate driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811600792.0A CN109448657A (en) | 2018-12-26 | 2018-12-26 | Shift registor and gate driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109448657A true CN109448657A (en) | 2019-03-08 |
Family
ID=65535895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811600792.0A Pending CN109448657A (en) | 2018-12-26 | 2018-12-26 | Shift registor and gate driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109448657A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI726523B (en) * | 2019-12-06 | 2021-05-01 | 友達光電股份有限公司 | Driving circuit |
| CN113421517A (en) * | 2021-06-25 | 2021-09-21 | 惠科股份有限公司 | Shift register and driving method thereof, and display panel |
| CN113421516A (en) * | 2021-06-25 | 2021-09-21 | 惠科股份有限公司 | Shift register and display panel |
| CN113539202A (en) * | 2021-06-25 | 2021-10-22 | 北海惠科光电技术有限公司 | Grid driving circuit and display panel |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102226940A (en) * | 2010-06-25 | 2011-10-26 | 友达光电股份有限公司 | Shift register on display panel and grid drive array structure |
| CN103927960A (en) * | 2013-12-30 | 2014-07-16 | 上海中航光电子有限公司 | Grid driving device and display device |
| CN103943085A (en) * | 2014-04-02 | 2014-07-23 | 京东方科技集团股份有限公司 | Grid driving circuit, display device and driving method for zoning display |
| CN104299591A (en) * | 2014-10-31 | 2015-01-21 | 深圳市华星光电技术有限公司 | Array substrate line driving circuit and liquid crystal display device |
| CN104505046A (en) * | 2014-12-29 | 2015-04-08 | 上海天马微电子有限公司 | Grid driving circuit, array substrate, display panel and display device |
| CN104637461A (en) * | 2015-02-12 | 2015-05-20 | 昆山龙腾光电有限公司 | Gate drive circuit and display device |
| CN105390115A (en) * | 2015-12-24 | 2016-03-09 | 深圳市华星光电技术有限公司 | Liquid crystal display device and GOA circuit |
| CN108986732A (en) * | 2018-08-13 | 2018-12-11 | 惠科股份有限公司 | Shift scratch circuit and display device |
| US20180366208A1 (en) * | 2015-06-11 | 2018-12-20 | Hannstar Display (Nanjing) Corporation | Shift register and display apparatus |
-
2018
- 2018-12-26 CN CN201811600792.0A patent/CN109448657A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102226940A (en) * | 2010-06-25 | 2011-10-26 | 友达光电股份有限公司 | Shift register on display panel and grid drive array structure |
| CN103927960A (en) * | 2013-12-30 | 2014-07-16 | 上海中航光电子有限公司 | Grid driving device and display device |
| CN103943085A (en) * | 2014-04-02 | 2014-07-23 | 京东方科技集团股份有限公司 | Grid driving circuit, display device and driving method for zoning display |
| CN104299591A (en) * | 2014-10-31 | 2015-01-21 | 深圳市华星光电技术有限公司 | Array substrate line driving circuit and liquid crystal display device |
| CN104505046A (en) * | 2014-12-29 | 2015-04-08 | 上海天马微电子有限公司 | Grid driving circuit, array substrate, display panel and display device |
| CN104637461A (en) * | 2015-02-12 | 2015-05-20 | 昆山龙腾光电有限公司 | Gate drive circuit and display device |
| US20180366208A1 (en) * | 2015-06-11 | 2018-12-20 | Hannstar Display (Nanjing) Corporation | Shift register and display apparatus |
| CN105390115A (en) * | 2015-12-24 | 2016-03-09 | 深圳市华星光电技术有限公司 | Liquid crystal display device and GOA circuit |
| CN108986732A (en) * | 2018-08-13 | 2018-12-11 | 惠科股份有限公司 | Shift scratch circuit and display device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI726523B (en) * | 2019-12-06 | 2021-05-01 | 友達光電股份有限公司 | Driving circuit |
| CN113421517A (en) * | 2021-06-25 | 2021-09-21 | 惠科股份有限公司 | Shift register and driving method thereof, and display panel |
| CN113421516A (en) * | 2021-06-25 | 2021-09-21 | 惠科股份有限公司 | Shift register and display panel |
| CN113539202A (en) * | 2021-06-25 | 2021-10-22 | 北海惠科光电技术有限公司 | Grid driving circuit and display panel |
| CN113421517B (en) * | 2021-06-25 | 2022-05-06 | 惠科股份有限公司 | Shift register and driving method thereof, and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109448656A (en) | Shift registor and gate driving circuit | |
| CN109448657A (en) | Shift registor and gate driving circuit | |
| CN104575430B (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN105185292B (en) | Gate driving circuit and display device | |
| CN104718568B (en) | Display device and its driving method | |
| CN106951123B (en) | Touch-control driving unit and its driving method, touch drive circuit, display device | |
| CN205595037U (en) | Shifting register, grid driving circuit and display device | |
| CN107564491B (en) | A kind of shutdown discharge circuit, driving method, driving circuit and display device | |
| CN105609072B (en) | Gate driving circuit and the liquid crystal display using gate driving circuit | |
| CN107093414B (en) | A kind of shift register, its driving method, gate driving circuit and display device | |
| CN106128347A (en) | Shift register cell and driving method, gate driver circuit, display device | |
| CN107464521A (en) | Shift register cell, gate driving circuit and driving method, display device | |
| CN107633833A (en) | Shift register cell and its driving method, gate driving circuit, display device | |
| CN106228927A (en) | Shift register cell, driving method, gate driver circuit and display device | |
| CN106448536A (en) | Shifting register, grid driving circuit, display panel and driving method | |
| CN106710566B (en) | Discharge circuit and its driving method, display device | |
| CN109448624A (en) | GOA circuit and display panel | |
| CN106157874A (en) | Shift register cell, driving method, gate driver circuit and display device | |
| CN105810167B (en) | Shift register cell circuit, shift register and its liquid crystal display | |
| CN105469759B (en) | A kind of shift register | |
| CN108399902A (en) | Shift register, gate driving circuit and display device | |
| CN108573668A (en) | Shift register cell and its driving method, gate driving circuit and display device | |
| CN106057116A (en) | Shift register unit, driving method, gate driving circuit and display device | |
| CN107492338A (en) | A kind of gate driving circuit and display device | |
| CN109300428A (en) | GOA circuit and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190308 |