CN106128347A

CN106128347A - Shift register cell and driving method, gate driver circuit, display device

Info

Publication number: CN106128347A
Application number: CN201610551812.4A
Authority: CN
Inventors: 古宏刚; 邵贤杰; 宋洁; 李磊; 许徐飞
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2016-07-13
Filing date: 2016-07-13
Publication date: 2016-11-16
Anticipated expiration: 2036-07-13
Also published as: CN106128347B

Abstract

The embodiment of the present invention provides a kind of shift register cell and driving method, gate driver circuit, display device, relate to Display Technique field, touch scanning signals is not interfere with each other with gated sweep signal, and the gated sweep signal avoiding shift register cell to export is pulled low or no signal output.This shift register cell includes that the signal of the first voltage end is exported to pulling up node by the first input module；The signal of the second voltage end is exported to pulling up node by the second input module；The signal of the first clock signal input terminal is exported to signal output part by pull-up module；The signal of the first clock signal input terminal, second clock signal input part or tertiary voltage end is exported to pull-down node by drop-down control module.The current potential of signal output part is pulled down to tertiary voltage end by the drop-down module of touch-control；Touching signals is controlled the signal of end and exports to pulling up node by charging module；The current potential of pull-up node and signal output part is pulled down to tertiary voltage end by noise reduction module respectively.

Description

Shift register cell and driving method, gate driver circuit, display device

Technical field

The present invention relates to Display Technique field, particularly relate to a kind of shift register cell and driving method thereof, grid drives Galvanic electricity road, display device.

Background technology

(Thin Film Transistor Liquid Crystal Display, TFT-LCD shows TFT-LCD Show device) or OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) display in be provided with array Substrate, wherein, array base palte can be divided into viewing area and be positioned at the wiring area of viewing area periphery.Wherein neighboring area Inside it is provided with the gate driver circuit for grid line is progressively scanned.Existing gate driver circuit is frequently with GOA (Gate Driver on Array, array base palte row cutting) design TFT (Thin Film Transistor, thin film field-effect crystal Pipe) gate switch circuit is integrated in above-mentioned neighboring area, to form gate driver circuit.

In addition along with the development of touch-control (Touch) technology, aforementioned display device includes touch screen, and this touch screen can be divided into External hanging type is with embedded, and the panel with touch controllable function can be positioned at the light emission side of display by external hanging type, and covers display The viewing area of device.Embedded is to be integrated in having touch controllable function on the display floater (Panel) of display.

Above-mentioned gate driver circuit includes the shift register cell of multiple cascade, in prior art, in order to avoid touch-control During scanning signal input, the gated sweep signal of shift register cell defeated with GOA circuit output clashes, generally When touch scanning signals inputs, the outfan controlling shift register cell is needed to export to grid line no signal.When touch-control is swept After retouching signal input, the outfan of shift register cell continues to be scanned grid line.But, due to shift register cell In thin film transistor (TFT) there is leakage current so that touch scanning signals input after, the outfan of shift register cell continues Continuous when being scanned grid line, the gated sweep signal of shift register cell output is pulled low or no signal output, thus Affect the normal display of display.

Summary of the invention

Embodiments of the invention provide a kind of shift register cell and driving method, gate driver circuit, display dress Put, it is possible to while making touch scanning signals and gated sweep signal not interfere with each other, after touching signals end of input, it is to avoid The gated sweep signal that TFT electric leakage causes GOA circuit to export is pulled low or no signal output.

For reaching above-mentioned purpose, embodiments of the invention adopt the following technical scheme that

The one side of the embodiment of the present invention, it is provided that a kind of shift register cell, including the first input module, the second input Module, pull-up module, drop-down control module, the drop-down module of touch-control, charging module, noise reduction module；Described first input module is even Connect the first signal input part, the first voltage end and pull-up node, under the control of described first signal input part, by institute State the signal output of the first voltage end to described pull-up node；Described second input module connect secondary signal input, second Voltage end and described pull-up node, under the control of secondary signal input, by defeated for the signal of described second voltage end Go out to described pull-up node；Described pull-up module connect described first clock signal input terminal, signal output part and described on Draw node, under the control of described pull-up node, by the first clock signal output of described first clock signal input terminal To described signal output part, and the current potential of described pull-up node is stored；Described drop-down control module connects described pull-up Node, described first clock signal input terminal, second clock signal input part, tertiary voltage end and pull-down node, be used for Under the control of described first clock signal input terminal, the first clock signal of described first clock signal input terminal is exported to institute State pull-down node；Or it is used for described second clock signal input part under the control of described second clock signal input part The output of second clock signal is to described pull-down node；Or it is used for described pull-down node under the control of described pull-up node Current potential is pulled down to the current potential of described tertiary voltage end；The drop-down module of described touch-control connects described signal output part, touching signals control End processed and described tertiary voltage end, under the control controlling end at described touching signals, by the electricity of described signal output part Position is pulled down to the current potential of described tertiary voltage end；Described charging module connects described touching signals and controls end and described pull-up joint Point, under the control of described pull-up node and touching signals end, the signal that described touching signals controls end exports to institute State pull-up node；Described noise reduction module connects described pull-down node, described pull-up node, signal output part and described 3rd electricity Pressure side, under the control of described pull-down node, the current potential by described pull-up node and described signal output part is drop-down respectively Current potential to described tertiary voltage end.

Preferably, described first input module includes the first transistor, and the grid of described the first transistor connects described the One signal input part, the first pole connects described first voltage end, and the second pole is connected with described pull-up node.

Preferably, described second input module includes transistor seconds, and the grid of described transistor seconds connects described the Binary signal input, the first pole connects described second voltage end, and the second pole is connected with described pull-up node.

Preferably, described pull-up module includes third transistor and the first electric capacity；The grid of described third transistor connects Described pull-up node, the first pole connects described first clock signal input terminal, and the second pole is connected with described signal output part；Institute The one end stating the first electric capacity is connected with described pull-up node, and the other end connects described signal output part.

Preferably, described drop-down control module includes the 4th transistor, the 5th transistor and the second electric capacity；4th transistor Grid and the first pole connect described first clock signal input terminal, the second pole is connected with described pull-down node；Described 5th The grid of transistor connects described pull-up node, and the first pole connects described pull-down node, the second pole and described tertiary voltage end phase Connect；One end of described second electric capacity connects described second clock signal input part, and the other end is connected with described pull-down node.

Preferably, the drop-down module of described touch-control includes the 6th transistor, and the grid of described 6th transistor connects touch-control letter Number control end, first pole connect described signal output part.

Preferably, described charging module includes the 7th transistor and the 8th transistor；The grid of described 7th transistor and First pole connects described touching signals and controls end, and the second pole connects the first pole of described 8th transistor；Described 8th transistor Grid and the second pole connect described pull-up node.

Preferably, described charging module includes the 7th transistor and the 8th transistor；The grid of described 7th transistor is even Connecting and draw node, the first pole connects described touching signals and controls end, and the second pole is connected with the grid of described 8th transistor；Institute The first pole stating the 8th transistor connects described touching signals control end, and the second pole is connected with described pull-up node.

Preferably, described noise reduction module includes the 9th transistor and the tenth transistor；The grid of described 9th transistor is even Connecing described pull-down node, the first pole connects described pull-up node, and the second pole is connected with described tertiary voltage end；Described tenth is brilliant The grid of body pipe connects described pull-down node, and the first pole connects described signal output part, the second pole and described tertiary voltage end phase Connect.

The another aspect of the embodiment of the present invention, it is provided that a kind of gate driver circuit, as above including multiple cascades Any one shift register cell, the first signal input part of first order shift register cell connects initial signal end；Remove Beyond first order shift register cell, the signal output part of upper level shift register cell connects next stage shift LD First signal input part of device unit；In addition to afterbody shift register cell, next stage shift register cell Secondary signal input connects the signal output part of upper level shift register cell；The of afterbody shift register cell Binary signal input connects described initial signal end.

The another aspect of the embodiment of the present invention, it is provided that a kind of display device, including gate driver circuit as above.

The another further aspect of the embodiment of the present invention, it is provided that a kind of driving method, is included in a picture frame, described method bag Including: input phase: under the control of the first signal input part, the signal of the first voltage end is exported to pull-up by the first input module Node；The current potential of described pull-up node is stored by pull-up module, and under the control of described pull-up node, described upper drawing-die The signal of the first clock signal input terminal is exported to signal output part by block；The output stage: will deposit on last stage in pull-up module The signal output of storage is to described pull-up node, and under the control of described pull-up node, described pull-up module is by described first clock First clock signal output of signal input part is to described signal output part, described signal output part output gated sweep signal； Reseting stage: drop-down control module is under the control of described second clock signal input part and described pull-up node, by described The second clock signal of two clock signal input terminals exports to pull-down node；Under the control of described pull-down node, described noise reduction The voltage of described pull-up node and described signal output part is pulled down to the current potential of described tertiary voltage end by module；Second input mould The current potential of pull-up node, under the control of secondary signal input, is pulled down to the current potential of described second voltage end by block；Noise reduction is protected Hold the stage: described drop-down control module is under the control of described first clock signal input terminal and described pull-up node, by described First clock signal of the first clock signal input terminal exports to pull-down node；Under the control of described pull-down node, described fall The voltage of described pull-up node and described signal output part is pulled down to the current potential of described tertiary voltage end by module of making an uproar；At next figure As repeat before frame described reseting stage and described noise reduction keep stage the first signal input part, secondary signal input, first Clock signal input terminal and the control signal of second clock signal input part so that described signal output part keeps no signal defeated The state gone out；Touching signals input phase: described signal, under touching signals controls the control of end, is exported by the drop-down module of touch-control The current potential of end is pulled down to the current potential of described tertiary voltage end.

Preferably, between adjacent two two field picture frames, described touching signals input phase is inserted.

Preferably, the output stage in a picture frame inserts described touching signals input phase, in described input phase, institute State driving method also to include: charging module, under the control that described pull-up node and described touching signals control end, touches described Control signal controls the signal of end and exports to pulling up node, and is stored the current potential of described pull-up node by pull-up module.

Preferably, when the transistor in described shift register cell is N-type transistor, input at the first voltage end High level, in the case of tertiary voltage end input low level, described method includes: described input phase: described first signal is defeated Enter and hold input high level, described first input module under the control of the high level of described first signal input part by described first The high level output of voltage end is to pulling up node；The described output stage: under the control of described pull-up node high level, described on Drawing-die block is by the high level output of described first clock signal input terminal to described signal output part；Described reseting stage: described The high level output of second clock signal input part is to described pull-down node, under the control of described pull-down node, described noise reduction The voltage of described pull-up node and described signal output part is pulled down to the low level of described tertiary voltage end by module；Described second Signal input part input high level, under the control of the high level that described second input module inputs at described secondary signal input The current potential of pull-up node is pulled down to the low level of described second voltage end；Described noise reduction keeps the stage: described first clock letter The high level output of number input is to described pull-down node, and under the control of described pull-down node, described noise reduction module is by described The voltage of pull-up node and described signal output part is pulled down to the low level of described tertiary voltage end；Described touching signals input rank Section: touching signals controls end output high level, and the drop-down module of described touch-control controls the high level of end output at described touching signals Control under the current potential of described signal output part is pulled down to the low level of described tertiary voltage end.

Preferably, when the transistor in described shift register cell is N-type transistor, described touching signals inputs Stage: described touching signals controls end output high level, described pull-up node output high level, and described charging module touches described Control signal controls the high level output of end to described pull-up node

The embodiment of the present invention provides a kind of shift register cell and driving method, gate driver circuit, display device. This shift register cell includes that the first input module, the second input module, pull-up module, drop-down control module, touch-control are drop-down Module, charging module, noise reduction module.Wherein, the first input module connects the first signal input part, the first voltage end and pull-up Node, under the control of the first signal input part, exports the signal of the first voltage end to pulling up node.Second input mould Block connects secondary signal input, the second voltage end and pull-up node, under the control of secondary signal input, by the The signal of two voltage ends exports to pulling up node.Pull-up module connect the first clock signal input terminal, signal output part and on Draw node, under the control at pull-up node, by defeated to signal for the first clock signal output of the first clock signal input terminal Go out end, and the current potential of pull-up node is stored.Drop-down control module connect pull-up node, the first clock signal input terminal, Second clock signal input part, tertiary voltage end and pull-down node, for the control at described first clock signal input terminal Lower by the first clock signal output extremely described pull-down node of described first clock signal input terminal；Or for described second Under the control of clock signal input terminal, the second clock signal of described second clock signal input part is exported to described drop-down joint Point；Or for the current potential of described pull-down node being pulled down to the electricity of described tertiary voltage end under the control of described pull-up node Position.Touch-control drop-down Module connection signal outfan, touching signals control end and tertiary voltage end, in touching signals control Under the control of end, the current potential of signal output part is pulled down to the current potential of tertiary voltage end.Charging module connects touching signals and controls End and pull-up node, under the control at pull-up node, the signal that touching signals controls end exports to pulling up node.Noise reduction Module connects pull-down node, pull-up node, signal output part and tertiary voltage end, under the control of pull-down node, divides The current potential of pull-up node and signal output part is not pulled down to the current potential of tertiary voltage end.

So, on the one hand, the voltage of the first signal input part can be exported to pull-up by pull-up control module Node, additionally, the voltage of the second voltage end can be exported supreme under the control of secondary signal input by the second input module Draw node.In the case, when this shift register cell uses forward scan, the voltage of the first voltage end is for pull-up Node is charged, and the voltage of the second voltage end is for resetting to pull-up node, and works as this shift register cell and use During reverse scan, the voltage of the second voltage end is for being charged pull-up node, and the voltage of the first voltage end is for pull-up Node resets.

Based on this, after pull-up node is electrically charged, pull-up module, can be by the first clock under the control of this pull-up node Signal input part first clock signal export to signal output part so that signal output part output the stage can to this The grid line output gated sweep signal that signal output part is connected, additionally, drop-down control module can control the electricity of pull-down node Position, so that this pull-down node can control noise reduction module and the current potential of pull-up node and signal output part is pulled down to tertiary voltage The current potential of end, to carry out noise reduction to pull-up node and signal output part.

On the other hand, in the output stage of this shift register cell, when the drop-down module of touch-control can be defeated at touching signals Fashionable, the current potential of signal output part is pulled down to the current potential of tertiary voltage end, thus avoids touching signals defeated with signal output part The gated sweep signal gone out interferes.Additionally, the voltage that touching signals can be controlled end by charging module exports to pulling up joint Point, to be charged pull-up node so that after touching signals end of input, the current potential of pull-up node can be maintained, from And electric leakage causes pulling up the problem of the current potential reduction of node to avoid the TFT in shift register cell to occur, so that letter Number outfan keeps output gated sweep signal in the above-mentioned output stage.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing In having technology to describe, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to Other accompanying drawing is obtained according to these accompanying drawings.

The structural representation of a kind of shift register cell that Fig. 1 provides for the embodiment of the present invention；

Fig. 2 is a kind of concrete structure schematic diagram of modules in Fig. 1；

Fig. 3 is the another kind of concrete structure schematic diagram of modules in Fig. 1；

Fig. 4 is a kind of signal timing diagram controlling the shift register cell shown in Fig. 2 or 3；

Fig. 5 is the another kind of signal timing diagram controlling the shift register cell shown in Fig. 2 or 3；

The structural representation of a kind of gate driver circuit that Fig. 6 provides for the embodiment of the present invention.

Reference:

10-the first input module；20-the second input module；30-pulls up module；The drop-down control module of 40-；Under 50-touch-control Drawing-die block；60-charging module；70-noise reduction module；IN1-the first signal input part；IN2-secondary signal input；CLK-first Clock signal input terminal；CLKB-second clock signal input part；OUTPUT-signal output part；V1-the first voltage end；V2- Two voltage ends；V3-tertiary voltage end.

Detailed description of the invention

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Describe, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments wholely.Based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise Embodiment, broadly falls into the scope of protection of the invention.

The embodiment of the present invention provides a kind of shift register cell, as it is shown in figure 1, include the first input module 10, second Input module 20, pull-up module 30, drop-down control module 40, the drop-down module of touch-control 50, charging module 60, noise reduction module 70.

Wherein, the first input module 10 connects the first signal input part IN1, the first voltage end V1 and pull-up node PU, Under the control at the first signal input part IN1, the signal of the first voltage end V1 is exported to pull-up node PU.

Second input module 20 connects secondary signal input IN2, the second voltage end V2 and pull-up node PU, is used for Under the control of secondary signal input IN2, the signal of the second voltage end V2 is exported to pull-up node PU.

Pull-up module 30 connects the first clock signal input terminal CLK, signal output part OUTPUT and pull-up node PU, uses Under the control at pull-up node PU, first clock signal of the first clock signal input terminal CLK is exported to signal output part OUTPUT, and the current potential of pull-up node PU is stored.

Drop-down control module 40 connects pull-up node PU, the first clock signal input terminal CLK, second clock signal input part CLKB, tertiary voltage end V3 and pull-down node PD, be used for the first clock under the control of the first clock signal input terminal CLK First clock signal of signal input part CLK exports to pull-down node PD.Or, at second clock signal input part CLK Control under, the second clock signal of second clock signal input part CLKB is exported to pull-down node PD.Or, it is used for Draw under the control of node PU, the current potential of pull-down node PD is pulled down to the current potential of tertiary voltage end V3.

The drop-down module of touch-control 50 connects signal output part OUTPUT, touching signals controls end SW and tertiary voltage end V3, Under the control controlling end SW at touching signals, the current potential of signal output part OUTPUT is pulled down to the electricity of tertiary voltage end V3 Position.

Charging module 60 connects touching signals and controls end SW and pull-up node PU, at pull-up node PU and touching signals Under the control of end SW, touching signals is controlled the signal output of end SW to pulling up node PU.

Noise reduction module 70 connects pull-down node PD, pull-up node PU, signal output part OUTPUT and tertiary voltage end V3, For under the control of pull-down node PD, respectively the current potential of pull-up node PU and signal output part OUTPUT is pulled down to the 3rd electricity The current potential of pressure side V3.

Hereinafter the concrete structure of modules in Fig. 1 is described in detail.

Concrete, above-mentioned first input module 10 includes the first transistor M1.The grid of this first transistor M1 connects the One signal input part IN1, the first pole connects the first voltage end V1, and the second pole is connected with pull-up node PU.

Second input module 20 includes transistor seconds M2, and the grid of this transistor seconds M2 connects secondary signal input IN2, the first pole connects the second voltage end V2, and the second pole is connected with pull-up node PU.

Pull-up module 30 can include third transistor M3 and the first electric capacity C1.

Wherein, the grid of third transistor M3 connects pull-up node PU, and the first pole connects the first clock signal input terminal CLK, the second pole is connected with signal output part OUTPUT.

One end of first electric capacity C1 is connected with pull-up node PU, and the other end connects signal output part OUTPUT.

Drop-down control module 40 includes the 4th transistor M4, the 5th transistor M5 and the second electric capacity C2.

The grid of the 4th transistor M4 and the first pole connect the first clock signal input terminal CLK, the second pole and pull-down node PD is connected.

The grid of the 5th transistor M5 connects pull-up node PU, and the first pole connects pull-down node PD, the second pole and the 3rd electricity Pressure side V3 is connected.

One end of second electric capacity C2 connects second clock signal input part CLKB, and the other end is connected with pull-down node PD.

The drop-down module of touch-control 50 includes that the grid of the 6th transistor M6, the 6th transistor M6 connects touching signals and controls end SW, the first pole connects signal output part OUTPUT.

Charging module 60 includes the 7th transistor M7 and the 8th transistor M8.

Wherein, as in figure 2 it is shown, the grid of the 7th transistor M7 and the first pole connect touching signals controls end SW, the second pole Connect first pole of the 8th transistor M8.The grid of the 8th transistor M8 and the second pole connect pull-up node PU.

Or, when charging module 60 includes the 7th transistor M7 and the 8th transistor M8, the 7th transistor M7 and the 8th The connected mode of transistor M8 can be as it is shown on figure 3, the grid of the 7th transistor M7 connects pull-up node PU, and the first pole connects touches Control signal controls end SW, and the second pole is connected with the grid of the 8th transistor M8.First pole of the 8th transistor M8 connects touch-control Signal controls end SW, and the second pole is connected with pull-up node PU.

Additionally, noise reduction module 70 includes the 9th transistor M9 and the tenth transistor M10.

Wherein, the grid of the 9th transistor M9 connects pull-down node PD, and the first pole connects pull-up node PU, the second pole and the Three voltage end V3 are connected.

The grid of the tenth transistor M10 connects pull-down node PD, and the first pole connects signal output part OUTPUT, the second pole with Tertiary voltage end V3 is connected.

It should be noted that above-mentioned transistor can be N-type transistor, it is also possible to for P-type transistor；Can be enhancement mode Transistor, it is also possible to for depletion mode transistor；The first of above-mentioned transistor can be extremely source electrode, and second can be extremely drain electrode, or The first of the above-mentioned transistor of person can be extremely drain electrode, and the second extremely source electrode, this is not construed as limiting by the present invention.

Below as a example by above-mentioned transistor is N-type transistor, and combine Fig. 4 or Fig. 5 to shifting as shown in Figures 2 and 3 Each transistor in bit register unit, in the different stage of a picture frame (U is positive integer for such as U frame, U >=1) The break-make situation of (P1～P4) carries out detailed illustration.Wherein, the embodiment of the present invention is constant with the first voltage end V1 Output high level, the explanation carried out as a example by the second voltage end V2 and V3 constant output low level.Additionally, following description is with first Signal input part IN1 receives input signal INPUT, as a example by secondary signal input IN2 receives reset signal RESET.

When inputting without touching signals, above-mentioned touching signals controls end SW input low level, the 6th transistor M6, the 7th crystalline substance Body pipe M7 and the 8th transistor M8 is in cut-off state.

In the case, input phase P1, INPUT=1, RESET=0, CLK=0, CLKB=1；Wherein " 0 " represents low Level, " 1 " represents high level.

Now, owing to the first signal input part IN1 exports high level, therefore the first transistor M1 conducting, thus by first The high level output of voltage end V1 is to pull-up node PU, and is stored this high level by the first electric capacity C1.At pull-up joint Under the control of some PU, third transistor M3 turns on, by the low level of the first clock signal input terminal CLK to signal output part OUTPUT。

Under the control of pull-up node PU high potential, the 5th transistor M5 conducting.Therefore, even if second clock signal inputs End CLKB exports high level, and the current potential of pull-down node PD also can be pulled down to the low electricity of tertiary voltage end V3 by the 5th transistor M5 Flat.In the case, the 9th transistor M9 and the tenth transistor M10 is in cut-off state.

Additionally, the first clock signal input terminal CLK input low level so that the 4th transistor M4 cut-off, secondary signal is defeated Enter to hold IN2 input low level so that transistor seconds M2 ends.

In sum, signal output part OUTPUT is in above-mentioned input phase P1 output low level.

Output stage P2, INPUT=0, RESET=0, CLK=1, CLKB=0；

Now, due to the first signal input part IN1 output low level, therefore the first transistor M1 is in cut-off state.The Pull-up node PU is charged by the high level that input phase P1 is stored by one electric capacity C1, so that third transistor M3 keeps Opening.In the case, the high level of the first clock signal input terminal CLK is defeated to signal by the output of third transistor M3 Go out to hold OUTPUT.Additionally, under the bootstrapping (Bootstrapping) of the first electric capacity C1 acts on, the current potential of pull-up node PU enters one Step raises, with the state maintaining third transistor M3 to be on, so that the high level of the first clock signal input terminal CLK Can be as in gated sweep signal output to the grid line being connected with signal output part OUTPUT.

Additionally, under the control of pull-up node PU high potential, the 5th transistor M5 conducting, therefore, even if the first clock letter 4th transistor M4 is turned on by the high level of number input CLK input, and the high level of this first clock signal input terminal CLK passes through 4th transistor M4 exports to pull-down node, and the current potential of this pull-down node PD still can be pulled down to the 3rd by the 5th transistor M5 The low level of voltage end V3.In the case, the 9th transistor M9 and the tenth transistor M10 is in cut-off state.

Additionally, secondary signal input IN2 input low level so that transistor seconds M2 ends.

In sum, signal output part OUTPUT above-mentioned output stage P2 export high level, with to signal output part The grid line output gated sweep signal that OUTPUT is connected.

Reseting stage P3, INPUT=0, RESET=1, CLK=0, CLKB=1；

Now, owing to secondary signal input IN2 exports high level, transistor seconds M2 turns on, thus will pull up node The current potential of PU is pulled down to the low level of the second voltage end V2, so that pull-up node PU is resetted, and third transistor M3, the 5th crystalline substance Body pipe is in cut-off state.

Due to the first clock signal input terminal CLK input low level, so that the 4th transistor M4 is in cut-off state. And second clock signal input part CLKB input high level, under the boot strap of the second electric capacity C2, the current potential of pull-down node PD It is increased to high level, thus the 9th transistor M9 and the tenth transistor M10 is turned on, will be by the 9th by the 9th transistor M9 The current potential of pull-up node PU is pulled down to the low level of tertiary voltage end V3 by transistor M9, so that pull-up node PU is resetted, And by the tenth transistor M10, the current potential of signal output part OUTPUT is pulled down to the low level of tertiary voltage end V3, with to letter Number outfan OUTPUT resets.

Additionally, third transistor M3 is turned on by second clock signal input part CLKB output high level, and second clock letter Number input CLKB output high level grid by third transistor M3 transmission to the 4th transistor M4, described 4th transistor M4 turns on so that second clock signal input part CLKB output high level transmits to pull-down node PD, and by the second electric capacity C2 Above-mentioned high level is stored.

Additionally, the first signal input part IN1 input low level, transistor seconds M2 ends.

Noise reduction keeps stage P4, INPUT=0, RESET=0, CLK=1, CLKB=0；

Now, the first clock signal input terminal CLK input high level, by the 4th transistor M4 conducting, so that first The high level output of clock signal input terminal CLK is to pull-down node, under the control of this pull-down node PD, by the 9th transistor M9 With the tenth transistor M10 conducting, by the 9th transistor M9 by by the 9th transistor M9 by pull-up node PU current potential drop-down To the low level of tertiary voltage end V3, so that pull-up node PU is carried out noise reduction, and by the tenth transistor M10 by signal output part The current potential of OUTPUT is pulled down to the low level of tertiary voltage end V3, so that signal output part OUTPUT is carried out noise reduction.

Additionally, in this stage in addition to the 9th transistor M9 and the tenth transistor M10 turns on, remaining transistor is in Cut-off state.

It follows that can repeat reseting stage P3's and noise reduction holding stage P4 before next picture frame (U+1 frame) First signal input part IN1, secondary signal input IN2, the first clock signal input terminal CLK and the input of second clock signal The control signal of end CLKB, to carry out lasting noise reduction to signal output part OUTPUT.

When there being touching signals to input, as shown in Figure 4, touching signals can insert between two adjacent picture frames, example As inserted touching signals input phase P5 between U frame and U+1 frame, to input touch-control at this touching signals input phase P5 Signal.Or, when in display floater, the rate of scanning of grid line increases, when being greater than 60HZ, can be as it is shown in figure 5, at a figure As frame is inserted into, the such as input phase P2 in a picture frame is inserted into above-mentioned touching signals input phase P5, to touch at this Control signal input phase P5 inputs touching signals.

It should be noted that when above-mentioned touching signals input phase P5 inserts between two adjacent picture frames, or When in one picture frame, in addition to input phase P2, the stage inserts, although above-mentioned signal output part OUTPUT inputs at touching signals The stage P5 insertion moment is in the state of non-grid scanning signal output, but in order to avoid due to signal output part OUTPUT The signal of output produces fluctuation thus interferes touching signals, the shape that the 6th transistor M6 in Fig. 2 or Fig. 3 is on State such that it is able to the current potential of signal output part OUTPUT is pulled down to the low level of tertiary voltage end V3 so that signal output part OUTPUT avoids, at touching signals input phase P5, the interference that touching signals causes by signal fluctuation.

Additionally, as above-mentioned touching signals input phase P5 as it is shown in figure 5, the input phase that is inserted in a picture frame P2, in order to avoid signal output part OUTPUT interferes with touching signals at input phase P2 output gated sweep signal, Fig. 2 Or the 6th transistor M6 conducting in Fig. 3, it is possible to the current potential of signal output part OUTPUT is pulled down to the low of tertiary voltage end V3 Level so that signal output part OUTPUT avoids exporting gated sweep signal, to solve grid at touching signals input phase P5 The problem that scanning signal can interfere with touching signals.

On this basis, the 7th transistor M7 in Fig. 2 or Fig. 3 and the 8th transistor M8 is at input phase P2 The state of conducting, such that it is able to control the high level output extremely pull-up node PU of end SW, with to pull-up node PU by touching signals It is charged so that after touching signals end of input (i.e. after touching signals input phase P5 terminates), the current potential of pull-up node PU Can be maintained, thus avoid the TFT in shift register cell the such as the tenth transistor 10 and the 9th transistor M9 to occur The phenomenon leaked electricity and cause the current potential pulling up node PU to reduce so that signal output part OUTPUT keeps at above-mentioned output stage P2 Output gated sweep signal.

It should be noted that the switching process of transistor is to be for N-type transistor with all transistors in above-described embodiment Example illustrates, and when all transistors are p-type, need to overturn each control signal in Fig. 4 or Fig. 5, and moves In bit register unit, the make and break process of the transistor of modules is same as above, and here is omitted.

Additionally, the work process of above-mentioned shift register cell, it is to be constituted with the cascade of above-mentioned multiple shift register cells Gate driver circuit use the explanation that carries out as a example by the mode of forward scan.When using reverse scan, in Fig. 2 and Fig. 3 institute In the shift register cell shown, the first signal input part IN1 can be received reset signal RESET, secondary signal input IN2 receives input signal INPUT.Additionally, above-mentioned first voltage end V1 input low level, the second voltage end V2 input high level is i.e. Can.

The embodiment of the present invention provides a kind of gate driver circuit, as shown in Figure 6, and as described above including multiple cascades Any one shift register cell (RS1, RS2 ... RSn).

The first signal input part IN1 of first order shift register cell RS1 connects initial signal end STV, except first Beyond level shift register cell RS1, the signal output part OUTPUT of upper level shift register cell RS (n-1) and next stage First signal input part IN1 of shift register cell RS (n) is connected.Wherein, initial signal end STV is used for exporting initial letter Number, the first order shift register cell RS1 of this gate driver circuit starts grid line after receiving above-mentioned initial signal (G1, G2 ... Gn) progressively scans.

Additionally, in addition to afterbody shift register cell RSn, the secondary signal of next stage shift register cell Input IN2 connects the signal output part OUTPUT of upper level shift register cell.Afterbody shift register cell RSn Secondary signal input IN2 connect above-mentioned initial signal end STV.So, defeated when the initial signal of initial signal end STV When entering the first signal input part IN1 of first order shift register cell RS1, the of afterbody shift register cell RSn Binary signal input IN2 can using the initial signal of initial signal end STV as reset signal to afterbody shift register The signal output part OUTPUT of unit R Sn resets.

It should be noted that so that the first clock signal input terminal CLK of each shift register cell and The signal frequency of waveform, amplitude as shown in Fig. 4 or Fig. 5 of two clock signal input terminal CLKB outputs are identical, opposite in phase.Permissible As shown in Figure 6, the first clock signal input terminal CLK on different shift register cells and second clock signal input part CLKB Alternately it is connected with the first system clock signal input terminal CLK1 and second system clock signal input terminal CLK2 respectively.

Such as, the first clock signal input terminal CLK of first order shift register cell RS1 connects the first system clock letter Number input CLK1, second clock signal input part CLKB connect second system clock signal input terminal CLK2；The second level shifts The first clock signal input terminal CLK of register cell RS2 connects second system clock signal input terminal CLK2, and second clock is believed Number input CLKB connects the first system clock signal input terminal CLK3.The connected mode of following shift register cell ibid institute State.

On this basis, the first voltage end V1 of every one-level shift register cell connects high level VDD, the second voltage end V1 connects low level VSS, and tertiary voltage end V3 connects low level VGL.

Additionally, the connection side of each control signal when the gate driver circuit shown in Fig. 6 is that grid line carries out forward scan Method.When using this gate driver circuit that grid line is carried out reverse scan,

The secondary signal input IN2 of first order shift register cell RS1 connects initial signal end STV, except first Beyond level shift register cell RS1, the signal output part OUTPUT of upper level shift register cell RS (n-1) and next stage The secondary signal input IN2 of shift register cell RS (n) is connected.Except afterbody shift register cell RSn with Outward, the first signal input part IN1 of next stage shift register cell connects the signal output of upper level shift register cell End OUTPUT.The first signal input part IN1 of afterbody shift register cell RSn connects above-mentioned initial signal end STV.

On this basis, the first voltage end V1 of every one-level shift register cell connects low level VSS, the second voltage end V1 connects high level VDD, tertiary voltage end V3 and connects low level VGL.

The embodiment of the present invention provides a kind of display device, including any one gate driver circuit as above, has The structure identical with the gate driver circuit that previous embodiment provides and beneficial effect.Owing to grid is driven by previous embodiment Structure and the beneficial effect on galvanic electricity road are described in detail, and here is omitted.

The embodiment of the present invention provides a kind of method for driving any one shift register cell above-mentioned, concrete In one picture frame, described method includes:

Input phase P1 as shown in Fig. 4 or Fig. 5:

Under the control of the first signal input part IN1, the signal of the first voltage end V1 is exported extremely by the first input module 10 Pull-up node PU.The current potential of pull-up node PU is stored by pull-up module 30, and under the control of pull-up node PU, upper drawing-die The signal of the first clock signal input terminal CLK is exported to signal output part OUTPUT by block 30.

Additionally, drop-down control module 40 is under the control of second clock signal input part CLKB and pull-up node PU, under inciting somebody to action The current potential drawing node PD is pulled down to tertiary voltage end V3.Additionally, the second input module 20 and noise reduction module 70 are not all opened.

When in above-mentioned shift register cell the structure of modules as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in this input phase P1, the first clock signal input terminal CLK inputs low electricity Flat, second clock signal input part CKLB input high level, the first signal input part IN1 input high level, secondary signal inputs End IN2 input low level, pull-up node PU is high level, and pull-down node PD is low level, and signal output part OUTPUT output is low Level.

Based on this, the first signal input part IN1 input high level, the first input module 10 is at described first signal input part High level control under by the high level output of the first voltage end V1 to pull-up node PU.Concrete, at this input phase P1 In in above-mentioned modules the break-make situation of transistor be: owing to the first signal input part IN1 exports high level, therefore first is brilliant Body pipe M1 turns on, thus by the high level output of the first voltage end V1 to pull-up node PU, and by the first electric capacity C1 to this height Level stores.Under the control of pull-up node PU, third transistor M3 turns on, by the first clock signal input terminal CLK's Low level is to signal output part OUTPUT.

At output stage P2:

At the signal output extremely pull-up node PU that pull-up module 30 will store on last stage, in the control of pull-up node PU Under, first clock signal of the first clock signal input terminal CLK is exported to signal output part OUTPUT by pull-up module 30, this letter Number outfan OUTPUT exports gated sweep signal.

Additionally, drop-down control module 40 is under the control of second clock signal input part CLKB and pull-up node PU, under inciting somebody to action The current potential drawing node PD is pulled down to tertiary voltage end V3.Additionally, in this stage, first input module the 10, second input module 20 All do not open with noise reduction module 70.

When in above-mentioned shift register cell the structure of modules as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in this output stage P2, the first high electricity of clock signal input terminal CLK input Flat, second clock signal input part CLKB input low level, the first signal input part IN1 input low level, secondary signal inputs End IN2 input low level；Pull-up node PU is high level, and pull-down node PD is low level, and signal output part OUTPUT exports height Level.

Based on this, under the control of pull-up node PU high level, pull-up module 30 is by the first clock signal input terminal CLK's High level output is to signal output part OUTPUT.Concrete, transistor logical in above-mentioned modules in this output stage P2 Disconnected situation is: due to the first signal input part IN1 output low level, therefore the first transistor M1 is in cut-off state.First electricity Pull-up node PU is charged, so that third transistor M3 is held open by the high level that input phase P1 is stored by appearance C1 State.In the case, the high level of the first clock signal input terminal CLK is exported to signal output part by third transistor M3 OUTPUT.Additionally, under the bootstrapping (Bootstrapping) of the first electric capacity C1 acts on, the current potential of pull-up node PU rises further Height, with the state maintaining third transistor M3 to be on, so that the high level of the first clock signal input terminal CLK can As in gated sweep signal output to the grid line being connected with signal output part OUTPUT.

Reseting stage P3:

Drop-down control module 40 is under the control of second clock signal input part CLKB and pull-up node PU, by second clock The second clock signal of signal input part CLKB exports to pull-down node PD.Under the control of this pull-down node PD, noise reduction module The voltage of pull-up node PU and signal output part OUTPUT is pulled down to the current potential of tertiary voltage end V3 by 70.Second input module 20 Under the control of secondary signal input IN2, the current potential of pull-up node PU is pulled down to the current potential of the second voltage end V2.

Additionally, in this stage, the first input module 20, pull-up module 30 and drop-down control module 40 are not all opened.

When in above-mentioned shift register cell the structure of modules as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, in reseting stage P3, the first clock signal input terminal CLK inputs low electricity Flat, second clock signal input part CLKB input high level, the first signal input part IN1 input low level, secondary signal inputs End IN2 input high level；Pull-up node PU is low level, and pull-down node PD is high level, and signal output part OUTPUT output is low Level.

Based on this, the high level output of second clock signal input part CLKB is to pull-down node PD, in pull-down node PD Under control, the voltage of pull-up node PU and signal output part OUTPUT is pulled down to the low electricity of tertiary voltage end V3 by noise reduction module 70 Flat.Secondary signal input CLKB input high level, the current potential of pull-up node PU is pulled down to the second electricity by the second input module 20 The low level of pressure side V2.Concrete, in this reseting stage P3, in above-mentioned modules, the break-make situation of transistor is: due to the Binary signal input IN2 exports high level, and transistor seconds M2 turns on, thus the current potential of pull-up node PU is pulled down to the second electricity The low level of pressure side V2, to reset pull-up node PU, third transistor M3, the 5th transistor are in cut-off state.

Noise reduction holding stage P4:

Drop-down control module 40 is under the control of the first clock signal input terminal CLK and pull-up node PU, by the first clock First clock signal of signal input part CLK exports to pull-down node PD.Under the control of pull-down node PD, noise reduction module 70 will The voltage of pull-up node PU and signal output part OUTPUT is pulled down to the current potential of tertiary voltage end V3.

It follows that repeated reseting stage P3 and the first of noise reduction holding stage P4 before next picture frame (U+1 frame) Signal input part IN1, secondary signal input IN2, the first clock signal input terminal CLK and second clock signal input part The control signal of CLKB so that signal output part OUTPUT keeps the state of no signal output.

When in above-mentioned shift register cell the structure of modules as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, keep stage P4, the first high electricity of clock signal input terminal CLK input at noise reduction Flat, second clock signal input part CLKB input low level, the first signal input part IN1 input low level, secondary signal inputs End IN2 input low level；Pull-up node PU is low level, and pull-down node PD is high level, and signal output part OUTPUT output is low Level.

Based on this, the high level output of the first clock signal input terminal CLK to pull-down node PD, in the control of pull-down node PD Under system, the voltage of pull-up node PU and signal output part OUTPUT is pulled down to the low electricity of tertiary voltage end V3 by noise reduction module 70 Flat.Concrete, in this noise reduction keeps stage P4, in above-mentioned modules, the break-make situation of transistor is: the first clock signal is defeated Enter to hold CLK input high level, by the 4th transistor M4 conducting, so that the high level of the first clock signal input terminal CLK is defeated Go out to pull-down node, under the control of this pull-down node PD, the 9th transistor M9 and the tenth transistor M10 are turned on, by the Nine transistor M9 by being pulled down to the low level of tertiary voltage end V3 by the 9th transistor M9 by the current potential of pull-up node PU, with right Pull-up node PU carries out noise reduction, and by the tenth transistor M10, the current potential of signal output part OUTPUT is pulled down to tertiary voltage The low level of end V3, to carry out noise reduction to signal output part OUTPUT.

Further, when there being touching signals to input, above-mentioned driving method also includes that touch-control is believed as shown in Fig. 4 or Fig. 5 Number input phase P5, in this stage, the drop-down module of touch-control 50 is under touching signals controls the control of end SW, by signal output part The current potential of OUTPUT is pulled down to the current potential of tertiary voltage end V3.

When in above-mentioned shift register cell the structure of modules as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, at touching signals input phase P5, touching signals controls end 50 and inputs high electricity Flat；Described signal output part output low level.

Based on this, touching signals controls end SW and exports high level, and the drop-down module of touch-control 50 is by signal output part OUTPUT's Current potential is pulled down to the low level of tertiary voltage end V3.Concrete, the drop-down module of touch-control 50 in this touching signals input phase P5 In the state that is on of the 6th transistor M6 such that it is able to the current potential of signal output part OUTPUT is pulled down to tertiary voltage The low level of end V3 so that signal output part OUTPUT avoids signal fluctuation to make touching signals at touching signals input phase P5 The interference become.

It should be noted that as shown in Figure 4, touching signals can insert, adjacent two between two adjacent picture frames Between two field picture frame, such as between U frame and U+1 frame, insert above-mentioned touching signals input phase P5.

Or, when there being touching signals to input, as it is shown in figure 5, the output stage in a picture frame (such as U frame) inserts Entering touching signals input phase P5, this driving method also includes:

Touching signals, under the control that pull-up node PU and touching signals control end SW, is controlled end SW's by charging module 60 Signal output is to pull-up node PU, and is stored the current potential of pull-up node PU by pull-up module 30.

When in above-mentioned shift register cell the structure of modules as shown in figures 2 and 3, and the transistor in modules When being N-type transistor, as shown in Fig. 4 or Fig. 5, at touching signals input phase P5, touching signals controls end 50 and inputs high electricity Flat；Pull-up node PU is high level, and pull-down node PD is low level, signal output part OUTPUT output low level.

Based on this, touching signals controls end SW and exports high level, and pull-up node PU exports high level, and charging module 60 will touch Control signal controls the high level output of end SW to pulling up node PU.Concrete, in this touching signals input phase P5 above-mentioned respectively In individual module, the break-make situation of transistor is: the 6th transistor M6 conducting in Fig. 2 or Fig. 3, it is possible to by signal output part The current potential of OUTPUT is pulled down to the low level of tertiary voltage end V3 so that signal output part OUTPUT is at touching signals input phase P5 avoids exporting gated sweep signal, to solve the problem that gated sweep signal can interfere with touching signals.

The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited thereto, and any Those familiar with the art, in the technical scope that the invention discloses, can readily occur in change or replace, should contain Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with described scope of the claims.

Claims

1. a shift register cell, it is characterised in that include the first input module, the second input module, pull-up module, under Draw the drop-down module of control module, touch-control, charging module, noise reduction module；

Described first input module connects the first signal input part, the first voltage end and pull-up node, for described first Under the control of signal input part, the signal of described first voltage end is exported to described pull-up node；

Described second input module connects secondary signal input, the second voltage end and described pull-up node, for second Under the control of signal input part, the signal of described second voltage end is exported to described pull-up node；

Described pull-up module connects described first clock signal input terminal, signal output part and described pull-up node, is used for Under the control of described pull-up node, the first clock signal output of described first clock signal input terminal is exported to described signal End, and the current potential of described pull-up node is stored；

Described drop-down control module connects described pull-up node, described first clock signal input terminal, the input of second clock signal End, tertiary voltage end and pull-down node, be used for described first clock under the control of described first clock signal input terminal First clock signal output of signal input part is to described pull-down node；Or at described second clock signal input part Under control, the second clock signal of described second clock signal input part is exported to described pull-down node；Or for described Under the control of pull-up node, the current potential of described pull-down node is pulled down to the current potential of described tertiary voltage end；

The drop-down module of described touch-control connects described signal output part, touching signals controls end and described tertiary voltage end, is used for Under described touching signals controls the control of end, the current potential of described signal output part is pulled down to the electricity of described tertiary voltage end Position；

Described charging module connects described touching signals and controls end and described pull-up node, at described pull-up node and touch-control Under the control of signal end, described touching signals is controlled the signal output of end to described pull-up node；

Described noise reduction module connects described pull-down node, described pull-up node, signal output part and described tertiary voltage end, uses Under the control in described pull-down node, respectively the current potential of described pull-up node and described signal output part is pulled down to described The current potential of three voltage ends.

Shift register cell the most according to claim 1, it is characterised in that described first input module includes that first is brilliant Body pipe, grid described first signal input part of connection of described the first transistor, the first described first voltage end of pole connection, second Pole is connected with described pull-up node.

Shift register cell the most according to claim 1, it is characterised in that described second input module includes that second is brilliant Body pipe, the grid described secondary signal input of connection of described transistor seconds, the first described second voltage end of pole connection, second Pole is connected with described pull-up node.

Shift register cell the most according to claim 1, it is characterised in that described pull-up module includes third transistor With the first electric capacity；

The grid of described third transistor connects described pull-up node, and the first pole connects described first clock signal input terminal, the Two poles are connected with described signal output part；

One end of described first electric capacity is connected with described pull-up node, and the other end connects described signal output part.

Shift register cell the most according to claim 1, it is characterised in that described drop-down control module includes that the 4th is brilliant Body pipe, the 5th transistor and the second electric capacity；

The grid of the 4th transistor and the first pole connect described first clock signal input terminal, the second pole and described pull-down node phase Connect；

The grid of described 5th transistor connects described pull-up node, and the first pole connects described pull-down node, and the second pole is with described Tertiary voltage end is connected；

One end of described second electric capacity connects described second clock signal input part, and the other end is connected with described pull-down node.

Shift register cell the most according to claim 1, it is characterised in that the drop-down module of described touch-control includes that the 6th is brilliant Body pipe, the grid of described 6th transistor connects touching signals and controls end, and the first pole connects described signal output part.

Shift register cell the most according to claim 1, it is characterised in that described charging module includes the 7th transistor With the 8th transistor；

The grid of described 7th transistor and the first pole connect described touching signals and control end, and the second pole connects described 8th crystal First pole of pipe；

The grid of described 8th transistor and the second pole connect described pull-up node.

The grid of described 7th transistor connects pull-up node, and the first pole connects described touching signals and controls end, the second pole and institute The grid stating the 8th transistor is connected；

First pole of described 8th transistor connects described touching signals and controls end, and the second pole is connected with described pull-up node.

Shift register cell the most according to claim 1, it is characterised in that described noise reduction module includes the 9th transistor With the tenth transistor；

The grid of described 9th transistor connects described pull-down node, and the first pole connects described pull-up node, and the second pole is with described Tertiary voltage end is connected；

The grid of described tenth transistor connects described pull-down node, and the first pole connects described signal output part, the second pole and institute State tertiary voltage end to be connected.

10. a gate driver circuit, it is characterised in that include the shifting as described in any one of claim 1-9 of multiple cascade Bit register unit, it is characterised in that

First signal input part of first order shift register cell connects initial signal end；

In addition to first order shift register cell, the signal output part of upper level shift register cell connects next stage and moves First signal input part of bit register unit；

In addition to afterbody shift register cell, in the secondary signal input connection of next stage shift register cell The signal output part of one-level shift register cell；

The secondary signal input of afterbody shift register cell connects described initial signal end.

11. 1 kinds of display devices, it is characterised in that include gate driver circuit as claimed in claim 10.

The driving method of 12. 1 kinds of shift register cells, it is characterised in that in a picture frame, described method includes:

Input phase:

Under the control of the first signal input part, the signal of the first voltage end is exported to pulling up node by the first input module；

The current potential of described pull-up node is stored by pull-up module, and under the control of described pull-up node, described upper drawing-die The signal of the first clock signal input terminal is exported to signal output part by block；

The output stage:

At the signal output extremely described pull-up node that pull-up module will store on last stage, under the control of described pull-up node, Described pull-up module is by the first clock signal output extremely described signal output part, described letter of described first clock signal input terminal Number outfan output gated sweep signal；

Reseting stage:

Drop-down control module is under the control of described second clock signal input part and described pull-up node, by described second clock The second clock signal of signal input part exports to pull-down node；

Under the control of described pull-down node, described noise reduction module is by under the voltage of described pull-up node and described signal output part It is pulled to the current potential of described tertiary voltage end；

The current potential of pull-up node, under the control of secondary signal input, is pulled down to described second voltage end by the second input module Current potential；

Noise reduction keeps the stage:

Described drop-down control module is under the control of described first clock signal input terminal and described pull-up node, by described first First clock signal of clock signal input terminal exports to pull-down node；

Before next picture frame, repeat described reseting stage and described noise reduction keeps first signal input part in stage, the second letter Number input, the first clock signal input terminal and the control signal of second clock signal input part so that described signal exports End keeps the state of no signal output；

Touching signals input phase:

The current potential of described signal output part, under touching signals controls the control of end, is pulled down to the described 3rd by the drop-down module of touch-control The current potential of voltage end.

The driving method of 13. shift register cells according to claim 12, it is characterised in that at adjacent two two field pictures Described touching signals input phase is inserted between frame.

The driving method of 14. shift register cells according to claim 12, it is characterised in that defeated in a picture frame Going out the described touching signals input phase of stage insertion, at described input phase, described driving method also includes:

Described touching signals, under the control that described pull-up node and described touching signals control end, is controlled end by charging module Signal exports to pulling up node, and is stored the current potential of described pull-up node by pull-up module.

The driving method of 15. shift register cells according to claim 12, it is characterised in that when described shift LD When transistor in device unit is N-type transistor, at the first voltage end input high level, tertiary voltage end input low level In the case of, described method includes:

Described input phase: described first signal input part input high level, described first input module is at described first signal By the high level output of described first voltage end to pulling up node under the control of the high level of input；

The described output stage: under the control of described pull-up node high level, described pull-up module is by described first clock signal The high level output of input is to described signal output part；

Described reseting stage: the high level output of described second clock signal input part to described pull-down node, described drop-down Under the control of node, the voltage of described pull-up node and described signal output part is pulled down to described 3rd electricity by described noise reduction module The low level of pressure side；

Described secondary signal input input high level, the height that described second input module inputs at described secondary signal input Under the control of level, the current potential of pull-up node is pulled down to the low level of described second voltage end；

Described noise reduction keeps the stage: the high level output of described first clock signal input terminal to described pull-down node, described Under the control of pull-down node, the voltage of described pull-up node and described signal output part is pulled down to described by described noise reduction module The low level of three voltage ends；

Described touching signals input phase: described touching signals controls end output high level, and the drop-down module of described touch-control is described Under the control of the high level that touching signals controls end output, the current potential of described signal output part is pulled down to described tertiary voltage end Low level.

The driving method of 16. shift register cells according to claim 14, it is characterised in that when described shift LD When transistor in device unit is N-type transistor,

Described touching signals input phase: described touching signals controls end output high level, and described pull-up node exports high level, Described touching signals is controlled the high level output of end to described pull-up node by described charging module.