CN103413531A - Shifting register unit, gate driving circuit and display device - Google Patents

Shifting register unit, gate driving circuit and display device Download PDF

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Publication number
CN103413531A
CN103413531A CN2013103089949A CN201310308994A CN103413531A CN 103413531 A CN103413531 A CN 103413531A CN 2013103089949 A CN2013103089949 A CN 2013103089949A CN 201310308994 A CN201310308994 A CN 201310308994A CN 103413531 A CN103413531 A CN 103413531A
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China
Prior art keywords
utmost point
transistor
signal
control node
shift register
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CN2013103089949A
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Chinese (zh)
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CN103413531B (en
Inventor
马磊
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北京京东方光电科技有限公司
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift register stack stores, push-down stores using semiconductor elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • G09G3/3677Details of drivers for scan electrodes suitable for active matrices only

Abstract

The invention provides a shifting register unit, a gate driving circuit and a display device, and relates to the technical field of display. The coupling capacitance of a thin film transistor can be reduced. Noise of an output signal can be reduced. The shifting register unit comprises an input module, a control module, a restoration module, an upwards-pulling module, a downwards-pulling module and a noise reduction module. The shifting register unit, the gate driving circuit and the display device are used for achieving scanning driving.

Description

A kind of shift register cell, gate driver circuit and display device

Technical field

The present invention relates to the display technique field, relate in particular to a kind of shift register cell, gate driver circuit and display device.

Background technology

Liquid crystal display (Liquid Crystal Display, be called for short LCD) has low radiation, volume is little and the advantage such as low power consuming, is widely used in the electronic products such as notebook computer, flat-surface television or mobile phone.

Liquid crystal display is to form by the picture element matrix that is positioned at horizontal and vertical directions is staggered, when liquid crystal display shows, data drive circuit can sequentially latch the demonstration data of input and clock signal timing, convert after simulating signal the data line that is input to liquid crystal panel to, the grid stage drive circuit can convert the clock signal of input to the voltage of controlling the pixel on/off through shift register, and is applied to line by line on the grid level line of liquid crystal panel.

In order further to reduce the production cost of lcd products, existing gate driver circuit often adopts GOA(Gate Driver on Array, the capable driving of array base palte) design is by TFT(Thin Film Transistor, Thin Film Transistor (TFT)) the gate switch circuit is integrated on the array base palte of display panel to form the turntable driving to display panel, thereby can save the grid-driving integrated circuit part, it not only can reduce cost of products from material cost and manufacture craft two aspects, and display panel can be accomplished the design for aesthetic of both sides symmetry and narrow frame.This GOA of utilization technology is integrated in gate switch circuit on array base palte also referred to as GOA circuit or shift-register circuit.

In prior art, typically utilize the GOA technology shift register structure as shown in Figure 1, Fig. 2 is the input and output sequential chart of this shift register.As can be known in conjunction with Fig. 1 and Fig. 2, the course of work of this shift register is: the T1 stage, and signal input part Input input high level, thin film transistor (TFT) M1 conducting is capacitor C 1 charging, thin film transistor (TFT) M3 closes and makes the Output output low level; The T2 stage, clock signal terminal CLK input high level, the bootstrapping of capacitor C 1 (Bootstrapping) effect is further drawn high the grid level of thin film transistor (TFT) M3, thin film transistor (TFT) M3 conducting, Output exports high level; The T3 stage, reset signal end Reset input high level, now thin film transistor (TFT) M2 and M4 conducting, be pulled low to the Vss low level by the level of the grid level of thin film transistor (TFT) M3 and Output; In the T4 stage, the grid level of thin film transistor (TFT) M3 and the level of Output are pulled low to the Vss low level; The T5 stage, Input, CLK, the equal input low level of Reset, now thin film transistor (TFT) M1 to M4 keeps closing, the Output output low level.After this until when Input was high level, this shift register repeated T4 and T5 stage next time, can be called the non-working time of shift register this period.Can find out shift register in the course of the work, electric weight in the coupling capacitance of M3 self is not discharged fully, so can cause noise to signal output part Output, thereby reduce the stability of GOA circuit, and in each shift register, include a plurality of TFT, can increase the size of GOA circuit and the production cost of product.

Summary of the invention

Embodiments of the invention provide a kind of shift register cell, gate driver circuit and display device.Can reduce the coupling capacitance of thin film transistor (TFT), reduce the noise of output signal.

For achieving the above object, embodiments of the invention adopt following technical scheme:

The one side of the embodiment of the present invention provides a kind of shift register cell, comprising: load module, control module, reseting module, upper drawing-die piece, drop-down module and noise reduction module;

Described load module, connect respectively the first signal input end and on draw the control node, draw the current potential of controlling node on described for the signal controlling according to the input of described first signal input end;

Described control module, connect respectively the first clock signal terminal, second clock signal end, the first voltage end, draw on described and control node and drop-down control node, for the signal of the signal according to described the first clock signal terminal input, the input of described second clock signal end or described on draw the current potential of the described drop-down control node of control of Electric potentials of controlling node;

Described reseting module, connect respectively secondary signal input end, described the first voltage end, draw on described and control node and described drop-down control node, resets on described and draw the current potential of controlling node for the signal according to described secondary signal input end input;

Described upper drawing-die piece, connect respectively described the first clock signal terminal, draw on described and control node and signal output part at the corresponding levels, on described, drawing under the control of controlling node potential the signal that makes described the first clock signal terminal of described signal output part output at the corresponding levels;

Described drop-down module, connect respectively described the first voltage end, described drop-down control node and described signal output part at the corresponding levels, under the control at described drop-down control node potential by the signal of described signal output part at the corresponding levels output drop-down be low level;

Described noise reduction module, connect respectively described the first clock signal terminal, draw on described and control node and signal output part at the corresponding levels, for the signal by described the first clock signal terminal of described signal output part output at the corresponding levels.

Described load module comprises:

The first transistor, its first utmost point is connected described first signal input end with grid, second utmost point with described on draw and control node and be connected.

Described reseting module comprises:

Transistor seconds, draw the control node on its first utmost point connection is described, and grid connects described secondary signal input end, and second utmost point is connected with described the first voltage end;

The 5th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described secondary signal input end, and second utmost point is connected with described the first voltage end.

Described drop-down module comprises:

The 3rd transistor, draw the control node on its first utmost point connection is described, and grid connects described drop-down control node, and second utmost point is connected with described the first voltage end.

The 4th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described drop-down control node, and second utmost point is connected with described the first voltage end.

Described load module comprises:

The first transistor, its first utmost point connects second voltage end, grid connects described first signal input end, second utmost point with described on draw the control node to be connected.

Described reseting module comprises:

Transistor seconds, draw the control node on its first utmost point connection is described, and grid connects described secondary signal input end, and second utmost point is connected with the tertiary voltage end;

Described drop-down module also comprises:

The 3rd transistor, draw the control node on its first utmost point connection is described, and grid connects described drop-down control node, and second utmost point is connected with described the first voltage end.

The 4th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described drop-down control node, and second utmost point connects described the first voltage end;

The 5th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described second clock signal end, and second utmost point is connected with described the first voltage end.

Described control module comprises:

The 6th transistor, grid connects described the first clock signal terminal, and its first utmost point connects described second clock signal end, and second utmost point is connected with described drop-down control node;

The 7th transistor, its first utmost point is connected described second clock signal end with grid, and second utmost point is connected with described drop-down control node;

The 8th transistor, its first utmost point connects described drop-down control node, draws the control node on the grid connection is described, and second utmost point is connected with described the first voltage end.

Described upper drawing-die piece comprises:

The 9th transistor, its first utmost point connects described the first clock signal terminal, draws the control node on the grid connection is described, and second utmost point is connected with described signal output part at the corresponding levels;

Electric capacity, it is parallel between described the 9th transistorized grid and second utmost point.

Described noise reduction module comprises:

At least one the tenth transistor, its first utmost point connects described the first clock signal terminal, draws the control node on the grid connection is described, and second utmost point is connected with described signal output part at the corresponding levels.

The embodiment of the present invention a kind of gate driver circuit is provided on the other hand, comprise multistage shift register cell as above.

Except first order shift register cell, the signal input part of all the other each shift register cells connects the signal output part at the corresponding levels of the upper level shift register cell be adjacent;

Except the afterbody shift register cell, the signal input part of the next stage shift register cell that the signal output part at the corresponding levels of all the other each shift register cells is adjacent is connected.

The another aspect of the embodiment of the present invention provides a kind of display device, comprises grid circuit as above.

The invention provides a kind of shift register cell, gate driver circuit and display device.This shift register cell comprises load module, control module, reseting module, upper drawing-die piece, drop-down module and noise reduction module, by the noise reduction module of connecting with drawing-die piece on this, can reduce the size of thin film transistor (TFT) in upper drawing-die piece, so, can reduce the coupling capacitance of thin film transistor (TFT) in upper drawing-die piece, thereby reduce the noise of output signal.

The accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

The structural representation of a kind of shift register cell that Fig. 1 provides for prior art;

Signal sequence oscillogram when a kind of shift register cell that Fig. 2 provides for prior art is worked;

The circuit connection structure schematic diagram of a kind of shift register cell that Fig. 3 provides for the embodiment of the present invention;

The structural representation of a kind of shift register cell that Fig. 4 provides for the embodiment of the present invention;

The structural representation of the another kind of shift register cell that Fig. 5 provides for the embodiment of the present invention;

Signal sequence oscillogram when a kind of shift register cell that Fig. 6 provides for the embodiment of the present invention is worked;

The working state schematic representation of the shift register cell that Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 provide for the embodiment of the present invention;

The structural representation of a kind of gate driver circuit that Figure 12 embodiment of the present invention provides.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.

The transistor adopted in all embodiment of the present invention all can be thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the transistorized source electrode adopted here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein a utmost point is called source electrode, and another utmost point is called drain electrode.In addition, according to transistorized characteristic, distinguish and transistor can be divided into to N-type transistor or P transistor npn npn, in embodiments of the present invention, when adopting the N-type transistor, it first can be extremely source electrode, and second can be extremely drain electrode, when adopting the P transistor npn npn, its first can be extremely the drain electrode, second can be extremely source electrode.The transistor adopted in the embodiment of the present invention can be the N-type transistor, also can be the P transistor npn npn.In following examples, be all to take transistor to be the explanation that the N-type transistor carries out as example, can expect, when all adopting the P transistor npn npn, need corresponding adjustment to drive the sequential of signal.

Embodiments of the invention provide a kind of shift register cell, as shown in Figure 3, can comprise: load module 10, control module 20, reseting module 30, upper drawing-die piece 40, drop-down module 50 and noise reduction module 60.

Wherein, load module 10, can connect respectively first signal input end Input and on draw and control node PU, on the signal controlling according to first signal input end Input input, drawing the current potential of controlling node PU.For example, when the signal of first signal input end Input input is high level, on draw the current potential of controlling node PU to be drawn high as noble potential.

Control module 20, can connect respectively the first clock signal terminal CLK, second clock signal end CLKB, the first voltage end V1, on draw and control node PU and drop-down control node PD, for the signal of the signal according to this first clock signal terminal CLK input, second clock signal end CLKB input or on draw the current potential of this drop-down control node PD of control of Electric potentials that controls node PU.It should be noted that, the signal period same phase of the first clock signal terminal CLK and second clock signal end CLKB input is opposite.

In embodiments of the present invention, on draw and control node PU and refer to the circuit node of opening or closing be used to controlling upper drawing-die piece, drop-down control node PD refers to the circuit node of opening or closing be used to controlling drop-down module.

Reseting module 30, can connect respectively secondary signal input end Reset, the first voltage end V1, on draw and control node PU and drop-down control node PD, on for the signal according to secondary signal input end Reset input, resetting, draw the current potential of controlling node PU.

Upper drawing-die piece 40, can connect respectively the first clock signal terminal CLK, on draw and control node PU and signal output part Output at the corresponding levels, thereby for upper drawing under the control of controlling node PU current potential, making the signal of signal output part Output output at the corresponding levels the first clock signal terminal CLK make this shift register cell output drive signal.

Drop-down module 50, can connect respectively described the first voltage end V1, drop-down control node PD and signal output part Output at the corresponding levels, under the control at drop-down control node PD current potential by the signal of signal output part Output at the corresponding levels output drop-down be low level.

Noise reduction module 60, can connect respectively the first clock signal terminal CLK, on draw and control node PU and signal output part Output at the corresponding levels, for the signal by signal output part Output output at the corresponding levels the first clock signal terminal CLK, thereby reduce the above noise of drawing-die piece 40 output signals.

The invention provides a kind of shift register cell, this shift register cell comprises load module, control module, reseting module, upper drawing-die piece, drop-down module and noise reduction module, by the noise reduction module of connecting with drawing-die piece on this, can reduce the size of thin film transistor (TFT) in upper drawing-die piece, so, can reduce the coupling capacitance of thin film transistor (TFT) in upper drawing-die piece, thereby reduce the noise of output signal.

Wherein, the first voltage end V1 can be earth terminal, or the first voltage end V1 input low level VSS or VGL.In embodiments of the present invention, as shown in Figure 4, be all to take the explanation that the first voltage end V1 input low level VSS carries out as example.

Further, as shown in Figure 4, load module 10 can comprise: the first transistor M1, its first utmost point is connected first signal input end Input with grid, second utmost point with on draw and control node PU and be connected.So, by the first transistor M1, can be somebody's turn to do and draw the current potential of controlling node PU according to the signal controlling of first signal input end Input input.

Further, reseting module 30 can comprise: transistor seconds M2, its first utmost point draw on connecting and control node PU, and grid connects secondary signal input end Reset, and second utmost point is connected with the first voltage end V1.

The 5th transistor M5, its first utmost point connects signal output part Output at the corresponding levels, and grid connects secondary signal input end Reset, and second utmost point is connected with the first voltage end V1.So, by transistor seconds M2 and the 5th transistor M5, can make according to the reset signal of secondary signal input end Reset input and draw the current potential of controlling node PU and signal output part Output at the corresponding levels to be resetted.

Further, drop-down module 50 can comprise: the 3rd transistor M3, its first utmost point draw on connecting and control node PU, and grid connects drop-down control node PD, and second utmost point is connected with the first voltage end V1.

The 4th transistor M4, its first utmost point connects signal output part Output at the corresponding levels, and grid connects drop-down control node PD, and second utmost point is connected with the first voltage end V1.So, when on draw when controlling node PU and being high level, drop-down control node PD is low level, the 3rd transistor M3 and the 4th transistor M4 are in cut-off state, guarantee the output that PU node and Output are ordered; When on draw that to control node PU be low level, drop-down control node PD is high level, and during second clock signal end CLKB input high level, by the 3rd transistor M3, the 4th transistor M4, by the signal of signal output part Output output drop-down be low level, thereby can avoid better signal output part Output at the corresponding levels to become high level under the effect of other undesired signals, and its delegation's grid line of controlling is opened under the high level effect, finally cause grid line to open mistake.

Perhaps, as shown in Figure 5, load module 10 can comprise:

The first transistor M1, its first utmost point connect second voltage end V2, and grid connects first signal input end Input, second utmost point with on draw control node PU to be connected.So, by the first transistor M1, can be somebody's turn to do and draw the current potential of controlling node PU according to the signal controlling of first signal input end Input input.

Further, reseting module 30 can comprise: transistor seconds M2, its first utmost point draw on connecting and control node PU, and grid connects secondary signal input end Reset, and second utmost point is connected with the first voltage end V1.So, by transistor seconds M2, can make according to the reset signal of secondary signal input end Reset input and draw the current potential of controlling node PU to be resetted.

It should be noted that, in the structure of as shown in Figure 5 shift register cell, be with the first voltage end V1 input low level VGL, and second voltage end V2 input high level VDD and tertiary voltage end V3 input low level VSS are the explanation that example is carried out.

Further, drop-down module 50 can comprise: the 3rd transistor M3, its first utmost point draw on connecting and control node PU, and grid connects drop-down control node PD, and second utmost point is connected with the first voltage end V1.

The 4th transistor M4, its first utmost point connects signal output part Output at the corresponding levels, and grid connects drop-down control node PD, and second utmost point connects the first voltage end V1.

The 5th transistor M5, its first utmost point connects signal output part Output at the corresponding levels, and grid connects second clock signal end CLKB, and second utmost point is connected with the first voltage end V1.So, when on draw that to control node PU be low level, drop-down control node PD is high level, and during second clock signal end CLKB input high level, by the 3rd transistor M3, the 4th transistor M4, the 5th transistor M5, can by the signal of signal output part Output output drop-down be low level, thereby can avoid better signal output part Output at the corresponding levels to become high level under the effect of other undesired signals, and its delegation's grid line of controlling is opened under the high level effect, finally cause grid line to open mistake.

It should be noted that, as shown in Figure 4, the signal output part at the corresponding levels of shift register cells at different levels is output signal control each row grid line and open successively under the high level effect from top to bottom, realizes each row grid line is lined by line scan.

As shown in Figure 5, the signal output part at the corresponding levels of shift register cells at different levels not only from top to bottom output signal each row grid line is lined by line scan, and can to each row grid line, line by line scan from bottom to top.Concrete when input signal and voltage end as shown in Figure 5 the time, shift register cells at different levels can be lined by line scan to each row grid line from top to bottom, when the first signal input end Input by Fig. 5 and secondary signal input end Reset exchange, second voltage end V2 is during with tertiary voltage end V3 exchange, shift register cells at different levels are output signal each row grid line is lined by line scan from bottom to top just, so can realize bilateral scanning.Thereby can with the current potential that is connected voltage, just can carry out the scanning of different directions to each row grid line by the input signal that changes shift register cell, those skilled in the art can adjust it as the case may be.

Further, as Fig. 4 or shown in Figure 5, control module 20 can comprise:

The 6th transistor M6, grid connects the first clock signal terminal CLK, and its first utmost point connects second clock signal end CLKB, and second utmost point is connected with drop-down control node PD.

The 7th transistor M7, its first utmost point is connected second clock signal end CLKB with grid, and second utmost point is connected with drop-down control node PD.

The 8th transistor M8, its first utmost point connects drop-down control node PD, and grid draws and controls node PU on connecting, and second utmost point is connected with the first voltage end V1.So, by the 6th transistor M6, the 7th transistor M7 and the 8th transistor M8, can according to the signal of the signal of this first clock signal terminal CLK input, second clock signal end CLKB input or on draw the current potential of this drop-down control node PD of control of Electric potentials that controls node PU.

Further, as Fig. 4 or shown in Figure 5, upper drawing-die piece 40 can comprise:

The 9th transistor M9, its first utmost point connects the first clock signal terminal CLK, and grid draws and controls node PU on connecting, and second utmost point is connected with signal output part Output at the corresponding levels.

Capacitor C 1, it is parallel between the grid and second utmost point of the 9th transistor M9.So, by the 9th transistor M9 and capacitor C 1, can will on the signal of described signal output part output at the corresponding levels, draw as high level upper drawing under the control of controlling node potential;

In embodiments of the present invention, the effect of upper drawing-die piece 40 is after capacitor C 1 is carried out to preliminary filling, and the first clock signal clk is in half clock period of high level, the high level signal that makes signal output part Output output grid at the corresponding levels drive.

Further, as Fig. 4 or shown in Figure 5, noise reduction module 60 can comprise: at least one the tenth transistor M10, and its first utmost point connects the first clock signal terminal CLK, and grid draws and controls node PU on connecting, and second utmost point is connected with signal output part Output at the corresponding levels.

It should be noted that; noise reduction module 60 can also be a plurality of transistors identical with the tenth transistor M10 connected mode; here be only to take to include only as the noise reduction module in Fig. 4 or Fig. 5 the explanation that the tenth a transistor M10 carries out as example; the noise reduction module of other structure is given an example no longer one by one at this, but within all should belonging to protection scope of the present invention.

In the embodiment of the present invention, noise reduction module 60 is for the signal by signal output part Output output at the corresponding levels the first clock signal terminal CLK, thus the noise of upper drawing-die piece 40 output signals of reduction.Specifically by the 9th transistor M9 in the tenth transistor M10 and upper drawing-die piece 40 as Fig. 4 or connected mode shown in Figure 5, to be connected, so, the size of the tenth transistor M10 does not need very large, and the coupling capacitance that the tenth transistor M10 and the coupling capacitance after the 9th transistor M9 is connected are compared the 9th transistor M9 is little, and then reduced the impact of the 9th transistor M9 coupling capacitance, thereby reduced the noise of upper drawing-die piece 40 output signals; In general, adopt shift register to realize that GOA is mainly in order to make the narrow frame of display device, therefore, in each shift register cell, transistorized quantity is very crucial, the number of transistors adopted is fewer, more easily realizes narrow frame, and the present embodiment is by increasing transistorized scheme, through verification experimental verification, can reduce transistorized size in output module, and then realize decrease of noise functions.

Below take structure shown in Figure 5 as example and in conjunction with the input and output sequential chart of this shift register as shown in Figure 6, the course of work of shift register cell is described in detail.

The T1 stage: CLK=0; CLKB=1; Pu=1; Input=1; Output=0; Reset=0.

As shown in Figure 7, due to first signal input end Input=1, therefore the first transistor M1 conducting control shift register and start working, first signal input end Input by the first transistor M1 by draw the current potential of controlling node PU to draw high and be that memory capacitance C1 charges.Due to second clock signal end CLKB=1, therefore the 5th transistor M5 conducting, be pulled low to low level VGL by signal output part Output at the corresponding levels, and simultaneously, the 7th also conducting of transistor M7, draw high drop-down control node PD to high level.But due on draw and control node PU and drawn high, therefore the 8th transistor M8 conducting drop-down control node PD is pulled low to low level VGL.Can make like this 3rd transistor M3 and the 4th transistor M4 keep closing, so as not to the 3rd transistor M3 by draw and control node PU and be pulled low to low level VGL.Due to when the 7th transistor M7 draws high drop-down control node PD, the 8th transistor M8 can drag down drop-down control node PD, and therefore the 7th transistor M7 and the 8th transistor M8 can form phase inverter.Upper, draw when controlling node PU and being high level, the 9th transistor M9 and the tenth transistor M10 conducting, but due to the first clock signal terminal CLK=0, so signal output part Output output low level at the corresponding levels, and the 6th transistor M6 closes, avoid drop-down control node PD is pulled to high level.The T1 stage is the charging stage of capacitor C 1 in this shift register.

The T2 stage: CLK=1; CLKB=0; Pu=1; Input=0; Output=1; Reset=0.

As shown in Figure 8, due to first signal input end Input=0, so the first transistor M1 closes, the boot strap of capacitor C 1 by draw and control node PU and further draw high.Due to second clock signal end CLKB=0, therefore the 5th transistor M5 closes, to avoid the 5th transistor M5 that signal output part Output at the corresponding levels is pulled low to low level VGL, simultaneously, the 7th transistor M7 closes, and on draw when controlling node PU and being drawn high the 8th transistor M8 conducting and drop-down control node PD be pulled low to low level VGL, therefore drop-down control node PD keeps low level.Due to the first clock signal terminal CLK=1, therefore the 9th transistor M9, the tenth transistor M10 draw conducting when controlling node PU and being high level upper, and the high level output on the first clock signal terminal CLK is arrived to signal output part Output at the corresponding levels, and then by signal output part Output at the corresponding levels by this high level output to the delegation grid line corresponding with this shift register cell, the all thin film transistor (TFT)s that make to be positioned on this row grid line in the viewing area of liquid crystal panel are opened, and data line starts write signal.The stage that the T2 stage opens for this shift register.

The T3 stage: CLK=0; CLKB=1; Pu=0; Input=0; Output=0; Reset=1.

As shown in Figure 9, due to secondary signal input end Reset=1, so transistor seconds M2 conducting.After transistor seconds M2 conducting by draw and control node PU and be pulled low to low level VSS.In addition, due to second clock signal end CLKB=1, therefore the 5th transistor M5 and the 7th transistor M7 conducting.After the 5th transistor M5 conducting, signal output part Output at the corresponding levels is pulled low to low level VGL, thereby makes signal output part Output output low level at the corresponding levels; After the 7th transistor M7 conducting, drop-down control node PD is drawn high to (now, drawing and controlling node PU is low level, and therefore the 8th transistor M8 closes).When drop-down control node PD is high level, the 3rd transistor M3 and the 4th transistor M4 conducting, the 3rd transistor M3 conducting can by draw and control node PU and be pulled low to VGL, the 4th transistor M4 conducting can be pulled low to VGL by signal output part Output at the corresponding levels.Due to the 3rd transistor M3 and the 4th transistor M4 conducting simultaneously, and finally can make signal output part Output output low level at the corresponding levels, therefore when being damaged for one in these two thin film transistor (TFT)s, another still can keep signal output part Output output low level at the corresponding levels, this set has played the effect of dual fail-safe, thereby can avoid better signal output part Output to become high level under the effect of other undesired signals, and its delegation's grid line of controlling is opened under the high level effect, finally cause grid line to open mistake.

The T4 stage: CLK=1; CLKB=0; Pu=0; Input=0; Output=0; Reset=0.

As shown in figure 10, due to second clock signal end CLKB=0, secondary signal input end Reset=0, therefore the 7th transistor M7, transistor seconds M2 and the 5th transistor M5 close.Due to the first clock signal terminal CLK=1, the 6th transistor M6 conducting, the level of drop-down control node PD is dragged down, and the 3rd transistor M3 and the 4th transistor M4 close.On draw and control node PU=0, so the 9th transistor M9 and the tenth transistor M10 close.Signal output part Output output low level at the corresponding levels.

The T5 stage: CLK=0; CLKB=1; Pu=0; Input=0; Output=0; Reset=0.

As shown in figure 11, due to second clock signal end CLKB=1, therefore the 5th transistor M5 and the 7th transistor M7 conducting, making drop-down control node PD is high level.Therefore, the 3rd transistor M3 and the 4th transistor M4 keep conducting.The 3rd transistor M3 conducting can by draw and control node PU and be pulled low to VGL, the 4th transistor M4 conducting can be pulled low to VGL by signal output part Output at the corresponding levels, thereby avoid signal output part Output at the corresponding levels to become high level under the effect of other undesired signals, and its delegation's grid line of controlling is opened under the high level effect, finally cause grid line to open mistake.

After this until when first signal input end Input was high level, this shift register cell repeated T4 and T5 stage next time, can be called the non-working time of shift register cell this period.And T1~T3 stage can be called the working time of shift register cell.As can be known by top description, within the non-working time of shift register cell, when drop-down control node PD is low level, signal output part Output output low level at the corresponding levels.When drop-down control module PD keeps high level, make the 3rd transistor M3 and the 4th transistor M4 keep conducting, thereby make to draw control node PU and signal output part Output at the corresponding levels to keep low level.In the T2 stage, because the 9th transistor M9 connects with the tenth transistor M10, when the size of the tenth transistor M10 does not need when very large, two transistorized coupling capacitances after series connection are relatively little with the coupling capacitance of the 9th transistor M9, and then reduced the impact of the 9th transistor M9 coupling capacitance on output signal, thereby reduced the noise of output signal.

The embodiment of the present invention provides a kind of gate driver circuit, as shown in figure 12, comprises multistage shift register cell as above.Wherein, the output terminal Output of every one-level shift register cell SR output line scanning letter G at the corresponding levels; Each shift register cell has first a clock signal clk input and a second clock signal CLKB input; Second clock signal CLKB and the first clock signal clk have the phase differential of 180 degree, and the equal half the time output high level within the work period separately of the first clock signal clk and second clock signal CLKB, second half time output low level.

Wherein VGH can be VDD, and VGL can be VSS.

Except first order shift register cell SR0, the first signal input end G (N-1) of all the other each shift register cells connects the signal output part Output at the corresponding levels of the upper level shift register cell be adjacent.

Except afterbody shift register cell SRn, the signal first signal input end G (N-1) of the next stage shift register cell that the signal output part Output at the corresponding levels of all the other each shift register cells is adjacent is connected.

In embodiments of the present invention, first signal input end G (N-1) I of first order shift register cell SR0 can incoming frame start signal STV; The secondary signal input end G (N+1) of afterbody shift register cell SRn can input reset signal RST, or the output Output(Gn of afterbody shift register cell SRn) as reset signal RST at the corresponding levels.

The invention provides a kind of gate driver circuit.This gate driver circuit comprises shift register cells at different levels, this shift register cell comprises load module, control module, reseting module, upper drawing-die piece, drop-down module and noise reduction module, by the noise reduction module of connecting with drawing-die piece on this, can reduce the size of thin film transistor (TFT) in upper drawing-die piece, so, can reduce the coupling capacitance of thin film transistor (TFT) in upper drawing-die piece, thereby reduce the noise of output signal.

The embodiment of the present invention also provides a kind of display device, comprises gate driver circuit as above.

The invention provides a kind of display device.This display device comprises gate driver circuit, this gate driver circuit comprises shift register cells at different levels, this shift register cell comprises load module, control module, reseting module, upper drawing-die piece, drop-down module and noise reduction module, by the noise reduction module of connecting with drawing-die piece on this, can reduce the size of thin film transistor (TFT) in upper drawing-die piece, so, can reduce the coupling capacitance of thin film transistor (TFT) in upper drawing-die piece, thereby reduce the noise of output signal.

One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can complete by the hardware that programmed instruction is correlated with, aforesaid program can be stored in a computer read/write memory medium, this program, when carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.

The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.

Claims (12)

1. a shift register cell, is characterized in that, comprising: load module, control module, reseting module, upper drawing-die piece, drop-down module and noise reduction module;
Described load module, connect respectively the first signal input end and on draw the control node, draw the current potential of controlling node on described for the signal controlling according to the input of described first signal input end;
Described control module, connect respectively the first clock signal terminal, second clock signal end, the first voltage end, draw on described and control node and drop-down control node, for the signal of the signal according to described the first clock signal terminal input, the input of described second clock signal end or described on draw the current potential of the described drop-down control node of control of Electric potentials of controlling node;
Described reseting module, connect respectively secondary signal input end, described the first voltage end, draw on described and control node and described drop-down control node, resets on described and draw the current potential of controlling node for the signal according to described secondary signal input end input;
Described upper drawing-die piece, connect respectively described the first clock signal terminal, draw on described and control node and signal output part at the corresponding levels, on described, drawing under the control of controlling node potential the signal that makes described the first clock signal terminal of described signal output part output at the corresponding levels;
Described drop-down module, connect respectively described the first voltage end, described drop-down control node and described signal output part at the corresponding levels, under the control at described drop-down control node potential by the signal of described signal output part at the corresponding levels output drop-down be low level;
Described noise reduction module, connect respectively described the first clock signal terminal, draw on described and control node and signal output part at the corresponding levels, for the signal by described the first clock signal terminal of described signal output part output at the corresponding levels.
2. shift register cell according to claim 1, is characterized in that, described load module comprises:
The first transistor, its first utmost point is connected described first signal input end with grid, second utmost point with described on draw and control node and be connected.
3. shift register cell according to claim 2, is characterized in that, described reseting module comprises:
Transistor seconds, draw the control node on its first utmost point connection is described, and grid connects described secondary signal input end, and second utmost point is connected with described the first voltage end;
The 5th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described secondary signal input end, and second utmost point is connected with described the first voltage end.
4. shift register cell according to claim 3, is characterized in that, described drop-down module comprises:
The 3rd transistor, draw the control node on its first utmost point connection is described, and grid connects described drop-down control node, and second utmost point is connected with described the first voltage end;
The 4th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described drop-down control node, and second utmost point is connected with described the first voltage end.
5. shift register cell according to claim 1, is characterized in that, described load module comprises:
The first transistor, its first utmost point connects second voltage end, grid connects described first signal input end, second utmost point with described on draw the control node to be connected.
6. shift register cell according to claim 5, is characterized in that, described reseting module comprises:
Transistor seconds, draw the control node on its first utmost point connection is described, and grid connects described secondary signal input end, and second utmost point is connected with the tertiary voltage end.
7. shift register cell according to claim 6, is characterized in that, described drop-down module also comprises:
The 3rd transistor, draw the control node on its first utmost point connection is described, and grid connects described drop-down control node, and second utmost point is connected with described the first voltage end;
The 4th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described drop-down control node, and second utmost point connects described the first voltage end;
The 5th transistor, its first utmost point connects described signal output part at the corresponding levels, and grid connects described second clock signal end, and second utmost point is connected with described the first voltage end.
8. according to the arbitrary described shift register cell of claim 1 to 7, it is characterized in that, described control module comprises:
The 6th transistor, grid connects described the first clock signal terminal, and its first utmost point connects described second clock signal end, and second utmost point is connected with described drop-down control node;
The 7th transistor, its first utmost point is connected described second clock signal end with grid, and second utmost point is connected with described drop-down control node;
The 8th transistor, its first utmost point connects described drop-down control node, draws the control node on the grid connection is described, and second utmost point is connected with described the first voltage end.
9. according to the arbitrary described shift register cell of claim 1 to 7, it is characterized in that, described upper drawing-die piece comprises:
The 9th transistor, its first utmost point connects described the first clock signal terminal, draws the control node on the grid connection is described, and second utmost point is connected with described signal output part at the corresponding levels;
Electric capacity, it is parallel between described the 9th transistorized grid and second utmost point.
10. according to the arbitrary described shift register cell of claim 1 to 7, it is characterized in that, described noise reduction module comprises:
At least one the tenth transistor, its first utmost point connects described the first clock signal terminal, draws the control node on the grid connection is described, and second utmost point is connected with described signal output part at the corresponding levels.
11. a gate driver circuit, is characterized in that, comprises multistage described shift register cell as arbitrary as claim 1 to 10;
Except first order shift register cell, the signal input part of all the other each shift register cells connects the signal output part at the corresponding levels of the upper level shift register cell be adjacent;
Except the afterbody shift register cell, the signal input part of the next stage shift register cell that the signal output part at the corresponding levels of all the other each shift register cells is adjacent is connected.
12. a display device, is characterized in that, comprises gate driver circuit as claimed in claim 11.
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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103996370A (en) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 Shifting register unit, grid drive circuit, display device and drive method
CN104167192A (en) * 2014-07-22 2014-11-26 京东方科技集团股份有限公司 Shift register unit, gate drive circuit and display device
CN104282283A (en) * 2014-10-21 2015-01-14 重庆京东方光电科技有限公司 Shifting register unit, grid drive circuit and display device
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WO2019015630A1 (en) * 2017-07-20 2019-01-24 京东方科技集团股份有限公司 Shift register unit, method for driving shift register unit, gate drive circuit, method for driving gate drive circuit, and display device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050008114A1 (en) * 2003-07-09 2005-01-13 Seung-Hwan Moon Shift register, scan driving circuit and display apparatus having the same
JP2010277001A (en) * 2009-05-29 2010-12-09 Hitachi Displays Ltd Gate signal line driving circuit and display
CN102237029A (en) * 2010-04-23 2011-11-09 北京京东方光电科技有限公司 Shift register and grid drive device and data line drive of liquid crystal display
CN102654969A (en) * 2011-12-31 2012-09-05 京东方科技集团股份有限公司 Shift register unit, shift register circuit, array substrate and display device
US20130027377A1 (en) * 2011-07-29 2013-01-31 Jin-Wook Yang Gate driver and display device including the same
CN102956213A (en) * 2012-10-16 2013-03-06 北京京东方光电科技有限公司 Shifting register unit and array substrate gird driving device
CN103021358A (en) * 2012-12-07 2013-04-03 京东方科技集团股份有限公司 Shifting register unit, gate driving circuit and display device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102708925B (en) * 2011-05-26 2015-08-12 京东方科技集团股份有限公司 Shift register for thin-film transistor and application process thereof
CN102945657B (en) * 2012-10-29 2014-09-10 京东方科技集团股份有限公司 Shift register unit, grid drive circuit, array substrate and display device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050008114A1 (en) * 2003-07-09 2005-01-13 Seung-Hwan Moon Shift register, scan driving circuit and display apparatus having the same
JP2010277001A (en) * 2009-05-29 2010-12-09 Hitachi Displays Ltd Gate signal line driving circuit and display
CN102237029A (en) * 2010-04-23 2011-11-09 北京京东方光电科技有限公司 Shift register and grid drive device and data line drive of liquid crystal display
US20130027377A1 (en) * 2011-07-29 2013-01-31 Jin-Wook Yang Gate driver and display device including the same
CN102654969A (en) * 2011-12-31 2012-09-05 京东方科技集团股份有限公司 Shift register unit, shift register circuit, array substrate and display device
CN102956213A (en) * 2012-10-16 2013-03-06 北京京东方光电科技有限公司 Shifting register unit and array substrate gird driving device
CN103021358A (en) * 2012-12-07 2013-04-03 京东方科技集团股份有限公司 Shifting register unit, gate driving circuit and display device

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* Cited by examiner, † Cited by third party
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US9865211B2 (en) 2013-12-20 2018-01-09 Boe Technology Group Co., Ltd. Shift register unit, gate driving circuit and display device
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US9459730B2 (en) 2014-05-30 2016-10-04 Boe Technology Group Co., Ltd. Shift register unit, display device and driving method
US20150346904A1 (en) * 2014-05-30 2015-12-03 Boe Technology Group Co., Ltd. Shift Register Unit, Display Device and Driving Method
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US10043461B2 (en) 2014-10-21 2018-08-07 Boe Technology Group Co., Ltd. Shift register unit, gate driving circuit and display device
CN104282283B (en) * 2014-10-21 2016-09-28 重庆京东方光电科技有限公司 A kind of shift register cell, gate driver circuit and display device
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US9972238B2 (en) 2015-05-13 2018-05-15 Boe Technology Group Co., Ltd. Shift register and driving method therefor, gate drive circuit and display apparatus
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US10027329B2 (en) 2015-06-10 2018-07-17 Boe Technology Group Co., Ltd. NOR gate circuit, shift register, array substrate and display apparatus
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