CN104240765B - Shift register cell and driving method, gate driving circuit and display device - Google Patents
Shift register cell and driving method, gate driving circuit and display device Download PDFInfo
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- CN104240765B CN104240765B CN201410429757.2A CN201410429757A CN104240765B CN 104240765 B CN104240765 B CN 104240765B CN 201410429757 A CN201410429757 A CN 201410429757A CN 104240765 B CN104240765 B CN 104240765B
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Abstract
The embodiment of the present invention provides shift register cell and driving method, gate driving circuit and display device, is related to display technology field, can reduce the noise of bilateral scanning gate driving circuit.The shift register cell includes the first scan control module, the second scan control module, pull-up control module, pull-up module, drop-down control module and drop-down module.
Description
Technical field
The present invention relates to display technology field, more particularly to shift register cell and driving method, gate driving circuit
And display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-
LCD it is) to intersect the picture element matrix defined by the grid line and data wire of horizontal and vertical directions to form, when TFT-LCD enters
During row display, the square wave for inputting one fixed width to each pixel column successively by grid (Gate) driving on grid line selects
It is logical, then driven by the source electrode (Source) on data wire and be sequentially output the signal needed for every one-row pixels.However, when resolution
When rate is higher, the raster data model of display and the output of source drive are more, and the length of drive circuit will also increase, and this will not
Beneficial to binding (Bonding) technique of module drive circuit.
In order to solve the above problems, the manufacture of existing display is frequently with GOA (Gate Driver on Array, array
Substrate row drives) design of circuit, by TFT (Thin Film Transistor, TFT) gate switch electricity
Road is integrated in form the turntable driving to display panel on the array base palte of display panel, so as to save raster data model electricity
The Bonding regions on road and peripheral wiring space, so as to realize that the both sides of display panel are symmetrical and the design for aesthetic of narrow frame.
A kind of current GOA designs are as shown in figure 1, the shift register on the gate driving circuit includes multistage level
Shift register cell SR0, SR1 ... SRn of connection.Wherein, this grade of signal output part is passed through per one-level shift register cell
Scanning signal is input to corresponding gate lines G n by Output, and scanning signal is output to next stage SRn+1 letter
Number input Input and upper level SRn-1 signal reset terminal Rst；For starting to next stage shift register cell,
Resetted with to next stage shift register cell.But the one-level shift register cell of above-mentioned gate driving circuit, example
Such as, SRn signal input part Input is after the scanning signal of upper level shift register cell SRn-1 outputs is received, certainly
In the presence of the clock signal of the clock signal input terminal CLK inputs of body, scanning signal is exported.Therefore, above-mentioned raster data model electricity
Road can only realize simple scanning.So, there is the display device of simple scanning, such as mobile phone, when user in viewing or makes
When being rotated during to screen, display picture can not change with the change of the viewing mode of user.So,
Demand and the experience of user can be substantially reduced.
In order to solve the above problems, those skilled in the art propose a kind of GOA circuits that can carry out bilateral scanning, no
Every a line grid can be only scanned from top to bottom, every a line grid can also be scanned from bottom to up.However, tool
There are the GOA circuits of bilateral scanning function, for the GOA circuits of simple scanning, its circuit structure is relative complex, includes
The more transistor of number.Therefore, understand because the electricity in itself coupled capacitor of some transistors is not discharged sufficiently,
And cause GOA circuits to produce noise jamming, so as to reduce the stability of GOA circuits.
The content of the invention
Embodiments of the invention provide a kind of shift register cell and driving method, gate driving circuit and display dress
Put, the noise of bilateral scanning gate driving circuit can be reduced.
To reach above-mentioned purpose, embodiments of the invention adopt the following technical scheme that：
The one side of the embodiment of the present invention, there is provided a kind of shift register cell, including：First scan control module,
Two scan control modules, pull-up control module, pull-up module, drop-down control module and drop-down module；
The first scan control module, the first signal input part, first voltage end and the pull-up control are connected respectively
Molding block；For the signal inputted according to first signal input part, the pull-up control module is turned on；
The second scan control module, secondary signal input, second voltage end and the pull-up control are connected respectively
Molding block；For the signal inputted according to the secondary signal input, the pull-up control module is turned on；
The pull-up control module, the first scan control module, the second scan control module, are connected respectively
Four voltage ends and pull-up control node；For the control in the first scan control module or the second scan control module
The current potential of the pull-up control node is pulled to the voltage of the 4th voltage end under system；
The pull-up module, the first clock signal terminal, the pull-up control node and this grade of signal output are connected respectively
End；For the current potential according to the pull-up control node, the signal that first clock signal terminal inputs is provided to described
Level signal output part；
The drop-down control module, the drop-down control node, the pull-up control module, tertiary voltage are connected respectively
End, the 4th voltage end and second clock signal end；For the signal inputted according to the second clock signal end, control
The current potential of the drop-down control node；
The drop-down module, the drop-down control node, the pull-up control node and described level letter are connected respectively
Number output end, under the control of Electric potentials of the drop-down control node by the current potential of the pull-up control node and described
The output signal of level signal output part is pulled down to the voltage at the tertiary voltage end.
The another aspect of the embodiment of the present invention, there is provided a kind of gate driving circuit, including it is multistage as described above any one
Kind shift register cell；
In addition to first order shift register cell, the first signal input part and its phase of remaining each shift register cell
This grade of signal output part of adjacent upper level shift register cell is connected；
In addition to afterbody shift register cell, the secondary signal input of remaining each shift register cell and its
This grade of signal output part of adjacent next stage shift register cell is connected.
The another aspect of the embodiment of the present invention, there is provided a kind of display device, including any one grid as described above drive
Dynamic circuit.
On the one hand the embodiment of the present invention has, there is provided a kind of driving method of shift register cell, including：
First stage, the first scan control module or the second scan control module, pass through the first signal input part or second
The signal of signal input part input will pull up control module conducting, and the pull-up control module is by the current potential for pulling up control node
It is pulled to the voltage of the 4th voltage end；The voltage of the 4th voltage end is stored by the pull-up module；
Second stage, the pull-up control node control pull-up module carry the signal that the first clock signal terminal inputs
It is supplied to this grade of signal output part；The current potential for pulling down control node is pulled down to the voltage at tertiary voltage end by drop-down control module；
Phase III, the drop-down control module is by second clock signal end by the current potential of the drop-down control node
It is pulled to the voltage of the 4th voltage end；The drop-down control node is by pulling down module by the current potential of the pull-up control node
With and the output signal of described level signal output part be pulled down to the voltage at the tertiary voltage end.
The embodiment of the present invention provides a kind of shift register cell and driving method, gate driving circuit and display device.
The shift register cell includes the first scan control module, the second scan control module, pull-up control module, pull-up module
And drop-down control module.So, the first signal that can respectively by being connected with the first scan control module
Input, and the signal that the secondary signal input being connected with the second scan control module inputs is to the raster data model
Circuit is scanned forward or backwards, so as to realize bilateral scanning.Also, when this grade of signal output part of shift register cell
When needing to export scanning signal, pull-up control module can pull up the current potential of control node by controlling so that pull-up module is led
Logical, the signal that the first clock signal terminal is inputted is exported as scanning signal by this grade of signal output part, with to a line grid line
It is scanned.In addition, when this grade of signal output part of shift register cell need not export scanning signal, the drop-down control
Molding block can pull down the current potential of control node by controlling, to be carried out down to pull-up control node and this grade of signal output part
Draw, so as to carry out noise reduction to above-mentioned bilateral scanning gate driving circuit.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of structural representation for gate driving circuit that prior art provides；
Fig. 2 is a kind of structural representation of shift register cell provided in an embodiment of the present invention；
Fig. 3 is the structural representation of another shift register cell provided in an embodiment of the present invention；
Fig. 4 is a kind of shift register cell working signal timing waveform provided in an embodiment of the present invention；
Fig. 5 is another shift register cell working signal timing waveform provided in an embodiment of the present invention；
Working condition signal when Fig. 6-Fig. 8 is a kind of shift register cell forward scan provided in an embodiment of the present invention
Figure；
Fig. 9 is a kind of structural representation of gate driving circuit provided in an embodiment of the present invention；
Figure 10 is a kind of signal sequence oscillogram of gate driving circuit provided in an embodiment of the present invention；
Figure 11 is the signal sequence oscillogram of another gate driving circuit provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of shift register cell, as shown in Fig. 2 can include：First scan control mould
Block 10, the second scan control module 20, pull-up control module 30, pull-up module 40, drop-down control module 50 and drop-down module
60。
Above-mentioned first scan control module 10, the first signal input part Input1, first voltage end Vcn can be connected respectively
And pull-up control module 30.For the signal inputted according to the first signal input part Input1, the pull-up control mould is turned on
Block 30.
Above-mentioned second scan control module 20, can connect secondary signal input Input2, second voltage end respectively
Vcnb and pull-up control module 20；For the signal inputted according to secondary signal input Input2, conducting pull-up control mould
Block 30.
Above-mentioned pull-up control module 30, can connect respectively the first scan control module 10, the second scan control module 20,
4th voltage end VGH and pull-up control node PU.For in the first scan control module 10 or the second scan control module 20
Control under the current potential for pulling up control node PU is pulled to the 4th voltage end VGH voltage.
Above-mentioned pull-up module 40, the first clock signal terminal CLK, pull-up control section PU points and this grade of letter can be connected respectively
Number output end Output.For the current potential according to pull-up control node PU, by above-mentioned first clock signal terminal input CLK signal
There is provided to this grade of signal output part Output.It is scanned with a pair grid line corresponding with this level signal output part.
Above-mentioned drop-down control module 50, respectively connection pull down control node PD, pull-up control module 30, tertiary voltage end
VGL, the 4th voltage end VGH and second clock signal end CLKB.For what is inputted according to above-mentioned second clock signal end CLKB
Signal, control drop-down control node PD current potential.
Above-mentioned drop-down module 60, drop-down control node PD, pull-up control node PU and this grade of signal can be connected respectively
Output end Output, for believing the current potential for pulling up control node PU and this level under drop-down control node PD control of Electric potentials
Number output end Output output signal is pulled down to tertiary voltage end VGL voltage.
It should be noted that the first, embodiment of the present invention is with by forward scan signal STV_U and reverse scan signal
STV_D is respectively connected to the first signal input part Input1 and secondary signal input Input2 of shift register cells at different levels
Exemplified by the explanation that carries out.Specifically, shift registers at different levels pass through sheet at different levels according to the forward scan signal STV_U of input
Level signal output part Output presses forward direction (from top to bottom) and is sequentially output to scanning signal and above-mentioned level signal output part
Corresponding to Output on grid line.Or shift registers at different levels are according to the reverse scan signal STV_D of input, by different levels
This grade of signal output part Output presses reverse (from bottom to up) and is sequentially output to scanning signal and above-mentioned level signal output
Hold corresponding to Output on grid line.
Certainly, forward scan signal STV_U and reverse scan signal can also be respectively connected to displacements at different levels post by STV_D
The secondary signal input Input2 of storage unit and the first signal input part Input1.Specific scanning process can similarly obtain,
Here is omitted.
Secondth, it is with tertiary voltage end VGL input low levels, the high electricity of the 4th voltage end VGH inputs in the embodiment of the present invention
The explanation carried out exemplified by flat.
The embodiment of the present invention provides a kind of shift register cell, can include the first scan control module, the second scanning
Control module, pull-up control module, pull-up module and drop-down control module.So, can be respectively by with described
The first signal input part that one scan control module is connected, and the second letter being connected with the second scan control module
The signal of number input input is scanned forward or backwards to the gate driving circuit, so as to realize bilateral scanning.Also, work as
When this grade of signal output part of shift register cell needs to export scanning signal, pull-up control module can be pulled up by controlling
The current potential of control node so that pull-up module conducting, the signal of the first clock signal terminal input is passed through this as scanning signal
Level signal output part output, to be scanned to a line grid line.In addition, when shift register cell this grade of signal output part not
When needing to export scanning signal, the drop-down control module can pull down the current potential of control node by controlling, to be controlled to pull-up
Node processed and this grade of signal output part are pulled down, so as to carry out noise reduction to above-mentioned bilateral scanning gate driving circuit.
Hereinafter, Fig. 3 will be combined and detailed illustration is carried out to the concrete structure of above-mentioned shift register cell.
It should be noted that the above-mentioned modules of shift register cell include multiple transistors, following examples
In be the explanation that carries out so that the transistor in shift register cell uses N-type transistor as an example.
Embodiment one
Above-mentioned first scan control module 10 can include：The first transistor M1 and second transistor M2.
Wherein, the first transistor M1 the first pole connects first voltage end Vcn, the second pole and second transistor M2 with grid
Grid be connected.
Second transistor M2 the first pole connects the first signal input part Input1, grid connection the first transistor M1
The second pole, the second pole with pull-up control module 30 be connected.
So, as shown in figure 4, in the case of the Vcn input high levels of first voltage end, first scan control
Module 10 is turned on, and when the first signal input part Input1 inputs forward scan signal STV_U, shift register cells at different levels are opened
Beginning forward scan works.
Above-mentioned second scan control module 20 can include：Third transistor M3 and the 4th transistor M4.
Wherein, third transistor M3 the first pole connects second voltage end Vcnb, the second pole and the 4th transistor with grid
M4 grid is connected.
4th transistor M4 the first pole connection secondary signal input Input2, grid connect above-mentioned third transistor M3
The second pole, the second pole with pull-up control module 30 be connected.
So, as shown in figure 5, in the case of the Vcnb input high levels of second voltage end, the second scanning control
Molding block 20 turns on, when secondary signal input Input2 inputs reverse scan signal STV_D so that shift registers at different levels
Unit starts reverse scan work.
Pull-up control module 30 can include：7th transistor M7.
7th transistor M7, its first pole connection pull-up control node PU, the second pole connects the 4th voltage end VGH, grid
It is connected with second transistor M2 and the 4th transistor M4 the second pole.
Pull-up module 40 can include：8th transistor M8, the 9th transistor M9 and the first electric capacity C1.
8th transistor M8 the first pole connects the first clock signal terminal CLK, grid connection pull-up control node PU, and second
Pole is connected with this grade of signal output part Output.
First electric capacity C1 one end connection pull-up control node PU, the other end are extremely connected with the second of the 8th transistor M8
Connect.
Drop-down control module 50 can include：6th transistor M6, the 9th transistor M9 and the 11st transistor M11.
Wherein, the 6th transistor M6, the connection of its first pole drop-down control node PD, the second pole connection tertiary voltage end VGL,
Grid is connected with second transistor M2 and the 4th transistor M4 the second pole.
9th transistor M9 the first pole connection tertiary voltage end VGL, grid connect the 8th transistor M8 the second pole, the
Two poles are connected with drop-down control node PD.
11st transistor M11 the first pole connects the 4th voltage end VGH, and the second pole is connected with drop-down control node PD
Connect, grid is connected with second clock signal end CLKB.
Drop-down module 60 can include：5th transistor M5, the tenth transistor M10 and the second electric capacity C2.
Wherein, the 5th transistor M5 the first pole connection pull-up control node PU, grid connection drop-down control node PD, the
Two poles are connected with tertiary voltage end VGL.
Tenth transistor M10 the first pole connection tertiary voltage end VGL, grid connection drop-down control node PD, the second pole
It is connected with the 8th transistor M8 the second pole and the 9th transistor M9 grid.
Second electric capacity C2 one end connects the tenth transistor M10 grid, the second pole and the tenth transistor M10 the first pole
It is connected.
It should be noted that the first of above-mentioned transistor extremely can be source class, second extremely can be drain electrode.
Hereinafter, according to the sequential working figure of forward scan, as shown in figure 4, the shift register cell with reference to shown in Fig. 3,
The course of work of the shift register cell is described in detail.
Embodiment two
First stage T1, Vcn=1；CLKB=1；CLK=0；PU=1；PD=0；Input1=1；Output=0.Need
Illustrate, in following examples, 0 represents low level VGL；1 represents high level VGH.
As shown in fig. 6, first voltage end Vcn input high levels, the first transistor M1 and second transistor M2 is turned on.
In this case, the forward scan signal STV_U of the first signal input part Input1 inputs is high level, so that the 7th crystal
Pipe M7, the 6th transistor M6 are turned on, because the 7th transistor M7 the second pole connects the 4th voltage end VGH, so as to which pull-up be controlled
Node PU processed current potential is drawn high to high level, and the first electric capacity C1 is charged.8th transistor M8 is turned on, by the first clock
The low level of signal end CLK inputs is transmitted to this grade of signal output part Output so that this grade of signal output part Output outputs
Low level, grid line corresponding thereto will not be scanned.
It is brilliant by the 11st because the 6th transistor M6 is turned on, therefore even if second clock signal end CLKB1 input high levels
Body pipe M11 is turned on, and drop-down control node PD current potential still can be pulled low to low level by the 6th transistor M6.So,
Five transistor M5 end, and will not drag down the current potential for pulling up control node PU.To ensure that the first electric capacity C1 is in charged state.This
Outside, the 9th transistor M9 and the tenth transistor M10 are in cut-off state.
In summary, first stage T1 is the pre-charging stage of the first electric capacity C1 in the shift register cell.
Second stage T2, Vcn=1；CLKB=0；CLK=1；PU=1；PD=0；Input1=0；Output=1.
As shown in fig. 7, first voltage end Vcn input high levels, the first transistor M1 and second transistor M2 continue to keep
Conducting state.In the case, the forward scan signal STV_U of the first signal input part Input1 inputs is low level, so as to
So that the 7th transistor M7, the 6th transistor M6 are in cut-off state, and under the first electric capacity C1 boot strap, the current potential through PU
It is further pulled up.8th transistor M8 is still within conducting state, by the first clock signal terminal CLK input high level transmit to
This grade of signal output part Output so that this grade of signal output part Output exports high level, and to grid line corresponding thereto
It is scanned.
In addition, the 9th transistor M9 is turned on, by the tertiary voltage end VGL transistor M10 of voltage input levels the tenth grid,
Because tertiary voltage end VGL voltage is low level, therefore, the tenth transistor M10 cut-offs.Second clock signal end CLKB1 is defeated
Enter low level, the 11st transistor M11 cut-offs.
In summary, second stage T2 is the stage that the shift register cell is opened.
Second stage T3, Vcn=1；CLKB=1；CLK=0；PU=0；PD=1；Input1=0；Output=0.
As shown in figure 8, first voltage end Vcn input high levels, the first transistor M1 and second transistor M2 continue to keep
Conducting state.In the case, the forward scan signal STV_U of the first signal input part Input1 inputs is low level, so as to
So that the 7th transistor M7, the 6th transistor M6 are in cut-off state.
Second clock signal end CLKB1 input high levels, the 11st transistor M11 conductings, it will pull down control node PD's
Voltage boost is to high level.Because the 6th transistor M6 is in cut-off state, therefore it will not will pull down control node PD current potential
Drag down.In the case, the 5th transistor M5 is turned on, and pull-up control node PU current potential is pulled to low level, the 8th transistor
M8 is in cut-off state, and this grade of signal output part Output is without output.So, on before the input of next frame scanning signal
The state that the 5th transistor M5 is in conducting is stated, so as to effectively prevent the pull-up control node PU noises under off working state
Generation.
At the same time, the tenth transistor M10 is turned on, and this grade of signal output part Output current potential can be pulled low into an electricity
It is flat, so as to reduce the generation of this grade of signal output part Output noise under off working state.
In summary, phase III T3 can be the reset noise reduction stage of the shift register cell.
Above-mentioned is the explanation carried out by taking forward scan as an example, and reverse scan can similarly be obtained, repeated no more here.
It should be noted that the transistor in above-described embodiment is the explanation carried out by taking N-type transistor as an example, when adopting
During with P-type transistor.The work that the specific course of work is referred to the shift register cell that above-mentioned N-type transistor is formed is former
Reason, wherein needing the sequential of corresponding adjustment drive signal, here is omitted.
The embodiment of the present invention provides a kind of gate driving circuit, as shown in figure 9, including multistage shift LD as described above
Device unit (SR0, SR1 ... SRn).
Outside first order shift register cell SR0, the first signal input part of remaining each shift register cell
This grade of signal output part Output of upper level shift register cell adjacent thereto Input1 is connected.
In addition to afterbody shift register cell SRn, the secondary signal input of remaining each shift register cell
This grade of signal output part Output of next stage shift register cell adjacent thereto Input2 is connected.
Specifically, when gate driving circuit carries out forward scan, the timing diagram of each signal input is as shown in Figure 10, should
Each line scan signals of GOA circuits be G1, G2, G3, G4 ... Gn-1, Gn；When gate driving circuit carries out reverse scan, respectively
The timing diagram of individual signal input is as shown in figure 11, each line scan signals of the GOA circuits are Gn, Gn-1, Gn-2, Gn-3 ... G2,
G1。
The embodiment of the present invention provides a kind of gate driving circuit, including shift register cell.The shift register cell
Including the first scan control module, the second scan control module, pull-up control module, pull-up module and drop-down control module.
So, can respectively by the first signal input part being connected with the first scan control module, and with it is described
The signal for the secondary signal input input that second scan control module is connected carries out positive or anti-to the gate driving circuit
To scanning, so as to realize bilateral scanning.Also, when this grade of signal output part of shift register cell needs to export scanning signal
When, pull-up control module can pull up the current potential of control node by controlling so that pull-up module conducting, by the first clock signal
The signal of end input is exported as scanning signal by this grade of signal output part, to be scanned to a line grid line.In addition, when shifting
When this grade of signal output part of bit register unit need not export scanning signal, the drop-down control module can pass through control
The current potential of control node is pulled down, to be pulled down to pull-up control node and this grade of signal output part, so as to above-mentioned double
Noise reduction is carried out to scanning gate driving circuit.
The embodiment of the present invention provides a kind of display device, including any one gate driving circuit as described above.Have
The gate driving circuit identical beneficial effect provided with present invention, because gate driving circuit is in foregoing implementation
Have been carried out describing in detail in example, here is omitted.
It is any that the display device is specifically as follows liquid crystal display, LCD TV, DPF, mobile phone, tablet personal computer etc.
Liquid crystal display product or part with display function.
The embodiment of the present invention provides a kind of driving method of shift register cell, can include：
First stage, the first scan control module 10 or the second scan control module 20, pass through the first signal input part
The signal of Input1 or secondary signal input Input2 inputs turns on control module 30 is pulled up, the pull-up control module 30
The current potential for pulling up control node PU is pulled to the 4th voltage end VGH voltage；By pulling up module 30 by the 4th voltage end VGH
Voltage stored.First stage is the pre-charging stage of the shift register cell.
Second stage, pull-up control node PU control pull-up modules 40 carry the first clock signal terminal CLK signals inputted
It is supplied to this grade of signal output part Output；The current potential for pulling down control node PD is pulled down to tertiary voltage end by drop-down control module 50
VGL voltage.Second stage T2 is the stage that the shift register cell is opened.
Phase III, drop-down control module 50 is by second clock signal end CLKB by the current potential for pulling down control node PD
It is pulled to the 4th voltage end VGH voltage；Drop-down control node PD by pull down module 60 by pull up control node PD current potential and
And this grade of signal output part Output output signal is pulled down to tertiary voltage end VGL voltage.Phase III T3 can be
The reset noise reduction stage of the shift register cell.
Above-mentioned driving method can respectively by the first signal input part being connected with the first scan control module,
And the signal for the secondary signal input input being connected with the second scan control module enters to the gate driving circuit
Row scans forward or backwards, so as to realize bilateral scanning.Also, when this grade of signal output part needs of shift register cell are defeated
When going out scanning signal, pull-up control module can pass through the current potential for controlling pull-up control node so that pull-up module conducting, by the
The signal of one clock signal terminal input is exported as scanning signal by this grade of signal output part, to be swept to a line grid line
Retouch.In addition, when this grade of signal output part of shift register cell need not export scanning signal, the drop-down control module
The current potential of control node can be pulled down by controlling, to be pulled down to pull-up control node and this grade of signal output part, so as to
Noise reduction can be carried out to above-mentioned bilateral scanning gate driving circuit.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of above method embodiment can pass through
Programmed instruction related hardware is completed, and foregoing program can be stored in a computer read/write memory medium, the program
Upon execution, the step of execution includes above method embodiment；And foregoing storage medium includes：ROM, RAM, magnetic disc or light
Disk etc. is various can be with the medium of store program codes.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
- A kind of 1. shift register cell, it is characterised in that including：First scan control module, the second scan control module, on Draw control module, pull-up module, drop-down control module and drop-down module；The first scan control module, the first signal input part, first voltage end and the pull-up control mould are connected respectively Block；For the signal inputted according to first signal input part, the pull-up control module is turned on；The second scan control module, secondary signal input, second voltage end and the pull-up control mould are connected respectively Block；For the signal inputted according to the secondary signal input, the pull-up control module is turned on；The pull-up control module, the first scan control module, the second scan control module, the 4th electricity are connected respectively Pressure side and pull-up control node；For under the control of the first scan control module or the second scan control module The current potential of the pull-up control node is pulled to the voltage of the 4th voltage end；The pull-up module, the first clock signal terminal, the pull-up control node and this grade of signal output part are connected respectively；With In the current potential according to the pull-up control node, the signal that first clock signal terminal inputs is provided to described level signal Output end；The drop-down control module, respectively connection drop-down control node, the pull-up control module, tertiary voltage end, described the Four voltage ends and second clock signal end；For the signal inputted according to the second clock signal end, the drop-down is controlled The current potential of control node；The drop-down module, it is defeated that the drop-down control node, the pull-up control node and described level signal are connected respectively Go out end, for the current potential of the pull-up control node and described level being believed under the control of Electric potentials of the drop-down control node The output signal of number output end is pulled down to the voltage at the tertiary voltage end.
- 2. shift register cell according to claim 1, it is characterised in that the first scan control module includes：The first transistor, its first pole connect the first voltage end with grid；Second transistor, its first pole connect first signal input part, and grid connects the second pole of the first transistor, Second pole is connected with the pull-up control module.
- 3. shift register cell according to claim 2, it is characterised in that the second scan control module includes：Third transistor, its first pole connect second voltage end with grid；4th transistor, its first pole connection secondary signal input, the second pole of the grid connection third transistor, second Pole is connected with the pull-up control module.
- 4. shift register cell according to claim 3, it is characterised in that the pull-up control module includes：7th transistor, its first pole connect the pull-up control node, and the second pole connects the 4th voltage end, grid and institute The second pole that second transistor is stated with the 4th transistor is connected.
- 5. shift register cell according to claim 4, it is characterised in that the pull-up module includes：8th transistor, its first pole connect first clock signal terminal, and grid connects the pull-up control node, the second pole It is connected with this grade of signal output part；First electric capacity, its one end connect the pull-up control node, and the other end is connected with the second pole of the 8th transistor.
- 6. shift register cell according to claim 5, it is characterised in that the drop-down control module includes：6th transistor, its first pole connect the drop-down control node, and the second pole connects the tertiary voltage end, grid and institute The second pole that second transistor is stated with the 4th transistor is connected；9th transistor, its first pole connect the tertiary voltage end, and grid connects the second pole of the 8th transistor, the second pole with The drop-down control node is connected；11st transistor, its first pole connect the 4th voltage end, and the second pole is connected with the drop-down control node, grid Pole is connected with the second clock signal end.
- 7. shift register cell according to claim 6, it is characterised in that the drop-down module includes：5th transistor, its first pole connect the pull-up control node, and grid connects the drop-down control node, the second pole with The tertiary voltage end is connected；Tenth transistor, its first pole connect the tertiary voltage end, and grid connects the drop-down control node, the second pole and institute The second pole for stating the 8th transistor is connected with the grid of the 9th transistor；Second electric capacity, its one end connect the grid of the tenth transistor, the first pole phase of the other end and the tenth transistor Connection.
- 8. a kind of gate driving circuit, it is characterised in that including the multistage shift register as described in claim 1 to 7 is any Unit；In addition to first order shift register cell, the first signal input part of remaining each shift register cell is adjacent thereto This grade of signal output part of upper level shift register cell is connected；In addition to afterbody shift register cell, the secondary signal input of remaining each shift register cell is adjacent thereto This grade of signal output part of next stage shift register cell be connected.
- 9. a kind of display device, it is characterised in that including gate driving circuit as claimed in claim 8.
- A kind of 10. method for being used to drive the shift register cell as described in any one of claim 1 to 7, it is characterised in that Methods described includes：First stage, the first scan control module or the second scan control module, pass through the first signal input part or secondary signal The signal of input input will pull up control module conducting, and the current potential for pulling up control node is pulled to by the pull-up control module The voltage of 4th voltage end；The voltage of the 4th voltage end is stored by pulling up module；Second stage, it is described pull-up control node control it is described pull-up module by the signal that the first clock signal terminal inputs provide to This grade of signal output part；The current potential for pulling down control node is pulled down to the voltage at tertiary voltage end by drop-down control module；The current potential of the drop-down control node is pulled to by phase III, the drop-down control module by second clock signal end The voltage of 4th voltage end；It is described drop-down control node by pull down module by it is described pull-up control node current potential and with And the output signal of described level signal output part is pulled down to the voltage at the tertiary voltage end.
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| CN104537992B (en) * | 2014-12-30 | 2017-01-18 | 深圳市华星光电技术有限公司 | GOA circuit for liquid crystal display device |
| US9626928B2 (en) | 2014-12-31 | 2017-04-18 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display device comprising gate driver on array circuit |
| CN104485079B (en) * | 2014-12-31 | 2017-01-18 | 深圳市华星光电技术有限公司 | GOA (Gate Driver On Array) circuit for liquid crystal display device |
| CN104575430B (en) | 2015-02-02 | 2017-05-31 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit, display device |
| CN104916262B (en) * | 2015-06-04 | 2017-09-19 | 武汉华星光电技术有限公司 | A kind of scan drive circuit |
| CN105096904B (en) * | 2015-09-30 | 2018-04-10 | 京东方科技集团股份有限公司 | Gate driving circuit, display device and driving method |
| CN105261340A (en) * | 2015-11-09 | 2016-01-20 | 武汉华星光电技术有限公司 | GOA drive circuit, TFT display panel and display device |
| CN105657898B (en) * | 2016-02-19 | 2017-12-08 | 京东方科技集团股份有限公司 | A kind of power circuit and its driving method, display device |
| CN108682380B (en) * | 2018-07-26 | 2021-01-08 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| CN109448656B (en) * | 2018-12-26 | 2021-01-26 | 惠科股份有限公司 | Shift register and gate drive circuit |
| CN110223623B (en) * | 2019-06-18 | 2022-12-16 | 京东方科技集团股份有限公司 | Gate driving unit and control method thereof, gate driving circuit and display device |
| CN112992247B (en) * | 2021-03-05 | 2024-08-06 | 京东方科技集团股份有限公司 | Shift register unit, shift register, display panel and driving method thereof |
| CN113284459B (en) * | 2021-07-19 | 2021-10-22 | 深圳市柔宇科技股份有限公司 | Scanning driving unit, scanning driving circuit, array substrate and display |
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| KR101482635B1 (en) * | 2008-08-01 | 2015-01-21 | 삼성디스플레이 주식회사 | Gate driving circuit, display device having the same, and method for manufacturing display device |
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| CN103065592A (en) * | 2012-12-13 | 2013-04-24 | 京东方科技集团股份有限公司 | Shift register unit and driving method, gate drive circuit and displaying device thereof |
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