CN103413531B - A kind of shift register cell, gate driver circuit and display device - Google Patents
A kind of shift register cell, gate driver circuit and display device Download PDFInfo
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- CN103413531B CN103413531B CN201310308994.9A CN201310308994A CN103413531B CN 103413531 B CN103413531 B CN 103413531B CN 201310308994 A CN201310308994 A CN 201310308994A CN 103413531 B CN103413531 B CN 103413531B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a kind of shift register cell, gate driver circuit and display device, relate to display technique field.The coupling capacitance of thin film transistor (TFT) can be reduced, reduce the noise of output signal.Shift register cell comprises load module, control module, reseting module, pull-up module, drop-down module and noise reduction module.The embodiment of the present invention is used for realizing turntable driving.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of shift register cell, gate driver circuit and display device.
Background technology
Liquid crystal display (LiquidCrystalDisplay, be called for short LCD) has the advantages such as the little and low power consuming of Low emissivity, volume, is widely used in the electronic products such as notebook computer, flat-surface television or mobile phone.
Liquid crystal display forms by the picture element matrix being positioned at horizontal and vertical directions is staggered, when liquid crystal display shows, timely for the display data of input clock signal timing order can latch by data drive circuit, the data line of liquid crystal panel is input to after converting simulating signal to, grid stage drive circuit then can convert the clock signal of input to control pixel on/off voltage through shift register, and is applied to line by line on the grid level line of liquid crystal panel.
In order to reduce the production cost of lcd products further, existing gate driver circuit often adopts GOA(GateDriveronArray, array base palte row cutting) design TFT(ThinFilmTransistor, Thin Film Transistor (TFT)) gate switch circuit be integrated in display panel array base palte on to form the turntable driving to display panel, thus grid-driving integrated circuit part can be saved, it not only can reduce cost of products from material cost and manufacture craft two aspect, and display panel can accomplish the design for aesthetic of both sides symmetry and narrow frame.This gate switch circuit of GOA Integration ofTechnology on array base palte that utilize is also referred to as GOA circuit or shift-register circuit.
Typically utilize the structure of the shift register of GOA technology in prior art as shown in Figure 1, Fig. 2 is the input and output sequential chart of this shift register.Composition graphs 1 and Fig. 2 known, the course of work of this shift register is: the T1 stage, signal input part Input input high level, and thin film transistor (TFT) M1 conducting is that electric capacity C1 charges, thin film transistor (TFT) M3 close make Output output low level; The T2 stage, clock signal terminal CLK input high level, the grid level of thin film transistor (TFT) M3 is drawn high by bootstrapping (Bootstrapping) effect of electric capacity C1 further, thin film transistor (TFT) M3 conducting, and Output exports high level; In the T3 stage, reset signal end Reset input high level, now thin film transistor (TFT) M2 and M4 conducting, be pulled low to Vss low level by the grid level of thin film transistor (TFT) M3 and the level of Output; In the T4 stage, the grid level of thin film transistor (TFT) M3 and the level of Output are pulled low to Vss low level; In the T5 stage, the equal input low level of Input, CLK, Reset, now thin film transistor (TFT) M1 to M4 keeps closing, Output output low level.After this until when Input is high level next time, this shift register repeats T4 and the T5 stage, can be called the non-working time of shift register this period.Shift register can be found out in the course of the work, electricity in the coupling capacitance of M3 self is not discharged fully, so noise can be caused to signal output part Output, thus reduce the stability of GOA circuit, and include multiple TFT in each shift register, the size of GOA circuit and the production cost of product can be increased.
Summary of the invention
Embodiments of the invention provide a kind of shift register cell, gate driver circuit and display device.The coupling capacitance of thin film transistor (TFT) can be reduced, reduce the noise of output signal.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the present invention provides a kind of shift register cell, comprising: load module, control module, reseting module, pull-up module, drop-down module and noise reduction module;
Described load module, connects the first signal input part and pull-up Controlling vertex respectively, for controlling the current potential of described pull-up Controlling vertex according to the signal of described first signal input part input;
Described control module, connect the first clock signal terminal, second clock signal end, the first voltage end, described pull-up Controlling vertex and drop-down Controlling vertex respectively, for the current potential of drop-down Controlling vertex described in the signal according to described first clock signal terminal input, the signal of described second clock signal end input or the control of Electric potentials of described pull-up Controlling vertex;
Described reseting module, connects secondary signal input end, described first voltage end, described pull-up Controlling vertex and described drop-down Controlling vertex respectively, for the current potential of the described pull-up Controlling vertex that resets according to the signal of described secondary signal input end input;
Described pull-up module, connecting described first clock signal terminal, described pull-up Controlling vertex and signal output part at the corresponding levels respectively, exporting the signal of described first clock signal terminal for making described signal output part at the corresponding levels under the control of described pull-up Controlling vertex current potential;
Described drop-down module, connects described first voltage end, described drop-down Controlling vertex and described signal output part at the corresponding levels respectively, and the signal for being exported by described signal output part at the corresponding levels under the control of described drop-down Controlling vertex current potential is drop-down is low level;
Described noise reduction module, connects described first clock signal terminal, described pull-up Controlling vertex and signal output part at the corresponding levels respectively, for being exported the signal of described first clock signal terminal by described signal output part at the corresponding levels.
Described load module comprises:
The first transistor, its first pole is connected described first signal input part with grid, the second pole is connected with described pull-up Controlling vertex.
Described reseting module comprises:
Transistor seconds, its first pole connects described pull-up Controlling vertex, and grid connects described secondary signal input end, and the second pole is connected with described first voltage end;
5th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described secondary signal input end, and the second pole is connected with described first voltage end.
Described drop-down module comprises:
Third transistor, its first pole connects described pull-up Controlling vertex, and grid connects described drop-down Controlling vertex, and the second pole is connected with described first voltage end.
4th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described drop-down Controlling vertex, and the second pole is connected with described first voltage end.
Described load module comprises:
The first transistor, its first pole connects the second voltage end, and grid connects described first signal input part, and the second pole is connected with described pull-up Controlling vertex.
Described reseting module comprises:
Transistor seconds, its first pole connects described pull-up Controlling vertex, and grid connects described secondary signal input end, and the second pole is connected with tertiary voltage end;
Described drop-down module also comprises:
Third transistor, its first pole connects described pull-up Controlling vertex, and grid connects described drop-down Controlling vertex, and the second pole is connected with described first voltage end.
4th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described drop-down Controlling vertex, and the second pole connects described first voltage end;
5th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described second clock signal end, and the second pole is connected with described first voltage end.
Described control module comprises:
6th transistor, grid connects described first clock signal terminal, and its first pole connects described second clock signal end, and the second pole is connected with described drop-down Controlling vertex;
7th transistor, its first pole is connected described second clock signal end with grid, the second pole is connected with described drop-down Controlling vertex;
8th transistor, its first pole connects described drop-down Controlling vertex, and grid connects described pull-up Controlling vertex, and the second pole is connected with described first voltage end.
Described pull-up module comprises:
9th transistor, its first pole connects described first clock signal terminal, and grid connects described pull-up Controlling vertex, and the second pole is connected with described signal output part at the corresponding levels;
Electric capacity, between its grid being parallel to described 9th transistor and the second pole.
Described noise reduction module comprises:
At least one the tenth transistor, its first pole connects described first clock signal terminal, and grid connects described pull-up Controlling vertex, and the second pole is connected with described signal output part at the corresponding levels.
The another aspect of the embodiment of the present invention provides a kind of gate driver circuit, comprises multistage shift register cell as above.
Except first order shift register cell, the signal input part of all the other each shift register cells connects the signal output part at the corresponding levels of the upper level shift register cell be adjacent;
Except afterbody shift register cell, the signal input part of the next stage shift register cell that the signal output part at the corresponding levels of all the other each shift register cells is adjacent is connected.
The another aspect of the embodiment of the present invention provides a kind of display device, comprises grid circuit as above.
The invention provides a kind of shift register cell, gate driver circuit and display device.This shift register cell comprises load module, control module, reseting module, pull-up module, drop-down module and noise reduction module, by the noise reduction module with this pull-up block coupled in series, the size of thin film transistor (TFT) in pull-up module can be reduced, so, the coupling capacitance of thin film transistor (TFT) in pull-up module can be reduced, thus reduce the noise of output signal.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of shift register cell that Fig. 1 provides for prior art;
Signal sequence oscillogram during a kind of shift register cell work that Fig. 2 provides for prior art;
The circuit connection structure schematic diagram of a kind of shift register cell that Fig. 3 provides for the embodiment of the present invention;
The structural representation of a kind of shift register cell that Fig. 4 provides for the embodiment of the present invention;
The structural representation of the another kind of shift register cell that Fig. 5 provides for the embodiment of the present invention;
Signal sequence oscillogram during a kind of shift register cell work that Fig. 6 provides for the embodiment of the present invention;
The working state schematic representation of the shift register cell that Fig. 7, Fig. 8, Fig. 9, Figure 10, Figure 11 provide for the embodiment of the present invention;
The structural representation of a kind of gate driver circuit that Figure 12 embodiment of the present invention provides.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The transistor adopted in all embodiments of the present invention can be all thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the source electrode of the transistor that adopts here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein will be called source electrode in a pole, another pole is called drain electrode.In addition, distinguish transistor can be divided into N-type transistor or P-type crystal pipe according to the characteristic of transistor, in embodiments of the present invention, when adopting N-type transistor, it first can be extremely source electrode, and second can be extremely drain electrode, when adopting P-type crystal pipe, its first can be extremely drain electrode, second can be extremely source electrode.The transistor adopted in the embodiment of the present invention can be N-type transistor, also can be P-type crystal pipe.In the examples below, be all be for transistor the explanation that N-type transistor carries out, can expect, needing the sequential of corresponding adjustment drive singal when all adopting P-type crystal pipe.
Embodiments of the invention provide a kind of shift register cell, as shown in Figure 3, can comprise: load module 10, control module 20, reseting module 30, pull-up module 40, drop-down module 50 and noise reduction module 60.
Wherein, load module 10, can connect the first signal input part Input and pull-up Controlling vertex PU respectively, and the signal for inputting according to the first signal input part Input controls the current potential of pull-up Controlling vertex PU.Such as, when the signal that the first signal input part Input inputs is high level, the current potential of pull-up Controlling vertex PU is drawn high as noble potential.
Control module 20, the first clock signal terminal CLK, second clock signal end CLKB, the first voltage end V1, pull-up Controlling vertex PU and drop-down Controlling vertex PD can be connected respectively, for the current potential of this drop-down Controlling vertex PD of control of Electric potentials of the signal inputted according to this first clock signal terminal CLK, signal that second clock signal end CLKB inputs or pull-up Controlling vertex PU.It should be noted that, the signal period same phase that the first clock signal terminal CLK and second clock signal end CLKB inputs is contrary.
In embodiments of the present invention, pull-up Controlling vertex PU refers to the circuit node opened for controlling pull-up module or close, and drop-down Controlling vertex PD refers to the circuit node opened for controlling drop-down module or close.
Reseting module 30, can connect secondary signal input end Reset, the first voltage end V1, pull-up Controlling vertex PU and drop-down Controlling vertex PD respectively, for the current potential of signal reset pull-up Controlling vertex PU inputted according to secondary signal input end Reset.
Pull-up module 40, the first clock signal terminal CLK, pull-up Controlling vertex PU and signal output part Output at the corresponding levels can be connected respectively, export the signal of the first clock signal terminal CLK for making signal output part Output at the corresponding levels under the control of pull-up Controlling vertex PU current potential thus make this shift register cell output drive signal.
Drop-down module 50, can connect described first voltage end V1, drop-down Controlling vertex PD and signal output part Output at the corresponding levels respectively, and the signal for being exported by signal output part Output at the corresponding levels under the control of drop-down Controlling vertex PD current potential is drop-down is low level.
Noise reduction module 60, the first clock signal terminal CLK, pull-up Controlling vertex PU and signal output part Output at the corresponding levels can be connected respectively, for being exported the signal of the first clock signal terminal CLK by signal output part Output at the corresponding levels, thus reduce the noise of pull-up module 40 output signal.
The invention provides a kind of shift register cell, this shift register cell comprises load module, control module, reseting module, pull-up module, drop-down module and noise reduction module, by the noise reduction module with this pull-up block coupled in series, the size of thin film transistor (TFT) in pull-up module can be reduced, so, the coupling capacitance of thin film transistor (TFT) in pull-up module can be reduced, thus reduce the noise of output signal.
Wherein, the first voltage end V1 can be earth terminal, or the first voltage end V1 input low level VSS or VGL.In embodiments of the present invention, as shown in Figure 4, be all the explanation carried out for the first voltage end V1 input low level VSS.
Further, as shown in Figure 4, load module 10 can comprise: the first transistor M1, and its first pole is connected the first signal input part Input with grid, and the second pole is connected with pull-up Controlling vertex PU.So, by the first transistor M1, the signal that can input according to the first signal input part Input controls the current potential of this pull-up Controlling vertex PU.
Further, reseting module 30 can comprise: transistor seconds M2, and its first pole connects pull-up Controlling vertex PU, and grid connects secondary signal input end Reset, and the second pole is connected with the first voltage end V1.
5th transistor M5, its first pole connects signal output part Output at the corresponding levels, and grid connects secondary signal input end Reset, and the second pole is connected with the first voltage end V1.So, by transistor seconds M2 and the 5th transistor M5, the reset signal that can input according to secondary signal input end Reset makes the current potential of pull-up Controlling vertex PU and signal output part Output at the corresponding levels be resetted.
Further, drop-down module 50 can comprise: third transistor M3, and its first pole connects pull-up Controlling vertex PU, and grid connects drop-down Controlling vertex PD, and the second pole is connected with the first voltage end V1.
4th transistor M4, its first pole connects signal output part Output at the corresponding levels, and grid connects drop-down Controlling vertex PD, and the second pole is connected with the first voltage end V1.So, when pull-up Controlling vertex PU is high level, drop-down Controlling vertex PD is low level, and third transistor M3 and the 4th transistor M4 is in cut-off state, ensures the output of PU node and Output point; When pull-up Controlling vertex PU is low level, drop-down Controlling vertex PD is high level, and during second clock signal end CLKB input high level, by third transistor M3, the 4th transistor M4, the signal exported by signal output part Output is drop-down is low level, thus signal output part Output at the corresponding levels can be avoided better under the effect of other undesired signals to become high level, and a line grid line making it control is opened under high level effect, finally causes grid line to open mistake.
Or as shown in Figure 5, load module 10 can comprise:
The first transistor M1, its first pole connects the second voltage end V2, and grid connects the first signal input part Input, and the second pole is connected with pull-up Controlling vertex PU.So, by the first transistor M1, the signal that can input according to the first signal input part Input controls the current potential of this pull-up Controlling vertex PU.
Further, reseting module 30 can comprise: transistor seconds M2, and its first pole connects pull-up Controlling vertex PU, and grid connects secondary signal input end Reset, and the second pole is connected with the first voltage end V1.So, the reset signal that can be inputted according to secondary signal input end Reset by transistor seconds M2 makes the current potential of pull-up Controlling vertex PU be resetted.
It should be noted that, in the structure of shift register cell as shown in Figure 5, be the explanation that example is carried out with the first voltage end V1 input low level VGL, the second voltage end V2 input high level VDD and tertiary voltage end V3 input low level VSS.
Further, drop-down module 50 can comprise: third transistor M3, and its first pole connects pull-up Controlling vertex PU, and grid connects drop-down Controlling vertex PD, and the second pole is connected with the first voltage end V1.
4th transistor M4, its first pole connects signal output part Output at the corresponding levels, and grid connects drop-down Controlling vertex PD, and the second pole connects the first voltage end V1.
5th transistor M5, its first pole connects signal output part Output at the corresponding levels, and grid connects second clock signal end CLKB, and the second pole is connected with the first voltage end V1.So, when pull-up Controlling vertex PU is low level, drop-down Controlling vertex PD is high level, and during second clock signal end CLKB input high level, by third transistor M3, the 4th transistor M4, the 5th transistor M5, the signal that signal output part Output can be exported is drop-down is low level, thus signal output part Output at the corresponding levels can be avoided better under the effect of other undesired signals to become high level, and a line grid line making it control is opened under high level effect, finally causes grid line to open mistake.
It should be noted that, as shown in Figure 4, the signal output part at the corresponding levels of shift register cell at different levels outputs signal from top to bottom and controls each row grid line and opens successively under high level effect, realizes lining by line scan to each row grid line.
As shown in Figure 5, the signal output part at the corresponding levels of shift register cell at different levels not only can output signal from top to bottom lines by line scan to each row grid line, and can line by line scan to each row grid line from bottom to top.Concrete when input signal and voltage end as shown in Figure 5 time, shift register cell at different levels can be lined by line scan to each row grid line from top to bottom, when being exchanged by the first signal input part Input in Fig. 5 and secondary signal input end Reset, the second voltage end V2 and tertiary voltage end V3 is when exchanging, shift register cell at different levels just can output signal from bottom to top and line by line scan to each row grid line, so can realize bilateral scanning.Thus just can be carried out the scanning of different directions to each row grid line by the input signal of change shift register cell and the current potential being connected voltage, those skilled in the art can adjust it as the case may be.
Further, as shown in Fig. 4 or Fig. 5, control module 20 can comprise:
6th transistor M6, grid connects the first clock signal terminal CLK, and its first pole connects second clock signal end CLKB, and the second pole is connected with drop-down Controlling vertex PD.
7th transistor M7, its first pole is connected second clock signal end CLKB with grid, the second pole is connected with drop-down Controlling vertex PD.
8th transistor M8, its first pole connects drop-down Controlling vertex PD, and grid connects pull-up Controlling vertex PU, and the second pole is connected with the first voltage end V1.So, by the 6th transistor M6, the 7th transistor M7 and the 8th transistor M8, the current potential of the signal that can input according to this first clock signal terminal CLK, the signal of second clock signal end CLKB input or this drop-down Controlling vertex PD of control of Electric potentials of pull-up Controlling vertex PU.
Further, as shown in Fig. 4 or Fig. 5, pull-up module 40 can comprise:
9th transistor M9, its first pole connects the first clock signal terminal CLK, and grid connects pull-up Controlling vertex PU, and the second pole is connected with signal output part Output at the corresponding levels.
Electric capacity C1, between its grid being parallel to the 9th transistor M9 and the second pole.So, by the 9th transistor M9 and electric capacity C1, the signal pull-up that can be exported by described signal output part at the corresponding levels under the control of pull-up Controlling vertex current potential is high level;
In embodiments of the present invention, the effect of pull-up module 40 is after carrying out preliminary filling to electric capacity C1, and the first clock signal clk is in half clock period of high level, makes signal output part Output at the corresponding levels export the high level signal of raster data model.
Further, as shown in Fig. 4 or Fig. 5, noise reduction module 60 can comprise: at least one the tenth transistor M10, and its first pole connects the first clock signal terminal CLK, and grid connects pull-up Controlling vertex PU, and the second pole is connected with signal output part Output at the corresponding levels.
It should be noted that; noise reduction module 60 can also be multiple transistors identical with the tenth transistor M10 connected mode; here be only only include for the noise reduction module in such as Fig. 4 or Fig. 5 the explanation that a tenth transistor M10 carries out; the noise reduction module of other structure is illustrated no longer one by one at this, but all should belong within protection scope of the present invention.
In the embodiment of the present invention, noise reduction module 60 for being exported the signal of the first clock signal terminal CLK by signal output part Output at the corresponding levels, thus reduces the noise of pull-up module 40 output signal.Specifically the tenth transistor M10 is connected with the connected mode such as shown in Fig. 4 or Fig. 5 with the 9th transistor M9 in pull-up module 40, so, the size of the tenth transistor M10 does not need very large, and the tenth transistor M10 be connected with the 9th transistor M9 after coupling capacitance to compare the coupling capacitance of the 9th transistor M9 little, and then reduce the impact of the 9th transistor M9 coupling capacitance, thus reduce the noise of pull-up module 40 output signal; In general, shift register is adopted to realize GOA mainly in order to make the narrow frame of display device, therefore, in each shift register cell, the quantity of transistor is very crucial, the number of transistors adopted is fewer, more easily realizes narrow frame, and the present embodiment is by increasing the scheme of transistor, the size of transistor in output module can be reduced through verification experimental verification, and then realize decrease of noise functions.
Below for the structure shown in Fig. 5 and in conjunction with this shift register input and output sequential chart as shown in Figure 6, the course of work of shift register cell is described in detail.
The T1 stage: CLK=0; CLKB=1; Pu=1; Input=1; Output=0; Reset=0.
As shown in Figure 7, due to the first signal input part Input=1, therefore the first transistor M1 conducting control shift register and start working, the current potential of pull-up Controlling vertex PU to be drawn high by the first transistor M1 and is memory capacitance C1 charging by the first signal input part Input.Due to second clock signal end CLKB=1, therefore the 5th transistor M5 conducting, is pulled low to low level VGL by signal output part Output at the corresponding levels, and meanwhile, the 7th transistor M7 also conducting, draws high drop-down Controlling vertex PD to high level.But because pull-up Controlling vertex PU is driven high, therefore the 8th transistor M8 conducting drop-down Controlling vertex PD is pulled low to low level VGL.Third transistor M3 and the 4th transistor M4 can be made like this to keep closing, in order to avoid pull-up Controlling vertex PU is pulled low to low level VGL by third transistor M3.Due to when drop-down Controlling vertex PD draws high by the 7th transistor M7, drop-down Controlling vertex PD can drag down by the 8th transistor M8, and therefore the 7th transistor M7 and the 8th transistor M8 can form phase inverter.When pull-up Controlling vertex PU is high level, 9th transistor M9 and the tenth transistor M10 conducting, but due to the first clock signal terminal CLK=0, therefore signal output part Output output low level at the corresponding levels, and the 6th transistor M6 closes, avoid drop-down Controlling vertex PD to be pulled to high level.The T1 stage is charging stage of electric capacity C1 in this shift register.
The T2 stage: CLK=1; CLKB=0; Pu=1; Input=0; Output=1; Reset=0.
As shown in Figure 8, due to the first signal input part Input=0, therefore the first transistor M1 closes, and pull-up Controlling vertex PU draws high by the boot strap of electric capacity C1 further.Due to second clock signal end CLKB=0, therefore the 5th transistor M5 closes, signal output part Output at the corresponding levels is pulled low to low level VGL, simultaneously to avoid the 5th transistor M5,7th transistor M7 closes, and drop-down Controlling vertex PD is also pulled low to low level VGL by the 8th transistor M8 conducting when pull-up Controlling vertex PU is driven high, therefore drop-down Controlling vertex PD keeps low level.Due to the first clock signal terminal CLK=1, therefore the 9th transistor M9, the tenth transistor M10 conducting when pull-up Controlling vertex PU is high level, and by the high level output on the first clock signal terminal CLK to signal output part Output at the corresponding levels, and then by signal output part Output at the corresponding levels by this high level output on a line grid line corresponding with this shift register cell, the all thin film transistor (TFT)s be positioned in the viewing area of liquid crystal panel on this row grid line are opened, and data line starts write signal.The T2 stage is the stage that this shift register is opened.
The T3 stage: CLK=0; CLKB=1; Pu=0; Input=0; Output=0; Reset=1.
As shown in Figure 9, due to secondary signal input end Reset=1, therefore transistor seconds M2 conducting.After transistor seconds M2 conducting, pull-up Controlling vertex PU is pulled low to low level VSS.In addition, due to second clock signal end CLKB=1, therefore the 5th transistor M5 and the 7th transistor M7 conducting.After 5th transistor M5 conducting, signal output part Output at the corresponding levels is pulled low to low level VGL, thus makes signal output part Output output low level at the corresponding levels; After 7th transistor M7 conducting, drop-down Controlling vertex PD is drawn high (now pull-up Controlling vertex PU is low level, and therefore the 8th transistor M8 closes).When drop-down Controlling vertex PD is high level, third transistor M3 and the 4th transistor M4 conducting, pull-up Controlling vertex PU can be pulled low to VGL by third transistor M3 conducting, and signal output part Output at the corresponding levels can be pulled low to VGL by the 4th transistor M4 conducting.Because third transistor M3 and the 4th transistor M4 can simultaneously conducting, and finally can make signal output part Output output low level at the corresponding levels, therefore when in these two thin film transistor (TFT)s is damaged, another still can keep signal output part Output output low level at the corresponding levels, this set serves the effect of dual fail-safe, thus signal output part Output can be avoided better under the effect of other undesired signals to become high level, and a line grid line making it control is opened under high level effect, finally causes grid line to open mistake.
The T4 stage: CLK=1; CLKB=0; Pu=0; Input=0; Output=0; Reset=0.
As shown in Figure 10, due to second clock signal end CLKB=0, secondary signal input end Reset=0, therefore the 7th transistor M7, transistor seconds M2 and the 5th transistor M5 close.Due to the first clock signal terminal CLK=1, the 6th transistor M6 conducting, the level of drop-down Controlling vertex PD is dragged down, and third transistor M3 and the 4th transistor M4 closes.Pull-up Controlling vertex PU=0, so the 9th transistor M9 and the tenth transistor M10 closes.Signal output part Output output low level at the corresponding levels.
The T5 stage: CLK=0; CLKB=1; Pu=0; Input=0; Output=0; Reset=0.
As shown in figure 11, due to second clock signal end CLKB=1, therefore the 5th transistor M5 and the 7th transistor M7 conducting, make drop-down Controlling vertex PD be high level.Therefore, third transistor M3 and the 4th transistor M4 keeps conducting.Pull-up Controlling vertex PU can be pulled low to VGL by third transistor M3 conducting, signal output part Output at the corresponding levels can be pulled low to VGL by the 4th transistor M4 conducting, thus avoid signal output part Output at the corresponding levels to become high level under the effect of other undesired signals, and a line grid line making it control is opened under high level effect, finally causes grid line to open mistake.
After this until when the first signal input part Input is high level next time, this shift register cell repeats T4 and the T5 stage, can be called the non-working time of shift register cell this period.And T1 ~ T3 stage can be called the working time of shift register cell.From description above, within the non-working time of shift register cell, when drop-down Controlling vertex PD is low level, signal output part Output output low level at the corresponding levels.When drop-down control unit PD keeps high level, make third transistor M3 and the 4th transistor M4 keep conducting, thus make pull-up Controlling vertex PU and signal output part Output at the corresponding levels keep low level.In the T2 stage, because the 9th transistor M9 connects with the tenth transistor M10, when the size of the tenth transistor M10 does not need very large, the coupling capacitance of two transistors after series connection is relatively little with the coupling capacitance of the 9th transistor M9, and then reduce the impact of the 9th transistor M9 coupling capacitance on output signal, thus reduce the noise of output signal.
The embodiment of the present invention provides a kind of gate driver circuit, as shown in figure 12, comprises multistage shift register cell as above.Wherein, the output terminal Output of every one-level shift register cell SR exports line scanning letter G at the corresponding levels; Each shift register cell has a first clock signal clk input and a second clock signal CLKB to input; Second clock signal CLKB and the first clock signal clk have the phase differential of 180 degree, and the first clock signal clk and second clock signal CLKB all half the time output high level within the respective work period, second half time output low level.
Wherein VGH can be VDD, VGL can be VSS.
Except first order shift register cell SR0, the first signal input part G (N-1) of all the other each shift register cells connects the signal output part Output at the corresponding levels of the upper level shift register cell be adjacent.
Except afterbody shift register cell SRn, signal first signal input part G (N-1) of the next stage shift register cell that the signal output part Output at the corresponding levels of all the other each shift register cells is adjacent is connected.
In embodiments of the present invention, first signal input part G (N-1) I of first order shift register cell SR0 can incoming frame start signal STV; The secondary signal input end G (N+1) of afterbody shift register cell SRn can input reset signal RST, or the output Output(Gn of afterbody shift register cell SRn) as reset signal RST at the corresponding levels.
The invention provides a kind of gate driver circuit.This gate driver circuit comprises shift register cell at different levels, this shift register cell comprises load module, control module, reseting module, pull-up module, drop-down module and noise reduction module, by the noise reduction module with this pull-up block coupled in series, the size of thin film transistor (TFT) in pull-up module can be reduced, so, the coupling capacitance of thin film transistor (TFT) in pull-up module can be reduced, thus reduce the noise of output signal.
The embodiment of the present invention also provides a kind of display device, comprises gate driver circuit as above.
The invention provides a kind of display device.This display device comprises gate driver circuit, this gate driver circuit comprises shift register cell at different levels, this shift register cell comprises load module, control module, reseting module, pull-up module, drop-down module and noise reduction module, by the noise reduction module with this pull-up block coupled in series, the size of thin film transistor (TFT) in pull-up module can be reduced, so, the coupling capacitance of thin film transistor (TFT) in pull-up module can be reduced, thus reduce the noise of output signal.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (10)
1. a shift register cell, is characterized in that, comprising: load module, control module, reseting module, pull-up module, drop-down module and noise reduction module;
Described load module, connects the first signal input part and pull-up Controlling vertex respectively, for controlling the current potential of described pull-up Controlling vertex according to the signal of described first signal input part input;
Described control module, connect the first clock signal terminal, second clock signal end, the first voltage end, described pull-up Controlling vertex and drop-down Controlling vertex respectively, for the current potential of drop-down Controlling vertex described in the signal according to described first clock signal terminal input, the signal of described second clock signal end input or the control of Electric potentials of described pull-up Controlling vertex;
Described reseting module, connects secondary signal input end, described first voltage end, described pull-up Controlling vertex and described drop-down Controlling vertex respectively, for the current potential of the described pull-up Controlling vertex that resets according to the signal of described secondary signal input end input;
Described pull-up module, connecting described first clock signal terminal, described pull-up Controlling vertex and signal output part at the corresponding levels respectively, exporting the signal of described first clock signal terminal for making described signal output part at the corresponding levels under the control of described pull-up Controlling vertex current potential;
Described pull-up module comprises the 9th transistor and electric capacity; First pole of described 9th transistor connects described first clock signal terminal, and grid connects described pull-up Controlling vertex, and the second pole is connected with described signal output part at the corresponding levels; Described Capacitance parallel connection is between the grid and the second pole of described 9th transistor;
Described drop-down module, connects described first voltage end, described drop-down Controlling vertex and described signal output part at the corresponding levels respectively, and the signal for being exported by described signal output part at the corresponding levels under the control of described drop-down Controlling vertex current potential is drop-down is low level;
Described noise reduction module, connects described first clock signal terminal, described pull-up Controlling vertex and signal output part at the corresponding levels respectively, for being exported the signal of described first clock signal terminal by described signal output part at the corresponding levels;
Described noise reduction module comprises at least one the tenth transistor, and its first pole connects described first clock signal terminal, and grid connects described pull-up Controlling vertex, and the second pole is connected with described signal output part at the corresponding levels.
2. shift register cell according to claim 1, is characterized in that, described load module comprises:
The first transistor, its first pole is connected described first signal input part with grid, the second pole is connected with described pull-up Controlling vertex.
3. shift register cell according to claim 2, is characterized in that, described reseting module comprises:
Transistor seconds, its first pole connects described pull-up Controlling vertex, and grid connects described secondary signal input end, and the second pole is connected with described first voltage end;
5th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described secondary signal input end, and the second pole is connected with described first voltage end.
4. shift register cell according to claim 3, is characterized in that, described drop-down module comprises:
Third transistor, its first pole connects described pull-up Controlling vertex, and grid connects described drop-down Controlling vertex, and the second pole is connected with described first voltage end;
4th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described drop-down Controlling vertex, and the second pole is connected with described first voltage end.
5. shift register cell according to claim 1, is characterized in that, described load module comprises:
The first transistor, its first pole connects the second voltage end, and grid connects described first signal input part, and the second pole is connected with described pull-up Controlling vertex.
6. shift register cell according to claim 5, is characterized in that, described reseting module comprises:
Transistor seconds, its first pole connects described pull-up Controlling vertex, and grid connects described secondary signal input end, and the second pole is connected with tertiary voltage end.
7. shift register cell according to claim 6, is characterized in that, described drop-down module also comprises:
Third transistor, its first pole connects described pull-up Controlling vertex, and grid connects described drop-down Controlling vertex, and the second pole is connected with described first voltage end;
4th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described drop-down Controlling vertex, and the second pole connects described first voltage end;
5th transistor, its first pole connects described signal output part at the corresponding levels, and grid connects described second clock signal end, and the second pole is connected with described first voltage end.
8., according to the arbitrary described shift register cell of claim 1 to 7, it is characterized in that, described control module comprises:
6th transistor, grid connects described first clock signal terminal, and its first pole connects described second clock signal end, and the second pole is connected with described drop-down Controlling vertex;
7th transistor, its first pole is connected described second clock signal end with grid, the second pole is connected with described drop-down Controlling vertex;
8th transistor, its first pole connects described drop-down Controlling vertex, and grid connects described pull-up Controlling vertex, and the second pole is connected with described first voltage end.
9. a gate driver circuit, is characterized in that, comprise multistage as arbitrary in claim 1 to 8 as described in shift register cell;
Except first order shift register cell, the signal input part of all the other each shift register cells connects the signal output part at the corresponding levels of the upper level shift register cell be adjacent;
Except afterbody shift register cell, the signal input part of the next stage shift register cell that the signal output part at the corresponding levels of all the other each shift register cells is adjacent is connected.
10. a display device, is characterized in that, comprises gate driver circuit as claimed in claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310308994.9A CN103413531B (en) | 2013-07-22 | 2013-07-22 | A kind of shift register cell, gate driver circuit and display device |
| PCT/CN2013/084192 WO2015010364A1 (en) | 2013-07-22 | 2013-09-25 | Shift register unit, gate drive circuit and display device |
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| CN201310308994.9A CN103413531B (en) | 2013-07-22 | 2013-07-22 | A kind of shift register cell, gate driver circuit and display device |
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| CN103700355B (en) | 2013-12-20 | 2016-05-04 | 京东方科技集团股份有限公司 | A kind of shift register cell, gate driver circuit and display device |
| CN103996370B (en) * | 2014-05-30 | 2017-01-25 | 京东方科技集团股份有限公司 | Shifting register unit, grid drive circuit, display device and drive method |
| CN104167192B (en) * | 2014-07-22 | 2017-01-18 | 京东方科技集团股份有限公司 | Shift register unit, gate drive circuit and display device |
| CN104282283B (en) * | 2014-10-21 | 2016-09-28 | 重庆京东方光电科技有限公司 | A kind of shift register cell, gate driver circuit and display device |
| CN104299590B (en) * | 2014-10-30 | 2016-08-24 | 京东方科技集团股份有限公司 | A kind of shift register, its driving method, gate driver circuit and display device |
| CN104537980B (en) * | 2015-02-03 | 2017-03-29 | 京东方科技集团股份有限公司 | A kind of shift register and its driving method, gate driver circuit, display device |
| CN104810058B (en) * | 2015-05-13 | 2018-04-06 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit and display device |
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| CN104867472B (en) * | 2015-06-15 | 2017-10-17 | 合肥京东方光电科技有限公司 | A kind of shift register cell, gate driving circuit and display device |
| CN105096811B (en) * | 2015-09-23 | 2017-12-08 | 京东方科技集团股份有限公司 | GOA unit, gate driving circuit and display device |
| US11127336B2 (en) | 2015-09-23 | 2021-09-21 | Boe Technology Group Co., Ltd. | Gate on array (GOA) unit, gate driver circuit and display device |
| CN105185345B (en) * | 2015-10-23 | 2018-09-07 | 京东方科技集团股份有限公司 | A kind of gate driving circuit and its driving method, display panel |
| CN105374314B (en) * | 2015-12-24 | 2018-01-19 | 京东方科技集团股份有限公司 | Shifting deposit unit and its driving method, gate driving circuit and display device |
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| CN106991958B (en) * | 2017-06-09 | 2020-07-17 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN107154234B (en) * | 2017-07-20 | 2020-01-21 | 京东方科技集团股份有限公司 | Shifting register unit, driving method, grid driving circuit and display device |
| CN109545164B (en) | 2019-01-02 | 2021-04-09 | 合肥京东方显示技术有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN110599978B (en) * | 2019-09-19 | 2021-11-05 | 京东方科技集团股份有限公司 | Shift register, grid drive circuit and display device |
| CN111627486B (en) * | 2020-06-18 | 2022-04-12 | 武汉京东方光电科技有限公司 | Shift register, driving method thereof and driving circuit |
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