CN203746393U - Gate drive circuit and display device - Google Patents

Gate drive circuit and display device Download PDF

Info

Publication number
CN203746393U
CN203746393U CN201420143721.3U CN201420143721U CN203746393U CN 203746393 U CN203746393 U CN 203746393U CN 201420143721 U CN201420143721 U CN 201420143721U CN 203746393 U CN203746393 U CN 203746393U
Authority
CN
China
Prior art keywords
shift register
utmost point
register cell
control node
control
Prior art date
Application number
CN201420143721.3U
Other languages
Chinese (zh)
Inventor
张元波
赵家阳
韩承佑
邹祥祥
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201420143721.3U priority Critical patent/CN203746393U/en
Application granted granted Critical
Publication of CN203746393U publication Critical patent/CN203746393U/en

Links

Abstract

The utility model provides a gate drive circuit and a display device, and relates to the displaying technical field. The gate drive circuit comprises a plurality of cascaded shifting register units and a precharging unit. The scan outputting and touch control scanning of the plurality of stages of the shifting register units are carried out at intervals. The additionally-arranged precharging unit which is connected with the first stage of shifting register unit after finishing touch control scanning pre-charges the first stage of shifting register unit during touch control scanning, thereby preventing PU node electric leakage, due to relatively long touch control scanning time between the outputs of two stages of shifting register units, of the first stage of shifting register unit after finishing touch control scanning, and guaranteeing high-point-reporting-rate touch control scanning, and meanwhile, preventing the defects of insufficient line pixel charging rate.

Description

A kind of gate driver circuit and display device

Technical field

The utility model relates to display technique field, relates in particular to a kind of gate driver circuit and display device.

Background technology

Day by day universal along with touch control display device, people are also more and more higher for the quality requirements of touch control display device, and embedded touch (In-cell touch) technology is widely used because of advantages such as its thin thickness having and touch-control sensitivity height.

Embedded touch technology is within touch control component is integrated in display panel, makes panel itself just have touch controllable function, does not need to carry out in addition can reach with the laminating of contact panel and assembling effect and the application of touch-control.With typical TFT-LCD(Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor (TFT) liquid crystal display) be example, be characterized in completing the manufacturing technology of touch-control sensing element in TFT-LCD standard processing procedure, due to without contact panel is additionally set, thereby there is no the problem of laminating and contraposition, weight and thickness also significantly reduce, and product will be more frivolous.Due to embedding technique in adopting, make display device product without frame, can reach whole plane design, the design of product also more succinct clever falls, and application is wider.

Existing embedded touch technology generally adopts projection-type multiple spot capacitance touching control mode, the collection of its touching signals is by two-layer signal wire, wherein one deck signal wire is drive wire (Tx lines), and another layer signal line is as the line of induction (Rx lines), and two sandwich circuits are perpendicular to one another.In implementation, adopt scan-type to drive in turn each drive wire, and measure with the staggered line of induction of this drive wire whether have certain some generation capacitive coupling phenomenon.Through scanning one by one, can obtain definite contact position, and can realize multi-point touch.

For existing touch control display apparatus, can interfere with each other when be positioned at when the pixel of identical row or column and sweep trace charge simultaneously, so the process of pixel charging and scanning is all that timesharing is carried out conventionally, concrete, sequential mode generally have two kinds of V-Blank and H-Blank in a frame time.V-Blank mode refers in a frame, after all pixel chargings, stays a period of time to carry out touching signals scanning, i.e. pixel charging separates and carries out with touch-control scanning.This kind of mode can only be supported the touch-control scanning refresh rate (1:1 relation) identical with display picture refresh rate, if picture refreshing rate is 60HZ, touch-control scanning refresh rate can only be 60HZ.In order to improve the sensitivity of touch-control, the frequency that improves touch-control scanning is crucial, and in the time pursuing high performance touch-control experience effect, 120HZ and above touch refresh rate are necessary.

H-Blank mode can effectively improve touch-control scanning refresh rate, which is by a frame, in the gap of certain line number pixel charging, reserved a period of time is carried out the scanning of part touching signals, be that pixel charging intersects and carries out with touch-control scanning, this kind of mode can be supported to touch scanning refresh rate and be greater than picture refreshing rate, becomes multiple relation with picture refreshing rate.Adopt H-Blank mode to realize and double and show that the embedded touch scanning sequence of refreshing frequency can be as shown in Figure 1, by reading scan being divided into two sections, after every section of end, suspend picture element scan GOA(Gate Drive on Array, the capable driving of array base palte) circuit working, carries out single pass (Tx scanning) to all touch induction lines, therefore in a reading scan, can complete 2 touch-control scanning, realize and double the touch-control scanning that shows refreshing frequency.

Traditional GOA circuit generally includes the shift register cell of multiple cascades, its structure can be as shown in Figure 2, wherein, each shift register cell is connected with the shift register cell of adjacent lines respectively, the equal corresponding a line grid line of each shift register cell, when each line shift register unit output gate drive signal, can carry out precharge to next line shift register cell, to ensure the realization output within the next clock period of next line shift register cell.In the prior art, as shown in Figure 3, shift register cell is taking the simplest 4T1C structure as example, when carry out as shown in Figure 1 H-Blank sequence scanning time, because N/2+1 line shift register unit is a line starting most of second 1/2 reading scan, but on it, draw control PU node in the time of N/2 line output, to be charged to high level, owing to being separated by longer sweep time between N/2 and N/2+1 line output, therefore PU point current potential can be by connected TFT electric leakage, thereby have a strong impact on the precharge of N/2+1 line shift register unit, lower voltage while making to export in N/2+1 line shift register unit, thereby cause this row pixel charge rate deficiency, occur that concealed wire or bright line are bad.

Utility model content

Embodiment of the present utility model provides a kind of gate driver circuit and display device, can avoid row pixel charge rate deficiency, improves concealed wire or bright line is bad.

For achieving the above object, embodiment of the present utility model adopts following technical scheme:

The one side of the utility model embodiment, provides a kind of gate driver circuit, comprises shift register cell and the precharge unit of multiple mutual cascades, and scanning output and the touch-control sweep spacing of multistage described shift register cell are carried out;

Except first order shift register cell, the signal output part of all the other each shift register cells all connects the reset signal end of the upper level shift register cell being adjacent;

Except afterbody shift register cell, the signal output part of all the other each shift register cells all connects the signal input part of the next stage shift register cell being adjacent;

Described precharge unit is connected with the first order shift register cell after having carried out touch-control scanning, for carry out touch-control while scanning to the precharge of described first order shift register cell.

Wherein, described shift register cell comprises: load module, reseting module, upper drawing-die piece, control module and drop-down module;

Described load module, connect signal input part and on draw control node, for draw the level of controlling node on described in the signal controlling of described signal input part input, drawing on described and controlling node is the tie point of described load module and described upper drawing-die piece;

Described reseting module, connect reset signal end, voltage end and described on draw control node, for draw the level of controlling node on described in the signal controlling of described reset signal end input;

Described upper drawing-die piece, connect the first clock signal input terminal, draw on described and control node and signal output part, for according to drawing the clock signal of controlling node and described the first clock signal input terminal input to draw as high level on the signal of described signal output part output on described;

Described control module, connect second clock signal input part, described voltage end, draw on described and control node and drop-down control node, for according to the clock signal of described second clock signal input part input and described on draw the level of drop-down control node described in the level control of controlling node;

Described drop-down module, connects on described and draws and control node, described drop-down control node, described voltage end and described signal output part, for by drop-down the signal of described signal output part output be low level.

Concrete, described load module comprises:

The first transistor, draws control node on its first utmost point connection is described, and its second utmost point is all connected described signal input part with grid.

Further, described reseting module comprises:

Transistor seconds, its first utmost point connects described voltage end, and its grid connects described reset signal end, on its second utmost point connection is described, draws control node.

Described upper drawing-die piece comprises:

The 3rd transistor, its first utmost point connects described signal output part, on its grid connection is described, draws control node, and its second utmost point connects described the first clock signal input terminal;

Electric capacity, described Capacitance parallel connection is between described the 3rd transistorized grid and described the 3rd transistorized first utmost point.

Described control module comprises:

The 4th transistor, its grid and second is extremely all connected described second clock signal input part;

The 5th transistor, its grid connects described the 4th transistorized first utmost point, and its second utmost point connects described second clock signal input part;

The 6th transistor, its first utmost point connects described voltage end, on its grid connection is described, draws control node, and its second utmost point connects described the 4th transistorized first utmost point;

The 7th transistor, its first utmost point connects described voltage end, on its grid connection is described, draws control node, and its second utmost point connects described drop-down control node.

Described drop-down module comprises:

The 8th transistor, its first utmost point connects described voltage end, and its grid connects described drop-down control node, on its second utmost point connection is described, draws control node;

The 9th transistor, its first utmost point connects described voltage end, and its grid connects described drop-down control node, and its second utmost point connects described signal output part.

Further, described precharge unit connect respectively charging signals input end and described first order shift register cell on draw control node.

Further, described precharge unit comprises:

The tenth transistor, its first utmost point connect described first order shift register cell on draw control node, its grid is connected described charging signals input end with second utmost point.

Wherein, the signal input part incoming frame start signal of described first order shift register cell; The reset signal end input reset signal of described afterbody shift register cell.

On the other hand, the utility model embodiment also provides a kind of display device, comprises gate driver circuit as above.

The gate driver circuit that the utility model embodiment provides and display device, the precharge unit being connected with the first order shift register cell after having carried out touch-control scanning by extra setting, carrying out touch-control when scanning to the precharge of described first order shift register cell, so, avoid between two line shift register unit outputs the first order shift register cell PU point leaky after having carried out touch-control scanning having caused sweep time compared with long touch-control owing to being separated by, thereby in the touch-control scanning that ensures high report point rate, avoid the defect of row pixel charge rate deficiency, significantly improve concealed wire or bright line is bad, improve display quality.

Brief description of the drawings

Fig. 1 is that in prior art, a kind of H-Blank of employing mode realizes the embedded touch scanning sequence structural representation that doubles demonstration refreshing frequency;

Fig. 2 is the structural representation of a kind of gate driver circuit in prior art;

Fig. 3 is the structural representation of shift register cell in a kind of gate driver circuit in prior art;

The structural representation of a kind of gate driver circuit that Fig. 4 provides for the utility model embodiment;

The structural representation of shift register cell in the gate driver circuit that Fig. 5 provides for the utility model embodiment;

The circuit connection structure schematic diagram of a kind of shift register cell that Fig. 6 provides for the utility model embodiment;

Signal sequence oscillogram when a kind of gate driver circuit that Fig. 7 provides for the utility model embodiment is worked;

The schematic flow sheet of the driving method of a kind of gate driver circuit that Fig. 8 provides for the utility model embodiment.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiment.Based on the embodiment in the utility model, the every other embodiment that those of ordinary skill in the art obtain, belongs to the scope that the utility model is protected.

The transistor adopting in all embodiment of the utility model all can be for thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the transistorized source electrode adopting here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In the utility model embodiment, for distinguishing transistor the two poles of the earth except grid, wherein a utmost point is called first utmost point, and another utmost point is called to second utmost point.In addition, distinguish and transistor can be divided into N-type and P type according to transistorized characteristic, following examples all describe as an example of N transistor example, in the time adopting N-type transistor, first can be extremely the transistorized source electrode of this N-type, and second utmost point can be the transistorized drain electrode of this N-type.What can expect is that those skilled in the art can expect easily not making under creative work prerequisite in the time adopting P transistor npn npn to realize, therefore also in embodiment protection domain of the present utility model.

The gate driver circuit that the utility model embodiment provides, as shown in Figure 4, comprises shift register cell 41 and the precharge unit 42 of multiple mutual cascades, and scanning output and the touch-control sweep spacing of multi-stage shift register unit 41 are carried out.

Wherein, except first order shift register cell, the signal output part OUTPUT of all the other each shift register cells 41 all connects the reset signal end RESET of the upper level shift register cell 41 being adjacent.

Except afterbody shift register cell, the signal output part OUTPUT of all the other each shift register cells 41 all connects the signal input part INPUT of the next stage shift register cell 41 being adjacent.

Precharge unit 42 is connected with the first order shift register cell after having carried out touch-control scanning, for carry out touch-control while scanning to these first order shift register cell 41 precharge.

The gate driver circuit that the utility model embodiment provides, the precharge unit being connected with the first order shift register cell after having carried out touch-control scanning by extra setting, carrying out touch-control when scanning to the precharge of described first order shift register cell, so, avoid between two line shift register unit outputs the first order shift register cell PU point leaky after having carried out touch-control scanning having caused sweep time compared with long touch-control owing to being separated by, thereby in the touch-control scanning that ensures high report point rate, avoid the defect of row pixel charge rate deficiency, significantly improve concealed wire or bright line is bad, improve display quality.

It should be noted that, the array base palte with the capable grid line of N is carried out, grid is capable to be driven in the process that scanning adds touch-control scanning, in order to improve the precision and report point rate of touch-control scanning, the frequency that improves touch-control scanning is crucial, this just requires to add repeatedly touch-control scanning in a capable process that drives scanning of grid, can be by the gap of certain line number pixel charging, reserved a period of time is carried out the scanning of part touching signals, be that pixel charging intersects and carries out with touch-control scanning, this kind of mode can be supported to touch scanning refresh rate and be greater than picture refreshing rate, become multiple relation with picture refreshing rate.

Concrete, in gate driver circuit as shown in Figure 4, two explanations that carry out in region that there is same number of rows grid line so that array base palte is divided into, wherein, capable front N/2 grid line region can be called to first area, capable rear N/2 grid line region is called to second area, after first area has been scanned and second area start scanning before a period of time be touch-control sweep time.Precharge unit 42 for carrying out precharge to the first order shift register cell 41 that is positioned at second area in the time carrying out touch-control scanning.Certainly, also only illustrate above, in order further to improve the refresh rate that touches scanning, the grid line on array base palte can be divided into more region and scan, the utility model does not limit this.

Further, as shown in Figure 5, shift register cell 41 can comprise: load module 411, reseting module 412, upper drawing-die piece 413, control module 414 and drop-down module 415.

Wherein, load module 411, connect signal input part INPUT and on draw and control node PU, for according to drawing the level of controlling node PU in the signal controlling of signal input part INPUT input, drawing on this, to control node PU be load module 411 and the tie point of upper drawing-die piece 413.

Reseting module 412, connect reset signal end RESET, voltage end VSS and on draw and control node PU, for according to drawing the level of controlling node PU in the signal controlling of reset signal end RESET input.

Upper drawing-die piece 413, connect the first clock signal input terminal CLK, on draw and control node PU and signal output part OUTPUT, for according to above drawing the clock signal of controlling node PU and the first clock signal input terminal CLK input to draw as high level on the signal of signal output part OUTPUT output.

Control module 414, connect second clock signal input part CLKB, voltage end VSS, on draw and control node PU and drop-down control node PD, for according to the clock signal of second clock signal input part CLKB input and on draw the level of the drop-down control node of the level control PD that controls node PU.

Drop-down module 415, draws in connection and controls node PU, drop-down control node PD, voltage end VSS and signal output part OUTPUT, for by drop-down the signal of signal output part OUTPUT output be low level.

Wherein, voltage end VSS can be low level input.The clock signal that the first clock signal terminal CLK and second clock signal end CLKB input is square wave clock signal and has identical cycle and dutycycle, but the single spin-echo of two clock signals, in the time of CLK input high level, and CLKB input low level.

Further, the concrete structure of the shift register cell that the utility model embodiment provides can be with reference to shown in Fig. 6, and wherein, load module 411 can comprise:

The first transistor M1, its first utmost point draws and controls node PU on connecting, and its second utmost point is all connected signal input part INPUT with grid.

Reseting module 412 can comprise:

Transistor seconds M2, its first utmost point connects voltage end VSS, and its grid connects reset signal end RESET, and its second utmost point draws on connecting controls node PU.

In the utility model embodiment, above draw control node PU to refer to and control the circuit node of upper drawing-die piece 413 in unlatching or closed condition.The effect of load module 411 and reseting module 412 is drawn the level height of controlling node PU on specifically determining according to the low and high level of signal input part INPUT and reset signal end RESET different, thereby determines that shift register cell is current in output or reset mode.

A kind of like this load module 411 of structure and reseting module 412 can be realized the capable driving of grid simple scanning from top to bottom.Concrete, in the time of the output terminal OUTPUT of upper level shift register cell output signal, this output signal is by the input end INPUT of input shift register cell at the corresponding levels, thereby realize the precharge to PU node at the corresponding levels, until the next clock period is realized the output of shift register cell OUTOPUT end at the corresponding levels temporarily.The output signal of shift register cell at the corresponding levels inputs to again the RESET end of higher level's shift register cell and the INPUT end of subordinate's shift register cell simultaneously, realize the reset to upper level shift register cell and the precharge to the shift register cell PU of subordinate node, by that analogy, the final unidirectional scanning step by step realizing from top to bottom.

Further, as shown in Figure 6, upper drawing-die piece 413 can comprise:

The 3rd transistor M3, its first utmost point connects signal output part OUTPUT, and its grid draws and controls node PU on connecting, and its second utmost point connects the first clock signal input terminal CLK.

Capacitor C, this capacitor C is parallel between the grid of the 3rd transistor M3 and first utmost point of the 3rd transistor M3.

In the utility model embodiment, the effect of upper drawing-die piece 413 is after carrying out preliminary filling, and in the clock signal of the first clock signal input terminal CLK input clock period that is high level, the high level signal that signal output part OUTPUT output grid is driven.

Further, as shown in Figure 6, control module 414 can comprise:

The 4th transistor M4, its grid and second is extremely all connected second clock signal input part CLKB.

The 5th transistor M5, its grid connects first utmost point of the 4th transistor M4, and its second utmost point connects second clock signal input part CLKB.

The 6th transistor M6, its first utmost point connects voltage end VSS, and its grid draws on connecting controls node PU, and its second utmost point connects first utmost point of the 4th transistor M4.

The 7th transistor M7, its first utmost point connects voltage end VSS, and its grid draws and controls node PU on connecting, and its second utmost point connects drop-down control node PD.

In the utility model embodiment, the effect of control module 414 is according to the level that above draws the drop-down control node of the Control of Voltage PD that controls node PU, and wherein, drop-down control node PD refers to and controls the circuit node of drop-down module in unlatching or closed condition.

Further, as shown in Figure 6, drop-down module 415 can comprise:

The 8th transistor M8, its first utmost point connects voltage end VSS, and its grid connects drop-down control node PD, and its second utmost point draws on connecting controls node PU.

The 9th transistor M9, its first utmost point connects voltage end VSS, and its grid connects drop-down control node PD, and its second utmost point connects signal output part OUTPUT.

In the utility model embodiment, the effect of drop-down module 415 is specifically when drop-down control node PD point current potential is while being high, and in the time that clock signal is low level respectively on draw and control node PU current potential and signal output part OUTPUT carries out drop-down.

In shift register cell as shown in Figure 6, comprise respectively 9 N-type transistors and 1 electric capacity (9T1C), compared with current comparatively conventional shift register cell, in the design of sort circuit structure, components and parts are relatively less, thereby significantly simplify the difficulty of circuit design and production, effectively control the size of circuit region and wiring space, realized the design of the narrow frame of display device.

In the utility model embodiment, as shown in Figure 4, precharge unit 42 connect respectively charging signals input end SW and be positioned at second area first order shift register cell 41 on draw and control node PU.

Concrete, as shown in Figure 4, precharge unit 42 can comprise:

The tenth transistor M10, draws and controls node PU on its first utmost point connection first order shift register cell 41, and its grid is connected charging signals input end SW with second utmost point.

Known according to the analysis to prior art, N/2+1 shift register cell is owing to being touch-control scanning first shift register cell afterwards, so its PU point there will be decay, therefore introduce extra SW signal, in the time that scanning, touch-control is set to high level, can make the PU point of N/2+1 keep noble potential, thereby ensure that output is normal.As can be seen from Figure 7, under the effect of SW signal, the PU point of N/2+1 level shift register cell and output signal all can keep normally, do not occur the phenomenon of decay, produce a desired effect.Wherein the effect of transistor M10 is one-way conduction, in the time that SW is high level, inputs the PU point of N/2+1 level shift register cell for high, and SW inputs the PU point of N/2+1 level shift register cell for low while being low level.As long as should be appreciated that circuit or the electronic component that can realize this function can adopt, be not limited to transistor M10, also can comprise multiple transistors, adopt the design of transistor M10 can further simplify circuit structure.This functional circuit specifically can be realized by thin film transistor (TFT) technique, also can be by integrated circuit (IC) control, or other circuit structures are realized.

In the utility model embodiment, as shown in Figure 4, the signal input part INPUT of first order shift register cell can incoming frame start signal STV; The reset signal end RESET of afterbody shift register cell can input reset signal RST.

Adopt gate driver circuit as shown in Figure 4, the precharge unit being connected with the first order shift register cell after having carried out touch-control scanning by extra setting, carrying out touch-control when scanning to the precharge of described first order shift register cell, so, avoid between two line shift register unit outputs the first order shift register cell PU point leaky after having carried out touch-control scanning having caused sweep time compared with long touch-control owing to being separated by, thereby in the touch-control scanning that ensures high report point rate, avoid the defect of row pixel charge rate deficiency, significantly improve concealed wire or bright line is bad, improve display quality.

Corresponding with gate driver circuit, the utility model embodiment also provides a kind of driving method of gate driver circuit, can be applied to gate driver circuit as above, as shown in Figure 8, comprising:

S801, carry out the capable driving of grid scanning to being positioned at the shift register cell of first area in gate driver circuit.

S802, after the capable driving of grid of first area shift register cell has scanned, carry out touch-control scanning, time the first order shift register cell that is positioned at second area is carried out to precharge carrying out touch-control scanning.

S803, carry out the capable driving of grid scanning to being positioned at the shift register cell of second area in gate driver circuit, be positioned at the afterbody shift register cell and the first order shift register cell phase cascade that is positioned at second area of first area.

The driving method of the gate driver circuit that the utility model embodiment provides, the precharge unit being connected with the first order shift register cell after having carried out touch-control scanning by extra setting, carrying out touch-control when scanning to the precharge of described first order shift register cell, so, avoid between two line shift register unit outputs the first order shift register cell PU point leaky after having carried out touch-control scanning having caused sweep time compared with long touch-control owing to being separated by, thereby in the touch-control scanning that ensures high report point rate, avoid the defect of row pixel charge rate deficiency, significantly improve concealed wire or bright line is bad, improve display quality.

It should be noted that, the array base palte with the capable grid line of N is carried out, grid is capable to be driven in the process that scanning adds touch-control scanning, in order to improve the precision and report point rate of touch-control scanning, the frequency that improves touch-control scanning is crucial, this just requires to add repeatedly touch-control scanning in a capable process that drives scanning of grid, can be by the gap of certain line number pixel charging, reserved a period of time is carried out the scanning of part touching signals, be that pixel charging intersects and carries out with touch-control scanning, this kind of mode can be supported to touch scanning refresh rate and be greater than picture refreshing rate, become multiple relation with picture refreshing rate.

Concrete, in gate driver circuit as shown in Figure 4, two explanations that carry out in region that there is same number of rows grid line so that array base palte is divided into, wherein, capable front N/2 grid line region can be called to first area, capable rear N/2 grid line region is called to second area, after first area has been scanned and second area start scanning before a period of time be touch-control sweep time.Precharge unit 42 for carrying out precharge to the first order shift register cell 41 that is positioned at second area in the time carrying out touch-control scanning.Certainly, also only illustrate above, in order further to improve the refresh rate that touches scanning, the grid line on array base palte can be divided into more region and scan, the utility model does not limit this.

Wherein, the structure of shift register cell specifically can, with reference to shown in Fig. 6, not repeat herein.Further, can as shown in Figure 4, realize the precharge of the first order shift register cell to being positioned at second area by precharge unit 42.

Concrete, in the time carrying out touch-control scanning, carry out precharge and can comprise being positioned at the first order shift register cell of second area:

Carrying out touch-control when scanning, to be positioned at second area first order shift register cell on draw the charging signals of controlling node input high level; In the time carrying out the capable driving of grid scanning, stop first order shift register cell to being positioned at second area on draw and control node input charging signals.

For example, precharge unit 42 can comprise transistor M10, on its first utmost point connection first order shift register cell 41, draws and controls node PU, and its grid is connected charging signals input end with second utmost point.In the time carrying out touch-control scanning, SW signal by turn-on transistor M10 to be positioned at second area first order shift register cell on draw and control node input high level, in the time carrying out the capable driving scanning of grid, SW signal will be closed transistor M10, stop first order shift register cell to being positioned at second area on draw and control node input charging signals.

As long as should be appreciated that circuit or the electronic component that can realize this function can adopt, be not limited to transistor M10, also can comprise multiple transistors, adopt the design of transistor M10 can further simplify circuit structure.This functional circuit specifically can be realized by thin film transistor (TFT) technique, also can be by integrated circuit (IC) control, or other circuit structures are realized.

In addition, the utility model embodiment also provides a kind of display device, comprises gate driver circuit as above.

Because the structure of gate driver circuit has been done detailed description in the aforementioned embodiment, do not repeat herein.

The display device that the utility model embodiment provides, comprise gate driver circuit, this gate driver circuit comprises again shift register cell, the precharge unit being connected with the first order shift register cell after having carried out touch-control scanning by extra setting, carrying out touch-control when scanning to the precharge of described first order shift register cell, so, avoid between two line shift register unit outputs the first order shift register cell PU point leaky after having carried out touch-control scanning having caused sweep time compared with long touch-control owing to being separated by, thereby in the touch-control scanning that ensures high report point rate, avoid the defect of row pixel charge rate deficiency, significantly improve concealed wire or bright line is bad, improve display quality.

One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can complete by the relevant hardware of programmed instruction, aforesaid program can be stored in a computer read/write memory medium, this program, in the time carrying out, is carried out the step that comprises said method embodiment; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CDs.

The above; it is only embodiment of the present utility model; but protection domain of the present utility model is not limited to this; any be familiar with those skilled in the art the utility model disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection domain of the present utility model.Therefore, protection domain of the present utility model should described be as the criterion with the protection domain of claim.

Claims (11)

1. a gate driver circuit, is characterized in that, comprises shift register cell and the precharge unit of multiple mutual cascades, and scanning output and the touch-control sweep spacing of multistage described shift register cell are carried out;
Except first order shift register cell, the signal output part of all the other each shift register cells all connects the reset signal end of the upper level shift register cell being adjacent;
Except afterbody shift register cell, the signal output part of all the other each shift register cells all connects the signal input part of the next stage shift register cell being adjacent;
Described precharge unit is connected with the first order shift register cell after having carried out touch-control scanning, for carry out touch-control while scanning to the precharge of described first order shift register cell.
2. gate driver circuit according to claim 1, is characterized in that, described shift register cell comprises: load module, reseting module, upper drawing-die piece, control module and drop-down module;
Described load module, connect signal input part and on draw control node, for draw the level of controlling node on described in the signal controlling of described signal input part input, drawing on described and controlling node is the tie point of described load module and described upper drawing-die piece;
Described reseting module, connect reset signal end, voltage end and described on draw control node, for draw the level of controlling node on described in the signal controlling of described reset signal end input;
Described upper drawing-die piece, connect the first clock signal input terminal, draw on described and control node and signal output part, for according to drawing the clock signal of controlling node and described the first clock signal input terminal input to draw as high level on the signal of described signal output part output on described;
Described control module, connect second clock signal input part, described voltage end, draw on described and control node and drop-down control node, for according to the clock signal of described second clock signal input part input and described on draw the level of drop-down control node described in the level control of controlling node;
Described drop-down module, connects on described and draws and control node, described drop-down control node, described voltage end and described signal output part, for by drop-down the signal of described signal output part output be low level.
3. gate driver circuit according to claim 2, is characterized in that, described load module comprises:
The first transistor, draws control node on its first utmost point connection is described, and its second utmost point is all connected described signal input part with grid.
4. gate driver circuit according to claim 2, is characterized in that, described reseting module comprises:
Transistor seconds, its first utmost point connects described voltage end, and its grid connects described reset signal end, on its second utmost point connection is described, draws control node.
5. gate driver circuit according to claim 2, is characterized in that, described upper drawing-die piece comprises:
The 3rd transistor, its first utmost point connects described signal output part, on its grid connection is described, draws control node, and its second utmost point connects described the first clock signal input terminal;
Electric capacity, described Capacitance parallel connection is between described the 3rd transistorized grid and described the 3rd transistorized first utmost point.
6. gate driver circuit according to claim 2, is characterized in that, described control module comprises:
The 4th transistor, its grid and second is extremely all connected described second clock signal input part;
The 5th transistor, its grid connects described the 4th transistorized first utmost point, and its second utmost point connects described second clock signal input part;
The 6th transistor, its first utmost point connects described voltage end, on its grid connection is described, draws control node, and its second utmost point connects described the 4th transistorized first utmost point;
The 7th transistor, its first utmost point connects described voltage end, on its grid connection is described, draws control node, and its second utmost point connects described drop-down control node.
7. gate driver circuit according to claim 2, is characterized in that, described drop-down module comprises:
The 8th transistor, its first utmost point connects described voltage end, and its grid connects described drop-down control node, on its second utmost point connection is described, draws control node;
The 9th transistor, its first utmost point connects described voltage end, and its grid connects described drop-down control node, and its second utmost point connects described signal output part.
8. gate driver circuit according to claim 1 and 2, is characterized in that, described precharge unit connect respectively charging signals input end and described first order shift register cell on draw control node.
9. gate driver circuit according to claim 8, is characterized in that, described precharge unit comprises:
The tenth transistor, its first utmost point connect described first order shift register cell on draw control node, its grid is connected described charging signals input end with second utmost point.
10. gate driver circuit according to claim 1, is characterized in that, the signal input part incoming frame start signal of described first order shift register cell; The reset signal end input reset signal of described afterbody shift register cell.
11. 1 kinds of display device, is characterized in that, comprise the gate driver circuit as described in as arbitrary in claim 1-10.
CN201420143721.3U 2014-03-27 2014-03-27 Gate drive circuit and display device CN203746393U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420143721.3U CN203746393U (en) 2014-03-27 2014-03-27 Gate drive circuit and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420143721.3U CN203746393U (en) 2014-03-27 2014-03-27 Gate drive circuit and display device

Publications (1)

Publication Number Publication Date
CN203746393U true CN203746393U (en) 2014-07-30

Family

ID=51346164

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420143721.3U CN203746393U (en) 2014-03-27 2014-03-27 Gate drive circuit and display device

Country Status (1)

Country Link
CN (1) CN203746393U (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943083A (en) * 2014-03-27 2014-07-23 京东方科技集团股份有限公司 Gate drive circuit and method and display device
CN104299590A (en) * 2014-10-30 2015-01-21 京东方科技集团股份有限公司 Shifting register, drive method thereof, gate drive circuit and display device
CN104485080A (en) * 2014-12-31 2015-04-01 深圳市华星光电技术有限公司 GOA (Gate Driver On Array) circuit for liquid crystal display device
CN104966497A (en) * 2015-06-04 2015-10-07 深圳市华星光电技术有限公司 Scanning driving circuit and touch liquid crystal display device
CN105185349A (en) * 2015-11-04 2015-12-23 京东方科技集团股份有限公司 Shifting register, grid electrode integrated driving circuit and display device
CN105280153A (en) * 2015-11-24 2016-01-27 深圳市华星光电技术有限公司 Gate drive circuit and display device thereof
CN105528988A (en) * 2016-02-15 2016-04-27 京东方科技集团股份有限公司 Gate driving circuit, touch control display panel and display device
WO2016115797A1 (en) * 2015-01-21 2016-07-28 京东方科技集团股份有限公司 Touch control circuit, touch control panel and display apparatus
CN106097997A (en) * 2016-06-14 2016-11-09 武汉华星光电技术有限公司 The driving method of In Cell touch-control display panel and drive circuit
CN106251820A (en) * 2016-09-23 2016-12-21 南京华东电子信息科技股份有限公司 Gate driver circuit in cell touching display screen
CN106328074A (en) * 2015-06-25 2017-01-11 群创光电股份有限公司 Image display system and gate driving circuit
WO2017008499A1 (en) * 2015-07-10 2017-01-19 京东方科技集团股份有限公司 Gate drive circuit, touch control display apparatus and touch control display drive method
CN106531048A (en) * 2016-11-29 2017-03-22 京东方科技集团股份有限公司 Shift register, gate drive circuit, display panel and driving method
CN109859699A (en) * 2018-12-19 2019-06-07 惠科股份有限公司 The driving method and display device of display panel

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9690419B2 (en) 2014-03-27 2017-06-27 Boe Technology Group Co., Ltd. Gate driving circuit and a driving method thereof, as well as a display device
CN103943083A (en) * 2014-03-27 2014-07-23 京东方科技集团股份有限公司 Gate drive circuit and method and display device
WO2015143813A1 (en) * 2014-03-27 2015-10-01 京东方科技集团股份有限公司 Gate driving circuit and driving method therefor and display device
CN104299590A (en) * 2014-10-30 2015-01-21 京东方科技集团股份有限公司 Shifting register, drive method thereof, gate drive circuit and display device
CN104485080A (en) * 2014-12-31 2015-04-01 深圳市华星光电技术有限公司 GOA (Gate Driver On Array) circuit for liquid crystal display device
US9703416B2 (en) 2015-01-21 2017-07-11 Boe Technology Group Co., Ltd. Touch circuit, touch panel and display apparatus
WO2016115797A1 (en) * 2015-01-21 2016-07-28 京东方科技集团股份有限公司 Touch control circuit, touch control panel and display apparatus
CN104966497A (en) * 2015-06-04 2015-10-07 深圳市华星光电技术有限公司 Scanning driving circuit and touch liquid crystal display device
CN106328074A (en) * 2015-06-25 2017-01-11 群创光电股份有限公司 Image display system and gate driving circuit
US9953721B2 (en) 2015-07-10 2018-04-24 Boe Technology Group Co., Ltd. Gate driver circuit, touch display device and touch display driving method
WO2017008499A1 (en) * 2015-07-10 2017-01-19 京东方科技集团股份有限公司 Gate drive circuit, touch control display apparatus and touch control display drive method
CN105185349B (en) * 2015-11-04 2018-09-11 京东方科技集团股份有限公司 A kind of shift register, grid integrated drive electronics and display device
CN105185349A (en) * 2015-11-04 2015-12-23 京东方科技集团股份有限公司 Shifting register, grid electrode integrated driving circuit and display device
CN105280153A (en) * 2015-11-24 2016-01-27 深圳市华星光电技术有限公司 Gate drive circuit and display device thereof
CN105528988B (en) * 2016-02-15 2018-09-11 京东方科技集团股份有限公司 A kind of gate driving circuit, touch-control display panel and display device
CN105528988A (en) * 2016-02-15 2016-04-27 京东方科技集团股份有限公司 Gate driving circuit, touch control display panel and display device
WO2017215068A1 (en) * 2016-06-14 2017-12-21 武汉华星光电技术有限公司 Driving method and driving circuit for in-cell touch control display panel
CN106097997A (en) * 2016-06-14 2016-11-09 武汉华星光电技术有限公司 The driving method of In Cell touch-control display panel and drive circuit
CN106251820A (en) * 2016-09-23 2016-12-21 南京华东电子信息科技股份有限公司 Gate driver circuit in cell touching display screen
CN106251820B (en) * 2016-09-23 2018-12-21 南京华东电子信息科技股份有限公司 Gate driving circuit for in-cell touching display screen
CN106531048A (en) * 2016-11-29 2017-03-22 京东方科技集团股份有限公司 Shift register, gate drive circuit, display panel and driving method
US10593286B2 (en) 2016-11-29 2020-03-17 Boe Technology Group Co., Ltd. Shift register, gate driving circuit, display panel and driving method
CN109859699A (en) * 2018-12-19 2019-06-07 惠科股份有限公司 The driving method and display device of display panel

Similar Documents

Publication Publication Date Title
US9734918B2 (en) Shift register and the driving method thereof, gate driving apparatus and display apparatus
US9766741B2 (en) Shift register, gate integrated driving circuit and display screen
CN105185343B (en) Shift register cell and its driving method, gate driving circuit and display device
US9196211B2 (en) Shift register unit, gate driving circuit and display device
CN103698927B (en) touch display device, drive circuit and drive method
US9715860B2 (en) Shift register unit and driving method thereof, gate driving circuit and display apparatus
US10446104B2 (en) Shift register unit, gate line driving device, and driving method
DE102014104631B4 (en) Sliding register unit, display panel and display device
US9632611B1 (en) GOA circuit for in-cell type touch display panel
US9558843B2 (en) Shift register unit, gate driving circuit, and display device comprising the same
CN105427821B (en) Suitable for the GOA circuits of In Cell type touch-control display panels
CN104217763B (en) Shift register cell and its driving method, gate driving circuit, display device
CN103823589B (en) A kind of touch circuit and driving method, touch display unit
CN105390115B (en) Liquid crystal display and GOA circuits
CN104715734B (en) Shift register, gate driving circuit and display device
CN104866141B (en) Touch drive circuit, display device and its driving method
WO2017107285A1 (en) Goa circuit for narrow-bezel liquid crystal display panel
US9269455B2 (en) Shift register unit, gate driving circuit, array substrate and display apparatus
CN103714785B (en) Liquid crystal display
EP2725581B1 (en) Shift register and method for driving the same, gate driving device, display device and electronic product
DE102015121750A1 (en) Control unit, arraysubstrat, touch display apparatus and method for controlling the touch display device
US20160224175A1 (en) Display Device, and Device and Method for Driving the Same
CN103700355B (en) A kind of shift register cell, gate driver circuit and display device
CN102778986B (en) Touching control panel controller and semiconductor devices
CN102750062B (en) A kind of capacitance type in-cell touch panel and display device

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant