CN113284459B

CN113284459B - Scanning driving unit, scanning driving circuit, array substrate and display

Info

Publication number: CN113284459B
Application number: CN202110810263.9A
Authority: CN
Inventors: 颜尧
Original assignee: Shenzhen Royole Technologies Co Ltd
Current assignee: Shenzhen Royole Technologies Co Ltd
Priority date: 2021-07-19
Filing date: 2021-07-19
Publication date: 2021-10-22
Anticipated expiration: 2041-07-19
Also published as: CN113284459A

Abstract

The invention relates to a scanning driving unit, a scanning driving circuit, an array substrate and a display, wherein the scanning driving unit comprises: and the GOA driving unit is electrically connected with a pull-down control unit on a pull-up node and a pull-down node, and the pull-down control unit is used for controlling the pull-up node to be kept in a normally high level state and the pull-down node to be kept in a normally low level state during an AGO stage of fully opening the grid line, so that the GOA driving unit outputs a normally high level signal. The technical scheme provided by the invention solves the problem that the display cannot normally display when the display is awakened in a black screen due to the fact that the GOA driving unit cannot output a high driving signal in the AGO stage in the prior art.

Description

Scanning driving unit, scanning driving circuit, array substrate and display

Technical Field

The invention relates to the technical field of display driving, in particular to a scanning driving unit, a scanning driving circuit, an array substrate and a display.

Background

Among the flat panel display technologies, an Organic Light-Emitting Diode (OLED) display is considered as a third generation display technology following a Liquid Crystal Display (LCD) due to its advantages of lightness, thinness, active Light emission, fast response speed, wide viewing angle, rich colors, high brightness, low power consumption, high and low temperature resistance, etc.

OLEDs are classified into Passive OLEDs (PMOLEDs) and Active OLEDs (AMOLEDs) according to driving methods. The PMOLED is also called a passive matrix OLED, and the AMOLED is also called an active matrix OLED, wherein the PMOLED can only manufacture a small-sized and low-resolution display panel, and the AMOLED can realize a large-sized and high-resolution display panel by integrating a Thin Film Transistor (TFT) and a capacitor in each pixel and maintaining a voltage by the capacitor, and thus is an important point of current research and a development direction of a future display technology. Referring to fig. 1, in an Array substrate AY of an OLED display, each row of pixel lines is controlled by a Gate Driver On Array (Gate Driver On Array) and an EOA Driver (emission control signal Driver) unit. When the GOA driving unit is turned on, outputting a line scanning driving signal, and storing a data signal on a data line into a pixel circuit; when the EOA driving unit is switched on, the OLED outputs a light-emitting control signal, the OLED emits light according to the stored data signal, and the level of the data signal determines the brightness of the light emitted by the OLED.

In practical use, since the OLED display is usually used with a touch screen function, the GOA driving unit needs to implement a function of stopping in a signal to cooperate with the touch screen, such as scanning of the touch screen. In general, after the GOA driving unit stops in signal realization, the display needs to be woken up in a black screen mode, at this time, the GOA driving unit needs to set All Gate lines in the pixel circuit to be in a conducting state within a period of time, and the black voltage is applied to the data lines to clear up the residual level in the pixel capacitor, so that the display effect of the display is good, and the period of time is called as an All Gate On (AGO) stage.

In the AGO stage with the gate lines fully opened, in order to make the display normally display when the black screen is awakened, the GOA driving unit is required to output a normally high line scanning driving signal, and the EOA driving unit is required to output a normally low light emitting control signal.

In the prior art, in order to rapidly and accurately pull down the pull-up node to the low level state in the non-scanning period by the GOA driving unit, prevent a plurality of scanning driving units from outputting scanning signals to a plurality of scanning lines simultaneously, and ensure the accuracy of image display, the pull-down control unit generally transmits a low level reference signal to the pull-up node when the next-stage GOA driving unit outputs scanning driving signals (i.e., when a scanning clock signal of the next-stage GOA driving unit arrives) so as to ensure that the pull-up node is in the low level state. At the stage of gate line full open AGO, the circuit structure of the GOA driving unit cannot ensure that the pull-up node is in a normally high level state, and further the scan output end cannot output a normally high row scan driving signal.

Disclosure of Invention

In order to overcome the problems in the related art at least to a certain extent, the present invention provides a scan driving unit, a scan driving circuit, an array substrate and a display, so as to solve the problem in the prior art that the display cannot normally display when the display is woken up in a black screen because the GOA driving unit cannot output a normally high and/or low driving signal in an AGO stage.

According to a first aspect of embodiments of the present invention, there is provided a scan driving unit including:

and the GOA driving unit is electrically connected with a pull-down control unit on a pull-up node and a pull-down node, and the pull-down control unit is used for controlling the pull-up node to be kept in a normally high level state and the pull-down node to be kept in a normally low level state during an AGO stage of fully opening the grid line, so that the GOA driving unit outputs a normally high level signal.

Preferably, the GOA driving unit, the pull-down control unit thereof, includes:

the first pull-down control unit is used for controlling a pull-up node to be kept in a normal high level state in an AGO stage when the grid line is fully opened;

and the second pull-down control unit is used for controlling the pull-down node to be kept in a normal low level state in the AGO stage of fully opening the grid line.

Preferably, the first pull-down control unit includes: a first transistor;

the grid electrode of the first transistor is connected with the second clock signal input end, the drain electrode of the first transistor is connected with the first clock signal input end, and the source electrode of the first transistor is electrically connected with the pull-up node;

the first clock signal input by the first clock signal input end is a scanning clock signal of the current GOA driving unit; in a normal working stage, a second clock signal input by the second clock signal input end is delayed by a first preset time length compared with the first clock signal; in the AGO stage of the grid line being fully opened, the second clock signal and the first clock signal are both normal high level signals;

the first preset time length is greater than or equal to the pulse time length of the first clock signal.

Preferably, the second clock signal is a scanning clock signal of the next two levels of the GOA driving units;

and the lower two-stage GOA driving units are second-stage GOA driving units which are cascaded behind the current GOA driving unit.

Preferably, the pull-down node includes: odd and even pull-down nodes;

the second pull-down control unit includes:

the odd pull-down control unit is electrically connected with the pull-up node and the odd pull-down node;

the even pull-down control unit is electrically connected with the pull-up node and the even pull-down node;

the odd pull-down control unit and the even pull-down control unit have the same structure and are used for controlling odd pull-down nodes or even pull-down nodes which are respectively and electrically connected to be in a low level state after a scanning clock signal of the current GOA driving unit arrives; and the control circuit is also used for alternately controlling the odd pull-down nodes or the even pull-down nodes which are respectively and electrically connected to be in a high level state after the scanning clock signal disappears in the scanning period of two adjacent frames of images.

Preferably, the odd pull-down control unit includes:

a second transistor having a gate and a drain both connected to an odd variable level power supply and a source connected to the odd pull-down node;

a third transistor, wherein the grid electrode of the third transistor is connected with the pull-up node, the source electrode of the third transistor is connected with the odd pull-down node, and the drain electrode of the third transistor is connected with a low-level reference signal source;

a fourth transistor, a grid of which is connected with the odd pull-down node, a drain of which is connected with the low level reference signal source, and a source of which is connected with the pull-up node;

a fifth transistor, a grid of which is connected with the input end of the starting voltage, a drain of which is connected with the low level reference signal source, and a source of which is connected with the odd pull-down node;

the odd variable level power supply has opposite level states in the scanning periods of two adjacent frames of images in the normal working stage; in the AGO phase, the state is normally low.

Preferably, the even pull-down control unit includes:

a sixth transistor having a gate and a drain both connected to an even variable level power supply, and a source connected to the even pull-down node;

a seventh transistor, a gate of which is connected to the pull-up node, a source of which is connected to the even pull-down node, and a drain of which is connected to a low-level reference signal source;

a gate of the eighth transistor is connected with the even pull-down node, a drain of the eighth transistor is connected with the low-level reference signal source, and a source of the eighth transistor is connected with the pull-up node;

a ninth transistor, a gate of which is connected to the start voltage input terminal, a drain of which is connected to the low level reference signal source, and a source of which is connected to the even pull-down node;

the level state of the even variable level power supply in a normal working stage is opposite to that of the odd variable level power supply; in the AGO phase, the state is normally low.

Preferably, the GOA driving unit, wherein a pull-down output unit is electrically connected to a pull-down node thereof, and includes:

a tenth transistor, a gate of which is connected to the odd pull-down node, a drain of which is connected to a low level reference signal source, and a source of which is connected to a scan output terminal;

and the grid electrode of the eleventh transistor is connected with the even pull-down node, the drain electrode of the eleventh transistor is connected with a low-level reference signal source, and the source electrode of the eleventh transistor is connected with the scanning output end.

Preferably, the GOA driving unit, wherein a pull-up control unit is electrically connected to a pull-up node thereof, and includes:

and a twelfth transistor, wherein a gate and a drain of the twelfth transistor are both connected to the start voltage input terminal, and a source of the twelfth transistor is connected to the pull-up node.

Preferably, the GOA driving unit, on a pull-up node of which a pull-up output unit is electrically connected, includes:

a thirteenth transistor, a gate of which is connected to the pull-up node, a drain of which is connected to the first clock signal input terminal, and a source of which is connected to the scan output terminal;

and a first capacitor connected between the gate and the source of the thirteenth transistor.

According to a second aspect of embodiments of the present invention, there is provided a scan driving circuit including:

a plurality of the above-mentioned scanning driving units.

According to a third aspect of the embodiments of the present invention, there is provided an array substrate, including:

an image display region including a pixel array for performing image display and a non-image display region including the above-described scan driving circuit.

According to a fourth aspect of embodiments of the present invention, there is provided a display including:

the array substrate is provided.

The technical scheme provided by the embodiment of the invention can have the following beneficial effects:

for the GOA driving unit, because the pull-down control unit controls the pull-up node to be kept in a normally high level state during the AGO stage of fully opening the grid line, and the pull-down node is kept in a normally low level state, the pull-down output unit electrically connected with the pull-down node stops working, and the pull-up output unit electrically connected with the pull-up node outputs a normally high line scanning driving signal, the problem that the display cannot normally display due to the fact that the GOA driving unit cannot output the normally high line scanning driving signal during the AGO stage in the prior art is solved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of an OLED display pixel circuit according to the background art;

fig. 2 is a schematic circuit diagram illustrating a GOA driving unit in accordance with an exemplary embodiment;

FIGS. 3A-3B are timing diagrams of circuit signals of the GOA driving unit shown in FIG. 2;

fig. 4 is a schematic view of an array substrate shown according to an exemplary embodiment.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.

As described in the foregoing background, in the AGO stage when the gate line is fully opened, the GOA driving unit is required to output a normally high row scan driving signal in order to make the display normally display when the black screen is woken up.

In order to achieve the aim, the invention provides the following technical scheme:

the improved AGO driving unit is used for constructing a scanning driving unit, a scanning driving circuit, an array substrate and a display on the basis of the improved AGO driving unit; the technical problem solved by the technical scheme is that the display cannot normally display due to the fact that the GOA driving unit cannot output a high line scanning driving signal in the AGO stage.

The implementation of each technical solution will now be described with reference to specific embodiments.

It should be noted that:

1. the transistors used in all embodiments of the present invention are all N-type Thin Film Transistors (TFTs) manufactured by an Indium Gallium Zinc Oxide (IGZO) process. Of course, in other modified embodiments, the tft may also be P-type, and the invention is not limited thereto.

2. The "normal operation phase" mentioned in all embodiments of the present invention refers to a "non-AGO phase", that is, an operation phase of the GOA driving unit or the EOA driving unit in each frame of the image scanning period.

3. The term.. once the signal arrives as mentioned in all embodiments of the present invention means that the term.. once the signal is in an active state; "... signal disappeared," both refer to "the.. signal was during the inactive state. Taking the second clock signal as a pulse signal as an example, the "coming of the second clock signal" refers to a pulse phase of the second clock signal, and the "disappearing of the second clock signal" refers to a non-pulse phase of the second clock signal. If the second clock signal is a normally high level signal, the "second clock signal arrives" refers to the whole high level stage of the second clock signal.

4. All embodiments of the present invention refer to the "high state" as the voltage of the corresponding node is high and sufficient to drive the corresponding transistor in the conducting state, and the "low state" as the voltage of the corresponding node is low and insufficient to maintain the transistor in the conducting state.

5. All embodiments of the present invention refer to the signal source providing the low-level reference voltage, for example, the low-level reference signal source of the GOA driving unit may be defined as VGL/LVGL (the low-level reference voltage provided by VGL/LVGL is the same, but the two low-level reference voltages provide different cell modules, so the names are different).

The implementation of the method will now be described in detail with reference to the first to fourth embodiments:

the first embodiment is as follows:

it should be noted that, in the present embodiment, both the "odd variable level power supply" and the "even variable level power supply" are dc power supplies with variable levels, for example, the "odd variable level power supply" may be a high level power supply in the first frame image scanning period, and output a high level signal; and outputting a low-level signal by a low-level power supply in the second frame image scanning period.

The functions of the odd variable level power supply and the even variable level power supply are the same, and the odd variable level power supply and the even variable level power supply can also be a high level power supply in a first frame image scanning period and output a high level signal; and outputting a low-level signal by a low-level power supply in the second frame image scanning period. However, the odd variable level power supply may be a low level power supply in the first frame image scanning period to output a low level signal; and outputting a high-level signal by a high-level power supply in the second frame image scanning period.

The level states of the odd variable level power supply and the even variable level power supply are changed, and the level state is changed according to the line scanning driving signal of which level state the GOA driving unit outputs. The odd and even are used for distinguishing the variable-level power supply, and no other characteristic meaning exists.

Fig. 2 is a schematic circuit diagram illustrating a scan driving unit according to an exemplary embodiment, the scan driving unit, as shown in fig. 2, including:

GOA drive unit 1, its pull-up node PU and drop-down node electrically connect with the drop-down control unit, the drop-down control unit is used for when the AGO stage that the grid line is opened entirely, controlling pull-up node PU to keep the normal high level state, and the drop-down node keeps the normal low level state, so that GOA drive unit outputs the normal high level signal.

It can be understood that, in the technical scheme provided in this embodiment, for the GOA driving unit, since the pull-down control unit controls the pull-up node PU to be kept in the normally high level state during the AGO stage in which the gate line is fully opened, and the pull-down node is kept in the normally low level state, so that the pull-down output unit electrically connected to the pull-down node stops working, and the pull-up output unit electrically connected to the pull-up node outputs a normally high line scanning driving signal, thereby solving the problem that the display cannot normally display because the GOA driving unit cannot output the normally high line scanning driving signal during the AGO stage in the prior art.

It should be noted that, in the technical solution provided in this embodiment, only the GOA driving unit in the scanning driving unit is improved, and in a specific practice, if the technical solution provided in this embodiment is applied to the scanning driving of the OLED display, the improved GOA driving unit in this embodiment can be used in cooperation with the EOA driving unit supporting the AGO function in the prior art, so as to ensure that the OLED display can normally display when the black screen is woken up.

In a specific practice, the pull-down control unit of the GOA driving unit 1 can be split into:

a first pull-down control unit 10, configured to control the pull-up node PU to remain in a normally high level state at an AGO stage when the gate line is fully opened;

and a second pull-down control unit 11, configured to control the pull-down node to remain in a normally low level state during an AGO stage when the gate line is fully opened.

In particular practice, the implementation of the first pull-down control unit 10 is various, and the schematic circuit diagram shown in fig. 4 shows one implementation.

Referring to fig. 2, the first pull-down control unit 10 includes: a first transistor M15;

the grid electrode of the first transistor M15 is connected with the second clock signal input end, the drain electrode is connected with the first clock signal input end CLKn (n is more than or equal to 1), and the source electrode is electrically connected with the pull-up node PU;

the first clock signal CKn input by the first clock signal input terminal CLKn is a scanning clock signal of the current GOA driving unit; in the normal working stage, the second clock signal input by the second clock signal input end is delayed by a first preset time length compared with the first clock signal CKn; in the AGO stage of the grid line being fully opened, the second clock signal and the first clock signal CKn are both normal high level signals;

the first preset time length is greater than or equal to the pulse time length of the first clock signal CKn.

It can be understood that, since the second clock signal CKn and the first clock signal CKn are both at the normal high level during the AGO stage when the gate line is fully opened, the first transistor M15 is turned on, and the first transistor M15 transmits the high level of the first clock signal CKn to the pull-up node, so as to control the pull-up node PU to keep at the normal high level.

The reason why the embodiment defines that the second clock signal is delayed by the first preset time length compared with the first clock signal CKn in the normal working stage is to control the first pull-down control unit 10 not to work after the first clock signal CKn (the scanning clock signal of the current GOA driving unit) arrives; after the first clock signal CKn disappears, the first pull-down control unit 10 is controlled to operate, and the low level of the first clock signal CKn is transmitted to the pull-up node PU, so as to control the pull-up node PU to maintain the low level state after the first clock signal CKn disappears.

As can be seen from FIG. 1 in the background art, there are a plurality of GOA driving units GOA N (N ≧ 1) on the array substrate AY of the display. In a specific practice, the GOA driving units corresponding to even rows of scan lines are cascaded with each other, and the GOA driving units corresponding to odd rows of scan lines are cascaded with each other.

Referring to fig. 3A, in the mutually cascaded GOA driving units, the scanning clock signals of two adjacent stages of GOA driving units are delayed by one pulse duration. In a specific implementation, the second clock signal may be provided by an external clock unit, or may be provided by the scan clock signal CKn +2 of the next GOA driving unit GOA N +2 cascaded after the current GOA driving unit GOA N, or may be provided by the scan clock signal CKn +4 of the next two GOA driving units GOA N +4 cascaded after the current GOA driving unit GOA N.

If the second clock signal is selected to be provided by the scanning clock signal CKn +2 of the next-stage GOA driving unit GOA N +2, in a normal working stage, due to the time delay existing in both arrival and disappearance of the first clock signal CKn, the first clock signal CKn may not completely disappear after the second clock signal arrives, and at this time, the first clock signal CKn is transmitted to the pull-up node PU, so that the pull-up node PU cannot be ensured to be in a low level state, and the falling speed of the falling edge of the line scanning driving signal output by the scanning output terminal Gout N is very slow, and the driving requirement of the system cannot be met.

Therefore, it is preferable to select the second clock signal provided by the scan clock signal CKn +4 of the next two stages of the GOA driving unit GOA N +4 to ensure that the pull-up node PU is pulled down to a low state after the first clock signal CKn disappears.

Therefore, preferably, the first preset time duration is a pulse duration of two first clock signals CKn.

Therefore, the second clock signal is the scanning clock signal CKn +4 of the next two levels of the GOA driving unit GOA N + 4;

the second-stage GOA driving unit is a second-stage GOA driving unit GOA N +4 cascaded after the current GOA driving unit GOA N.

It can be understood that, the implementation manner of the first pull-down control unit 10 shown in fig. 2 only needs to change the connection signal of the source of the first transistor M15 on the basis of the existing GOA driving unit, and other circuit parts do not need to be changed, so that the structure is simple, the operation is easy, the user experience is good, and the satisfaction is high.

In specific practice, the implementation of the second pull-down control unit 11 is various, and the circuit schematic shown in fig. 4 shows one implementation.

Referring to fig. 2, the pull-down node includes: odd pull-down node PD Odd and Even pull-down node PD Even;

the second pull-down control unit 11 includes:

the Odd pull-down control unit is electrically connected with the pull-up node PU and the Odd pull-down node PD Odd;

the Even pull-down control unit is electrically connected with the pull-up node PU and the Even pull-down node PD Even;

the odd pull-down control unit and the even pull-down control unit have the same structure and are used for controlling odd pull-down nodes or even pull-down nodes which are respectively and electrically connected to be in a low level state after a scanning clock signal of the current GOA driving unit arrives; and the controller is also used for alternately controlling the odd pull-down nodes or the even pull-down nodes which are respectively and electrically connected to be in a high level state after the scanning clock signal disappears for a pulse duration in the scanning period of two adjacent frames of images.

The odd pull-down control unit includes:

a second transistor M2 having a gate and a drain both connected to an Odd variable level power supply VDD Odd, and a source connected to the Odd pull-down node PD Odd;

a third transistor M7, having a gate connected to the pull-up node PU, a source connected to the Odd pull-down node PD Odd, and a drain connected to a low level reference signal source LVGL;

a fourth transistor M4, having a gate connected to the Odd pull-down node PD Odd, a drain connected to the low level reference signal source LVGL, and a source connected to the pull-up node PU;

a fifth transistor M8, having a gate connected to the start voltage input terminal, a drain connected to the low level reference signal source LVGL, and a source connected to the Odd pull-down node PD Odd;

the Odd variable level power supply VDD Odd, during the normal operation phase, has opposite level states in two adjacent image scanning periods (for example, if the Odd variable level power supply VDD Odd is in a high level state in the current image scanning period, the Odd variable level power supply VDD Odd is in a low level state in the next frame); in the AGO phase, the state is normally low.

The even pull-down control unit includes:

a sixth transistor M2' having a gate and a drain both connected to an Even variable level power supply VDD Even, and a source connected to the Even pull-down node PD Even;

a seventh transistor M7', a gate of which is connected to the pull-up node PU, a source of which is connected to the Even pull-down node PD Even, and a drain of which is connected to a low-level reference signal source LVGL;

an eighth transistor M4', a gate of which is connected to the Even pull-down node PD Even, a drain of which is connected to the low level reference signal source LVGL, and a source of which is connected to the pull-up node PU;

a ninth transistor M8', a gate of which is connected to the start voltage input terminal, a drain of which is connected to the low level reference signal source LVGL, and a source of which is connected to the Even pull-down node PD Even;

the level state of the Even variable level power supply VDD Even in the normal operation phase is opposite to the level state of the Odd variable level power supply VDD Odd (for example, if the Odd variable level power supply VDD Odd is in the high level state, VDD Even is in the low level state, and if the Odd variable level power supply VDD Odd is in the low level state, VDD Even is in the high level state); in the AGO phase, the state is normally low.

Referring to fig. 2, in particular practice, a reset transistor M20 may also be provided in the pull-down control unit. The gate of the reset transistor M20 is controlled by a reset signal TRST, and when the reset signal TRST arrives, the reset transistor M20 transmits a low-level reference signal to the pull-up node PU, so that the pull-up node PU maintains a low-level state.

GOA drive unit 1, the last electric connection of its drop-down node has drop-down output unit 12, includes:

a tenth transistor M14, having a gate connected to the Odd pull-down node PD Odd, a drain connected to a low level reference signal source VGL, and a source connected to the scan output terminal Gout N;

the eleventh transistor M14' has a gate connected to the Even pull-down node PD Even, a drain connected to a low level reference signal source VGL, and a source connected to the scan output terminal Gout N.

It can be understood that, in the technical solution provided in this embodiment, after the scan clock signal (including the pulse scan clock signal in the normal operation phase and the normally high level scan clock signal in the AGO phase) of the current GOA driving unit arrives, the Odd pull-down control unit and the Even pull-down control unit control the Odd pull-down node PD Odd or the Even pull-down node PD Even, which are electrically connected with each other, to be in the low level state, so as to ensure that the pull-down output unit is turned off without affecting the level state of the row scan driving signal output by the scan output terminal.

In two adjacent frame image scanning periods, for example, in a first frame image scanning period, when the scanning clock signal disappears for a pulse duration, because the Odd variable level power supply VDD Odd is in a normally high level state, the transistor M2 is turned on, the transistor M2 controls the Odd pull-down node PD Odd to be in a high level state, the transistor M14 of the pull-down output unit is turned on, and the row scanning driving signal output by the scanning output terminal is further pulled down, so that the stability of the circuit is ensured;

in the second frame image scanning period, after the scanning clock signal disappears for a pulse duration, because the Even variable level power supply VDD Even is in a normal high level state, the transistor M2 ' is turned on, the transistor M2 ' controls the Even pull-down node PD Even to be in a high level state, the transistor M14 ' of the pull-down output unit is turned on, and the line scanning driving signal output by the scanning output terminal is further pulled down, thereby ensuring the stability of the circuit.

It can be understood that the odd pull-down control unit and the even pull-down control unit are arranged to make the tenth transistor M14 and the eleventh transistor M14 'of the pull-down output unit turn on alternately, so as to prevent the transistor M14 or the transistor M14' from being under the pressure of high gate potential for a long time and performance failure.

For example, the Odd pull-down node PD Odd is controlled to be in the high state by the conduction of the transistor M2 in the first frame image scanning period, so as to control the transistor M14 to be turned on; in the second frame image scanning period, the Even pull-down node PD Even is controlled to be in a high state by the conduction of the transistor M2 ', and the transistor M14' is further controlled to be turned on.

In addition, the Odd variable level power supply VDD Odd is in a low level state in the next frame image scanning period if it is in a high level state in the current frame image scanning period in the normal working stage; the Even variable level power supply PD Even has a level state opposite to that of the Odd variable level power supply VDD Odd during the normal operation period. The purpose of this design is also to ensure that the Odd pull-down control unit and the Even pull-down control unit alternately control the Odd pull-down node PD Odd or the Even pull-down node PD Even electrically connected to each other to be in a high state in two adjacent frame image scanning periods.

The reason why the Odd variable level power supply VDD Odd outputs the normally high level signal during the first frame image scanning period in the normal operation stage and outputs the normally low level signal during the AGO stage in which the gate line is fully opened is to ensure that the Odd pull-down node PD Odd does not have the voltage division and is in the low level state during the AGO stage in which the gate line is fully opened, so as to better maintain the off state of M14 and further ensure that Gout 1 outputs the normally high line scanning driving signal.

The reason that the Even variable power supply VDD Even outputs a normally high level signal in the second frame image scanning period of the normal operation phase and outputs a normally low level signal in the AGO phase of the fully-opened gate line is to ensure that the Even pull-down node PD Even has no voltage division and is in a low level state in the AGO phase of the fully-opened gate line, so that the off state of M14' is better maintained, and it is further ensured that Gout 1 outputs a normally high row scanning driving signal.

GOA drive unit, pull up on its node PU and electrically connect with and pull up control unit 13, include:

a twelfth transistor M1 has a gate and a drain connected to the Input of the start voltage, and a source connected to the pull-up node PU.

GOA drive unit, it pulls up still electric connection on node PU has pull-up output unit 14, includes:

a thirteenth transistor M3 having a gate connected to the pull-up node PU, a drain connected to the first clock signal input terminal CLKn, and a source connected to the scan output terminal Gout N;

and a first capacitor C1 connected between the gate and the source of the thirteenth transistor M3.

It should be noted that the enable voltage Input terminal Input is a driving enable terminal EN (see fig. 4) of the GOA driving unit, and the enable voltage Input terminal Input is configured to receive an enable voltage to trigger the current GOA driving unit to be in an operating state.

It can be understood that, based on the improved GOA driving unit, the circuit timing signal does not need to be changed during the normal operation stage, and the circuit timing signal is independently adjusted at the stage of the gate line full open AGO, so that the normally high row scanning driving signal can be output.

Referring to the schematic circuit diagram shown in fig. 2 and the circuit signal timing diagrams shown in fig. 3A to 3B, taking the first GOA driving unit GOA1 on the left side of the array substrate as an example, the specific operation principle of the scan driving circuit provided in this embodiment is explained as follows:

1. in the normal working stage:

all clock signals CK1, CK3, CK5 are identical in amplitude and frequency, differing only in pulse start time. CK1 is a scanning clock signal of GOA1, and the pulse duration is 2H; CK3 is the scanning clock signal of GOA3, 2H later than CK 1; CK5 is the scan clock signal of GOA5, delayed by 2H from CK 3. The H is a unit time length, for example, 1H may be 8 microseconds (μ s), and of course, 1H may be set according to the actual requirement of image display, which is not limited thereto.

For the first GOA driving unit GOA1 on the left side of the array substrate, with its start voltage STV _ L, in the first frame image scanning period:

in a time period t1 after the starting voltage arrives, the transistor M1 is turned on, the transistor M1 transmits the starting voltage to the pull-up node PU so as to control the pull-up node PU to be in a high level state, and meanwhile, after the capacitor C1 is charged fully, the high level state of the pull-up node PU is maintained; at this time, the transistor M3 is turned on, but the scan output terminal Gout 1 has no output signal because the scan clock signal CK1 of the driving unit GOA1 does not arrive.

In a time period t1, the transistors M8 and M8' of the second pull-down control unit are turned on, and both the Odd pull-down node PD Odd and the Even pull-down node PD Even are in a low state; the transistors M2 and M7 are turned on to form an inverter, and further maintain the low state of the Odd pull-down node PD Odd; the transistor M7' is turned on to further maintain the low state of the Even pull-down node PD Even; transistors M14 and M14' are off and the pull-down output unit is inactive.

During the time period t1, the driving unit GOA1 is in an activated state.

In a time period t2 after the scan clock signal CK1 arrives, due to the energy storage effect of the first capacitor C1, the high level state of the pull-up node PU is continuously maintained, the transistor M3 keeps the on state, the transistor M3 transmits the high level state of the scan clock signal CK1 to the scan output terminal Gout 1, and the scan output terminal Gout 1 outputs a row scan driving signal in the high level state;

in a period t2, the transistors M8 and M8' are turned off, the transistors M2 and M7 are turned on, and the transistors M2 and M7 constitute an inverter maintaining a low state of the Odd pull-down node PD Odd; the transistor M7' is turned on to maintain the low level state of the Even pull-down node PD Even; transistors M14 and M14' are off and the pull-down output unit is inactive.

In a time period t3 after the scan clock signal CK1 disappears, due to the energy storage effect of the first capacitor C1, the high level state of the pull-up node PU is continuously maintained, the transistor M3 is kept in the on state, the transistor M3 transmits the low level state of the scan clock signal CK1 to the scan output terminal Gout 1, and the row scan driving signal in the high level state output in the time period t2 is pulled down to the low level state.

In a time period t3, the transistors M2 and M7 in the second pull-down control unit are turned on to constitute an inverter, and further maintain the low state of the Odd pull-down node PD Odd; the transistor M7' is turned on, and the low level state of the Even pull-down node PD Even is continuously maintained; transistors M14 and M14' are off and the pull-down output unit is inactive.

In a time period t4 after the scan clock signal CK5 arrives, the transistor M15 is turned on, the transistor M15 transmits the low level state of the scan clock signal CK1 to the pull-up node PU, and pulls down the pull-up node PU to the low level state, so that the transistor M3 is ensured to be turned off until the next pulse signal of the start voltage arrives.

In the second frame image scanning period, the operation principle of the driving unit GOA1 is the same as that in the first frame image scanning period, except that:

1. in the first frame image scanning period, when the scanning clock signal CK1 arrives, the Odd variable level power supply VDD Odd is in a high level state, and an inverter is formed by the transistors M2 and M7 to control the Odd pull-down node PD Odd to be in a low level state; the Even pull-down node PD Even is controlled to be in a low level state by the conduction of the transistor M7'; when the scan clock signal CK1 disappears for a pulse duration (after the scan clock signal CK5 corresponding to fig. 3A and 3B arrives), because the Odd variable level power supply VDD Odd is in a normally high level state, the transistor M2 is turned on, the transistor M2 controls the Odd pull-down node PD Odd to be in a high level state, the transistor M14 of the pull-down output unit is turned on, and the line scan driving signal output by the scan output terminal is further pulled down, so that the stability of the circuit is ensured;

2. in the second frame image scanning period, when the scanning clock signal CK1 comes, the Even variable level power supply VDD Even is in a high level state, the transistors M2 'and M7' form an inverter, and the Even pull-down node PD Even is controlled to be in a low level state; the transistor M7 is turned on, so that the Odd pull-down node PD Odd is controlled to be in a low level state; when the scanning clock signal CK1 disappears for a pulse duration, because the Even variable level power supply VDD Even is in a normally high level state, the transistor M2 ' is turned on, the transistor M2 ' controls the Even pull-down node PD Even to be in a high level state, the transistor M14 ' of the pull-down output unit is turned on, the row scanning driving signal output by the scanning output terminal is further pulled down, and the stability of the circuit is ensured.

Based on this, the operation principle of the driving unit GOA1 in the second frame image scanning period is not described in detail.

2. In the AGO stage of the grid line being fully opened:

the start voltage STV _ L, the clock signals CK1, CK3, and CK5 are all normal high level signals, the transistor M15 is in a conducting state, the pull-up node PU is maintained in a normal high level state, the transistor M3 is conducting, and the scan output end outputs a normal high row scan driving signal;

at this time, the Odd variable level power supply VDD Odd and the Even variable level power supply VDD Even output a normally low level signal, the transistors M2 and M2 'are turned off, the transistors M8 and M8' are turned on, the Odd pull-down node PD Odd and the Even pull-down node PD Even are maintained in a normally low state, and the pull-down output unit does not operate.

It should be noted that, no matter in the normal operation phase or in the AGO phase with the gate lines fully opened, the operation process of the other GOA driving units is the same as that of the GOA1, and the difference is only that:

1. for the GOA driving unit on the left side of the array substrate AY, except that the driving voltage of the GOA1 is provided by STV _ L, the start voltages of other GOA driving units are provided by the line scanning driving signal output by the GOA-2 of the previous stage of the GOA driving unit GOAN, for example, the start voltage of the GOA3 is provided by the line scanning driving signal output by the GOA 1;

2. for the GOA driving unit on the right side of the array substrate AY, except that the driving voltage of the GOA2 is provided by the STV _ R, the start voltages of the other GOA driving units are provided by the row scan driving signal output by the GOA-2 that is the previous stage of the GOA driving unit GOAN, for example, the start voltage of the GOA4 is provided by the row scan driving signal output by the GOA 2.

Based on this, the working principle of other GOA driving units in the normal working stage and the AGO stage with the gate line fully opened is not repeated.

In the scan driving unit provided in this embodiment, the input signal of the transistor M15 of the pull-down control unit of the AGO driving unit is provided by the low-level reference signal source, and is instead provided by the scan clock signal CLKn, so that the transistor M15 is always kept in the on state during the AGO stage, the high-level state of CLKn is transmitted to the pull-up node PU through the transistor M15, the normally high state of the pull-up node PU is further maintained, and the scan output terminal outputs the normally high row scan driving signal.

In a specific practice, if the technical scheme provided by this embodiment is applied to scan driving of an OLED display, the OLED display can be used in cooperation with an EOA driving unit supporting an AGO function in the prior art, so that the OLED display can normally display when the OLED display is awakened in a black screen.

Example two:

a scan driving circuit according to an exemplary embodiment is shown, including:

a plurality of the above-mentioned scanning drive units;

the GOA driving units of the plurality of scan driving units are cascaded with each other.

It can be understood that, in the technical scheme provided in this embodiment, since the improved scan driving unit can output a normally high line scan driving signal at the AGO stage when the gate line is fully opened, if the technical scheme provided in this embodiment is applied to the scan driving of the OLED display, the technical scheme can be used in cooperation with the EOA driving unit supporting the AGO function in the prior art, so as to ensure that the display can normally display when the display is awakened in the black screen.

Example three:

referring to fig. 4, an array substrate AY according to an exemplary embodiment is shown, including:

the image display area 200 and the non-image display area 100, the image display area 200 includes a pixel array for performing image display, and the non-image display area 100 includes the above-described scan driving circuit.

It can be understood that, in the technical scheme provided in this embodiment, since the improved scan driving circuit can output a normally high line scan driving signal at the AGO stage when the gate line is fully opened, if the technical scheme provided in this embodiment is applied to the scan driving of the OLED display, the technical scheme can be used in cooperation with the EOA driving unit supporting the AGO function in the prior art, so as to ensure that the display can normally display when the display is awakened in the black screen.

Example four:

a display is shown according to an exemplary embodiment, comprising:

the array substrate is provided.

It should be noted that the display includes, but is not limited to: LCD displays, LED displays, OLED displays, and the like, which may be installed in various electronic devices, for example, televisions, tablet computers, notebook computers, smart refrigerators, smart phones, and the like.

It can be understood that, in the technical scheme provided in this embodiment, since the improved array substrate can output a normally high line scanning driving signal at the AGO stage when the gate lines are fully opened, if the technical scheme provided in this embodiment is applied to the scanning driving of the OLED display, the technical scheme can be used in cooperation with the EOA driving unit supporting the AGO function in the prior art, so as to ensure that the display can normally display when the display is awakened in the black screen.

It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.

It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A scan drive unit, comprising:

the GOA driving unit is electrically connected with a pull-down control unit on a pull-up node and a pull-down node, the pull-down control unit is used for controlling the pull-up node to be kept in a normally high level state and the pull-down node to be kept in a normally low level state when a grid line is in an AGO stage of full opening, so that the GOA driving unit outputs a normally high level signal;

the GOA driving unit, the pull-down control unit thereof comprises:

the second pull-down control unit is used for controlling a pull-down node to be kept in a normal low level state in an AGO stage when the grid line is fully opened;

the first pull-down control unit includes: a first transistor;

2. The scan drive unit of claim 1,

the second clock signal is a scanning clock signal of a next two-stage GOA driving unit;

3. The scan drive unit of claim 1,

the pull-down node includes: odd and even pull-down nodes;

the second pull-down control unit includes:

the odd pull-down control unit and the even pull-down control unit have the same structure and are used for controlling odd pull-down nodes or even pull-down nodes which are respectively and electrically connected to be in a low level state after a scanning clock signal of the current GOA driving unit arrives;

and the controller is also used for alternately controlling the odd pull-down nodes or the even pull-down nodes which are respectively and electrically connected to be in a high level state after the scanning clock signal disappears for a pulse duration in the scanning period of two adjacent frames of images.

4. The scan driving unit of claim 3, wherein the odd pull-down control unit comprises:

5. The scan driving unit of claim 4, wherein the even pull-down control unit comprises:

6. The scan driving unit according to claim 3, wherein the GOA driving unit has a pull-down output unit electrically connected to a pull-down node thereof, and comprises:

7. The scan driving unit according to claim 1, wherein the GOA driving unit has a pull-up control unit electrically connected to a pull-up node thereof, comprising:

8. The scan driving unit according to claim 7, wherein the GOA driving unit further electrically connects to a pull-up output unit at a pull-up node thereof, and comprises:

9. A scan driving circuit, comprising:

a plurality of scan drive units as claimed in any one of claims 1 to 8.

10. An array substrate, comprising:

an image display region including a pixel array for performing image display and a non-image display region including the scan drive circuit according to claim 9.

11. A display, comprising:

the array substrate of claim 10.