CN204406959U - Shift register cell, shift-register circuit and display device - Google Patents
Shift register cell, shift-register circuit and display device Download PDFInfo
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- CN204406959U CN204406959U CN201420851062.9U CN201420851062U CN204406959U CN 204406959 U CN204406959 U CN 204406959U CN 201420851062 U CN201420851062 U CN 201420851062U CN 204406959 U CN204406959 U CN 204406959U
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Abstract
The utility model provides a kind of shift register cell, a kind of shift-register circuit and a kind of display device.This shift register cell comprises: charging module, and one end is connected with input end, and the other end is connected with pull-up node, produces pull-up signal; Pull-up module, one end is connected with pull-up node, and the other end is connected with the first clock signal terminal, charges to output terminal; First drop-down control module, one end is connected with second clock signal end, and the other end is connected with low-voltage end, produces drop-down control signal; Second drop-down control module, one end is connected with drop-down Controlling vertex, and the other end is connected with pull-up node, produces pulldown signal; First drop-down module, one end is connected with the first reset terminal, and the other end is connected with output terminal, discharges to output terminal; Second drop-down module, one end is connected with pull-down node, and the other end is connected with output terminal, discharges to output terminal; And reseting module, one end is connected with the second reset terminal, and the other end is connected with pull-up node, to pull-up node reset.
Description
Technical field
The utility model relates to display technique field, more specifically, relates to shift register cell, shift-register circuit and display device.
Background technology
Flat-panel monitor, because it is ultra-thin and energy-conservation and vigorously promoted the use.Shift register will be used in most flat-panel monitor, by the shift register that GOA (Gate Drive on Array) method realizes, namely raster data model IC can be saved, can also reduce by one production process, therefore not only reduce the manufacturing cost of flat-panel monitor, also shorten the manufacturing cycle to a certain extent.
Therefore GOA technology is widely used in flat-panel monitor manufacture in recent years.The power consumption of GOA self is larger relative to normal gate drive IC, in order to the power consumption reducing GOA unit itself often adopts clock (CLK) signal (clock signal number is the multiple of 2) of 4 or more, reduce the frequency of clock signal simultaneously, thus reach the object reducing power consumption.Adopt high level time in this design each clock period be the n of scanning one line time doubly (n be more than or equal to 2 integer), have overlapping part between the clock signal that two sequential are adjacent.As shown in Figure 1, the stage that the actual duration of charging that each grid is capable identifies for 2H.Based on this overlapping part, can open in advance each grid is capable, when treating often to go real writing pixel voltage, this grid is capable just to be opened completely, thus reduces the capable resistance of grid own, signal rising time (Tr) caused by capacitive load to the impact in duration of charging.Considering the capable stray capacitance of self of grid and the signal delay of resistance generation, is the correctness of the voltage ensureing each pixel write in display screen real work, for each pixel, often needs data-signal after signal is closed just to close.As shown in Figure 2, the signal negative edge time (Tf) that mistiming depends primarily on the capable resistance of grid own, capacitive load causes that signal (Vgate) and data-signal (Vdata) are closed, namely Tf is larger, effective duration of charging (Teff) of pixel will be fewer, as Fig. 2, shown Teff < 1H.
Fig. 3 shows the physical circuit figure of the shift register cell that a kind of conventional GOA method for designing realizes, and Fig. 4 shows the block diagram of the interconnected relationship of the shift register cell in multiple Fig. 3, and wherein, the sequential of each clock signal as shown in Figure 1.In figure 3, transistor M3 and M4 is responsible for carrying out charging and discharging to output terminal (OUTPUT) respectively.When the grid of transistor M3 be high level and clock signal (CLK) also non-high level time, output terminal exports high level signal; After completing a line gated sweep, CLK becomes low level, and reset signal (RESET) becomes high level, and now transistor M2 and M4 opens, and discharges to the grid of transistor M3 and output terminal.Under such transistor M3 and M4 is in the state of closing and open respectively, transistor M4 is therefore only had to discharge to output terminal.As shown in Figure 4, the output of the n-th register cell, except driving n-th line gate line, also resets to the n-th-2 register cells, and as the input of the n-th+2 register cells.Like this, the register circuit realized by traditional GOA method for designing, can only reduce Tr, thus reduces Tr to the impact in pixel effective duration of charging.
For the product of high resolving power or high refreshing frequency, the duration of charging of pixel is inherently little, and therefore the impact of Tf on effective duration of charging of pixel becomes more obvious.
Utility model content
The utility model provides a kind of shift register cell, a kind of shift-register circuit and a kind of display device, in order to solve the problem causing pixel effective duration of charging (Teff) short due to negative edge time (Tf) length of gate drive signal in prior art.
An aspect of the present utility model provides a kind of shift register cell, comprising:
Charging module, one end is connected with the input end of described shift register cell, and the other end is connected with pull-up node, for receiving input signal, and is drawn high to produce pull-up signal by the current potential of pull-up node under the control of input signal;
Pull-up module, one end is connected with pull-up node, the other end is connected with the first clock signal terminal of described shift register cell, for receiving described pull-up signal and the first clock signal, and the output terminal in the pull-up stage to described shift register cell under the control of pull-up signal and the first clock signal charges;
First drop-down control module, one end is connected with the second clock signal end of described shift register cell, the other end is connected with the low-voltage end of described shift register cell, for receiving second clock signal, and produce drop-down control signal at drop-down Controlling vertex place under the control of second clock signal;
Second drop-down control module, one end is connected with drop-down Controlling vertex, and the other end is connected with pull-up node, for receiving drop-down control signal, and under the control of drop-down control signal, produces pulldown signal at pull-down node place;
First drop-down module, one end is connected with the first reset terminal of described shift register cell, the other end is connected with the output terminal of described shift register cell, for receiving the first reset signal and discharging to the output terminal of described shift register cell under the control of the first reset signal in the first drop-down stage;
Second drop-down module, one end is connected with pull-down node, and the other end is connected with the output terminal of described shift register, for receiving pulldown signal, and discharges at the second output terminal of drop-down stage to described shift register cell under the control of pulldown signal; And
Reseting module, one end is connected with the second reset terminal of described shift register cell, and the other end is connected with described pull-up node, for receiving the second reset signal, and resets to described pull-up node under the control of the second reset signal;
Wherein, described pull-up module is discharged at described first output terminal of drop-down stage to described shift register cell.
Preferably, described charging module comprises the first transistor, and the grid of described the first transistor is connected with described input end with the first pole, and the second pole is connected with described pull-up node.
Preferably, described reseting module comprises transistor seconds, and the grid of described transistor seconds is connected with described second reset terminal, and the first pole is connected with described pull-up node, and the second pole is connected with low-voltage end.
Preferably, described pull-up module comprises third transistor, and the grid of described third transistor is connected with described pull-up node, and the first pole is connected with described first clock signal terminal, and the second pole is connected with described output terminal.
Preferably, described first drop-down module comprises the 4th transistor, and the grid of described 4th transistor is connected with described first reset terminal, and the first pole is connected with described output terminal, and the second pole is connected with described low-voltage end.
Preferably, described second drop-down control module comprises the 5th transistor and the 6th transistor, and the grid of described 5th transistor is connected with described drop-down Controlling vertex, and the first pole is connected with described second clock signal end, and the second pole is connected with described pull-down node; The grid of described 6th transistor is connected with the grid of described third transistor, and the first pole is connected with described pull-down node, and the second pole is connected with described low-voltage end.
Preferably, described first drop-down control module comprises the 7th transistor and the 8th transistor, and the grid of described 7th transistor is connected with the grid of described third transistor, and the first pole is connected with described drop-down Controlling vertex, and the second pole is connected with described low-voltage end; The grid of described 8th transistor is connected with described second clock signal with the first pole, and the second pole is connected with described drop-down Controlling vertex.
Preferably, described second drop-down module comprises the 9th transistor, the tenth transistor and the 11 transistor, and the grid of described 9th transistor is connected with described pull-down node, and the first pole is connected with described pull-up node, and the second pole is connected with described low-voltage end; The grid of described tenth transistor is connected with described pull-down node, and the first pole is connected with described output terminal, and the second pole is connected with described low-voltage end; The grid of described 11 transistor is connected with described second clock signal, and the first pole is connected with described output terminal, and the second pole is connected with described low-voltage end.
Preferably, described pull-up module and described first drop-down module were discharged to the output terminal of described shift register cell in the first drop-down stage simultaneously.
Preferably, the size of described third transistor and described 4th transistor is greater than the size of other transistors.
Preferably, described second reset signal postpones 1/2 of the actual duration of charging of a gate line relative to described first reset signal.
Preferably, the phase place of described first clock signal is contrary with the phase place of second clock signal.
Another aspect of the present utility model provides a kind of shift-register circuit, comprise the above-mentioned shift register cell of m cascade, the output terminal of each shift register cell connects with corresponding gate line, except the first two shift register cell with except latter two shift register cell, the output terminal of the n-th shift register cell also resets to the n-th-2 shift register cells and as the input of the n-th+2 shift register cells
Wherein each shift register cell comprises two reset terminals, and a reset terminal of the n-th shift register cell is connected with the output terminal of the n-th+2 shift register cells, and another reset terminal is connected with the output terminal of n+3 shift register cell, and
N is more than or equal to 3 and is less than or equal to m-3.
Another aspect of the present utility model provides a kind of display device, comprises described shift-register circuit.
Shift register cell of the present utility model by reducing the negative edge time Tf of gate drive signal, thus adds the effective duration of charging Teff of pixel, and ensures display frame quality.Particularly, discharge (namely by the output of the first drop-down stage to shift register cell that coexists of pull-up module and the first drop-down module one, drag down the level of shift register output end), further reduce the negative edge time that shift register cell exports, thus improve discharging efficiency.In addition, only work different in the pull-up stage from pull-up module in traditional GOA method for designing, the output that pull-up module in the utility model can not only be used in the pull-up stage to shift register is charged, and can be used in the output of drop-down stage to shift register cell and discharge, namely same module plays different effects in different phase, thus simplifies circuit structure while guarantee improves discharging efficiency.
Accompanying drawing explanation
According to following detailed description by reference to the accompanying drawings, the above and other aspect of multiple embodiment of the present disclosure, feature and advantage will be clearer, in the accompanying drawings:
Fig. 1 shows the working timing figure of the shift-register circuit adopting traditional GOA design;
Fig. 2 is the graph of a relation in the effective duration of charging adopting actual duration of charging that the grid of traditional GOA design is capable and pixel;
Fig. 3 shows the physical circuit figure of the shift register cell adopting traditional GOA design;
Fig. 4 shows the block diagram of the interconnected relationship of the shift register cell in multiple Fig. 3;
Fig. 5 shows the block diagram of the shift register cell according to the utility model embodiment;
Fig. 6 shows the physical circuit figure of the shift register cell of the Fig. 5 according to the utility model embodiment;
Fig. 7 is the driving method process flow diagram of the shift register cell according to the utility model embodiment; And
Fig. 8 shows the block diagram of the shift-register circuit of the shift register cell cascade in multiple Fig. 5.
Embodiment
The utility model embodiment provides a kind of shift register cell, a kind of shift-register circuit and a kind of display device, the negative edge time achieving shift register cell output is short, the shift register cell that effective duration of charging of pixel is long, and the simple and shift-register circuit that power consumption is lower of structure.
Below in conjunction with the drawings and specific embodiments, specific implementation of the present utility model is described in detail.
The block diagram of the shift register cell 500 according to the utility model embodiment is showed with reference to Fig. 5, Fig. 5.Shift register cell 500 comprises charging module 501, pull-up module 502, first drop-down control module the 530, second drop-down control module 504, first drop-down module 505, second drop-down module 506 and reseting module 507.
One end of charging module 501 is connected with the input end INPUT of shift register cell 500, the other end is connected with pull-up node PU, for receiving input signal, and for pull-up node PU charges (current potential by pull-up node PU is drawn high) to produce pull-up signal under the control of input signal.
One end of pull-up module 502 is connected with pull-up node PU, the other end is connected with the first clock signal terminal CLK of shift register cell 500, for receiving described pull-up signal and the first clock signal, and the output terminal OUTPUT in the pull-up stage to shift register cell 500 under the control of pull-up signal and the first clock signal charges (that is, being drawn high by the level of output terminal OUTPUT).
One end of first drop-down control module 503 is connected with the second clock signal end CLKB of shift register cell 500, the other end is connected with the low-voltage end VSS of shift register cell 500, for receiving second clock signal, and produce drop-down control signal at drop-down Controlling vertex PD_CN place under the control of second clock signal.
One end of second drop-down control module 504 is connected with drop-down Controlling vertex PD_CN, and the other end is connected with pull-up node PU, for receiving drop-down control signal, and under the control of drop-down control signal, produces pulldown signal at pull-down node PD place.That is, at pull-down node PD place, the level of pull-up signal is dragged down.
One end of first drop-down module 505 is connected with the first reset terminal RESET of shift register cell 500, the other end is connected with the output terminal OUTPUT of shift register cell 500, for receiving the first reset signal and discharging (that is, the current potential of output terminal OUTPUT dragged down) to the output terminal OUTPUT of shift register cell 500 in the first drop-down stage under the control of the first reset signal.
One end of second drop-down module 506 is connected with pull-down node PD, the output terminal OUTPUT of the other end and shift register cell 500, for receiving pulldown signal, and the output terminal OUTPUT in the second drop-down stage to shift register cell 500 under the control of pulldown signal discharges (that is, by the level of output terminal OUPUT drag down).
One end of reseting module 507 is connected with the second reset terminal RESET ' of shift register cell 500, and the other end is connected with described pull-up node PU, for receiving the second reset signal, and resets to described pull-up node PU under the control of the second reset signal.
In the present embodiment, the first drop-down module 505 is connected to separately the first reset terminal of shift register cell 500, that is, for the first drop-down module 505 provides independently reset signal.The the first reset signal reset being supplied to the first drop-down module 505 is with the difference of the second reset signal reset ' being supplied to reseting module 507, and the second reset signal reset ' is delayed 1/2 (1H) in the actual duration of charging of a gate line than the first reset signal reset.Well known, first drop-down module 505 is connected to same reset terminal with reseting module 507, after the scanning completing a line gate line, first clock signal transfers low level to, reset signal is high level, and reseting module 507 is by unsettled for pull-up node PU (pull-up node PU becomes low level), and now pull-up module 502 does not work, first drop-down module 505 and the second drop-down module 506 work, and are dragged down by the output terminal level of shift register cell.But, according to the present embodiment, after the scanning completing a line grid, first clock signal transfers low level to, the reset signal being supplied to the first drop-down module 505 is high level, the output level of shift register drags down by the first drop-down module 505, meanwhile, level due to the pull-up node be connected with pull-up module 502 is still high level, therefore pull-up module 502 is still in work, and because the first clock signal being supplied to pull-up module 502 now transfers low level to, therefore pull-up module 502 and the first drop-down module 505 are discharged to the output terminal of shift register cell simultaneously.Like this, the output terminal OUPUT of shift register cell 500 is discharged in the first drop-down stage by pull-up module 502 and the first drop-down module 505 simultaneously, improve the discharging efficiency of shift register cell output terminal, the negative edge time Tf of further reduction gate drive signal, thus add the effective duration of charging Teff of pixel.After 1H, the second reset signal be connected with reseting module 507 is opened, and causes pull-up module 502 not work, and now because pull-up node PU becomes low level, the second drop-down module 506 works, and continues to discharge to the output terminal of shift register cell 500.The first reset signal be simultaneously connected with the first drop-down module 505 transfers low level to, and the first drop-down module 505 does not also work.
In addition, charge according to the output that the pull-up module of the present embodiment can not only be used in the pull-up stage to shift register, and can be used in the output of drop-down stage to shift register cell and discharge, namely same module plays different effects in different phase, thus simplifies circuit structure while guarantee improves discharging efficiency.
Hereinafter with reference to Fig. 6, specifically describe the physical circuit figure of the modules of the shift register cell that the utility model embodiment provides.
Fig. 6 shows the modules physical circuit figure of the shift register cell 500 according to the utility model embodiment.
See Fig. 6, charging module 501 comprises the first transistor M1.The grid of the first transistor M1 is connected with input end INPUT with the first pole, and the second pole is connected with pull-up node PU.
Reseting module 507 comprises transistor seconds M2.The grid of transistor seconds M2 is connected with the second reset terminal RESET ', and the first pole is connected with pull-up node PU, and the second pole is connected with low-voltage end VSS.
Pull-up module 502 comprises third transistor M3.The grid of third transistor M3 is connected with pull-up node PU, and the first pole is connected with the first clock signal terminal CLK, and the second pole is connected with output terminal OUTPUT.
First drop-down module 505 comprises the 4th transistor M4.The grid of the 4th transistor M4 is connected with the first reset terminal RESET, and the first pole is connected with output terminal OUTPUT, and the second pole is connected with low-voltage end VSS.
Second drop-down control module 504 comprises the 5th transistor M5 and the 6th transistor M6.The grid of the 5th transistor M5 is connected with drop-down Controlling vertex PD_CN, and the first pole is connected with second clock signal end CLKB, and the second pole is connected with pull-down node PD.The grid of the 6th transistor M6 is connected with the grid of third transistor M3, and the first pole is connected with pull-down node PD, and the second pole is connected with low-voltage end VSS.Here the phase place of the first clock signal that sends of the first clock signal terminal CLK is contrary with the phase place of the second clock signal that second clock signal end CLKB sends.
First drop-down control module 503 comprises the 7th transistor M7 and the 8th transistor M8, and the grid of the 7th transistor M7 is connected with the grid of third transistor M3, and the first pole is connected with drop-down Controlling vertex PD_CN, and the second pole is connected with low-voltage end VSS.The grid of the 8th transistor M8 is connected with second clock signal end CLKB with the first pole, and the second pole is connected with drop-down Controlling vertex PD_CN.
Second drop-down module 506 comprises the 9th transistor M9, the tenth transistor M10 and the 11 transistor M11.The grid of the 9th transistor M9 is connected with pull-down node PD, and the first pole is connected with pull-up node PU, and the second pole is connected with low-voltage end VSS.The grid of the tenth transistor M10 is connected with pull-down node PD, and the first pole is connected with output terminal OUTPUT, and the second pole is connected VSS with low-voltage end.The grid of the 11 transistor M11 is connected with second clock signal CLKB, and the first pole is connected with output terminal OUTPUT, and the second pole is connected with low-voltage end VSS.
In the present embodiment, grid to transistor M4 provides the first reset signal reset, grid to transistor M2 provides the second reset signal reset ', and wherein the second reset signal reset ' is delayed 1/2 (1H) in the actual duration of charging of a gate line than the first reset signal reset.After the scanning completing a line gate line (namely, after the pull-up stage), first clock signal transfers low level to, the the first reset signal reset being supplied to transistor M4 is high level, transistor M4 opens, and the output terminal of shift register cell is discharged, meanwhile, level due to pull-up node PU is still high level, therefore grid is connected with pull-up node PU and the transistor M3 that the first pole is connected with low level first clock signal is still in opening, and discharges to the output terminal of shift register cell.Therefore transistor M3 and transistor M4 discharges to the output terminal of shift register cell simultaneously.After 1H, because the second reset signal reset ' opens, transistor M2 also opens, and simultaneously because pull-up node PU transfers low level to, transistor M3 closes.And transfer low level to due to the first reset signal reset, therefore transistor M4 also closes.Because now second clock signal is high level, pull-up node PU is low level, and the second drop-down module 506 works, and continues to discharge to the output terminal of shift register cell 500.Like this, the output terminal OUPUT of shift register cell 500 is discharged in the first drop-down stage by transistor M3 and transistor M4 simultaneously, improve the discharging efficiency of shift register cell output terminal, the negative edge time Tf of further reduction gate drive signal, thus add the effective duration of charging Teff of pixel.
In addition according to the present embodiment, because transistor M3 and transistor M4 carries out discharge and recharge to the output terminal of shift register cell, therefore the size of transistor M3 and transistor M4 will much larger than the size of other transistors.
It should be noted that, transistor M1-11 can be N-type TFT.But this instructions is not limited the type of above-mentioned transistor.
One of transistor in the present embodiment two poles except grid are source electrode, and another is drain electrode.Due to transistor symmetry structurally, therefore the source electrode of transistor and the function of drain electrode can be exchanged.
The driving method of the shift register cell that the utility model provides is described in detail referring to Fig. 7.This driving method comprises charging stage, pull-up stage, the first drop-down stage and the second drop-down stage.
In the charging stage, the charging module 501 shown in Fig. 5, under the control of the input signal of input end INPUT, charges to pull-up node PU, and the level by pull-up node PU is drawn high, to produce pull-up signal.Now the output terminal OUTPUT of shift register is low level.
In the pull-up stage, first clock signal terminal CLK exports the first clock signal of high level, under the control of the first clock signal of pull-up signal (that is, pull-up node PU is in high level) and high level, the output terminal OUTPUT of pull-up module 502 pairs of shift register cells charges.Output terminal OUTPUT is driven high to high level by low level, and pull-up node PU is still high level.
In the first drop-down stage, reset terminal RESET exports the first reset signal reset of high level, therefore the first drop-down module 505 is discharged to the output terminal OUTPUT of shift register cell under the control of the first reset signal reset, makes the level of output terminal OUTPUT be pulled low to low level by the high level in pull-up stage.Due to when the first reset signal reset is high level, the first clock signal terminal CLK transfers low level to, and pull-up node PU is still high level, and therefore pull-up module 502 is also discharged to output terminal OUTPUT.In addition, although now second clock signal end CLKB exports the second clock signal of high level, because pull-up node PU is high level, and by adjusting the size of transistor M8 and M9, transistor M5 and M6 is not opened, thus the second drop-down module 506 does not work.
Finally, in the drop-down stage of second after 1H, because reset terminal RESET ' exports the second reset signal reset ' of high level, pull-up node PU is pulled low to low level by the high level in pull-up stage by reseting module 507, therefore pull-up module 502 does not work, and namely stops the electric discharge to output terminal OUTPUT.Meanwhile, the first reset signal reset transfers low level to, and the first drop-down module 505 does not work, and becomes low level due to pull-up node PU, and the second drop-down module 506 works, and continues to discharge to output terminal OUTPUT.
Achieve like this in the first drop-down stage pull-up module 502 and the first drop-down module 505 together to the object that the output terminal of shift register cell discharges, and then achieve the object of quick pull-down output terminal level, thus shorten fall times.
Fig. 8 shows the block diagram of the shift-register circuit 800 of shift register cell 500 cascade in multiple Fig. 5.
Shift-register circuit 800 can comprise m shift register cell 500, the output terminal of each shift register cell connects with corresponding gate line, except the first two shift register cell with except latter two shift register cell, the output terminal of the n-th shift register cell also resets to the n-th-2 shift register cells and as the input of the n-th+2 shift register cells.In addition, be with Fig. 4 difference, each shift register cell comprises two reset terminals, and wherein a reset terminal of the n-th shift register cell is connected with the output terminal of lower the n-th+2 shift register cells, and another reset terminal is connected with the output terminal of n+3 shift register cell.
Here, n is more than or equal to 3 and is less than or equal to m-3.In addition in order to reduce the power consumption of shift-register circuit, the clock signal of employing 4 or more usually.Preferably, the number of clock signal is the multiple of 2.Reduce the frequency of clock signal, to reach the object reducing power consumption simultaneously.
The shift-register circuit of the present embodiment can provide that effective duration of charging of pixel is grown, structure is simple and the shift-register circuit that power consumption is lower.
Of the present utility modelly embodiment still provides a kind of display device, comprise above-mentioned shift-register circuit.Described display device can be: any product or parts with Presentation Function such as display panels, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
Obviously, those skilled in the art can make various changes and modifications embodiment of the present utility model under the prerequisite not departing from spirit and scope of the present utility model.Scope of the present utility model is limited by claims and equivalent thereof.
Claims (14)
1. a shift register cell, comprising:
Charging module, one end is connected with the input end of described shift register cell, and the other end is connected with pull-up node, for receiving input signal, and is drawn high to produce pull-up signal by the current potential of pull-up node under the control of input signal;
Pull-up module, one end is connected with pull-up node, the other end is connected with the first clock signal terminal of described shift register cell, for receiving described pull-up signal and the first clock signal, and the output terminal in the pull-up stage to described shift register cell under the control of pull-up signal and the first clock signal charges;
First drop-down control module, one end is connected with the second clock signal end of described shift register cell, the other end is connected with the low-voltage end of described shift register cell, for receiving second clock signal, and produce drop-down control signal at drop-down Controlling vertex place under the control of second clock signal;
Second drop-down control module, one end is connected with drop-down Controlling vertex, and the other end is connected with pull-up node, for receiving drop-down control signal, and under the control of drop-down control signal, produces pulldown signal at pull-down node place;
First drop-down module, one end is connected with the first reset terminal of described shift register cell, the other end is connected with the output terminal of described shift register cell, for receiving the first reset signal and discharging to the output terminal of described shift register cell under the control of the first reset signal in the first drop-down stage;
Second drop-down module, one end is connected with pull-down node, the other end is connected with the output terminal of described shift register cell, for receiving pulldown signal, and discharges at the second output terminal of drop-down stage to described shift register cell under the control of pulldown signal; And
Reseting module, one end is connected with the second reset terminal of described shift register cell, and the other end is connected with described pull-up node, for receiving the second reset signal, and resets to described pull-up node under the control of the second reset signal;
Wherein, described pull-up module is discharged at described first output terminal of drop-down stage to described shift register cell.
2. shift register cell according to claim 1, wherein, described charging module comprises the first transistor, and the grid of described the first transistor is connected with described input end with the first pole, and the second pole is connected with described pull-up node.
3. shift register cell according to claim 2, wherein, described reseting module comprises transistor seconds, and the grid of described transistor seconds is connected with described second reset terminal, and the first pole is connected with described pull-up node, and the second pole is connected with low-voltage end.
4. shift register cell according to claim 3, wherein, described pull-up module comprises third transistor, and the grid of described third transistor is connected with described pull-up node, first pole is connected with described first clock signal terminal, and the second pole is connected with described output terminal.
5. shift register cell according to claim 4, wherein, described first drop-down module comprises the 4th transistor, and the grid of described 4th transistor is connected with described first reset terminal, first pole is connected with described output terminal, and the second pole is connected with described low-voltage end.
6. shift register cell according to claim 5, wherein, described second drop-down control module comprises the 5th transistor and the 6th transistor, the grid of described 5th transistor is connected with described drop-down Controlling vertex, first pole is connected with described second clock signal end, and the second pole is connected with described pull-down node; The grid of described 6th transistor is connected with the grid of described third transistor, and the first pole is connected with described pull-down node, and the second pole is connected with described low-voltage end.
7. shift register cell according to claim 6, wherein, described first drop-down control module comprises the 7th transistor and the 8th transistor, the grid of described 7th transistor is connected with the grid of described third transistor, first pole is connected with described drop-down Controlling vertex, and the second pole is connected with described low-voltage end; The grid of described 8th transistor is connected with described second clock signal with the first pole, and the second pole is connected with described drop-down Controlling vertex.
8. shift register cell according to claim 7, wherein, described second drop-down module comprises the 9th transistor, the tenth transistor and the 11 transistor, the grid of described 9th transistor is connected with described pull-down node, first pole is connected with described pull-up node, and the second pole is connected with described low-voltage end; The grid of described tenth transistor is connected with described pull-down node, and the first pole is connected with described output terminal, and the second pole is connected with described low-voltage end; The grid of described 11 transistor is connected with described second clock signal, and the first pole is connected with described output terminal, and the second pole is connected with described low-voltage end.
9. shift register cell according to claim 1, wherein, described pull-up module and described first drop-down module were discharged to the output terminal of described shift register cell in the first drop-down stage simultaneously.
10. the shift register cell according to any one of claim 5 to 8, wherein, the size of described third transistor and described 4th transistor is greater than the size of other transistors.
11. shift register cells according to claim 1, wherein, described second reset signal postpones 1/2 of the actual duration of charging of a gate line relative to described first reset signal.
12. shift register cells according to claim 1, the phase place of wherein said first clock signal is contrary with the phase place of second clock signal.
13. 1 kinds of shift-register circuits, comprise the shift register cell according to any one of claim 1-12 of m cascade, the output terminal of each shift register cell connects with corresponding gate line, except the first two shift register cell with except latter two shift register cell, the output terminal of the n-th shift register cell also resets to the n-th-2 shift register cells and as the input of the n-th+2 shift register cells
Wherein each shift register cell comprises two reset terminals, and a reset terminal of the n-th shift register cell is connected with the output terminal of the n-th+2 shift register cells, and another reset terminal is connected with the output terminal of n+3 shift register cell, and
N is more than or equal to 3 and is less than or equal to m-3.
14. 1 kinds of display device, comprise shift-register circuit according to claim 13.
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| CN201420851062.9U CN204406959U (en) | 2014-12-26 | 2014-12-26 | Shift register cell, shift-register circuit and display device |
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| CN201420851062.9U CN204406959U (en) | 2014-12-26 | 2014-12-26 | Shift register cell, shift-register circuit and display device |
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