CN104240765A - Shifting register unit, driving method, gate drive circuit and display device - Google Patents
Shifting register unit, driving method, gate drive circuit and display device Download PDFInfo
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- CN104240765A CN104240765A CN201410429757.2A CN201410429757A CN104240765A CN 104240765 A CN104240765 A CN 104240765A CN 201410429757 A CN201410429757 A CN 201410429757A CN 104240765 A CN104240765 A CN 104240765A
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Abstract
The embodiment of the invention provides a shifting register unit and a driving method, a gate drive circuit and a display device, relates to the technical field of display and aims at reducing the noise of a bidirectional scanning gate drive circuit. The shifting register unit comprises a first scanning control module, a second scanning control module, a pull-up control module, a pull-up module, a pull-down control module and a pull-down module.
Description
Technical field
The present invention relates to display technique field, particularly relate to shift register cell and driving method, gate driver circuit and display device.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) be intersect by the grid line of horizontal and vertical directions and data line the picture element matrix defined to form, when TFT-LCD shows, driven by the grid (Gate) on grid line and successively gating is carried out to the square wave of each pixel column input one fixed width, then by source electrode (Source) driving on data line, the signal needed for every one-row pixels is exported successively.But, when resolution is higher, the raster data model of display and the output of source drive all more, the length of driving circuit also will increase, and this will be unfavorable for binding (Bonding) technique of module driving circuit.
In order to solve the problem, the manufacture of existing display often adopts GOA (Gate Driver on Array, array base palte row cutting) design of circuit, by TFT (Thin Film Transistor, Thin Film Transistor (TFT)) gate switch circuit be integrated in display panel array base palte on to form the turntable driving to display panel, thus can save the Bonding region of gate driver circuit and peripheral wiring space, thus the both sides realizing display panel are symmetrical and the design for aesthetic of narrow frame.
As shown in Figure 1, the shift register on this gate driver circuit comprises shift register cell SR0, SR1 of multi-stage cascade to current a kind of GOA design proposal ... SRn.Wherein, sweep signal is input to by signal output part Output at the corresponding levels the gate lines G n corresponded by every one-level shift register cell, and sweep signal is outputted to the signal input part Input of next stage SRn+1 and the signal reset terminal Rst of upper level SRn-1; For starting next stage shift register cell, and next stage shift register cell is resetted.But the one-level shift register cell of above-mentioned gate driver circuit, such as, the signal input part Input of SRn, after the sweep signal receiving upper level shift register cell SRn-1 output, under the effect of the clock signal of the clock signal input terminal CLK input of self, exports sweep signal.Therefore, above-mentioned gate driver circuit can only realize simple scanning.So, have the display device of simple scanning, such as mobile phone, when user rotates screen in viewing or use procedure, display frame cannot change along with the change of the viewing mode of user.So, demand and the experience of user can greatly be reduced.
In order to solve the problem, those skilled in the art propose a kind of GOA circuit that can carry out bilateral scanning, not only can scan every a line grid from top to bottom, can also scan every a line grid from bottom to up.But have the GOA circuit of bilateral scanning function, for the GOA circuit of simple scanning, its circuit structure relative complex, includes the transistor that number is more.Therefore, can because the electricity in self coupling capacitance of some transistors is not discharged fully, and cause GOA circuit to produce noise, thus reduce the stability of GOA circuit.
Summary of the invention
Embodiments of the invention provide a kind of shift register cell and driving method, gate driver circuit and display device, can reduce the noise of bilateral scanning gate driver circuit.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the present invention, provides a kind of shift register cell, comprising: the first scan control module, the second scan control module, pull-up control module, pull-up module, drop-down control module and drop-down module;
Described first scan control module, connects the first signal input part, the first voltage end and described pull-up control module respectively; For the signal according to described first signal input part input, pull-up control module described in conducting;
Described second scan control module, connects secondary signal input end, the second voltage end and described pull-up control module respectively; For the signal according to described secondary signal input end input, pull-up control module described in conducting;
Described pull-up control module, connects described first scan control module, described second scan control module, the 4th voltage end and pull-up Controlling vertex respectively; For the current potential of described pull-up Controlling vertex being pulled to the voltage of described 4th voltage end under the control of described first scan control module or described second scan control module;
Described pull-up module, connects the first clock signal terminal, described pull-up Controlling vertex and signal output part at the corresponding levels respectively; For the current potential according to described pull-up Controlling vertex, the signal of described first clock signal terminal input is provided to described signal output part at the corresponding levels;
Described drop-down control module, connects described drop-down Controlling vertex, described pull-up control module, described tertiary voltage end, described 4th voltage end and second clock signal end respectively; For the signal according to described second clock signal end input, control the current potential of described drop-down Controlling vertex;
Described drop-down module, connect described drop-down Controlling vertex, described pull-up Controlling vertex and described signal output part at the corresponding levels respectively, for the output signal of the current potential of described pull-up Controlling vertex and described signal output part at the corresponding levels being pulled down to the voltage of described tertiary voltage end under the control of Electric potentials of described drop-down Controlling vertex.
The another aspect of the embodiment of the present invention, provides a kind of gate driver circuit, comprises multistage any one shift register cell as above;
Except first order shift register cell, the signal output part at the corresponding levels of the upper level shift register cell that the first signal input part of all the other each shift register cells is adjacent is connected;
Except afterbody shift register cell, the signal output part at the corresponding levels of the next stage shift register cell that the secondary signal input end of all the other each shift register cells is adjacent is connected.
The another aspect of the embodiment of the present invention, provides a kind of display device, comprises any one gate driver circuit as above.
Having on the one hand of the embodiment of the present invention, provides a kind of driving method of shift register cell, comprising:
First stage, first scan control module or the second scan module, the signal inputted by the first signal input part or secondary signal input end is by the conducting of pull-up control module, and the current potential of pull-up Controlling vertex is pulled to the voltage of the 4th voltage end by described pull-up control module; Stored by the voltage of described pull-up module by described 4th voltage end;
Subordinate phase, described pull-up Controlling vertex controls described pull-up module and the signal that the first clock signal terminal inputs is provided to signal output part at the corresponding levels; The current potential of drop-down Controlling vertex is pulled down to the voltage of tertiary voltage end by drop-down control module;
Phase III, the current potential of described drop-down Controlling vertex is pulled to the voltage of described 4th voltage end by described drop-down control module by second clock signal end; Described drop-down Controlling vertex by drop-down module by the current potential of described pull-up Controlling vertex and and the output signal of described signal output part at the corresponding levels be pulled down to the voltage of described tertiary voltage end.
The embodiment of the present invention provides a kind of shift register cell and driving method, gate driver circuit and display device.Described shift register cell comprises the first scan control module, the second scan control module, pull-up control module, pull-up module and drop-down control module.So, can respectively by the first signal input part be connected with described first scan control module, and the signal that the secondary signal input end to be connected with described second scan control module inputs scans forward or backwards to this gate driver circuit, thus realize bilateral scanning.And, when the signal output part at the corresponding levels of shift register cell needs to export sweep signal, pull-up control module can by controlling the current potential of pull-up Controlling vertex, make the conducting of pull-up module, the signal of the first clock signal terminal input is exported as sweep signal by signal output part at the corresponding levels, to scan a line grid line.In addition, when the signal output part at the corresponding levels of shift register cell does not need to export sweep signal, described drop-down control module can by controlling the current potential of drop-down Controlling vertex, to carry out drop-down to pull-up Controlling vertex and signal output part at the corresponding levels, thus noise reduction can be carried out to above-mentioned bilateral scanning gate driver circuit.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of gate driver circuit that Fig. 1 provides for prior art;
The structural representation of a kind of shift register cell that Fig. 2 provides for the embodiment of the present invention;
The structural representation of the another kind of shift register cell that Fig. 3 provides for the embodiment of the present invention;
A kind of shift register cell working signal timing waveform that Fig. 4 provides for the embodiment of the present invention;
The another kind of shift register cell working signal timing waveform that Fig. 5 provides for the embodiment of the present invention;
Working state schematic representation during a kind of shift register cell forward scan that Fig. 6-Fig. 8 provides for the embodiment of the present invention;
The structural representation of a kind of gate driver circuit that Fig. 9 provides for the embodiment of the present invention;
The signal sequence oscillogram of a kind of gate driver circuit that Figure 10 provides for the embodiment of the present invention;
The signal sequence oscillogram of the another kind of gate driver circuit that Figure 11 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of shift register cell, as shown in Figure 2, can comprise: the first scan control module 10, second scan control module 20, pull-up control module 30, pull-up module 40, drop-down control module 50 and drop-down module 60.
Above-mentioned first scan control module 10, can connect the first signal input part Input1, the first voltage end Vcn and pull-up control module 30 respectively.For the signal inputted according to the first signal input part Input1, pull-up control module 30 described in conducting.
Above-mentioned second scan control module 20, can connect secondary signal input end Input2, the second voltage end Vcnb and pull-up control module 20 respectively; For the signal inputted according to secondary signal input end Input2, conducting pull-up control module 30.
Above-mentioned pull-up control module 30, can connect the first scan control module 10, second scan control module 20, the 4th voltage end VGH and pull-up Controlling vertex PU respectively.For the current potential of pull-up Controlling vertex PU being pulled to the voltage of the 4th voltage end VGH under the control of the first scan control module 10 or the second scan control module 20.
Above-mentioned pull-up module 40, can connect the first clock signal terminal CLK respectively, pull-up controls joint PU point and signal output part Output at the corresponding levels.For the current potential according to pull-up Controlling vertex PU, the signal of above-mentioned first clock signal terminal input CLK is provided to signal output part Output at the corresponding levels.To scan the grid line corresponding with this signal output part at the corresponding levels.
Above-mentioned drop-down control module 50, connects drop-down Controlling vertex PD, pull-up control module 30, tertiary voltage end VGL, the 4th voltage end VGH and second clock signal end CLKB respectively.For the signal inputted according to above-mentioned second clock signal end CLKB, control the current potential of drop-down Controlling vertex PD.
Above-mentioned drop-down module 60, drop-down Controlling vertex PD, pull-up Controlling vertex PU and signal output part Output at the corresponding levels can be connected respectively, for the output signal of the current potential of pull-up Controlling vertex PU and signal output part Output at the corresponding levels being pulled down to the voltage of tertiary voltage end VGL under the control of Electric potentials of drop-down Controlling vertex PD.
It should be noted that, first, the embodiment of the present invention is the explanation carried out for the first signal input part Input1 and secondary signal input end Input2 that forward scan signal STV_U and reverse scan signal STV_D are linked into respectively shift register cell at different levels.Concrete, sweep signal, according to the forward scan signal STV_U of input, is sequentially outputted on the grid line corresponding with above-mentioned signal output part Output at the corresponding levels by forward (from top to bottom) by signal output part Output at the corresponding levels at different levels by shift register at different levels.Or, sweep signal, according to the reverse scan signal STV_D of input, is sequentially outputted on the grid line corresponding with above-mentioned signal output part Output at the corresponding levels by reverse (from bottom to up) by signal output part Output at the corresponding levels at different levels by shift register at different levels.
Certainly, forward scan signal STV_U and reverse scan signal can also be linked into secondary signal input end Input2 and the first signal input part Input1 of shift register cell at different levels respectively by STV_D.Concrete scanning process in like manner can obtain, and repeats no more herein.
The second, in the embodiment of the present invention be the explanation carried out for tertiary voltage end VGL input low level, the 4th voltage end VGH input high level.
The embodiment of the present invention provides a kind of shift register cell, can comprise the first scan control module, the second scan control module, pull-up control module, pull-up module and drop-down control module.So, can respectively by the first signal input part be connected with described first scan control module, and the signal that the secondary signal input end to be connected with described second scan control module inputs scans forward or backwards to this gate driver circuit, thus realize bilateral scanning.And, when the signal output part at the corresponding levels of shift register cell needs to export sweep signal, pull-up control module can by controlling the current potential of pull-up Controlling vertex, make the conducting of pull-up module, the signal of the first clock signal terminal input is exported as sweep signal by signal output part at the corresponding levels, to scan a line grid line.In addition, when the signal output part at the corresponding levels of shift register cell does not need to export sweep signal, described drop-down control module can by controlling the current potential of drop-down Controlling vertex, to carry out drop-down to pull-up Controlling vertex and signal output part at the corresponding levels, thus noise reduction can be carried out to above-mentioned bilateral scanning gate driver circuit.
Below, composition graphs 3 is carried out detailed illustrating to the concrete structure of above-mentioned shift register cell.
It should be noted that, the above-mentioned modules of shift register cell comprises multiple transistor, is the explanation all adopting N-type transistor to carry out for the transistor in shift register cell in following examples.
Embodiment one
Above-mentioned first scan control module 10 can comprise: the first transistor M1 and transistor seconds M2.
Wherein, first pole of the first transistor M1 connects and is connected the first voltage end Vcn with grid, and the second pole is connected with the grid of transistor seconds M2.
First pole of transistor seconds M2 connects described first signal input part Input1, and grid connects second pole of the first transistor M1, and the second pole is connected with pull-up control module 30.
So, as shown in Figure 4, when the first voltage end Vcn input high level, described first scan control module 10 conducting, when the first signal input part Input1 inputs forward scan signal STV_U, shift register cell at different levels starts forward scan work.
Above-mentioned second scan control module 20 can comprise: third transistor M3 and the 4th transistor M4.
Wherein, first pole of third transistor M3 is connected the second voltage end Vcnb with grid, the second pole is connected with the grid of the 4th transistor M4.
First pole of the 4th transistor M4 connects secondary signal input end Input2, and grid connects second pole of above-mentioned third transistor M3, and the second pole is connected with pull-up control module 30.
So, as shown in Figure 5, when the second voltage end Vcnb input high level, described second scan control module 20 conducting, when secondary signal input end Input2 inputs reverse scan signal STV_D, shift register cell at different levels is made to start reverse scan work.
Pull-up control module 30 can comprise: the 7th transistor M7.
7th transistor M7, its first pole connects pull-up Controlling vertex PU, and the second pole connects the 4th voltage end VGH, and grid is connected with second pole of the 4th transistor M4 with transistor seconds M2.
Pull-up module 40 can comprise: the 8th transistor M8, the 9th transistor M9 and the first electric capacity C1.
First pole of the 8th transistor M8 connects the first clock signal terminal CLK, and grid connects pull-up Controlling vertex PU, and the second pole is connected with signal output part Output at the corresponding levels.
One end of first electric capacity C1 connects pull-up Controlling vertex PU, and the other end is connected with second pole of the 8th transistor M8.
Drop-down control module 50 can comprise: the 6th transistor M6, the 9th transistor M9 and the 11 transistor M11.
Wherein, the 6th transistor M6, its first pole connects drop-down Controlling vertex PD, and the second pole connects tertiary voltage end VGL, and grid is connected with second pole of the 4th transistor M4 with transistor seconds M2.
First pole of the 9th transistor M9 connects tertiary voltage end VGL, and grid connects second pole of the 8th transistor M8, and the second pole is connected with drop-down Controlling vertex PD.
First pole of the 11 transistor M11 connects the 4th voltage end VGH, and the second pole is connected with drop-down Controlling vertex PD, and grid is connected with second clock signal end CLKB.
Drop-down module 60 can comprise: the 5th transistor M5, the tenth transistor M10 and the second electric capacity C2.
Wherein, first pole of the 5th transistor M5 connects pull-up Controlling vertex PU, and grid connects drop-down Controlling vertex PD, and the second pole is connected with tertiary voltage end VGL.
First pole of the tenth transistor M10 connects tertiary voltage end VGL, and grid connects drop-down Controlling vertex PD, and the second pole is connected with the grid of the 9th transistor M9 with second pole of the 8th transistor M8.
One end of second electric capacity C2 connects the grid of the tenth transistor M10, and the second pole is connected with first pole of the tenth transistor M10.
It should be noted that, first of above-mentioned transistor can be extremely source class, and second can be extremely drain electrode.
Below, according to the sequential working figure of forward scan, as shown in Figure 4, the shift register cell shown in composition graphs 3, is described in detail the course of work of this shift register cell.
Embodiment two
First stage T1, Vcn=1; CLKB=1; CLK=0; PU=1; PD=0; Input1=1; Output=0.It should be noted that, in following examples, 0 represents low level VGL; 1 represents high level VGH.
As shown in Figure 6, the first voltage end Vcn input high level, by the first transistor M1 and transistor seconds M2 conducting.In the case, the forward scan signal STV_U that first signal input part Input1 inputs is high level, thus make the 7th transistor M7, the 6th transistor M6 conducting, because second pole of the 7th transistor M7 connects the 4th voltage end VGH, thus the current potential of pull-up Controlling vertex PU is drawn high to high level, and the first electric capacity C1 is charged.8th transistor M8 conducting, transfers to signal output part Output at the corresponding levels by the low level that the first clock signal terminal CLK inputs, makes signal output part Output output low level at the corresponding levels, can not scan grid line corresponding thereto.
Due to the 6th transistor M6 conducting, even if therefore second clock signal end CLKB1 input high level, by the 11 transistor M11 conducting, the current potential of drop-down Controlling vertex PD still can be pulled low to low level by the 6th transistor M6.So, the 5th transistor M5 ends, and the current potential of pull-up Controlling vertex PU can not be dragged down.To ensure that the first electric capacity C1 is in charged state.In addition, the 9th transistor M9 and the tenth transistor M10 is in cut-off state.
In sum, first stage T1 is the pre-charging stage of the first electric capacity C1 in this shift register cell.
Subordinate phase T2, Vcn=1; CLKB=0; CLK=1; PU=1; PD=0; Input1=0; Output=1.
As shown in Figure 7, the first voltage end Vcn input high level, the first transistor M1 and transistor seconds M2 continues to keep conducting state.In the case, the forward scan signal STV_U that the first signal input part Input1 inputs is low level, thus make the 7th transistor M7, the 6th transistor M6 is in cut-off state, under the boot strap of the first electric capacity C1, the current potential through PU is drawn high further.8th transistor M8 is still in conducting state, and the high level that the first clock signal terminal CLK inputs is transferred to signal output part Output at the corresponding levels, makes signal output part Output at the corresponding levels export high level, and scans grid line corresponding thereto.
In addition, the 9th transistor M9 conducting, by the grid of voltage input levels the tenth transistor M10 of tertiary voltage end VGL, the voltage due to tertiary voltage end VGL is low level, and therefore, the tenth transistor M10 ends.Second clock signal end CLKB1 input low level, the 11 transistor M11 ends.
In sum, subordinate phase T2 is the stage that this shift register cell is opened.
Subordinate phase T3, Vcn=1; CLKB=1; CLK=0; PU=0; PD=1; Input1=0; Output=0.
As shown in Figure 8, the first voltage end Vcn input high level, the first transistor M1 and transistor seconds M2 continues to keep conducting state.In the case, the forward scan signal STV_U that the first signal input part Input1 inputs is low level, thus make the 7th transistor M7, the 6th transistor M6 is in cut-off state.
Second clock signal end CLKB1 input high level, the 11 transistor M11 conducting, by the voltage boost of drop-down Controlling vertex PD to high level.Because the 6th transistor M6 is in cut-off state, therefore the current potential of drop-down Controlling vertex PD can not be dragged down.In the case, the 5th transistor M5 conducting, the current potential of pull-up Controlling vertex PU is pulled to low level, and the 8th transistor M8 is in cut-off state, signal output part Output no-output at the corresponding levels.So, before the input of next frame sweep signal, above-mentioned 5th transistor M5 is all in the state of conducting, thus the generation of pull-up Controlling vertex PU noise under effectively prevent off working state.
Meanwhile, the tenth transistor M10 conducting, can be pulled low to level point by the current potential of signal output part Output at the corresponding levels, thus the generation of signal output part Output noise at the corresponding levels under reducing off working state.
In sum, phase III T3 can be the reset noise reduction stage of this shift register cell.
Above-mentioned is the explanation carried out for forward scan, and reverse scan in like manner can obtain, and repeats no more here.
It should be noted that, the transistor in above-described embodiment is all the explanations carried out for N-type transistor, when all adopting P-type crystal pipe.The principle of work of the shift register cell that the concrete course of work can be formed with reference to above-mentioned N-type transistor, wherein needs the sequential of corresponding adjustment drive singal, repeats no more herein.
The embodiment of the present invention provides a kind of gate driver circuit, as shown in Figure 9, comprises multistage shift register cell (SR0, SR1 as above ... SRn).
Outside first order shift register cell SR0, the signal output part Output at the corresponding levels of the upper level shift register cell that the first signal input part Input1 of all the other each shift register cells is adjacent is connected.
Except afterbody shift register cell SRn, the signal output part Output at the corresponding levels of the next stage shift register cell that the secondary signal input end Input2 of all the other each shift register cells is adjacent is connected.
Concrete, when gate driver circuit carries out forward scan, the sequential chart of each signal input as shown in Figure 10, each line scan signals of this GOA circuit be G1, G2, G3, G4 ... Gn-1, Gn; When gate driver circuit carries out reverse scan, as shown in figure 11, each line scan signals of this GOA circuit is Gn, Gn-1, Gn-2, Gn-3 to the sequential chart of each signal input ... G2, G1.
The embodiment of the present invention provides a kind of gate driver circuit, comprises shift register cell.This shift register cell comprises the first scan control module, the second scan control module, pull-up control module, pull-up module and drop-down control module.So, can respectively by the first signal input part be connected with described first scan control module, and the signal that the secondary signal input end to be connected with described second scan control module inputs scans forward or backwards to this gate driver circuit, thus realize bilateral scanning.And, when the signal output part at the corresponding levels of shift register cell needs to export sweep signal, pull-up control module can by controlling the current potential of pull-up Controlling vertex, make the conducting of pull-up module, the signal of the first clock signal terminal input is exported as sweep signal by signal output part at the corresponding levels, to scan a line grid line.In addition, when the signal output part at the corresponding levels of shift register cell does not need to export sweep signal, described drop-down control module can by controlling the current potential of drop-down Controlling vertex, to carry out drop-down to pull-up Controlling vertex and signal output part at the corresponding levels, thus noise reduction can be carried out to above-mentioned bilateral scanning gate driver circuit.
The embodiment of the present invention provides a kind of display device, comprises any one gate driver circuit as above.There is the beneficial effect identical with the gate driver circuit that previous embodiment of the present invention provides, because gate driver circuit has been described in detail in the aforementioned embodiment, repeat no more herein.
This display device is specifically as follows any liquid crystal display product or parts with Presentation Function such as liquid crystal display, LCD TV, digital album (digital photo frame), mobile phone, panel computer.
The embodiment of the present invention provides a kind of driving method of shift register cell, can comprise:
First stage, first scan control module 10 or the second scan module 20, the signal inputted by the first signal input part Input1 or secondary signal input end Input2 is by pull-up control module 30 conducting, and the current potential of pull-up Controlling vertex PU is pulled to the voltage of the 4th voltage end VGH by described pull-up control module 30; Stored by the voltage of pull-up module 30 by the 4th voltage end VGH.First stage is the pre-charging stage of this shift register cell.
Subordinate phase, pull-up Controlling vertex PU controls pull-up module 40 and the signal that first clock signal terminal CLK inputs is provided to signal output part Output at the corresponding levels; The current potential of drop-down Controlling vertex PD is pulled down to the voltage of tertiary voltage end VGL by drop-down control module 50.Subordinate phase T2 is the stage that this shift register cell is opened.
Phase III, the current potential of drop-down Controlling vertex PD is pulled to the voltage of the 4th voltage end VGH by drop-down control module 50 by second clock signal end CLKB; Drop-down Controlling vertex PD by drop-down module 60 by the current potential of pull-up Controlling vertex PD and and the output signal of signal output part Output at the corresponding levels be pulled down to the voltage of tertiary voltage end VGL.Phase III T3 can be the reset noise reduction stage of this shift register cell.
Above-mentioned driving method can respectively by the first signal input part be connected with described first scan control module, and the signal that the secondary signal input end to be connected with described second scan control module inputs scans forward or backwards to this gate driver circuit, thus realize bilateral scanning.And, when the signal output part at the corresponding levels of shift register cell needs to export sweep signal, pull-up control module can by controlling the current potential of pull-up Controlling vertex, make the conducting of pull-up module, the signal of the first clock signal terminal input is exported as sweep signal by signal output part at the corresponding levels, to scan a line grid line.In addition, when the signal output part at the corresponding levels of shift register cell does not need to export sweep signal, described drop-down control module can by controlling the current potential of drop-down Controlling vertex, to carry out drop-down to pull-up Controlling vertex and signal output part at the corresponding levels, thus noise reduction can be carried out to above-mentioned bilateral scanning gate driver circuit.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that programmed instruction is relevant, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (10)
1. a shift register cell, is characterized in that, comprising: the first scan control module, the second scan control module, pull-up control module, pull-up module, drop-down control module and drop-down module;
Described first scan control module, connects the first signal input part, the first voltage end and described pull-up control module respectively; For the signal according to described first signal input part input, pull-up control module described in conducting;
Described second scan control module, connects secondary signal input end, the second voltage end and described pull-up control module respectively; For the signal according to described secondary signal input end input, pull-up control module described in conducting;
Described pull-up control module, connects described first scan control module, described second scan control module, the 4th voltage end and pull-up Controlling vertex respectively; For the current potential of described pull-up Controlling vertex being pulled to the voltage of described 4th voltage end under the control of described first scan control module or described second scan control module;
Described pull-up module, connects the first clock signal terminal, described pull-up Controlling vertex and signal output part at the corresponding levels respectively; For the current potential according to described pull-up Controlling vertex, the signal of described first clock signal terminal input is provided to described signal output part at the corresponding levels;
Described drop-down control module, connects described drop-down Controlling vertex, described pull-up control module, described tertiary voltage end, described 4th voltage end and second clock signal end respectively; For the signal according to described second clock signal end input, control the current potential of described drop-down Controlling vertex;
Described drop-down module, connect described drop-down Controlling vertex, described pull-up Controlling vertex and described signal output part at the corresponding levels respectively, for the output signal of the current potential of described pull-up Controlling vertex and described signal output part at the corresponding levels being pulled down to the voltage of described tertiary voltage end under the control of Electric potentials of described drop-down Controlling vertex.
2. shift register cell according to claim 1, is characterized in that, described first scan control module comprises:
The first transistor, its first pole connects and is connected described first voltage end with grid;
Transistor seconds, its first pole connects described first signal input part, and grid connects the second pole of described the first transistor, and the second pole is connected with described pull-up control module.
3. shift register cell according to claim 2, is characterized in that, described second scan control module comprises:
Third transistor, its first pole is connected the second voltage end with grid;
4th transistor, its first pole connects secondary signal input end, and grid connects the second pole of described third transistor, and the second pole is connected with described pull-up control module.
4. shift register cell according to claim 3, is characterized in that, described pull-up control module comprises:
7th transistor, its first pole connects described pull-up Controlling vertex, and the second pole connects described 4th voltage end, and grid is connected with second pole of described transistor seconds with described 4th transistor.
5. shift register cell according to claim 4, is characterized in that, described pull-up module comprises:
8th transistor, its first pole connects described first clock signal terminal, and grid connects described pull-up Controlling vertex, and the second pole is connected with signal output part at the corresponding levels;
First electric capacity, its one end connects described pull-up Controlling vertex, and the other end is connected with the second pole of described 8th transistor.
6. shift register cell according to claim 5, is characterized in that, described drop-down control module comprises:
6th transistor, its first pole connects described drop-down Controlling vertex, and the second pole connects described tertiary voltage end, and grid is connected with second pole of described transistor seconds with described 4th transistor;
9th transistor, its first pole connects described tertiary voltage end, and grid connects the second pole of the 8th transistor, and the second pole is connected with described drop-down Controlling vertex;
11 transistor, its first pole connects described 4th voltage end, and the second pole is connected with described drop-down Controlling vertex, and grid is connected with described second clock signal end.
7. shift register cell according to claim 6, is characterized in that, described drop-down module comprises:
5th transistor, its first pole connects described pull-up Controlling vertex, and grid connects described drop-down Controlling vertex, and the second pole is connected with described tertiary voltage end;
Tenth transistor, its first pole connects described tertiary voltage end, and grid connects described drop-down Controlling vertex, and the second pole is connected with the grid of described 9th transistor with the second pole of described 8th transistor;
Second electric capacity, its one end connects the grid of described tenth transistor, and the second pole is connected with the first pole of described tenth transistor.
8. a gate driver circuit, is characterized in that, comprise multistage as arbitrary in claim 1 to 7 as described in shift register cell;
Except first order shift register cell, the signal output part at the corresponding levels of the upper level shift register cell that the first signal input part of all the other each shift register cells is adjacent is connected;
Except afterbody shift register cell, the signal output part at the corresponding levels of the next stage shift register cell that the secondary signal input end of all the other each shift register cells is adjacent is connected.
9. a display device, is characterized in that, comprises gate driver circuit as claimed in claim 8.
10. a driving method for shift register cell, is characterized in that, comprising:
First stage, first scan control module or the second scan module, the signal inputted by the first signal input part or secondary signal input end is by the conducting of pull-up control module, and the current potential of pull-up Controlling vertex is pulled to the voltage of the 4th voltage end by described pull-up control module; Stored by the voltage of described pull-up module by described 4th voltage end;
Subordinate phase, described pull-up Controlling vertex controls described pull-up module and the signal that the first clock signal terminal inputs is provided to signal output part at the corresponding levels; The current potential of drop-down Controlling vertex is pulled down to the voltage of tertiary voltage end by drop-down control module;
Phase III, the current potential of described drop-down Controlling vertex is pulled to the voltage of described 4th voltage end by described drop-down control module by second clock signal end; Described drop-down Controlling vertex by drop-down module by the current potential of described pull-up Controlling vertex and and the output signal of described signal output part at the corresponding levels be pulled down to the voltage of described tertiary voltage end.
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