CN102881248B - Gate driver circuit and driving method thereof and display device - Google Patents
Gate driver circuit and driving method thereof and display device Download PDFInfo
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- CN102881248B CN102881248B CN201210375345.6A CN201210375345A CN102881248B CN 102881248 B CN102881248 B CN 102881248B CN 201210375345 A CN201210375345 A CN 201210375345A CN 102881248 B CN102881248 B CN 102881248B
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Abstract
The invention discloses a kind of gate driver circuit and driving method thereof and display device, relate to display field, can wiring space be reduced, realize the narrow frame of panel, be particularly useful for undersized panel.Gate driver circuit of the present invention comprises: shift register, also comprise: a control multiple-unit, be connected with described shift register output end, for the first pulse signal of described shift register output is converted into multiple second pulse signal, respectively in order to drive many grid lines.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of gate driver circuit and driving method thereof and display device.
Background technology
Array base palte row cutting (GateDriveronArray, GOA) technology, is directly be integrated on array base palte by gate driver circuit (GatedriverICs), replaces a kind of technology of external driving chip.The application of this technology not only can reduce production technology program, reduce cost of products, improve integrated level, and the design for aesthetic of panel both sides symmetry can be accomplished, also eliminate binding (Bonding) region and fan-out (Fan-out) wiring space of grid circuit (GateIC) simultaneously, thus the design of narrow frame can be realized, improve production capacity and yields.
As shown in Figure 1, for have employed the gate driver circuit of GOA technology, comprising multiple shift register (SR1 ~ SRn), ground voltage signal Vss provides line, unbalanced pulse signal STV provides line, the first and second clocks provide line.As shown in Figure 2, wherein, the phase place of the first clock signal clk 1 and second clock signal CLK2 is opposite each other for sequential chart during shift register work.The gate driver circuit course of work is as follows: work as STV=1, export the input end of the shift register SR1 that a high level pulse is connected to the first row pixel cell, the first row shift register (SR1) is opened, grid high level is exported in counter plate, other row is in closed condition, be that next line shift register (SR2) input end injects high level simultaneously, the second row is opened; When the second row SR2 exports high level, the first row SR1 is resetted, now except this row, other row is in closed condition, be that its next line (shift register SR3) input end injects high level simultaneously, postpone successively, to the last a line, the output signal OUT1 ~ OUTn of each line shift register (SR1 ~ SRn) as shown in Figure 2.
Inventor finds: each shift register in such scheme can only control a grid line, and the wiring space therefore needed is comparatively large, requires wider panel border, is difficult to meet actual design needs, be especially difficult to be applied on undersized panel.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of gate driver circuit and driving method thereof and display device, a shift register can control many grid lines simultaneously, the number of the shift register used reduces, thus reduction wiring space, realize the narrow frame of panel, be particularly useful for undersized panel.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of gate driver circuit, comprising: shift register, also comprises:
One control multiple-unit, for receiving the first pulse signal of described shift register output, and export multiple second pulse signal, described multiple second pulse signal is for driving many grid lines.
The duration of pulse of described multiple second pulse signal is equal.
In a picture frame, the duration of pulse sum of described multiple second pulse signal equals the duration of pulse of described first pulse signal, and the duration of pulse non-overlapping of described multiple second pulse signal.
Alternatively, a described control multiple-unit exports two described second pulse signals, and a described control multiple-unit comprises:
The first film transistor, its source electrode is connected with the output terminal of described shift register, drains to be connected with the odd-numbered line grid line in adjacent two grid lines, and grid receives the first control signal;
Second thin film transistor (TFT), its source electrode is also connected with the output terminal of described shift register, drains to be connected with the even number line grid line in described adjacent two grid lines, and grid receives the second control signal;
3rd thin film transistor (TFT), its source electrode input grounding voltage signal Vss, draining is connected with the even number line grid line in described adjacent two grid lines, and grid receives the first control signal;
4th thin film transistor (TFT), its source electrode is input grounding voltage signal Vss also, drains to be connected with the odd-numbered line grid line in described adjacent two grid lines, and grid receives described second control signal;
Wherein, described first control signal and the second control signal are the clock signal of 2 times that frequency is the clock signal that described shift register uses, and the phase place of described first control signal and the second control signal is opposite each other.
Alternatively, a described control multiple-unit exports two described second pulse signals, and a described control multiple-unit comprises:
5th thin film transistor (TFT), its grid is connected with the output terminal of described shift register, and source electrode inputs the first control signal, drains to be connected with the odd-numbered line grid line in adjacent two grid lines;
6th thin film transistor (TFT), its grid is also connected with the output terminal of described shift register, and source electrode inputs the second control signal, drains to be connected with the even number line grid line in adjacent two grid lines;
Wherein, described first control signal and the second control signal are the clock signal of 2 times that frequency is the clock signal that described shift register uses, and the phase place of described first control signal and the second control signal is opposite each other.
Alternatively, a described control multiple-unit exports three described second pulse signals, and a described control multiple-unit comprises:
7th thin film transistor (TFT), its source electrode is connected with the output terminal of described shift register, drains to be connected with the Article 1 in adjacent three grid lines, and grid receives the 3rd control signal;
8th thin film transistor (TFT), its source electrode is also connected with the output terminal of described shift register, drains to be connected with the Article 2 in described adjacent three grid lines, and grid receives the 4th control signal;
9th thin film transistor (TFT), its source electrode is also connected with the output terminal of described shift register, drains to be connected with the Article 3 in described adjacent three grid lines, and grid receives the 5th control signal;
Tenth thin film transistor (TFT), its source electrode input grounding voltage signal Vss, draining is connected with the Article 2 in described adjacent three grid lines, and grid receives the 3rd control signal;
11 thin film transistor (TFT), its source electrode is input grounding voltage signal Vss also, drains to be connected with the Article 1 in described adjacent three grid lines, and grid receives described 4th control signal;
12 thin film transistor (TFT), its source electrode is input grounding voltage signal Vss also, drains to be connected with the Article 1 in described adjacent three grid lines, and grid receives the 5th control signal;
13 thin film transistor (TFT), its source electrode is input grounding voltage signal Vss also, drains to be connected with the Article 3 in described adjacent three grid lines, and grid receives described 3rd control signal;
14 thin film transistor (TFT), its source electrode is input grounding voltage signal Vss also, drains to be connected with the Article 3 in described adjacent three grid lines, and grid receives described 4th control signal;
15 thin film transistor (TFT), its source electrode is input grounding voltage signal Vss also, drains to be connected with the Article 2 in described adjacent three grid lines, and grid receives the 5th control signal;
Wherein, described 3rd control signal, the 4th control signal and the 5th control signal are the clock signal of 3 times that frequency is the clock signal that described shift register uses, and the phase place of the 4th control signal falls behind 120 degree than described 3rd control signal, the phase place of the 5th control signal also falls behind 120 degree than the 4th control signal.
Gate driver circuit provided by the invention, described gate driver circuit comprises the multiple described shift register of upper and lower cascade, wherein, the output terminal of the described shift register of arbitrary level connects the input end of next stage shift register, and the reset signal input end of the described shift register of arbitrary level connects the output terminal of next stage shift register.
In addition, the present invention also provides a kind of display device, is provided with described arbitrary gate driver circuit.
Corresponding to above-mentioned driving circuit, the present invention also provides a kind of driving method, comprising:
First pulse signal of shift register output is converted into multiple second pulse signal;
Described multiple second pulse signal drives many grid lines respectively.
Alternatively, described multiple second pulse signal drives many grid lines respectively, is specially:
Described multiple second pulse signal is opened successively and is driven many grid lines, or described multiple second pulse signal opens many grid lines simultaneously.
In a picture frame, the duration of pulse sum of described multiple second pulse signal equals the duration of pulse of described first pulse signal, and the duration of pulse non-overlapping of described multiple second pulse signal.
Alternatively, when described first pulse signal is converted into two the second pulse signals, described driving method specifically comprises:
In the first half section of the high level lasting time of described first pulse signal, first control signal opens the first film transistor and the 3rd thin film transistor (TFT), second control signal turns off the second thin film transistor (TFT) and the 4th thin film transistor (TFT), the odd-numbered line grid line of high level in adjacent two grid lines of described the first film transistor input of described first pulse signal, the even number line grid line of described ground voltage signal Vss in the adjacent two articles of grid lines of the 3rd thin film transistor (TFT) input;
In the second half section of the high level lasting time of described first pulse signal, described first control signal turns off the first film transistor and the 3rd thin film transistor (TFT), described second control signal opens the second thin film transistor (TFT) and the 4th thin film transistor (TFT), the even number line grid line of high level in adjacent two grid lines of the second thin film transistor (TFT) input of described first pulse signal, the odd-numbered line grid line of described ground voltage signal Vss in the adjacent two articles of grid lines of the 4th thin film transistor (TFT) input.
Alternatively, when described first pulse signal is converted into two the second pulse signals, described driving method specifically comprises:
In the first half section of the high level lasting time of described first pulse signal, first control signal exports high level, second control signal output low level, the odd-numbered line grid line of the high level that described first control signal exports in the adjacent two articles of grid lines of the 5th thin film transistor (TFT) input, the even number line grid line of the low level that described second control signal exports in the adjacent two articles of grid lines of the 6th thin film transistor (TFT) input;
In the second half section of the high level lasting time of described first pulse signal, first control signal output low level, second control signal exports high level, the odd-numbered line grid line of the low level that described first control signal exports in the adjacent two articles of grid lines of the 5th thin film transistor (TFT) input, the even number line grid line of the high level that described second control signal exports in the adjacent two articles of grid lines of the 6th thin film transistor (TFT) input.
Alternatively, when described first pulse signal is converted into three the second pulse signals, described driving method specifically comprises:
1/3 period before the high level lasting time of described first pulse signal, 3rd control signal opens the 7th, the tenth and the 13 thin film transistor (TFT), 4th control signal shutoff the 8th, the 11 and the 14 thin film transistor (TFT), 5th control signal shutoff the 9th, the 12 and the 15 thin film transistor (TFT), the Article 1 grid line of high level in the adjacent three articles of grid lines of the 7th thin film transistor (TFT) input of described first pulse signal, second, third article grid line of described ground voltage signal Vss respectively in the adjacent three articles of grid lines of the tenth, the 13 thin film transistor (TFT) input;
In second 1/3 period of the high level lasting time of described first pulse signal, 3rd control signal turns off the 7th, tenth and the 13 thin film transistor (TFT), 4th control signal opens the 8th, 11 and the 14 thin film transistor (TFT), 5th control signal turns off the 9th, 12 and the 15 thin film transistor (TFT), the Article 2 grid line of high level in the adjacent three articles of grid lines of the 8th thin film transistor (TFT) input of described first pulse signal, described ground voltage signal Vss is respectively through the 11, in the adjacent three articles of grid lines of 14 thin film transistor (TFT) input first, Article 3 grid line,
In rear 1/3 period of the high level lasting time of described first pulse signal, 3rd control signal turns off the 7th, the tenth and the 13 thin film transistor (TFT), 4th control signal shutoff the 8th, the 11 and the 14 thin film transistor (TFT), 5th control signal unlatching the 9th, the 12 and the 15 thin film transistor (TFT), the Article 3 grid line of high level in the adjacent three articles of grid lines of the 9th thin film transistor (TFT) input of described first pulse signal, first, second article grid line of described ground voltage signal Vss respectively in the adjacent three articles of grid lines of the 12, the 15 thin film transistor (TFT) input.
Gate driver circuit provided by the invention and driving method thereof and display device, one one control multiple-unit is increased by giving each shift register, the pulse signal of shift register output is converted into multiple output of pulse signal, respectively in order to drive many grid lines, make a shift register can control many grid lines simultaneously, greatly reducing the number of shift register, thus reduce wiring space, realize the narrow frame of panel, be particularly useful for undersized panel.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the gate driver circuit that have employed GOA technology in prior art;
Fig. 2 is the sequential chart of existing gate driver circuit;
The structural representation one of gate driver circuit of Fig. 3 for providing in the embodiment of the present invention one;
The structural representation two of the gate driver circuit provided in Fig. 4 embodiment of the present invention one;
Fig. 5 is the gate driver circuit that provides in the embodiment of the present invention two and the multiunit structural representation of one control;
The structural representation of gate driver circuit of Fig. 6 for providing in the embodiment of the present invention two;
The sequential chart of gate driver circuit of Fig. 7 for providing in the embodiment of the present invention two;
Fig. 8 is the another kind of gate driver circuit that provides in the embodiment of the present invention two and the multiunit structural representation of one control;
The structural representation of gate driver circuit of Fig. 9 for providing in the embodiment of the present invention three;
The sequential chart of gate driver circuit of Figure 10 for providing in the embodiment of the present invention three;
The driving method process flow diagram being applicable to driving circuit described in embodiment one that Figure 11 provides for the embodiment of the present invention five;
The driving method process flow diagram being applicable to driving circuit shown in Fig. 5 that Figure 12 provides for the embodiment of the present invention five;
The driving method process flow diagram being applicable to driving circuit shown in Fig. 8 that Figure 13 provides for the embodiment of the present invention five;
The driving method process flow diagram that be applicable to Fig. 9 shown in driving circuit of Figure 14 for providing in the embodiment of the present invention five.
Description of reference numerals
11-shift register, 12-mono-controls multiple-unit.
Embodiment
The embodiment of the present invention provides a kind of gate driver circuit and driving method thereof and display device, can reduce wiring space, realize the narrow frame of panel, be particularly useful for undersized panel.
Below in conjunction with accompanying drawing, the embodiment of the present invention is described in detail.Embodiment described herein only in order to explain the present invention, is not intended to limit the present invention.
Usually, in a picture frame, the drive singal of being defeated by every bar grid line is the signal only including a square-wave pulse, and that is in an image frame, every bar grid line is only driven once, and grid lines all in whole display screen is driven successively according to the mode of lining by line scan from top to bottom; Certainly be not limited to the mode driven successively line by line, also can drive subregion, such as in single pass, driving two rows or more is gone simultaneously, etc.The specific implementation of described gate driver circuit is described with specific embodiment below.
Embodiment one
The embodiment of the present invention provides a kind of gate driver circuit, as shown in Figure 3, comprising: shift register 11, also comprises:
One control multiple-unit 12, for receiving the first pulse signal that described shift register 11 exports, and export multiple second pulse signal, described multiple second pulse signal is for driving many grid lines.
In the present embodiment, by increasing by one one control multiple-unit to shift register, a shift register output pulse signal is converted into multiple output of pulse signal, respectively in order to drive many grid lines, make a shift register can control many grid lines simultaneously, greatly reduce the number of shift register, thus reduce wiring space, be conducive to realizing the narrow frame of panel.
One control multiple-unit 12, is connected with shift register 11 output terminal, and for the first pulse signal received is divided into multiple second pulse signal, its principle and implementation have multiple, and the present embodiment only enumerates following embodiment as example at this.
For the timing graph of described multiple second pulse signal, kinds of schemes can be had.Two the second pulse signals are exported and drive two grid lines are adjacent for a described control multiple-unit, these two second pulse signals can be complementary synchronizing signals, namely one of them second pulse signal is high level within the front semiperiod, it is low level within the later half cycle, another second pulse signal is low level within the front semiperiod, be high level within the later half cycle, two now driven grid lines are driven successively; Also can be the identical signal of sequential of high level, two now driven grid lines be driven simultaneously; Also can be the partly overlapping signal of high level; Above in various situation, the high level lasting time of two the second pulse signals can be equal, also can be unequal.Described two the second pulse signals drive situation during non-conterminous two grid lines to make similar analysis.Certainly, most preferred scheme drives two adjacent grid lines successively, and driven order and the driven sequence consensus of all grid lines on display base plate, and the duration is identical, now image display effect is better.
Therefore preferably, consult shown in Fig. 7, a pulse signal of the first pulse signal (such as OUT12) is converted to the pulse (such as OUT1 and OUT2) in multiple second pulse signal by one control multiple-unit 12, respectively in order to drive many adjacent grid lines, in a picture frame, the duration of pulse sum of multiple second pulse signal, equals the duration of pulse of the first pulse signal; Preferably, the high level lasting time non-overlapping of multiple second pulse signal.
In this embodiment, pulse in first pulse signal of shift register output is changed by one control multiple-unit 12, form multiple second pulse signal, and the second pulse signal described in these is except pulse signal one by one a backward Time constant, frequency, amplitude etc. are all identical.Wherein, specifically how long fall behind one by one, control multiple-unit 12 with one to export how many individual second pulse signals relevant.Preferably, the width (duration of pulse) of mean allocation first pulse signal can be carried out according to the number of the second pulse signal, be the width of the second pulse signal.
Particularly, if the high level lasting time of the first pulse signal (pulse width) is t
0, the cycle is T, if the grid line making shift register wish driving two adjacent during design, then a control multiple-unit 12 exports two the second pulse signals, and the time phase difference t that in these two second pulse signals, pulse occurs
0/ 2, phase place falls behind π t
0/ T.As shown in Figure 7, corresponding in the period continued in the first pulse signal OUT12, two the second pulse signals changed into, (OUT1) signal first half period is high level, the later half period is low level, then the first half period is low level to another (OUT2) signal, and the later half period is high level.Now a control multiple-unit 12, also can be described as control two unit.Similarly, if as shown in Figures 9 and 10, drive 3 grid lines, then a control multiple-unit 12 exports three the second pulse signals, and the time phase difference t that these three the second pulse signal pulses occur
0/ 3, phase place falls behind 2 π t
0/ 3T, now a control multiple-unit 12, also can be described as control three element.
An above-mentioned control multiple-unit 12 is directly connected with grid line, and during other control multiple-unit of no longer connecting, the second pulse signal of output is directly used in driven grid line.But a multiple control multiple-unit 12 of also not getting rid of the present embodiment combines cascade and forms the new multiunit situation of a control, such as, as shown in Figure 4, three one control two element combination cascades form a new control multiple-unit, can control (or driving) 4 grid lines.
Existing shift register output pulse signal, can only carry out charging operations to a grid line, in other words, a shift register can only control the switch of one-row pixels thin film transistor (TFT) TFT; And control multiple-unit 12 by the first pulse signal of shift register output by one in the present embodiment, be converted into multiple second pulse signal, to carry out charging operations to many grid lines, open the pixel TFT switch on many grid lines, greatly can reduce the number of shift register, thus reduce wiring space, realize the narrow frame of panel, be particularly useful for undersized panel, and without the need to changing the indoor design of liquid crystal panel, convenient realization.
Described gate driver circuit comprises the multiple described shift register of upper and lower cascade, wherein, the input end of arbitrary grade of shift register connects the input end of next stage shift register, and the reset signal input end of the described shift register of arbitrary level connects the output terminal of next stage shift register.
Gate driver circuit in the present embodiment, because being provided with a control multiple-unit 12, first pulse signal can be converted into multiple second pulse signal, respectively in order to drive many grid lines, so the number of the shift register used can greatly reduce, thus reduction wiring space, realize the narrow frame of panel, be particularly useful for undersized panel.
Embodiment two
A kind of gate driver circuit of the present invention, another concrete embodiment is as follows:
As shown in Figure 5 and Figure 6, gate driver circuit comprises: shift register 11 and be connected with shift register 11 output terminal one control multiple-unit 12, a described control multiple-unit 12 comprises:
The first film transistor T1, its source electrode is connected with the output terminal of shift register 11, and drain electrode is connected with the odd-numbered line grid line (OUT-O) in adjacent two grid lines, and grid receives the first control signal V1;
Second thin film transistor (TFT) T2, its source electrode is also connected with the output terminal of shift register 11, and drain electrode is connected with the even number line grid line (OUT-E) in adjacent two grid lines, and grid receives the second control signal V2;
3rd thin film transistor (TFT) T3, its source electrode input grounding voltage signal Vss, drain electrode is connected with the even number line grid line (OUT-E) in adjacent two grid lines, and grid receives the first control signal V1;
4th thin film transistor (TFT) T4, its source electrode is input grounding voltage signal Vss also, and drain electrode is connected with the odd-numbered line grid line (OUT-O) in adjacent two grid lines, and grid receives the second control signal V2;
As shown in Figure 7, for the working timing figure of above-mentioned gate driver circuit, wherein, it is the clock signal clk 1 of shift register use and the clock signal of 2 times of CLK2 that the frequency of the first control signal V1 and the second control signal V2 is frequency, and the phase place of the first control signal V1 and the second control signal V2 is opposite each other.Therefore, export in the duration of high level at shift register 11, in the first half section time, first control signal V1 controls the first film transistor T1 wherein and the 3rd thin film transistor (TFT) T3 and opens, second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4 closes, OUT-O is made to export high level, OUT-E output low level; In latter half, second control signal V2 controls the second thin film transistor (TFT) T2 wherein and the 4th thin film transistor (TFT) T4 and opens, and the first film transistor T1 and the 3rd thin film transistor (TFT) T3 closes, and makes OUT-O output low level, OUT-E exports high level, and result makes parity rows light successively.
The present embodiment provides gate driver circuit, is provided with a control multiple-unit 12, the first pulse signal can be converted into two the second pulse signals, respectively in order to drive odd-numbered line in adjacent two grid lines and even number line grid line.Because a shift register can control two adjacent grid lines, so the number of shift register can be reduced to original half, thus greatly reduce wiring space, realize the narrow frame of panel, be particularly useful for undersized panel.
Wherein, described shift register about 11 cascade, wherein, the output of the input access upper level shift register of arbitrary grade of shift register (such as second level SR2), the output terminal of the described shift register of arbitrary level connects the input end of next stage shift register, and the reset signal input end of the described shift register of arbitrary level connects the output terminal of next stage shift register.The input of first order shift register SR1 meets unbalanced pulse signal STV.
As shown in Figure 7, the specific works sequential of whole circuit is as follows:
During t1, unbalanced pulse signal STV=1 maintains high level, export a high level pulse to the input end of first order shift register (SR1), before making SR1 when next pulse arrives, (during t2) opens, and makes the first pulse signal Out12 export high level.
During t2, Out12 exports high level, and the input end in the control multiple-unit 12 that the first row SR1 is connected is high level, due to the first half during t2, first control signal V1 is high level, second control signal V1 is low level, the first film transistor T1 and the 3rd thin film transistor (TFT) T3 is opened, and the second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4 closes, realize the charging to the 1st row grid line, realize the electric discharge to the 2nd row grid line simultaneously, the 1st row is opened, the 2nd row is closed; Later half during t2, first control signal V1 is low level, second control signal V1 is high level, the first film transistor T1 and the 3rd thin film transistor (TFT) T3 is closed, and the second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4 opens, realize the charging to the 2nd row grid line, realize the electric discharge to the 1st row grid line simultaneously, 1st row is closed, and the 2nd row is opened.In addition, during t2, Out12 exports high level to the input end of SR2, and SR2 (during t3) before next pulse arrives is opened, make second level shift register SR2 export high level, the first pulse signal Out34 that namely SR2 exports is now high level.
During t3, Out34 exports a high level to the reset terminal of SR1, and SR1 is resetted.Similar to during t2, a control multiple-unit 12 of the second row makes the first half period the 3rd row during t3 open, and the 4th row is closed, and the later half period during t3 makes the 3rd row close, and the 4th row is opened.In addition, during t3, Out34 also exports high level pulse to the input end of SR3, SR3 (during t4) before next pulse arrives is opened, makes Out56 export high level.
Next postpone successively, to the last a line.The signal (OUT1 ~ OUT6) that final each grid line obtains as shown in Figure 7, can be used for driving each grid line, controls the switch of the pixel TFT on different grid line.
In addition, preferably, the control multiple-unit in the present embodiment also realizes by two thin film transistor (TFT)s, and particularly, as shown in Figure 8, a described control multiple-unit comprises:
5th thin film transistor (TFT), its grid is connected with the output terminal of described shift register, and source electrode inputs the first control signal, drains to be connected with the odd-numbered line grid line in adjacent two grid lines;
6th thin film transistor (TFT), its grid is also connected with the output terminal of described shift register, and source electrode inputs the second control signal, drains to be connected with the even number line grid line in adjacent two grid lines;
Wherein, the first control signal used is with the second control signal with described identical above, and namely frequency is the clock signal of 2 times of the clock signal that shift register uses, and the phase place of the first control signal and the second control signal is opposite each other, concrete to do process roughly similar, repeats no longer one by one.
Gate driver circuit described in the present embodiment, each shift register can drive two adjacent grid lines, therefore can reduce the number of shift register, reduces wiring space, thus realizes the narrow frame of panel, be particularly useful for undersized panel.
Embodiment three
A kind of gate driver circuit of the present invention, as shown in Figure 9, another concrete embodiment is as follows:
Described gate driver circuit comprises: shift register 11 and be connected with shift register 11 output terminal one control multiple-unit 12, difference is, a described control multiple-unit 12 comprises:
7th thin film transistor (TFT) T7, its source electrode is connected with the output terminal of shift register 11, and drain electrode is connected with the Article 1 (OUT_1) in adjacent three grid lines, and grid receives the 3rd control signal V3;
8th thin film transistor (TFT) T8, its source electrode is also connected with the output terminal of shift register 11, and drain electrode is connected with the Article 2 (OUT_2) in adjacent three grid lines, and grid receives the 4th control signal V4;
9th thin film transistor (TFT) T9, its source electrode is also connected with the output terminal of shift register 11, and drain electrode is connected with the Article 3 (OUT_3) in adjacent three grid lines, and grid receives the 5th control signal V5;
Tenth thin film transistor (TFT) T10, its source electrode input grounding voltage signal Vss, drain electrode is connected with the Article 2 (OUT_2) in adjacent three grid lines, and grid receives the 3rd control signal V3;
11 thin film transistor (TFT) T11, its source electrode is input grounding voltage signal Vss also, and drain electrode is connected with the Article 1 (OUT_1) in adjacent three grid lines, and grid receives the 4th control signal V4;
12 thin film transistor (TFT) T12, its source electrode is input grounding voltage signal Vss also, and drain electrode is connected with the Article 1 (OUT_1) in described adjacent three grid lines, and grid receives the 5th control signal V5;
13 thin film transistor (TFT) T13, its source electrode is input grounding voltage signal Vss also, and drain electrode is connected with the Article 3 (OUT_3) in adjacent three grid lines, and grid receives the 3rd control signal V3;
14 thin film transistor (TFT) T14, its source electrode is input grounding voltage signal Vss also, and drain electrode is connected with the Article 3 (OUT_3) in adjacent three grid lines, and grid receives the 4th control signal V4;
15 thin film transistor (TFT) T15, its source electrode is input grounding voltage signal Vss also, and drain electrode is connected with the Article 2 (OUT_2) in described adjacent three grid lines, and grid receives the 5th control signal V5;
Wherein, as shown in Figure 10, it is the clock signal clk 1 of shift register 11 use and the clock signal of 3 times of CLK2 that 3rd control signal V3, the 4th control signal V4 and the 5th control signal V5 are frequency, and the phase place of the 4th control signal V4 falls behind 120 degree than the 3rd control signal V3, the phase place of the 5th control signal V5 also falls behind 120 degree than the 4th control signal V4.
The gate driver circuit that the present embodiment provides, be provided with a control multiple-unit 12, first pulse signal can be converted into three the second pulse signals, respectively in order to drive three adjacent grid lines, the number of the shift register therefore used can be reduced to original 1/3rd, thus greatly reduce wiring space, realize the narrow frame of panel, be particularly useful for undersized panel.
Wherein, the upper and lower cascade of described shift register, wherein, the output terminal of the described shift register of arbitrary level connects the input end of next stage shift register, and the reset signal input end of the described shift register of arbitrary level connects the output terminal of next stage shift register.
The course of work and embodiment two roughly similar, the control signal V3 of front 1/3 period the 3rd of each CLK pulse is high level, 4th control signal V4 and the 5th control signal V5 is low level, T7, T10 and T13 are opened, all the other 6 closedowns, Out1 is held and exports high level, Out2 and Out3 holds output low level.Centre 1/3 period the 4th control signal V4 of each CLK pulse is high level, 3rd control signal V3 and the 5th control signal V5 is low level, and TFT pipe T8, T11 and T14 are opened, all the other 6 closedowns, Out2 is held and exports high level, Out1 and Out3 holds output low level.The control signal V5 of rear 1/3 period the 5th of each CLK pulse is high level, 4th control signal V4 and the 3rd control signal V3 is low level, and TFT pipe T9, T12 and T15 are opened, all the other 6 closedowns, Out3 is held and exports high level, Out2 and Out1 holds output low level.
Gate driver circuit described in the present embodiment, each shift register can drive three adjacent grid lines, therefore the number of shift register can be reduced, reduce wiring space, thus realize the narrow frame of panel, be particularly useful for undersized panel, and can realize without the need to the indoor design changing panel, implement very convenient.
Embodiment four
The embodiment of the present invention additionally provides a kind of display device, is provided with any one gate driver circuit described in above-described embodiment.Described display device can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The display device that the present embodiment provides, each shift register in the gate driver circuit of use can drive many grid lines, and the wiring space of needs is little, and panel border therefore can be made to narrow further.
Embodiment five
The embodiment of the present invention provides a kind of driving method, and be applicable to the driving circuit (as shown in Figure 3) described in embodiment one, as shown in figure 11, the method comprises:
Step 101, the first pulse signal of shift register output is converted into multiple second pulse signal;
Step 102, described multiple second pulse signal drive many grid lines respectively.
Multiple second pulse signal described in the present embodiment is opened successively and is driven many grid lines (line by line successively type of drive), or described multiple second pulse signal opens many grid lines (subregion type of drive) simultaneously.
In a picture frame, the duration of pulse of the first pulse signal described in the duration of pulse sum of described multiple second pulse signal, and the duration of pulse non-overlapping of multiple second pulse signal.
Driving method described in the present embodiment, make each shift register can drive many grid lines, therefore the number of shift register can be reduced, reduce wiring space, thus realize the narrow frame of panel, be particularly useful for undersized panel, and can realize without the need to the indoor design changing panel, implement very convenient.
Particularly, with reference to figure 5 ~ 7, when described first pulse signal is converted into two the second pulse signals, described driving method as shown in figure 12, comprising:
201, in the first half section of the high level lasting time of the first pulse signal, first control signal V1 opens the first film transistor T1 and the 3rd thin film transistor (TFT) T3, second control signal V2 turns off the second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4 simultaneously, the high level of the first pulse signal inputs the odd-numbered line grid line OUT-O in adjacent two grid lines through the first film transistor T1, ground voltage signal Vss inputs the even number line grid line OUT-E in adjacent two articles of grid lines through the 3rd thin film transistor (TFT) T3;
202, in the second half section of the high level lasting time of the first pulse signal, first control signal V1 turns off the first film transistor T1 and the 3rd thin film transistor (TFT) T3, second control signal V2 opens the second thin film transistor (TFT) T2 and the 4th thin film transistor (TFT) T4, the high level of the first pulse signal inputs the even number line grid line OUT-E in adjacent two grid lines through the second thin film transistor (TFT) T2, ground voltage signal Vss inputs the odd-numbered line grid line OUT-O in adjacent two articles of grid lines through the 4th thin film transistor (TFT) T4.
Above-mentioned driving method is applicable to the first gate driver circuit described in embodiment two (as Suo Shi Fig. 5 ~ 6), each shift register can be made can to drive two adjacent grid lines, the specific works process of gate driver circuit did detailed description in embodiment two, did not repeat them here.
Particularly, when the first pulse signal is converted into two the second pulse signals, also realize by driving circuit shown in Fig. 8, now the driving method of this driving circuit as shown in figure 13, specifically comprises:
Step 301, first half section at the high level lasting time of the first pulse signal, first control signal V1 exports high level, second control signal V2 output low level, the high level that first control signal V1 exports inputs the odd-numbered line grid line OUT-O in adjacent two articles of grid lines through the 5th thin film transistor (TFT) T5, and the low level that the second control signal V2 exports inputs the even number line grid line OUT-E in adjacent two articles of grid lines through the 6th thin film transistor (TFT) T6;
Step 302, second half section at the high level lasting time of the first pulse signal, first control signal V1 output low level, second control signal V2 exports high level, the low level that first control signal V1 exports inputs the odd-numbered line grid line OUT-O in adjacent two articles of grid lines through the 5th thin film transistor (TFT) T5, and the high level that the second control signal V2 exports inputs the even number line grid line OUT-E in adjacent two articles of grid lines through the 6th thin film transistor (TFT) T6.
In driving circuit shown in Fig. 8, the grid of the first pulse signal input the 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6, in the high level lasting time of therefore the first pulse signal, 5th thin film transistor (TFT) T5 and the 6th thin film transistor (TFT) T6 is all in conducting state, in the first half section of high level lasting time, first control signal V1 exports high level to odd-numbered line grid line OUT-O, and the second control signal V2 is to even number line grid line OUT-E output low level; In the second half section of high level lasting time, the first control signal V1 is to odd-numbered line grid line OUT-O output low level, and the second control signal V2 exports high level to even number line grid line OUT-E.Odd-numbered line OUT-O in adjacent two grid lines and even number line grid line OUT-E is driven successively.
Driving method described in the present embodiment can make each shift register drive two adjacent grid lines, and only employ two thin film transistor (TFT)s, therefore wiring space can be reduced, thus realize the narrow frame of panel, be particularly useful for undersized panel, and can realize without the need to the indoor design changing panel, implement very convenient.
Particularly, with reference to figure 9 ~ 10, when described first pulse signal is converted into three the second pulse signals, described driving method as shown in figure 14, comprising:
Step 401, 1/3 period before the high level lasting time of described first pulse signal, 3rd control signal V3 opens the 7th, tenth and the 13 thin film transistor (TFT) (T7, T10 and T13), 4th control signal V4 turns off the 8th, 11 and the 14 thin film transistor (TFT) (T8, T11 and T14), 5th control signal V5 turns off the 9th, 12 and the 15 thin film transistor (TFT) (T9, T12 and T15), the high level of the first pulse signal inputs the Article 1 grid line OUT_1 in adjacent three articles of grid lines through the 7th thin film transistor (TFT) T7, described ground voltage signal Vss is respectively through the tenth, 13 thin film transistor (TFT) (T10, T13) second in adjacent three grid lines are inputted, Article 3 grid line (OUT_2 and OUT_3),
Step 402, in second 1/3 period of the high level lasting time of the first pulse signal, 3rd control signal V3 turns off the 7th, tenth and the 13 thin film transistor (TFT) (T7, T10 and T13), 4th control signal V4 opens the 8th, 11 and the 14 thin film transistor (TFT) (T8, T11 and T14), 5th control signal V5 turns off the 9th, 12 and the 15 thin film transistor (TFT) (T9, T12 and T15), the high level of the first pulse signal inputs the Article 2 grid line OUT_2 in adjacent three articles of grid lines through the 8th thin film transistor (TFT) T8, ground voltage signal Vss is respectively through the 11, 14 thin film transistor (TFT) (T11, T14) first in adjacent three grid lines are inputted, Article 3 grid line (OUT_1 and OUT_3),
Step 403, in rear 1/3 period of the high level lasting time of the first pulse signal, 3rd control signal V3 turns off the 7th, tenth and the 13 thin film transistor (TFT) (T7, T10 and T13), 4th control signal V4 turns off the 8th, 11 and the 14 thin film transistor (TFT) (T8, T11 and T14), 5th control signal opens the 9th, 12 and the 15 thin film transistor (TFT) (T9, T12 and T15), the high level of the first pulse signal inputs the Article 3 grid line OUT_3 in adjacent three articles of grid lines through the 9th thin film transistor (TFT) T9, ground voltage signal Vss is respectively through the 12, 15 thin film transistor (TFT) (T12, T15) first in adjacent three grid lines are inputted, Article 2 grid line (OUT_1 and OUT_2).
Above-mentioned driving method is applicable to the first gate driver circuit (as shown in Figure 9) described in embodiment three, each shift register can be made can to drive three adjacent grid lines, the specific works process of gate driver circuit did detailed description in embodiment two, did not repeat them here.
Driving method described in the present embodiment, each shift register can be made can to drive many grid lines, therefore the number of shift register can be reduced, reduce wiring space, thus realize the narrow frame of panel, be particularly useful for undersized panel, and can realize without the need to the indoor design changing panel, implement very convenient.
Technical characteristic described in the embodiment of the present invention, when not conflicting, can combinationally use arbitrarily mutually.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection domain of claim.
Claims (9)
1. a gate driver circuit, comprises shift register, it is characterized in that, also comprises:
One control multiple-unit, for receiving the first pulse signal of described shift register output, and export multiple second pulse signal, described multiple second pulse signal is for driving many grid lines;
A described control multiple-unit exports two described second pulse signals, and a described control multiple-unit comprises:
5th thin film transistor (TFT), its grid is connected with the output terminal of described shift register, and source electrode inputs the first control signal, drains to be connected with the odd-numbered line grid line in adjacent two grid lines,
6th thin film transistor (TFT), its grid is also connected with the output terminal of described shift register, and source electrode inputs the second control signal, drains to be connected with the even number line grid line in adjacent two grid lines,
Wherein, described first control signal and the second control signal are the clock signal of 2 times that frequency is the clock signal that described shift register uses, and the phase place of described first control signal and the second control signal is opposite each other.
2. gate driver circuit according to claim 1, is characterized in that,
The duration of pulse of described multiple second pulse signal is equal.
3. gate driver circuit according to claim 1 or 2, is characterized in that,
In a picture frame, the duration of pulse sum of described multiple second pulse signal equals the duration of pulse of described first pulse signal, and the duration of pulse non-overlapping of described multiple second pulse signal.
4. a gate driver circuit, comprises shift register, it is characterized in that, also comprises:
One control multiple-unit, for receiving the first pulse signal of described shift register output, and export multiple second pulse signal, described multiple second pulse signal is for driving many grid lines;
A described control multiple-unit exports three described second pulse signals, and a described control multiple-unit comprises:
7th thin film transistor (TFT), its source electrode is connected with the output terminal of described shift register, drains to be connected with the Article 1 in adjacent three grid lines, and grid receives the 3rd control signal,
8th thin film transistor (TFT), its source electrode is also connected with the output terminal of described shift register, drains to be connected with the Article 2 in described adjacent three grid lines, and grid receives the 4th control signal,
9th thin film transistor (TFT), its source electrode is also connected with the output terminal of described shift register, drains to be connected with the Article 3 in described adjacent three grid lines, and grid receives the 5th control signal,
Tenth thin film transistor (TFT), its source electrode input grounding voltage signal Vss, draining is connected with the Article 2 in described adjacent three grid lines, and grid receives the 3rd control signal,
11 thin film transistor (TFT), its source electrode also receives ground voltage signal Vss, drains to be connected with the Article 1 in described adjacent three grid lines, and grid receives described 4th control signal,
12 thin film transistor (TFT), its source electrode also receives ground voltage signal Vss, drains to be connected with the Article 1 in described adjacent three grid lines, and grid receives the 5th control signal,
13 thin film transistor (TFT), its source electrode also receives ground voltage signal Vss, drains to be connected with the Article 3 in described adjacent three grid lines, and grid receives described 3rd control signal,
14 thin film transistor (TFT), its source electrode also receives ground voltage signal Vss, drains to be connected with the Article 3 in described adjacent three grid lines, and grid receives described 4th control signal,
15 thin film transistor (TFT), its source electrode also receives ground voltage signal Vss, drains to be connected with the Article 2 in described adjacent three grid lines, and grid receives the 5th control signal,
Wherein, described 3rd control signal, the 4th control signal and the 5th control signal are the clock signal of 3 times that frequency is the clock signal that described shift register uses, and the phase place of the 4th control signal falls behind 120 degree than described 3rd control signal, the phase place of the 5th control signal also falls behind 120 degree than the 4th control signal.
5. the gate driver circuit according to any one of claim 1,2,4, it is characterized in that, described gate driver circuit comprises the multiple described shift register of upper and lower cascade, wherein, the output terminal of the described shift register of arbitrary level connects the input end of next stage shift register, and the reset signal input end of the described shift register of arbitrary level connects the output terminal of next stage shift register.
6. a display device, is characterized in that, is provided with the gate driver circuit described in any one of claim 1-5.
7. a grid drive method, is characterized in that, comprising: the first pulse signal of shift register output is converted into multiple second pulse signal, and described multiple second pulse signal drives many grid lines respectively;
When described first pulse signal is converted into two the second pulse signals, described driving method specifically comprises:
In the first half section of the high level lasting time of described first pulse signal, first control signal exports high level, second control signal output low level, the odd-numbered line grid line of the high level that described first control signal exports in the adjacent two articles of grid lines of the 5th thin film transistor (TFT) input, the even number line grid line of the low level that described second control signal exports in the adjacent two articles of grid lines of the 6th thin film transistor (TFT) input;
In the second half section of the high level lasting time of described first pulse signal, first control signal output low level, second control signal exports high level, the odd-numbered line grid line of the low level that described first control signal exports in the adjacent two articles of grid lines of the 5th thin film transistor (TFT) input, the even number line grid line of the high level that described second control signal exports in the adjacent two articles of grid lines of the 6th thin film transistor (TFT) input.
8. method according to claim 7, is characterized in that, described method also comprises:
In a picture frame, the duration of pulse sum of described multiple second pulse signal is made to equal the duration of pulse of described first pulse signal, and the duration of pulse non-overlapping of described multiple second pulse signal.
9. a grid drive method, is characterized in that, comprising: the first pulse signal of shift register output is converted into multiple second pulse signal, and described second pulse signal drives many grid lines respectively;
When described first pulse signal is converted into three the second pulse signals, described driving method specifically comprises:
1/3 period before the high level lasting time of described first pulse signal, 3rd control signal opens the 7th, tenth and the 13 thin film transistor (TFT), 4th control signal turns off the 8th, 11 and the 14 thin film transistor (TFT), 5th control signal turns off the 9th, 12 and the 15 thin film transistor (TFT), the Article 1 grid line of high level in the adjacent three articles of grid lines of the 7th thin film transistor (TFT) input of described first pulse signal, ground voltage signal Vss inputs the Article 2 grid line in described adjacent three articles of grid lines and the Article 3 grid line in the described adjacent three articles of grid lines of the 13 thin film transistor (TFT) input through the tenth thin film transistor (TFT),
In second 1/3 period of the high level lasting time of described first pulse signal, 3rd control signal turns off the 7th, tenth and the 13 thin film transistor (TFT), 4th control signal opens the 8th, 11 and the 14 thin film transistor (TFT), 5th control signal turns off the 9th, 12 and the 15 thin film transistor (TFT), the Article 2 grid line of high level in the described adjacent three articles of grid lines of the 8th thin film transistor (TFT) input of described first pulse signal, described ground voltage signal Vss inputs the Article 1 grid line in described adjacent three articles of grid lines and the Article 3 grid line in the described adjacent three articles of grid lines of the 14 thin film transistor (TFT) input through the 11 thin film transistor (TFT) respectively,
In rear 1/3 period of the high level lasting time of described first pulse signal, 3rd control signal turns off the 7th, tenth and the 13 thin film transistor (TFT), 4th control signal turns off the 8th, 11 and the 14 thin film transistor (TFT), 5th control signal opens the 9th, 12 and the 15 thin film transistor (TFT), the Article 3 grid line of high level in the described adjacent three articles of grid lines of the 9th thin film transistor (TFT) input of described first pulse signal, described ground voltage signal Vss inputs the Article 1 grid line in described adjacent three articles of grid lines and the Article 2 grid line in the described adjacent three articles of grid lines of the 15 thin film transistor (TFT) input through the 12 thin film transistor (TFT).
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