CN113035110B - Gate drive circuit and display device - Google Patents
Gate drive circuit and display device Download PDFInfo
- Publication number
- CN113035110B CN113035110B CN202110317855.7A CN202110317855A CN113035110B CN 113035110 B CN113035110 B CN 113035110B CN 202110317855 A CN202110317855 A CN 202110317855A CN 113035110 B CN113035110 B CN 113035110B
- Authority
- CN
- China
- Prior art keywords
- signal
- stage
- signal generating
- module
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
Abstract
The application provides a gate drive circuit and display device, wherein, the gate drive circuit includes multistage signal generation module and multistage signal output module, signal output module includes the first signal switch group of multiunit, multistage signal generation module is through the first signal switch group cross connection in proper order that corresponds, constitute multistage aversion gate drive circuit, the signal generation module of second level is used for triggering the first signal switch group of multiunit that this level connects respectively in proper order to the signal generation module of last level and opens, make the multichannel line scanning signal of the signal generation module of first level feed back to every gate line by line, realize line by line scanning drive, cross connection through multistage signal generation module and switch element, the structure of gate drive circuit has been simplified, design cost has been reduced and manufacturing process has been simplified simultaneously.
Description
Technical Field
The application belongs to the technical field of grid driving, and particularly relates to a grid driving circuit and a display device.
Background
At present, a conventional gate driving circuit is provided with N shift registers arranged in sequence, where the N shift registers are correspondingly connected to N scan lines of a display panel, and output row scan signals to sequentially turn on pixel units in each row.
However, the gate driving circuit needs one shift register for driving each row of pixel units, resulting in high cost and complicated manufacturing process.
Disclosure of Invention
The present application provides a gate driving circuit, which aims to solve the problems of high cost and complex manufacturing process of the conventional gate driving circuit.
A first aspect of an embodiment of the present application provides a gate driving circuit, which is applied to a display panel, and includes a multi-level signal generating module and a multi-level signal outputting module; the multi-stage signal output modules are connected between the signal generation module of the first stage and a plurality of gate lines of the display panel; the signal generating modules from the second stage to the last stage are respectively connected to the signal output modules at all stages one by one and used for triggering the signal output modules at all stages to be started so that the multi-path line scanning signals of the signal generating modules at the first stage are fed back to the gate lines line by line;
the signal generation module comprises a plurality of signal generation ends for circularly outputting line scanning signals; the signal output module comprises a plurality of groups of first signal switch groups, and each first signal switch group comprises a controlled end, a plurality of signal input ends and a plurality of signal output ends in one-to-one butt joint with the plurality of signal input ends;
a plurality of controlled ends of the plurality of groups of first signal switch groups are respectively connected to a plurality of signal generating ends of a signal generating module for triggering the signal output module to be started one by one; a plurality of signal input ends of each group of first signal switch groups in the signal output module of the first stage are respectively connected to a plurality of signal generation ends of the signal generation module of the first stage one by one; a plurality of signal input ends of each group of first signal switch groups in each signal output module from the second stage to the last stage are respectively connected with a plurality of signal output ends of the signal output module at the last stage one by one; and a plurality of signal output ends of the signal output module of the last stage are respectively connected to the plurality of gate lines one by one.
In one embodiment, the number of stages of the signal generation module is greater than or equal to 3.
In one embodiment, the frequency ratio of the line scanning signals of the two signal generation modules of the previous stage and the next stage is n 1: 1, n1 is the number of groups of the plurality of first signal switch groups connected with two signal generation modules of adjacent stages.
In one embodiment, the signal generation module of each stage includes a plurality of first shift registers connected in sequence, signal terminals of the plurality of first shift registers form a plurality of signal generation terminals of the signal generation module, and the plurality of first shift registers are configured to sequentially output line scanning signals according to a start signal and a clock pulse signal cycle.
In one embodiment, each stage of the signal generation module comprises a first signal generation unit, a second signal generation unit and a plurality of second signal switch groups;
the second signal switch group comprises a controlled end, a plurality of signal input ends and a plurality of signal output ends which are in one-to-one butt joint with the signal input ends;
the signal generating module comprises a first signal switch group, a second signal switch group, a plurality of signal output ends and a plurality of signal generating ends, wherein the signal generating ends of the first signal switch group are respectively connected with the signal generating ends of the first signal generating unit one by one, the signal generating ends of the second signal switch group are respectively connected to the controlled ends of the second signal switch group one by one, and the signal output ends of the second signal switch group form the signal generating ends of the signal generating module.
In one embodiment, the number of stages of the signal generation module is greater than or equal to 2.
In one embodiment, the first signal switch group includes a plurality of first switch units, each first switch unit includes a signal input end, a signal output end corresponding to the signal input end one by one, and a controlled end, and the controlled ends of the first switch units are connected together to form the controlled end of the first signal switch group;
the second signal switch group comprises a plurality of second switch units, each second switch unit comprises a signal input end, a signal output end and a controlled end, the signal output ends correspond to the signal input ends in a one-to-one mode, and the controlled ends of the second switch units are connected together to form the controlled end of the second signal switch group.
In one embodiment, a frequency ratio of the line scanning signals of the first signal generation unit and the second signal generation unit of each stage of the signal generation module is n 2: 1, n2 is the number of groups of the plurality of second signal switch groups connected to the two signal generating units.
In one embodiment, the first signal generation unit includes a plurality of sequentially connected second shift registers, and the second signal generation unit includes a plurality of sequentially connected third shift registers;
the second shift registers are used for outputting line scanning signals to a plurality of signal input ends of the second signal switch groups which are connected in sequence according to a starting signal and a clock pulse signal cycle;
and the third shift registers are used for sequentially outputting line scanning signals to a plurality of controlled ends of the second signal switch groups which are connected according to a starting signal and a clock pulse signal cycle.
A second aspect of the embodiments of the present application provides a display device, which includes a display panel, a timing controller, a source driver circuit, and the gate driver circuit described above, wherein the timing controller is respectively connected to the source driver circuit and the gate driver circuit, the source driver circuit is connected to a plurality of data lines of the display panel, and the gate driver circuit is connected to a plurality of gate lines of the display panel.
Compared with the prior art, the embodiment of the application has the advantages that: the gate driving circuit is provided with the multi-level signal generating modules and the multi-level signal output modules, each signal output module comprises a plurality of groups of first signal switch groups, the multi-level signal generating modules are sequentially connected in a cross mode through the corresponding first signal switch groups to form the multi-level shifting gate driving circuit, the signal generating modules from the second level to the last level are used for sequentially triggering the plurality of groups of first signal switch groups connected in the current level to be started respectively, multi-path line scanning signals of the signal generating modules in the first level are fed back to each gate line by line, line by line scanning driving is achieved, cross connection of the multi-level signal generating modules and the switch units is achieved, the structure of the gate driving circuit is simplified, design cost is reduced, and meanwhile manufacturing process is simplified.
Drawings
Fig. 1 is a schematic diagram of a first structure of a gate driving circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a second structure of a gate driving circuit according to an embodiment of the present disclosure;
FIG. 3 is a waveform diagram of a row scanning signal in the gate driving circuit shown in FIG. 1;
fig. 4 is a schematic diagram of a third structure of a gate driving circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a first structure of a signal generating module according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a second structure of a signal generating module according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a third signal generating module according to an embodiment of the present application;
fig. 8 is a schematic diagram illustrating a fourth structure of a signal generating module according to an embodiment of the present application;
fig. 9 is a schematic diagram of a fifth structure of a signal generating module according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a driving device according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
A first aspect of the embodiments of the present application provides a gate driving circuit 100, which is applied to a display panel 1.
As shown in fig. 1, in the present embodiment, the gate driving circuit 100 includes a multi-stage signal generating module 10 and a multi-stage signal outputting module 110.
The multi-stage signal output module 110 is connected between the first stage signal generation module 10 and a plurality of gate lines of the display panel 1; the signal generating modules 10 from the second stage to the last stage are respectively connected to the signal output modules 110 at each stage one by one, and are used for triggering the signal output modules 110 at each stage to start so that the multi-path line scanning signals of the signal generating modules 10 at the first stage are fed back to a plurality of gate lines line by line;
the signal generating module 10 includes a plurality of signal generating terminals for cyclically outputting the horizontal scanning signals; the signal output module 110 includes a plurality of first signal switch sets 111, where the first signal switch set 111 includes a controlled end, a plurality of signal input ends, and a plurality of signal output ends in one-to-one butt joint with the plurality of signal input ends;
a plurality of controlled terminals of the plurality of first signal switch groups 111 are respectively connected to a plurality of signal generating terminals of the signal generating module 10 for triggering the signal output module 110 to be turned on; a plurality of signal input ends of each first signal switch group 111 in the first-stage signal output module 110 are respectively connected to a plurality of signal generation ends of the first-stage signal generation module 10 one by one; a plurality of signal input ends of each first signal switch group 111 in each signal output module 110 from the second stage to the last stage are respectively connected to a plurality of signal output ends of the signal output module 110 at the last stage one by one; the signal output terminals of the last stage of the signal output module 110 are respectively connected to the gate lines one by one.
In this embodiment, the multiple line scanning signals of the first-stage signal generation module 10 are cyclically output as the line scanning signals finally output to the gate lines of the display panel 1, so as to implement line-by-line driving, the second-stage to last-stage signal generation module 10 is also used for outputting multiple line scanning signals, and is used for triggering the signal switch groups in the signal output modules 110 connected at different levels to be sequentially turned on or off, so as to output the multiple line scanning signals of the first-stage signal generation module 10 to the display panel 1, and the signal generation module 10 implements multi-stage displacement combination to form multiple signal output ends, without setting multiple shift registers equal to the number of the gate lines of the display panel 1, thereby simplifying the line structure of the gate driving circuit 100 and reducing the design cost.
Wherein, the number of stages of the signal generating module 10 and the signal outputting module 110 is set correspondingly according to the number of gate lines of the display panel 1, the multi-stage signal outputting module 110 realizes the step-by-step cross connection of the signal generating ends of the plurality of signal generating modules 10, the signal outputting module 110 includes a plurality of groups of first signal switch groups 111, the number of the plurality of signal input ends of each first signal switch group 111 in the signal outputting module 110 is equal and set in parallel, the plurality of signal input ends of each group of first signal switch groups 111 are respectively connected with the plurality of signal output ends of the signal outputting module 110 of the previous stage or the plurality of signal output ends of the signal generating module 10 of the first stage one by one.
For example, as shown in fig. 1, the signal output module 110 of the first stage includes three first signal switch groups 111, the first signal switch group 111 of the first stage includes three signal input terminals X1, X2, and X3, the first signal switch group 111 of the second stage includes three signal input terminals X4, X5, and X6, the first signal switch group 111 of the third stage includes three signal input terminals X7, X8, and X9, the signal input terminals X1, X4, and X7 are connected in parallel and connected to one of the signal output terminals of the signal output module 110 of the previous stage or one of the signal generation terminals of the signal generation module 10 of the first stage, the signal input terminals X2, X5, and X8 are connected in parallel and connected to one of the signal output terminals of the signal output module 110 of the previous stage or one of the signal generation terminals of the signal generation module 10 of the first stage, and the signal input terminals X3, X6, and X9 are connected in parallel and connected to one of the signal output terminals of the signal output module 110 of the previous stage or one of the signal generation module 10 of the first stage or one of the first stage The signal generating terminals are connected.
Meanwhile, the controlled terminals of each group of the first signal switch groups 111 are respectively connected to the signal generating terminals of the corresponding signal generating modules 10, and are sequentially turned on or off in the whole group, so that the received line scanning signal is transmitted to the next-stage signal generating module 10, and the number of the groups of the first signal switch groups 111 of the signal output module 110 is equal to the number of the signal generating terminals of the correspondingly connected signal generating modules 10 for controlling on/off.
For example, as shown in fig. 2, when the display panel 1 is provided with 27 rows, that is, 27 gate lines, it can be divided into 3 x3 according to the decomposition of the row number, that is, the signal generating module 10 of the first stage is provided with signal generating terminals a, b, c, the signal generating module 10 of the second stage is provided with three signal generating terminals d, e, f, the signal generating module 10 of the third stage is provided with three signal generating terminals x, y, z, the signal generating module 10 of the first stage and the signal generating module 10 of the second stage are cross-connected through three first signal switch sets 111 of the signal output module 110 of the first stage, the signal generating module 10 of the second stage and the signal generating module 10 of the third stage are cross-connected through three first signal switch sets 111 of the signal output module 110 of the second stage, and finally 27 signal output terminals are formed and are connected to the gate lines of the display panel 1 one by one, the three signal generating terminals of the first-stage signal generating module 10 sequentially cycle for 9 times, and finally sequentially output 27 line scanning signals to the gate lines of the display panel 1 to realize line-by-line scanning, wherein the cycle output frequency of the line scanning signals of the signal generating terminals of the first-stage signal generating module 10 is equal to the product of the number of the plurality of signal generating terminals of each stage of signal generating module 10 at the rear end.
The number of stages of the signal generating module 10 is set correspondingly according to the number of rows of the display panel 1 and the hierarchical requirement, wherein the total product of the number of the finally formed signal generating ends is greater than or equal to the number of the gate lines of the display panel 1, in one embodiment, the number of stages of the signal generating module 10 is greater than or equal to 3, and each stage of the signal generating module 10 can select a signal generator or is formed by cascading a corresponding number of shift registers, and the specific structure is not limited.
For example, when 1080 lines are provided on the display panel 1, the arrangement of the signal generating terminals divided into three stages of 10 × 11 (equal to 1100) or the arrangement of the signal generating terminals divided into four stages of 5 × 6 (equal to 1080) may be selected, and the signal generating modules 10 having three or more stages are provided to realize the stepwise cross connection, thereby reducing the number of shift registers and reducing the design cost.
Meanwhile, the frequency of the line scanning signals output by each stage is set correspondingly according to the connection position and the conduction sequence, and in one embodiment, the frequency ratio of the line scanning signals of two signal generation modules 10 of adjacent stages is n: 1, n1 is the number of sets of the plurality of first signal switch groups 111 connected to the two signal generation modules 10 of the adjacent stages.
For example, as shown in fig. 2 and fig. 3, the waveforms of the line scanning signals of the signal generating terminals a, b, and c in the signal generating module 10 of the first stage are the same and are sequentially set with the same phase difference, the waveforms of the line scanning signals of the signal generating terminals d, e, and f in the signal generating module 10 of the second stage are the same and are sequentially set with the same phase difference, the waveforms of the line scanning signals of the signal generating terminals x, y, and z in the signal generating module 10 of the third stage are the same and are sequentially set with the same phase difference, the frequency ratio of the line scanning signal of the signal generating module 10 of the second stage to the line scanning signal of the signal generating module 10 of the first stage is the number of sets of the first signal switch sets 111 of the signal outputting module 110 of the first stage, that is, the number of the signal generating terminals 3 of the signal generating module 10 of the second stage, and the frequency ratio of the line scanning signal of the signal generating module 10 of the third stage to the line scanning signal generating module 10 of the second stage is the signal outputting module 110 of the second stage The number of the first signal switch groups 111 of 110 is equal to 3, the number of the signal generating terminals of the signal generating module 10 of the third stage is sequentially and circularly output, the signal generating terminals a, b, c in the signal generating module 10 of the first stage are sequentially and circularly output, the signal output terminals d, e, f of the second stage and the signal output terminals x, y, z of the third stage are used for controlling the opening of the first signal switch groups 111, the signal output terminals a, b, c are conducted by combining the corresponding signal switch groups in the rear stage, and when each stage has a high level at the same time, a row scanning signal is output to each gate line, so that row scanning driving is realized.
As shown in fig. 4, when the display panel 1 has 16 rows, the gate driving circuit 100 has four stages, that is, four signal generating modules 10 are provided, the signal generating module 10 of the first stage has a signal generating terminal a1/a2, the signal generating module 10 of the second stage has a signal generating terminal B1/B2, the signal generating module 10 of the third stage has a signal generating terminal C1/C2, the signal generating module 10 of the fourth stage has a signal generating terminal D1/D2, the signal generating module 10 of the first stage is cross-connected with 2 first signal switch sets 111 of the signal outputting module 110 of the first stage to form four signal output terminals, the four signal output terminals are cross-connected with two first signal switch sets 111 of the signal outputting module 110 of the next stage to form 8 signal output terminals, the 8 signal output terminals are cross-connected with two first signal switch sets 111 of the signal outputting module 11011C of the next stage, 16 signal output terminals are formed and are connected with the gate lines of the display panel 1 one by one, the line scanning signals in the signal output terminals a1/a2 are output in a cycle, and the frequency ratio of the line scanning signals of each stage is 8: 4: 2: 1, the ratio is the number of the first signal switch group 111 of the rear-stage signal output module 110.
As can be seen from the above analysis, in this embodiment, the gate driving can be completed only by arranging the plurality of signal generating modules 10 and the corresponding first signal switch groups 111, and there is no need to arrange shift registers having the same number as that of the gate lines, thereby reducing the design cost.
Each stage of the signal generating module 10 may select a signal generator, or may be composed of a corresponding number of shift registers cascaded, and the specific structure is not limited, each first signal switch group 111 may include a plurality of switch units, the number of switch units of each first signal switch group 111 is correspondingly set according to the number of signal generating terminals of each signal generating module 10 to form a cross-connection structure, as shown in fig. 4, in an embodiment, the first signal switch group 111 includes a plurality of first switch units K11, each first switch unit K11 includes a signal input terminal, a signal output terminal corresponding to the signal input terminal one by one and a controlled terminal, the controlled terminals of each first switch unit K11 are connected in parallel to form a controlled terminal of the first signal switch group 111, each first switch unit K11 in each first signal switch group 111 is connected in parallel to each first switch unit K11 in another first signal switch group 111 in another group in the same signal output module 110, thereby forming a signal input end with the same amount as the signal generation end of the connected signal generation module 10 or the signal output end of the previous stage signal output module 110, and simultaneously, the controlled ends of the first switch units K11 in the same first signal switch group 111 are connected in parallel to realize synchronous on or off, and according to the frequency ratio of the signal generation module 10, the first switch units K11 are turned on according to a preset time sequence, so as to sequentially output a plurality of line scanning signals of the first signal generation module 10 to each gate line of the display panel 1.
As shown in fig. 5, in one embodiment, the signal generation module 10 of each stage includes a plurality of first shift registers U1 connected in sequence, signal terminals of the plurality of first shift registers U1 form a plurality of signal generation terminals of the signal generation module 10, and the plurality of first shift registers U1 are configured to sequentially output the line scan signals according to a start signal and a clock signal cycle.
In this embodiment, the same number of first shift registers are arranged according to the number of signal generating terminals required by each stage of signal generating module 10, for example, the first stage of signal generating module needs 4 signal generating terminals, then 4 first shift registers are arranged in the first stage of signal generating module, and so on, the signal terminal of each first shift register is used as one of the signal generating terminals of the signal generating module 10, and the plurality of shift registers output line by line according to the received start signal STV and clock pulse signal CLK, so as to sequentially output n line scanning signals to the plurality of groups of first signal switch groups 111 at the subsequent stage and output in cooperation with the shift register groups in the subsequent stage of signal generating module 10, and finally cyclically output a plurality of line scanning signals to each gate line of the display panel 1, so as to perform line-by-line start control on the display panel 1.
As shown in fig. 6, in one embodiment, each stage signal generation module 10 includes a first counter U21 and a first decoder U31;
the first counter U21 is used for sequentially outputting a plurality of preset system count values according to the clock pulse signal and circulating;
the first decoder U31 is configured to perform decoding conversion on the count value in the preset scale and sequentially output the line scanning signals with the preset voltage to the plurality of signal generating terminals of the signal generating module 10 at each stage in a circulating manner.
In this embodiment, to simplify the structure of the signal generating module 10, the signal generating module 10 is composed of a first counter U21 and a first decoder U31, the first counter U21 counts the rising edges of the clock signal CLK, the clock value is increased by 1 every time a rising edge is detected, when the rising edge is counted to a preset value, the clock value is reset to zero and counted again, a cycle detection count is realized, and a corresponding count value is fed back to the first decoder U31, the first decoder U31 sequentially cycles on the output channels IO1 to IOn according to the size of the count value fed back by the cycle, and outputs N line scan signals to the signal input end or the controlled end of each first signal switch group 111 through the output channels IO1 to IOn in a cycle manner, so as to output N line scan signals to N gate lines of the display panel 1, wherein the output channel in the first decoder U31 forms a mapping relationship with the count value, one count value corresponds to one output channel, only one output channel is switched on at the same time, and a voltage signal is output, so that line-by-line switching-on is realized.
As shown in fig. 7, in one embodiment, each stage of the signal generation module 10 includes a first signal generation unit 11, a second signal generation unit 12, and a plurality of second signal switch groups 31;
the second signal switch group 31 comprises a controlled terminal, a plurality of signal input terminals and a plurality of signal output terminals in one-to-one butt joint with the plurality of signal input terminals;
a plurality of signal input terminals of the second signal switch group 31 are respectively connected with the signal generating terminals of the first signal generating unit 11 one by one, a plurality of signal generating terminals of the second signal generating unit 12 are respectively connected to the controlled terminals of the second signal switch groups 31 one by one, and a plurality of signal output terminals of the second signal switch groups 31 form a plurality of signal generating terminals of the signal generating module 10.
In this embodiment, two signal generating units are grouped into one signal generating module 10 in pairs to realize nested connection, and a plurality of signal generating terminals of two signal generating units in a group are cross-connected through a plurality of second signal switch groups 31, and a plurality of signal generating terminals formed by adjacent signal generating modules 10 are cross-connected through a plurality of first switch units K11, for example, as shown in fig. 8, a first signal generating unit 11 of a first signal generating module 10 has a signal generating terminal a/b, a second signal generating unit 12 of the first signal generating module 10 has a signal generating terminal c/d, two signal generating units are cross-connected through two second signal switch groups 31, and signal generating terminals f/e and x/y of two signal generating units in a signal generating module 10 at the next stage are cross-connected through two second signal switch groups 31, finally, 4 signal generating ends respectively formed by the two signal generating modules 10 are cross-connected through 4 groups of first signal switch units, 16 signal output ends are formed to be connected with the gate lines of the display panel 1 or the signal input ends of the next-stage multiple groups of first signal switch groups 111 one by one, and finally, a plurality of signal output ends are formed to be connected with the gate lines of the display panel 1 one by one to realize line-by-line driving.
Two signal generating units are arranged in each stage of signal generating module 10, the signal generating modules 10 of adjacent stages are nested one by one, so that multiple groups of nesting are realized, the number of required switches is small, the more stages of the signal generating modules 10 needing to be shifted are, and the fewer the number of switches of multi-stage nesting simplification is.
In this embodiment, the number of the signal generating units is an even number and is greater than or equal to 4, and two pairs of the signal generating units form the first-stage signal generating module 10 in one group, therefore, the number of stages of the signal generating module 10 is greater than or equal to 2, and the number of stages of the signal generating module 10 is correspondingly set according to the number of rows of the display panel 1 and the grading requirement, wherein the number of the finally formed signal output ends is greater than or equal to the number of the gate lines of the display panel 1, and the step-by-step cross nested connection is realized by setting the signal generating units more than four stages, so that the number of the shift registers is reduced, and the design cost is reduced.
The second signal switch group 31 may employ the same components as the first signal switch group 111, in an embodiment, the second signal switch group 31 includes a plurality of second switch units K21, each second switch unit K21 includes a signal input end, a signal output end and a controlled end corresponding to the signal input end one by one, the controlled ends of the second switch units K21 are connected in common to form the controlled end of the second signal switch group 31, the second switch units K21 are turned on or off according to the row scanning signal of the signal generating end of the signal generating unit, the same operation manner as the first switch units K11, the controlled ends of the second switch units K21 in the same group are connected in parallel and synchronously turned on or off, so as to output the row scanning signal received by the signal input end to each first switch unit K11 in the signal output module 110 in the next stage row by row, and finally output the row scanning signal to each gate line of the display panel 1, line-by-line driving is realized.
Meanwhile, the duty ratios of the line scanning signals output by each stage are correspondingly set according to the connection positions and the conduction sequence, and in one embodiment, the frequency ratio of the line scanning signals of the first signal generating unit 11 and the second signal generating unit 12 of each stage of the signal generating module 10 is n 2: 1, n2 is the number of sets of the plurality of second signal switch sets 31 connected to the two signal generating units.
Taking fig. 8 as an example, the first signal generating unit 11 of the first signal generating module 10 has a signal generating terminal a/b, the second signal generating unit 12 of the first signal generating module 10 has a signal generating terminal c/d, the line scanning signal of the signal generating terminal c/d is used to turn on or off the connected 4 second switch units K21, and the frequency ratio of the line scanning signal of the signal generating terminal a/b to the line scanning signal of the output terminal c/d is 2: 1, that is, the number of the current second signal switch groups 31, two second switch units K21 controlled by the signal generating terminal c are turned on in advance, at this time, the line scanning signal output by the first signal generating unit 11 is output through two second switch units K21 controlled by the signal generating terminal c, then, two second switch units K21 controlled by the signal generating terminal d are turned on again, the line scanning signal output by the first signal generating unit 11 circulates through two second switch units K21 controlled by the signal generating terminal d to output line-by-line, thereby implementing line-by-line output, and similarly, the frequency ratio of the line scanning signals of the signal generating terminals f/e and x/y is 2: 1, the line scanning signals of the four signal generating terminals of the first-stage signal generating module 10 and the four signal output terminals of the second-stage signal generating module 10 are 4: 1 is the number of signal output terminals of the second signal generating module 10.
As shown in fig. 8, in one embodiment, the first signal generating unit 11 includes a plurality of sequentially connected second shift registers U2, and the second signal generating unit 12 includes a plurality of sequentially connected third shift registers U3;
a plurality of second shift registers U2 for outputting line scanning signals to a plurality of signal input terminals of a plurality of second signal switch groups 31 connected in sequence according to a start signal and a clock pulse signal cycle;
and the plurality of third shift registers U3 are configured to output the line scanning signals to the plurality of controlled terminals of the plurality of connected second signal switch groups 31 sequentially according to the start signal and the clock pulse signal cycle.
In this embodiment, the signal generating units are minimum execution units, and the same number of second shift registers or third shift registers may be arranged according to the number of signal generating terminals required for each stage, for example, if the first signal generating unit 11 in the first-stage signal generating module 10 needs 4 signal generating terminals, 4 second shift registers U2 are arranged in the first signal generating unit 11 in the first-stage signal generating module 10, and 4 signal generating terminals are required in the second signal generating unit 12 in the first-stage signal generating module 10, 4 third shift registers U2 are arranged in the second signal generating unit 12 in the first-stage signal generating module 10, and two shift registers respectively output row scanning signals and respectively output to the second switch units K21 in the connected sets of second signal switch sets 31, so as to implement synchronous turn-on or turn-off of the second switch units K21 in a switch set manner, the first signal generating unit 11 in the first-stage signal generating module 10 outputs line scanning signals in a circulating manner, and finally outputs the line scanning signals output by the first signal generating unit 11 in the first-stage signal generating module 10 line by line, so that n line scanning signals are sequentially output to the subsequent first signal switch group 111 and are output in cooperation with the subsequent shift register group, and finally a plurality of line scanning signals are output to each gate line of the display panel 1 to perform line-by-line on control on the display panel 1.
In order to realize bidirectional scan driving, in one embodiment, each shift register is a bidirectional shift register.
When the signal generating module 10 is used as a minimum execution unit, a counter and a decoder may be used, and similarly, when the signal generating module 10 is used as a minimum execution unit, a counter and a decoder may also be used, and the first signal generating unit 11 and the second signal generating unit 12 each include a second counter U22 and a second decoder;
the second counter U22 is used for sequentially outputting a plurality of preset system count values according to the clock pulse signal and circulating;
and the second decoder U32 is configured to perform decoding conversion on the count value in the preset scale and output the line scanning signals with the preset voltage to the signal input ends or the controlled ends of the connected second signal switch groups 31 in a cyclic and sequential manner.
In this embodiment, in order to simplify the structure of the signal generating module 10, the signal generating unit is composed of a second counter U22 and a second decoder U32, the second counter U22 counts the rising edges of the clock signal CLK, the clock value is increased by 1 every time a rising edge is detected, when the rising edge is counted to a preset value, the clock value is reset to zero and counted again, a cyclic detection count is realized, and a corresponding count value is fed back to the second decoder U32, the second decoder U32 sequentially and cyclically turns on the output channels IO1 to IOn according to the size of the cyclically fed back count value, and n line scan signals are cyclically output to the second switch units K21 in the second signal switch groups 31 through the output channels IO1 to IOn, wherein the output channel in the second decoder U32 forms a mapping relationship with the count value, one count value corresponds to one output channel, only one output channel is turned on at the same time, and one voltage signal is output, and realizing line-by-line starting.
The line scanning signals output by the second decoder U32 of the first signal generating unit 11 of the first signal generating module 10 are cyclically output to finally output N line scanning signals to N gate lines of the display panel 1, the line scanning signals output by the second decoder U32 of the second signal generating unit 12 of the first signal generating module 10 are used to trigger the connected second switch units, the second decoders U32 of the first signal generating units 11 of the other signal generating modules 10 are used to trigger the first signal switch group 111, and the second decoders U32 of the second signal generating units 11 of the other signal generating modules 10 are used to trigger the second signal switch group 31.
Meanwhile, as the minimum execution unit, the two signal generation units in the signal generation module 10 may also respectively adopt different structures, in an embodiment, the first signal generation unit 11 includes a plurality of shift registers connected in sequence, the second signal generation unit 12 includes a counter and a decoder, or the second signal generation unit 12 includes a plurality of second shift registers U2 connected in sequence, the first signal generation unit 11 includes a counter and a decoder, the plurality of shift registers sequentially output line scanning signals to a plurality of signal input ends or a plurality of controlled ends of the plurality of second signal switch groups 31 connected in sequence according to a start signal and a clock pulse signal cycle, the counter sequentially outputs a plurality of count values of a preset system according to the clock pulse signal cycle, and the decoder decodes and converts the count value of the preset system and sequentially outputs the line scanning signals of the preset voltage magnitude to a plurality of controlled ends or controlled ends of the plurality of second signal switch groups 31 connected in cycle The specific structures of the plurality of signal input ends, the first signal generating unit 11 and the second signal generating unit 12 can be correspondingly arranged according to requirements.
Compared with the prior art, the embodiment of the application has the advantages that: the gate driving circuit 100 is provided with the multi-level signal generating modules 10, the multi-level signal generating modules 10 are sequentially connected in a cross manner through the corresponding switch units to form the multi-level shifted gate driving circuit 100, the second-level signal generating module 10 to the last-level signal generating module 10 are used for respectively triggering the switch units of the controlled nodes connected in the current level to be turned on in sequence, so that the multi-path line scanning signals of the first-level signal generating module 10 are fed back to each gate line by line, line by line scanning driving is realized, the structure of the gate driving circuit 100 is simplified through the cross connection of the multi-level signal generating modules 10 and the switch units, the design cost is reduced, and meanwhile, the manufacturing process is simplified.
As shown in fig. 8, the present application further provides a display device, which includes a display panel 1, a timing controller 300, a source driving circuit 200, and a gate driving circuit 100, and the specific structure of the gate driving circuit 100 refers to the above embodiments, and since the display device adopts all the technical solutions of all the above embodiments, the display device at least has all the beneficial effects brought by the technical solutions of the above embodiments, and no further description is provided herein. The timing controller 300 is respectively connected to the source driving circuit 200 and the gate driving circuit 100, the source driving circuit 200 is connected to a plurality of data lines of the display panel 1, and the gate driving circuit 100 is connected to a plurality of gate lines of the display panel 1.
In this embodiment, the timing controller 300, the source driving circuit 200, and the gate driving circuit 100 form a driving device 2 of the display panel for driving the display panel 1 to operate, and the timing controller 300 converts a data signal, a control signal, and a clock signal received from the outside into a data signal, a control signal, and a clock signal suitable for the gate driving circuit 100 and the source driving circuit 200, thereby realizing image display of the display panel 1.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (9)
1. A gate driving circuit is applied to a display panel and is characterized by comprising a multi-stage signal generating module and a multi-stage signal output module; the multi-stage signal output modules are connected between the signal generation module of the first stage and a plurality of gate lines of the display panel; the signal generating modules from the second stage to the last stage are respectively connected to the signal output modules at all stages one by one and used for triggering the signal output modules at all stages to be started so that the multi-path line scanning signals of the signal generating modules at the first stage are fed back to the gate lines line by line;
the signal generation module comprises a plurality of signal generation ends for circularly outputting line scanning signals; the signal output module comprises a plurality of groups of first signal switch groups, and each first signal switch group comprises a controlled end, a plurality of signal input ends and a plurality of signal output ends in one-to-one butt joint with the plurality of signal input ends;
a plurality of controlled ends of the plurality of groups of first signal switch groups are respectively connected to a plurality of signal generating ends of a signal generating module for triggering the signal output module to be started one by one; a plurality of signal input ends of each group of first signal switch groups in the signal output module of the first stage are respectively connected to a plurality of signal generation ends of the signal generation module of the first stage one by one; a plurality of signal input ends of each group of first signal switch groups in each signal output module from the second stage to the last stage are respectively connected with a plurality of signal output ends of the signal output module at the last stage one by one; a plurality of signal output ends of the signal output module of the last stage are respectively connected to the plurality of gate lines one by one;
the frequency ratio of the line scanning signals of the two signal generation modules of the previous stage and the next stage is n 1: 1, n1 is the number of groups of the plurality of first signal switch groups connected with two signal generation modules of adjacent stages.
2. The gate driving circuit of claim 1, wherein the number of stages of the signal generation module is equal to or greater than 3.
3. The gate driving circuit according to claim 1, wherein the signal generation module of each stage includes a plurality of first shift registers connected in sequence, signal terminals of the plurality of first shift registers constitute a plurality of signal generation terminals of the signal generation module, and the plurality of first shift registers are configured to sequentially output the line scanning signal according to a start signal and a clock signal cycle.
4. A gate driving circuit as claimed in claim 1, wherein each stage of the signal generation module includes a first signal generation unit, a second signal generation unit, and a plurality of second signal switch sets;
the second signal switch group comprises a controlled end, a plurality of signal input ends and a plurality of signal output ends which are in one-to-one butt joint with the signal input ends;
the signal generating module comprises a first signal switch group, a second signal switch group, a plurality of signal output ends and a plurality of signal generating ends, wherein the signal generating ends of the first signal switch group are respectively connected with the signal generating ends of the first signal generating unit one by one, the signal generating ends of the second signal switch group are respectively connected to the controlled ends of the second signal switch group one by one, and the signal output ends of the second signal switch group form the signal generating ends of the signal generating module.
5. The gate driving circuit of claim 4, wherein the number of stages of the signal generation module is 2 or more.
6. The gate driving circuit according to claim 4, wherein the first signal switch group comprises a plurality of first switch units, each first switch unit comprises a signal input end, a signal output end corresponding to the signal input end and a controlled end, and the controlled ends of the first switch units are connected together to form the controlled end of the first signal switch group;
the second signal switch group comprises a plurality of second switch units, each second switch unit comprises a signal input end, a signal output end and a controlled end, the signal output ends correspond to the signal input ends in a one-to-one mode, and the controlled ends of the second switch units are connected together to form the controlled end of the second signal switch group.
7. The gate driving circuit according to claim 4, wherein a frequency ratio of the line scanning signals of the first signal generating unit and the second signal generating unit of each stage of the signal generating module is n 2: 1, n2 is the number of groups of the plurality of second signal switch groups connected to the two signal generating units.
8. The gate drive circuit according to claim 4, wherein the first signal generation unit includes a plurality of second shift registers connected in sequence, and the second signal generation unit includes a plurality of third shift registers connected in sequence;
the second shift registers are used for outputting line scanning signals to a plurality of signal input ends of the second signal switch groups which are connected in sequence according to a starting signal and a clock pulse signal cycle;
and the third shift registers are used for sequentially outputting line scanning signals to a plurality of controlled ends of the second signal switch groups which are connected according to a starting signal and a clock pulse signal cycle.
9. A display device comprising a display panel, a timing controller, a source driving circuit and a gate driving circuit according to claim 8, wherein the timing controller is connected to the source driving circuit and the gate driving circuit, the source driving circuit is connected to a plurality of data lines of the display panel, and the gate driving circuit is connected to a plurality of gate lines of the display panel.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110317855.7A CN113035110B (en) | 2021-03-25 | 2021-03-25 | Gate drive circuit and display device |
| PCT/CN2021/142160 WO2022199182A1 (en) | 2021-03-25 | 2021-12-28 | Gate driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110317855.7A CN113035110B (en) | 2021-03-25 | 2021-03-25 | Gate drive circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113035110A CN113035110A (en) | 2021-06-25 |
| CN113035110B true CN113035110B (en) | 2022-01-14 |
Family
ID=76473949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110317855.7A Active CN113035110B (en) | 2021-03-25 | 2021-03-25 | Gate drive circuit and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113035110B (en) |
| WO (1) | WO2022199182A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113035110B (en) * | 2021-03-25 | 2022-01-14 | 惠科股份有限公司 | Gate drive circuit and display device |
| CN114203124B (en) * | 2021-11-30 | 2023-03-17 | 重庆惠科金渝光电科技有限公司 | Gate driving method, gate driving circuit and display |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010091968A (en) * | 2008-10-10 | 2010-04-22 | Seiko Epson Corp | Scanning line drive circuit and electro-optical device |
| CN102881248A (en) * | 2012-09-29 | 2013-01-16 | 京东方科技集团股份有限公司 | Grid driving circuit and driving method thereof and display device |
| CN102982777A (en) * | 2012-12-07 | 2013-03-20 | 京东方科技集团股份有限公司 | Grid driving circuit of display device, switch control circuit and shifting register |
| CN103106881A (en) * | 2013-01-23 | 2013-05-15 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| CN105702189A (en) * | 2014-11-26 | 2016-06-22 | 群创光电股份有限公司 | Scanning driver circuit and display panel employing same |
| CN107799070A (en) * | 2017-12-08 | 2018-03-13 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display device and grid drive method |
| CN109410810A (en) * | 2017-08-16 | 2019-03-01 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103680439B (en) * | 2013-11-27 | 2016-03-16 | 合肥京东方光电科技有限公司 | A kind of gate driver circuit and display device |
| CN108682396B (en) * | 2018-06-13 | 2020-05-15 | 北京大学深圳研究生院 | Shift register and gate driving device |
| CN110136663A (en) * | 2019-04-08 | 2019-08-16 | 昆山龙腾光电有限公司 | Gate driving circuit and display device |
| CN113035110B (en) * | 2021-03-25 | 2022-01-14 | 惠科股份有限公司 | Gate drive circuit and display device |
-
2021
- 2021-03-25 CN CN202110317855.7A patent/CN113035110B/en active Active
- 2021-12-28 WO PCT/CN2021/142160 patent/WO2022199182A1/en unknown
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010091968A (en) * | 2008-10-10 | 2010-04-22 | Seiko Epson Corp | Scanning line drive circuit and electro-optical device |
| CN102881248A (en) * | 2012-09-29 | 2013-01-16 | 京东方科技集团股份有限公司 | Grid driving circuit and driving method thereof and display device |
| CN102982777A (en) * | 2012-12-07 | 2013-03-20 | 京东方科技集团股份有限公司 | Grid driving circuit of display device, switch control circuit and shifting register |
| CN103106881A (en) * | 2013-01-23 | 2013-05-15 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| CN105702189A (en) * | 2014-11-26 | 2016-06-22 | 群创光电股份有限公司 | Scanning driver circuit and display panel employing same |
| CN109410810A (en) * | 2017-08-16 | 2019-03-01 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, gate driving circuit and display device |
| CN107799070A (en) * | 2017-12-08 | 2018-03-13 | 京东方科技集团股份有限公司 | Shift register, gate driving circuit, display device and grid drive method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022199182A1 (en) | 2022-09-29 |
| CN113035110A (en) | 2021-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113035110B (en) | Gate drive circuit and display device | |
| CN106652867B (en) | Shifting register unit, grid driving circuit and display panel | |
| CN108877624B (en) | Special-shaped display panel and display device | |
| US10580361B2 (en) | Organic light-emitting display panel and organic light-emitting display device | |
| CN107025872B (en) | Shifting register unit, grid driving circuit and display device | |
| US6239781B1 (en) | Gray-scale signal generating circuit and liquid crystal display | |
| CN113035111B (en) | Gate drive circuit, drive device and display device | |
| US11361696B2 (en) | Shift register and driving method therefor, gate driver circuit, and display device | |
| CN113066417B (en) | Gate drive circuit, drive device and display device | |
| CN108831369B (en) | Display panel and driving method | |
| CN102214428B (en) | Gate driving circuit and driving method therefor | |
| CN113554970B (en) | GOA driving circuit, display panel and display device | |
| US7499517B2 (en) | Shift register and shift register set using the same | |
| CN112164364A (en) | Driving circuit of display panel, display panel and driving method thereof | |
| US7656381B2 (en) | Systems for providing dual resolution control of display panels | |
| US6765980B2 (en) | Shift register | |
| CN112865805B (en) | Data transmission circuit, display device and data transmission method | |
| US7053943B2 (en) | Scanning circuit, and imaging apparatus having the same | |
| KR970067084A (en) | Signal line driving circuit | |
| CN102170532B (en) | The driving method of potting gum driving method, drive circuit and device for pixel combination | |
| CN113129842A (en) | Drive board, backlight drive circuit and backlight system | |
| US4121197A (en) | Matrix circuit for an electrostatic recording device comprising cross-point elements for driving each pair of control electrodes on a common matrix conductor | |
| CN203118406U (en) | Display panel drive device | |
| CN113658535B (en) | Scan control driver and display device | |
| CN111883075A (en) | Panel driving circuit, method and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |