CN105702189A - Scanning driver circuit and display panel employing same - Google Patents
Scanning driver circuit and display panel employing same Download PDFInfo
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- CN105702189A CN105702189A CN201410696717.4A CN201410696717A CN105702189A CN 105702189 A CN105702189 A CN 105702189A CN 201410696717 A CN201410696717 A CN 201410696717A CN 105702189 A CN105702189 A CN 105702189A
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Abstract
The invention provides a scanning driver circuit and a display panel employing the same. The scanning driver circuit comprises multiple stages of first driver units which are controlled by a first start signal, a pulse signal and at least one selection signal, wherein the ith-stage first driver unit includes a shift register and a de-multiplexer. The shift register generates a scanning signal according to a pulse signal and a trigger signal. The de-multiplexer selectively outputs the scanning signal to multiple scanning lines according to the at least one selection signal. The trigger signal of the first-stage first driver unit is the first start signal, and the trigger signal of the (i+1)th-stage first driver unit is the scanning signal of the ith-stage first driver unit.
Description
Technical field
The invention relates to a kind of scan drive circuit and apply its display floater, and in particular to a kind of scan drive circuit utilizing de-multiplexer。
Background technology
Along with development in science and technology, current display floater has been widely used in various electronic installation, for instance mobile phone, TV, computer screen etc.。In response to the high-res demand of display floater, generally coordinate data drive circuit with scan drive circuit, to write the image information of whole picture。On the other hand, in order to save the printed circuit board (PCB) cost of outside, utilize the thin film transistor (TFT) (ThinFilmTransistor on panel, TFT), by the partial scan drive circuit in order to drive scanning line, when thin film transistor (TFT) array makes, being formed in the lump on the substrate of display floater, this technology can be described as the display floater of GOP (GateonPanel) technology。So, external scan drive circuit complexity and volume can be simplified, panel production cost can be reduced simultaneously。And how effectively to reduce area shared by scan drive circuit, become one of problem that current industry endeavours。
Summary of the invention
The present invention proposes a kind of scan drive circuit and applies its display floater, and particularly a kind of scan drive circuit utilizing de-multiplexer。
According to the first aspect of the invention, it is proposed to a kind of scan drive circuit。Scan drive circuit includes multistage first driver element。Multistage first driver element is controlled by the first initial signal, clock signal and at least one selection signal, and wherein i-stage the first driver element includes a shift register and a de-multiplexer。Shift register is according to clock signal and triggers signal generation scanning signal。De-multiplexer, will scanning signal-selectivity output extremely multiple scanning lines according at least one selection signal。Wherein the triggering signal of the 1st grade of the first driver element is the first initial signal, and the triggering signal of (i+1) level the first driver element is the scanning signal of i-stage the first driver element。
According to the second aspect of the invention, it is proposed to a kind of display floater, including thin-film transistor array base-plate, the first viewing area and scan drive circuit。First viewing area is formed on thin-film transistor array base-plate, and the first viewing area includes multiple first row image element circuit。Scan drive circuit includes multistage first driver element。Multistage first driver element is controlled by the first initial signal, clock signal and at least one selection signal, and wherein i-stage the first driver element includes a shift register and a de-multiplexer。Shift register is according to clock signal and triggers signal generation scanning signal。De-multiplexer according at least one selection signal, will scanning signal-selectivity output to multiple scanning lines, each scanning line driving first row image element circuit one of them。Wherein the triggering signal of the 1st grade of the first driver element is the first initial signal, and the triggering signal of (i+1) level the first driver element is the scanning signal of i-stage the first driver element。
Accompanying drawing explanation
For the above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated, wherein:
Figure 1A illustrates the schematic diagram of known display floater。
Figure 1B illustrates the signal timing diagram of known display floater。
Fig. 2 is shown according to the schematic diagram of first embodiment of the invention display floater。
Fig. 3 is shown according to the circuit framework figure of de-multiplexer in first embodiment of the invention display floater。
Fig. 4 A is shown according to the signal timing diagram in first embodiment of the invention display floater。
Fig. 4 B illustrates the signal timing diagram of progressive scan。
Fig. 5 is shown according to the schematic diagram of first embodiment of the invention write picture data。
Fig. 6 is shown according to the schematic diagram of second embodiment of the invention display floater。
Fig. 7 is shown according to the schematic diagram of second embodiment of the invention write picture data。
Fig. 8 illustrates the schematic diagram of a kind of external control circuit。
Fig. 9 A is shown according to the schematic diagram of third embodiment of the invention display floater。
Fig. 9 B is shown according to the schematic diagram of fourth embodiment of the invention display floater。
Figure 10 A and Figure 10 B is shown according to the schematic diagram of the de-multiplexer that fourth embodiment of the invention uses。
Figure 11 is shown according to the signal timing diagram in fourth embodiment of the invention display floater。
Figure 12 illustrates the circuit framework figure of shift register。
In figure, element numbers illustrates:
2,6,9: display floater
20,60,90: thin-film transistor array base-plate
21,61,91: scan drive circuit
22,62,92: the first viewing area
62 ': the second viewing area
80: mnemon
82: comparing unit
84: control unit
C1: electric capacity
C (1), C (2): compensate signal
Com (1)～Com (2n): compensating line
CKV: clock signal
Databus: data/address bus
DM (1), DM (2), DM ' (1), DM ' (2), DMc (1), DMc (2): de-multiplexer
F01～F04, F11～F20: picture
R (1)～R (2n): first row image element circuit
R (h+1)～R (h+2n): secondary series image element circuit
S (1), S (2), S ' (1), S ' (2): scanning signal
Scan (1)～Scan (2n): scanning line
Selector, Sel1, nSel1, Sel2, nSel2, Sel3, nSel3, Sel4, nSel14: select signal
SD (1), SD (2), SD ' (1), SD ' (2): the first drive circuit
SR (1), SR (2), SR ' (1), SR ' (2), SRc (1), SRc (2): shift register
STV: initial signal
STV1: the first initial signal
STV2: the second initial signal
STVc: compensate initial signal
T1～T8, T11～T16: transistor
VGL: blanking voltage current potential
Detailed description of the invention
Illustrate the schematic diagram of known display floater please also refer to Figure 1A and Figure 1B, Figure 1A, Figure 1B illustrates the sequencing contro figure of known display floater。Display floater 1 includes M row image element circuit (ROW) R (1)～R (M), for instance be equal to 960 for the display floater 1, M that resolution is 1280x960。The scan drive circuit of display floater 1 includes M shift register (ShiftRegister, SR) SR (1)～SR (M), M shift register is controlled by identical clock signal CKV, and the shift register SR (1) of the 1st grade receives the first initial signal STV1 to determine to proceed by the time of scanning。Owing to M shift register SR is one another in series, when the positive edge of clock signal CKV occurs, the pulse of initial signal STV can one-level one-level down shift, and is referred to Figure 1B each shift register SR (1)～SR (M) illustrated scanning signal Scan (1)～Scan (M) exported。Scanning signal Scan (i) drives row image element circuit R (i), so that the i-th row of display floater 1 can accept data the data that driver (for simplicity, not being illustrated in figure) writes。As shown in Figure 1B, display floater 1 is to write image data in the way of scanning by column, and after the M scanning through a picture (frame) arranges, again triggers initial signal STV, to re-start scanning by column。
Scan drive circuit such as Figure 1A depicted, for each row image element circuit, all need a corresponding shift register, and these shift registers can GOP technology be formed in the TFT substrate of display floater 1, or being present in grid integrated circuits drives in element (gatedriverIC), in this way by too big for circuit layout (layout) area that causes shared by scan drive circuit。Following example separately propose a kind of scan drive circuit that can effectively reduce circuit layout area。
Fig. 2 is shown according to the schematic diagram of first embodiment of the invention display floater。Display floater 2 includes thin-film transistor array base-plate 20, scan drive circuit 21 and the first viewing area 22。First viewing area 22 is formed on thin-film transistor array base-plate 20, including multiple first rows image element circuit R (1), and R (2) ...。Scan drive circuit 21 is formed on thin-film transistor array base-plate 20, including multistage first driver element SD (1), SD (2) ..., it is controlled by the first initial signal STV1, clock signal CKV and at least one selection signal Selector。Wherein i-stage the first driver element SD (i) includes shift register SR (i) and a de-multiplexer (De-multiplexer, DEMUX) DM (i)。Shift register SR (i) is according to clock signal CKV and triggers signal generation scanning signal S (i)。De-multiplexer DM (i) according at least one selection signal Selector, will scanning signal S (i) selectivity output to multiple scanning line Scan, each scanning line Scan drive first row image element circuit R one of them。Wherein the triggering signal of the 1st grade of first driver element SD (1) is the first initial signal STV1, the triggering signal of (i+1) level the first driver element SD (i+1) is scanning signal S (i) of i-stage the first driver element SD (i), and i is the positive integer more than or equal to 1。Describe in detail as follows。
In the embodiment of the present invention, available GOP technology realizes drive circuit 21 with thin film transistor (TFT) (TFT), scan drive circuit 21 is formed on thin-film transistor array base-plate 20, or drive circuit 21 is arranged in grid integrated circuits and drives element (gatedriverIC)。Scan drive circuit 21 received signal, including clock signal CKV, the first initial signal STV1, selects signal Selector, it is possible to the printed circuit board (PCB) beyond thin-film transistor array base-plate 20, for instance provided by specific drive integrated circult。
Below using the 1st grade of first driver element SD (1) as explanation。1st grade of first driver element SD (1) can only use 1 shift register SR (1) to coordinate 1 de-multiplexer DM (1), to produce to drive the signal of n scanning line Scan (1)～Scan (n)。N scanning line Scan (1)～Scan (n) may be used to drive n row image element circuit R (1)～R (n) of the first viewing area 22。De-multiplexer DM (1) is according at least one selection signal Selector, scanning signal S (1) selectivity output is extremely scanned line Scan (1)～Scan (n), for n=4, scanning signal S (1) can be exported to scanning line Scan (2) by de-multiplexer DM (1) according at least one selection signal Selector (such as selected is the 2nd bar of scanning line), and other non-selected 3 scannings line Scan (1), Scan (3) and Scan (4), then can give a blanking voltage current potential VGL, row image element circuit R (2) so can be made to be written into data, row image element circuit R (1), the switch keeping cut-off state of R (3) and R (4) is without being written into data。
Fig. 3 illustrates one can realize the circuit framework figure of de-multiplexer DM (1)。This example is use 1 de-multiplexer (n=4) to 4, de-multiplexer DM (1) includes 8 TFTT1～T8, signal Sel1, nSel1, Sel2 is selected according to 8, nSel2, Sel3, nSel3, Sel4, nSel4, to scanning line Scan (1)～Scan (4) selectivity output scanning signal S (1) respectively and blanking voltage current potential VGL one of them。Wherein selecting signal nSel1 is the inversion signal selecting signal Sel1, and all the other are by that analogy。When being logic high potential when selecting signal Sel1, scanning line Scan (1) output scanning signal S (1), and when selection signal Sel1 is logic low potential, scanning line Scan (1) output blanking voltage current potential VGL。As it is shown on figure 3, each scanning line can unit control output, independent each other, that is blanking voltage can be exported to whole scanning lines simultaneously。Via appropriately designed outside control circuit with produce select signal Sel1, nSel1, Sel2, nSel2, Sel3, nSel3, Sel4, nSel4, it is possible to complete user be intended to design control mode。
The quantity selecting signal Selector is relevant to the first driver element SD (1) number of scanning lines amount n exported, when the first driver element SD (1) number of scanning lines amount n that need to drive is more many, the quantity selecting signal Selector also just increases therewith, makes a choice can scan line from n。Above-mentioned example is the mode that one is likely to realize de-multiplexer DM (1), but it is not limited to this, for the de-multiplexer of 1 pair 4, selecting signal can be 2,4 or 8, looks closely function and design limit that de-multiplexer DM reality need to complete and determines。
Refer to Fig. 2,1st grade of first driver element SD (1) described above produces the driving signal of n scanning line Scan (1)～Scan (n), 2nd grade of first driver element SD (2) can also be also responsible for producing the driving signal of n scanning line Scan (n+1)～Scan (2n), the number of scanning lines amount of the first driver element outputs certainly at different levels can also be different, only when the progression of the first driver element increases, if the number of scanning lines amount of outputs at different levels is identical, being easier on hardware Winding Design, its sequencing contro is relatively easy to design。If the number of scanning lines amount of the first driver element outputs at different levels is all n, then for needing the scan drive circuit 21 of output M bar scanning line, need to use (M/n) level the first driver element SD (i), it is possible to only use (M/n) individual shift register SR (i)。
The shift register SR (2) in the middle of shift register SR (1) the 2nd grade of first driver element SD (2) of series connection in the middle of 1st grade of first driver element SD (1), in like manner, the shift register SR (3) in the middle of the shift register SR (2) series connection 3rd level the first driver element SD (3) in the middle of the 2nd grade of first driver element SD (2)。Namely the triggering signal of the 1st grade of first driver element SD (1) is the first initial signal STV1, and the triggering signal of (i+1) level the first driver element is scanning signal S (i) of i-stage the first driver element。
Fig. 4 A is shown according to the signal timing diagram in first embodiment of the invention display floater。In order to simplify diagram and clear explanation, being using n=2 as explanation in Figure 4 A, namely each first driver element SD (i) is all use 1 de-multiplexer DM (i) to 2, signal Selector is selected to include Sel1, Sel2, nSel1, nSel2。In this example, there is 2m row image element circuit R (1)～R (2m) the first viewing area 22, and scan drive circuit 21 includes m level the first driver element SD (1)～SD (m)。
Owing to using 1 de-multiplexer DM (i) to 2, the ablation process for an image (frame) can be divided into 2 stages (Phase)。Signal Sel1 is selected to maintain logic high potential in the first stage (Phase1), signal Sel2 is selected then to maintain logic low potential, therefore, for de-multiplexer DM (i) at different levels, its state is all by scanning signal S (i) output of input to its 1st output connecting pin。As shown in Figure 4 A, after triggering the first initial signal STV1, shift register SR (1)～SR (m) via series connection, can progressively drive scanning line Scan (1), Scan (3), Scan (5) ..., Scan (2m-1), now data driver need to coordinate the driving data D that output is corresponding1,D3,D5,…,D2m-1To data/address bus。
Signal Sel1 is selected to maintain logic low potential in second stage (Phase2), selecting signal Sel2 then to maintain logic high potential, now the state of de-multiplexers DM (i) at different levels is all that scanning signal S (i) of input is exported to its 2nd output connecting pin。Again trigger the first initial signal STV1, similarly via shift register SR (the 1)～SR (m) of series connection, can progressively drive scanning line Scan (2), Scan (4), Scan (6), ..., Scan (2m), now data driver need to coordinate the driving data D that output is corresponding2,D4,D6,…,D2mTo data/address bus。
In the above example, Scan (1), Scan (2), ..., Scan (2m) drives the 1st of display floater 2 to arrange respectively, the 2nd row ..., 2m row, therefore adopt the scan drive circuit 21 of first embodiment above, be the pixel data first writing odd column when writing picture, then write the pixel data of even column。
Fig. 5 illustrates the schematic diagram of write picture data, and for making diagram clearly, the example of Fig. 5 depicted is using n=3 as explanation。Picture F01 is previous picture (headstock is towards a left side), when will write current picture (as shown in F04, headstock is towards the right side), is divided into 3 stages (because n=3)。Sequentially the 1st, 4,7 are scanned ... row (picture F02) in the first stage (Phase1), second stage (Phase2) sequentially scans 2,5,8 ... row (picture F03), phase III (Phase3) sequentially scans the 3rd, 6,9 ... row (picture F04), 3 the first beginning signal STV1 need to be triggered altogether, complete one picture of write。
It should be noted that this case invention is not limited to above-mentioned row interlacing mode, according to different control signals or different hardware connection modes, and the scan mode of picture can be changed, for instance progressive scan can be changed into。With n=2, display floater 2 has 2m bar scanning line and illustrates as an example, and following description two kinds is likely to the mode adopted。A kind of mode is that the output of the 1st grade of de-multiplexer DM (1) is connected to scanning line Scan (1) and the Scan (m+1) of display floater 2, the output of the 2nd grade of de-multiplexer DM (2) is connected to scanning line Scan (2) and the Scan (m+2) of display floater 2, all the other by that analogy, then the write sequence of data can change into D1,D2,D3,D4…,D2m。Another way selects signal Selector for changing, refer to Fig. 4 B, it illustrates the signal timing diagram of progressive scan, select signal Sel1 and select signal Sel2 to be all and clock signal CKV same frequency, and it is the signal of phase 180 degree each other, the mode of connection remains identical with script, so within a cycle of clock signal CKV, 1st grade of first driver element SD (1) can sequentially scan Scan (1) and Scan (2), in the next cycle of clock signal CKV, 2nd grade of first driver element SD (2) can sequentially scan Scan (3) and Scan (4) (can change clock signal CKV frequency produced by external control circuit identical to maintain picture update rate), the write sequence of such data can also change into D1,D2,D3,D4…,D2m。
Above-mentioned first kind of way, need to change hardware connection mode, and when m value is big time, the outfan of a de-multiplexer need to be connected to very remote two bar scanning line of being separated by, and this kind of winding mode less easily realizes。And the second way, selection signal need to be frequently changed with upper frequency, extra power consumption can be caused。Therefore, when the scan drive circuit of this exposure is connected with the scanning line of viewing area, though different connected modes and control mode can be had, but following description, all adopt the mode of aforementioned first embodiment as explanation, be namely to carry out in the way of the scanning of n row during write picture。
Such as the scan drive circuit of above-described embodiment, owing to using a shift register to coordinate a multiplexer to drive multi-strip scanning line in the first driver elements at different levels, therefore can reduce the TFT quantity used, reduce the area shared by scan drive circuit。Such as the circuit framework figure of Figure 12 depicted shift register, a shift register substantially can be estimated as 7 TFT of use。In the framework of Figure 1A, every 4 scanning lines need to use 4 shift registers, needs 28 TFT altogether。Comparing down, (for n=4) in the framework of Fig. 2, every 4 scanning lines use 1 shift register (7 TFT) and 1 de-multiplexer (8 TFT, see Fig. 3), it is only necessary to 15 TFT。Add hardware to put into effect border area reckoning around line width, if using low temperature polycrystalline silicon (LowTemperaturePoly-silicon, LTPS) TFT, entire area shared by scan drive circuit can be saved to 83%, if and use indium gallium zinc oxide (IGZO) TFT, because single the area of IGZOTFT is big compared with LTPSTFT, once save the TFT number used, the entire area shared by scan drive circuit more can be saved to 70%。Comparative result is arranged such as lower section table one。
Table one
Save the area of GOP scan drive circuit, be conducive to designing narrow frame panel, user visual experience more preferably can be brought。Save circuit area, also can reduce grid integrated circuits and drive size and the cost of element。In addition, sequencing contro mode as the aforementioned, select signal Selector can maintain same logic level in each stage (Phase), so can reduce the switching times selecting signal Selector, it is to avoid unnecessary power consumption。
Additionally, due to the multi-strip scanning line that exports of de-multiplexer can unit control, therefore via appropriately designed external control circuit, more can reach to save further the effect of power consumption。Fig. 8 illustrates the schematic diagram of a kind of external control circuit, and external control circuit includes memory element 80, comparing unit 82 and control unit 84。Memory element 80 is such as memorizer, stores previous picture Y (N-1)。Current picture Y (N) and previous picture Y (N-1) are compared by comparing unit 82, every string more can be compared by comparing unit 82, is identical to determine the pixel which current picture Y (N) and previous picture Y (N-1) have arrange。Such as the pixel of picture Y (N) pth row is identical with previous picture Y (N-1) at present, then picture reads action again without pth is arranged at present, control unit 84 can export the selection signal Selector of correspondence to control the de-multiplexer of correspondence, make scanning line Scan (p) maintain stopping potential VGL, again will not write for pth row in current picture Y (N)。Owing to IGZOTFT leakage rate relatively LTPSTFT and a-SiTFT in time closing is low, it is easier to keep the data of previous picture, this kind of practice is particularly well-suited to IGZO panel, and the row pixel for not changing is started without the transistor of correspondence, and can reduce power consumption further。And implementation limits and uses control circuit, the difference of picture Y (N) and previous picture Y (N-1) up till now can also be obtained through software computing by computer。
Above-mentioned first embodiment to whole picture by arrange staggered in the way of scan, as it is shown in figure 5, when being transformed into picture F04 by picture F01, it is possible to can cause for the vision perception of the mankind slightly uncomfortable, perceive the conversion between picture。Following example separately propose a kind of scan drive circuit that can lower human vision sense of discomfort。
Fig. 6 is shown according to the schematic diagram of second embodiment of the invention display floater。Exist with the difference of aforementioned first embodiment, display floater 6 more includes the second viewing area 62 ' and the first viewing area 62 and is similarly formed on thin-film transistor array base-plate 60, first viewing area 62 includes h first row image element circuit R (1)～R (h), second viewing area 62 ' includes multiple secondary series image element circuit R (h+1), R (h+2) ...。Scan drive circuit 61 more includes multistage second driver element SD ' (1), SD ' (2), ..., being controlled by the second initial signal STV2, clock signal CKV and at least one selection signal Selector, wherein j-th stage the second driver element SD ' (j) includes shift register SR ' (j) and solution multiplexer DM ' (j)。Shift register SR ' (j) is according to clock signal CKV and triggers signal generation scanning signal S ' (j)。De-multiplexer DM ' (j) is according at least one selection signal Selector, by the output of this scanning signal S ' (j) selectivity to multiple scanning line Scan, each scanning line Scan drive secondary series image element circuit R one of them。Wherein the triggering signal of the 1st grade of second driver element SD ' (1) is the second initial signal STV2, the triggering signal of (j+1) level the second driver element SD ' (j+1) is scanning signal S ' (j) of j-th stage the second driver element SD ' (j), and j is the positive integer more than or equal to 1。
As it was previously stated, the scanning line that each de-multiplexer exports can drive continuous print row image element circuit on panel, the mode of jumper connection can also be used, drive multiple row image element circuits with spacing。Accounting for coiling difficulty during entity design, this embodiment is to drive on display floater continuous print row image element circuit as explanation。Similarly, first row image element circuit R (1) in first viewing area 62 in this embodiment, R (2), ... succeed one another and be arranged on thin-film transistor array base-plate 60, secondary series image element circuit R (h+1) in second viewing area 62 ', R (h+2) ... succeed one another and be arranged on thin-film transistor array base-plate 60。Being not limited to this in implementation, for instance the first viewing area 62 can also include odd-numbered row image element circuit, the second viewing area 62 ' includes even-numbered row image element circuit。This embodiment is only used as the example being easier to hardware coiling, that is, the first viewing area 62 and the second viewing area 62 ' represent a horizontal block of display floater 6 respectively。
As can be seen from Figure 6, multistage second driver element SD ' (1), SD ' (2), ... with multistage first driver element SD (1), SD (2), ... framework similar, difference is in that the triggering signal of the 1st grade of first driver element SD (1) is the first initial signal STV1, and the triggering signal of the 1st grade of second driver element SD ' (1) is the second initial signal STV2。Therefore, the sequencing contro of the first viewing area 62 is identical with aforementioned first embodiment, is not repeating in this。And after completing the scanning of the first viewing area 62, trigger the second initial signal STV2, to be similar to the scan mode of the first viewing area 62, complete the scanning of the second viewing area 62 '。
Fig. 7 is shown according to the schematic diagram of second embodiment of the invention write picture data。In order to know explanation scanning sequency, in the figure 7, display floater is divided into 3 viewing areas as explanation, it is therefore desirable to have the first initial signal STV1, the second initial signal STV2, the 3rd initial signal STV3。Driver element at different levels is then use 1 de-multiplexer (n=3) to 3。Picture F11 is previous picture (headstock is towards a left side), when will write current picture (as shown in F20, headstock is towards the right side), is divided into the successively write of 3 viewing areas。First one of tripartite above write picture, it is similar to first embodiment, 3 stages are divided to trigger 3 the first beginning signal STV1, first stage sequentially scans the 1st, 4,7 ... row (picture F12), second stage sequentially scans 2,5,8 ... row (picture F13), and the phase III sequentially scans the 3rd, 6,9 ... row (picture F14)。Be then written to picture central authorities 1/3rd, triggers 3 the second initial signal STV2, divide 3 stages by arrange staggered in the way of scan (picture F15, F16, F17)。Be ultimately written 1/3rd below picture, trigger 3 order three initial signal STV3, point 3 stages by arrange staggered in the way of scan (picture F18, F19, F20), so complete whole picture。
Picture scan mode according to above-mentioned second embodiment, carries out row interlacing respectively owing to whole picture is divided into multiple block, it is possible to reduces whole picture and carries out ghost or the sense of discomfort that row interlacing brings。It should be noted that, no matter solution multiplexing's ratio (n) of de-multiplexer is how many, no matter also panel being divided into several viewing area, the sweep time of one required cost of picture is all identical, for there being the M display floater arranged, being need M clock cycle scanning of cost equally, what change is only the order of scanning, thus without the unnecessary burden causing sweep time。
For display device, so that the brightness of display can be considered and panel uniformity coefficient identical with the result desired by drive circuit, it usually needs arrange compensation circuit。Especially for Organic Light Emitting Diode (OrganicLightEmittingDiode, OLED) panel。This is due to interelement process variation, it is possible to cause critical voltage (Vth) differ, giving identical driving voltage even if causing, the electric current flowing through transistor still differs, and makes brightness inconsistent。This exposure is following more proposes a kind of scan drive circuit and display floater going for comprising compensation function。
For oled panel, one of which compensation way is through and gives suitable control signal, so that the electric current that drives of OLED can not be subject to the impact of critical voltage variation, its compensation process can divide into reset phase (Reset), data write phase (Program) and glow phase (Emission)。
Fig. 9 A is shown according to the schematic diagram of third embodiment of the invention display floater。For ask diagram clear for the purpose of, Fig. 9 A only illustrates about when being applied to compensate, compared to the part that first embodiment is newly-increased。Being in that with the difference of first embodiment, scan drive circuit 91 more includes Multilevel compensating driver element CD (1), CD (2) ..., it is controlled by a compensation initial signal STVc, clock signal CKV and at least one selection signal Selector。Wherein kth level compensation drive unit CD (k) includes shift register SRc (k) and de-multiplexer DMc (k)。Shift register SRc (k) is according to clock signal CKV and triggers signal generation one compensation signal C (k)。De-multiplexer DMc (k), according at least one selection signal Selector, will compensate signal C (k) selectivity output extremely multiple compensating line Com。Each compensating line Com be used for compensating first row image element circuit R one of them。Wherein the triggering signal of the 1st grade of compensation drive unit CD (1) is to compensate initial signal STVc, the triggering signal of (k+1) level compensation drive unit CD (k+1) is compensation signal C (k) of kth level compensation drive unit CD (k), and k is the positive integer more than or equal to 1。
Display floater 9 is such as oled panel。Compensating line Com (1), Com (2), ... it is such as controlling first row image element circuit R (1), R (2), ... in the reset control signal RST of reset phase, or control first row image element circuit R (1), and R (2) ... in the LED control signal EM of glow phase。As shown in Figure 9 A, the framework of compensation part is similar with the framework only comprising turntable driving in the middle of first embodiment, is use de-multiplexer equally, to reduce required shift register quantity。And the de-multiplexer DMc (1) in the middle of the 1st grade of compensation drive unit CD (1) and the de-multiplexer DM (1) in the middle of the 1st grade of first driver element SD (1), the selection signal Selector used can also be identical, for example, can be sent after the reset signal compensating the 1st bar of scanning line by Com (1), the scanning signal of the 1st article of scanning line Scan (1) is sent by Scan (1), so that image data write first row image element circuit R (1)。
This exposure a kind of display floater that can further reduce the shift register that compensation part uses of following another proposition。In following example, for multiple row image element circuits of display floater, a compensating control signal can be shared, for instance 2 row image element circuits can be regarded as a frequency band (band), give identical compensating control signal。
Fig. 9 B is shown according to the schematic diagram of fourth embodiment of the invention display floater。Fig. 9 B is illustrate as an example with the de-multiplexer of 1 pair 3, and 2 row image element circuits are regarded as a frequency band, for example, row image element circuit R (1) and R (4) are regarded as a frequency band。It should be noted that, de-multiplexer DMc (1) in the middle of 1st grade of compensation drive unit CD (1) is couple to 6 compensating line Com (1)～Com (6), but the control signal of selection signal Selector and the de-multiplexer DM (1) of de-multiplexer DMc (1) and DM (2) is identical。
Figure 10 A and Figure 10 B is shown according to the schematic diagram of the de-multiplexer that fourth embodiment of the invention uses。The control mode of de-multiplexer DM (1) and de-multiplexer DM (2) is similar with previous embodiment, repeats no more in this。De-multiplexer DMc (1) is then when selection signal Sel1 is logic high potential, scanning signal C (1) is exported to compensating line Com (1) and compensating line Com (4), when being logic high potential selecting signal Sel2, scanning signal C (1) is exported to compensating line Com (2) and compensating line Com (5), when being logic high potential selecting signal Sel3, scanning signal C (1) is exported to compensating line Com (3) and compensating line Com (6)。
In the middle of the 4th embodiment, owing to common 1 of 2 row image element circuits are compensated signal, therefore for 6 row image element circuit R (1)～R (6), the shift register number needed for turntable driving part is 2, and only needs 1 at the shift register number compensating part required。Quantity needed for can not only reducing shift register and can reach to reduce the effect of circuit area, more owing to jointly being compensated by multiple row image element circuits so that each row image element circuit can have the longer compensation time, therefore can obtain compensation effect more preferably。
Figure 11 is shown according to the signal timing diagram in fourth embodiment of the invention display floater。In Figure 11, compensate the reset control signal RST that signal C (1) is such as compensated stage。First stage (selecting signal Sel1 is logic high potential), first will compensate signal C (1) to export to compensating line Com (1) and Com (4), after replacement completes, again scanning signal S (1) output is extremely scanned line Scan (1), again scanning signal S (2) output is extremely scanned line Scan (4) afterwards, complete replacement and the scanning of first row image element circuit R (1) and R (4)。Similarly, sequentially complete the replacement to first row image element circuit R (2) and R (5) and scanning in second stage (selecting signal Sel2 is logic high potential), sequentially complete the replacement to first row image element circuit R (3) and R (6) and scanning in the phase III (selecting signal Sel3 is logic high potential)。
Scan drive circuit of the present invention, owing to utilizing de-multiplexer to export multi-strip scanning line with scanning signal-selectivity by one, can effectively reduce the quantity needed for shift register, reduce on panel with TFT implementation drive circuit or area shared in grid integrated circuits driving element, can be widely applied for various different display floater, be particularly conducive to the design of narrow frame panel。
Furthermore, such scan drive circuit will not increase the time needed for scan-image picture, it is possible to keeps identical picture update rate。And control via suitable wiring, the selection signal that de-multiplexer receives can't switch continually beats, it is possible to avoid unnecessary power consumption。And for having the TFT of Low dark curient character, owing to can effectively store pixel data, more propose to produce to control in the way of comparing image frame the method that de-multiplexer selects signal, further to save power consumption。
In addition, more consider the picture effect that human vision perceives, propose to be applicable to display floater is divided into different blocks, the circuit framework respectively different blocks being sequentially scanned and driving method, while reducing scan drive circuit area, what also can bring user happiness views and admires experience。
This exposure separately proposes to be applied in scan drive circuit the compensation method of the explicit module of Organic Light Emitting Diode, also with the framework of de-multiplexer to reduce the quantity used needed for shift register in compensating control。Additionally, more shared by the circuit compensation signal of multiple row pixels, further to reduce the quantity of shift register, also make each row image element circuit can have the longer compensation time, to obtain compensation effect more preferably simultaneously。
Although the present invention discloses as above with preferred embodiment; so it is not limited to the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little amendment and perfect, therefore protection scope of the present invention is when with being as the criterion that claims define。
Claims (20)
1. a scan drive circuit, including:
Multistage first driver element, is controlled by one first initial signal, a clock signal and at least one selection signal, and wherein the plurality of first driver element includes:
One shift register, this shift register triggers signal according to this clock signal and one and produces scan signal；And
One de-multiplexer, this de-multiplexer is according to this at least one selection signal, by this scanning signal-selectivity output to multiple scanning lines；
Wherein the triggering signal of the 1st grade of the first driver element is this first initial signal, and the triggering signal of this (i+1) level the first driver element is the scanning signal of this i-stage the first driver element, and i is the positive integer more than or equal to 1。
2. scan drive circuit as claimed in claim 1, it is characterised in that the de-multiplexer of this i-stage according to this at least one selection signal, each the plurality of scanning line selectivity respectively is exported this scanning signal and a blanking voltage current potential one of them。
3. scan drive circuit as claimed in claim 2, it is characterised in that this at least one selection signal is the comparative result according to a present picture and a previous picture and determines。
4. scan drive circuit as claimed in claim 1, it is characterised in that respectively the plurality of number of scanning lines amount of this grade the first driver element output is identical, the quantity of this at least one selection signal is relevant to the plurality of number of scanning lines amount of respectively this grade the first driver element output。
5. scan drive circuit as claimed in claim 1, also includes:
Multistage second driver element, is controlled by one second initial signal, this clock signal and this at least one selection signal, and wherein the plurality of second driver element includes:
One shift register, this shift register triggers signal according to this clock signal and one and produces scan signal；And
One de-multiplexer, this de-multiplexer is according to this at least one selection signal, by this scanning signal-selectivity output to multiple scanning lines；
Wherein the triggering signal of the 1st grade of the second driver element is this second initial signal, and the triggering signal of this (j+1) level the second driver element is the scanning signal of this j-th stage the second driver element, and j is the positive integer more than or equal to 1。
6. scan drive circuit as claimed in claim 5, it is characterized in that, respectively the plurality of number of scanning lines amount of this grade the second driver element output is identical, and identical with the plurality of number of scanning lines amount of respectively this grade the first driver element output, the quantity of this at least one selection signal is relevant to the plurality of number of scanning lines amount of respectively this grade the first driver element output。
7. scan drive circuit as claimed in claim 1, also includes:
Multilevel compensating driver element, is controlled by a compensation initial signal, this clock signal and this at least one selection signal, and wherein the plurality of compensation drive unit includes:
One shift register, this shift register triggers signal according to this clock signal and one and produces a compensation signal；And
One de-multiplexer, this de-multiplexer is according to this at least one selection signal, by this compensation signal-selectivity output to multiple compensating lines；
Wherein the triggering signal of the 1st grade of compensation drive unit is this compensation initial signal, and the triggering signal of this (k+1) level compensation drive unit is the compensation signal of this kth level compensation drive unit, and k is the positive integer more than or equal to 1。
8. scan drive circuit as claimed in claim 7, it is characterised in that the de-multiplexer of this kth level compensation drive unit according to this at least one selection signal, each the plurality of compensating line selectivity respectively is exported this compensation signal and a blanking voltage current potential one of them。
9. a display floater, including:
One thin-film transistor array base-plate；
One first viewing area, including multiple first row image element circuits；And
Scan driving circuit, including:
Multistage first driver element, is controlled by one first initial signal, a clock signal and at least one selection signal, and wherein the plurality of first driver element includes:
One shift register, this shift register triggers signal according to this clock signal and one and produces scan signal；And
One de-multiplexer, this de-multiplexer is according to this at least one selection signal, by the output of this scanning signal-selectivity to multiple scanning lines, the plurality of first row image element circuit of each the plurality of scanning line driving one of them；
Wherein the triggering signal of the 1st grade of the first driver element is this first initial signal, and the triggering signal of this (i+1) level the first driver element is the scanning signal of this i-stage the first driver element, and i is the positive integer more than or equal to 1。
10. display floater as claimed in claim 9, it is characterised in that the de-multiplexer of this i-stage according to this at least one selection signal, each the plurality of scanning line selectivity respectively is exported this scanning signal and a blanking voltage current potential one of them。
11. display floater as claimed in claim 10, it is characterised in that this at least one selection signal is the comparative result according to a present picture and a previous picture and determines。
12. display floater as claimed in claim 9, it is characterised in that respectively the quantity of the plurality of scanning line of this grade the first driver element output is identical, the quantity of this at least one selection signal is relevant to respectively this grade the first driver element and exports the quantity of the plurality of scanning line。
13. display floater as claimed in claim 9, it is characterised in that the plurality of scanning line of this i-stage first driver element output, it is drive multiple continuous print first row image element circuits in this first viewing area。
14. display floater as claimed in claim 9, more include:
One second viewing area, including multiple secondary series image element circuits；
Wherein this scan drive circuit more includes multistage second driver element, is controlled by one second initial signal, this clock signal and this at least one selection signal, and wherein the plurality of second driver element includes:
One shift register, this shift register triggers signal according to this clock signal and one and produces scan signal；And
One de-multiplexer, this de-multiplexer is according to this at least one selection signal, by the output of this scanning signal-selectivity to multiple scanning lines, the plurality of secondary series image element circuit of each the plurality of scanning line driving one of them；
Wherein the triggering signal of the 1st grade of the second driver element is this second initial signal, and the triggering signal of this (j+1) level the second driver element is the scanning signal of this j-th stage the second driver element, and j is the positive integer more than or equal to 1。
15. such as the display floater that claim 14 is stated, it is characterized in that, respectively the plurality of number of scanning lines amount of this grade the second driver element output is identical, and identical with the plurality of number of scanning lines amount of respectively this grade the first driver element output, the quantity of this at least one selection signal is relevant to the plurality of number of scanning lines amount of respectively this grade the first driver element output。
16. display floater as claimed in claim 14, it is characterised in that the plurality of first row image element circuit succeeds one another and is arranged on this thin-film transistor array base-plate, and the plurality of secondary series image element circuit succeeds one another and is arranged on this thin-film transistor array base-plate。
17. display floater as claimed in claim 9, it is characterised in that this scan drive circuit more includes:
Multilevel compensating driver element, is controlled by a compensation initial signal, this clock signal and this at least one selection signal, and wherein the plurality of compensation drive unit includes:
One shift register, this shift register triggers signal according to this clock signal and one and produces a compensation signal；And
One de-multiplexer, this de-multiplexer is according to this at least one selection signal, by this compensation signal-selectivity output to multiple compensating lines；
Wherein the triggering signal of the 1st grade of compensation drive unit is this compensation initial signal, and the triggering signal of this (k+1) level compensation drive unit is the compensation signal of this kth level compensation drive unit, and k is the positive integer more than or equal to 1。
18. display floater as claimed in claim 17, it is characterised in that respectively each the plurality of compensating line of this grade of compensation drive unit output be for compensate the plurality of first row image element circuit one of them。
19. display floater as claimed in claim 17, it is characterised in that respectively each the plurality of compensating line of this grade of compensation drive unit output be for compensate simultaneously the plurality of first row image element circuit therein at least the two。
20. display floater as claimed in claim 17, it is characterised in that this display floater is an Organic Light Emitting Diode (OLED) panel。
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