200905647 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種驅動電路、顯示面板及顯示裝置， 特別關於一種驅動電路、平面顯示面板及平面顯示裝置。 【先前技術】 隨著數位時代的來臨，平面顯示裝置，例如液晶顯示 裝置之技術亦快速成長，已成為不可或缺的電子產品，故 對於平面顯示裝置之技術及功能要求亦越來越高，而藉由 良好的驅動電路以驅動液晶分子已成為提升平面顯示裴 置之技術的要項之一。 3月> 圖丄所不，於習知技術中，平面顯不农直係爸 3種驅動電路1 ’而驅動電路1係設置於平面顯示裴j 之一平面顯示面板中（圖未示）。驅動電路1係具有一數4 处理模、、且11及一類比處理模組U來處理複數個晝素資李200905647 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a driving circuit, a display panel, and a display device, and more particularly to a driving circuit, a flat display panel, and a flat display device. [Prior Art] With the advent of the digital era, the technology of flat display devices, such as liquid crystal display devices, has also grown rapidly and has become an indispensable electronic product. Therefore, the technical and functional requirements for flat display devices are also increasing. The use of a good driving circuit to drive liquid crystal molecules has become one of the key technologies for improving the planar display device. March] 丄 丄 , , , , , , , , 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习. The driving circuit 1 has a number 4 processing mode, and 11 and an analog processing module U to process a plurality of 昼素资李
況號P ’以下為簡化說明，僅以單-個晝素資料訊號P I 2數位處理模組u係由—數位電源供電，並 畫素貧料訊號P。赵仂h ^ -第-绣1係具有一暫存器ill及 弟緩衝态暫存器接收一 次 制訊號SC移位後輸出5△ 控制訊遗SC並將控 後輸出弟—緩衝器112,第-综輪。。， 係依據控軸號SC接㈣”料辭p ⑴ 係緩衝晝素㈣tfL號P來輪$。" 、’衝器112 類比處理模組12係由-類比電源+ 處理模組11接收晝素資料訊號p。類比處理 200905647 有一位移器121、—轉換器122、-第二缓衝器123 ί工器124，位移器121係與數位處理模組11之第一緩衝 ^二電性連接’而轉換器122係電性連接位移器121及 -、、、衝益123’多工器124係與第二緩衝器123電性連 ==器、121係依據類比電源从之位準以轉態晝素資 ^ 並提升晝素資料訊號ρ之位準而產生一轉態資 ^冗號SG1 ’而通常轉態—個位元的晝素資料訊號ρ於實 包上係使肖#位移121，故倘若處理複數個晝素資 訊號P則使用複數個位移器121。 、 、轉換器m係從一電阻串接收複數個參考訊號Ref， 並依據參考訊號Ref以將轉態資料訊號s〇1轉換為一驅動 訊號S02’並透過第二緩衝器123及多工器124以緩衝輸 出之’而驅動電路1係輸出驅動訊號S02來驅動—平面顯 示面板的晝素，俾使晝素的液晶分子對應作動。 *、’、 然而，由於液晶分子的反應時間之快慢，係受到參考 訊號Ref的電㈣影響，故使類比電源VAt麵來越大； 此外’數位處理馳n的製料因越來越先進，故數位 電源VD貝ij可越來越小’因此造成類比電源與數 源VD的電壓差越來越大。而上述情形，在與位移器⑵ 配合時，倘若位移器121之增益值設計的;M、，則於轉態 晝素資料訊號P來提升晝素資料訊號？之位準時，容易產 生轉態失敗的問題。而若增益料計的太大，财轉 會使得類比電源VA的瞬間抽載電流過大。又偏若同 理複數個晝素資訊號P時，則㈣數個㈣器ΐ2ι必須同 200905647 時作動’故需要供應很面的電流量’此種情形容易造成整 體電源之供給部分不堪負荷，嚴重時更會造成驅動電路1 内部元件受到損壞。 承上所述，如何提供一種能夠解決上述問題之平面顯 示裝置、平面顯示面板及驅動電路，正是當前的重要課題 - 〇 【發明内容】 有鑑於上述課題，本發明之目的為提供一種能夠使轉 態順利進行，並降低抽換電流進而保護系統電源之驅動電 路、平面顯示面板及平面顯示裝置。 緣是，為達上述目的，依本發明之一種驅動電路係接 收至少一晝素資料訊號，驅動電路包含一第一處理模組、 一位準轉換模組以及一第二處理模組。第一處理模組係由 一第一電源供電，並缓衝晝素資料訊號後輸出。位準轉換 模組係由一第二電源供電並與第一處理模組電性連接，位 準轉換模組係在第二電源之位準範圍内提高晝素資料訊 號之位準以輸出互補之一第一資料訊號及一第二資料訊 號，並將第一資料訊號及第二資料訊號轉換以分別產生一 第一驅動訊號及一第二驅動訊號。第二處理模組係由一第 三電源供電，並與位準轉換模組電性連接，第二處理模組 係提高第一驅動訊號之位準以產生一第三驅動訊號，並選 擇第二驅動訊號或第三驅動訊號輸出，其中第二電源之位 準係介於第一電源及第三電源之位準間。 200905647 為達上述目的，依本發明之一 -晝素陣列以及一驅動電路 ：:，面板係包含 資料訊號，驅動電路具有—第接收至少一晝素 组以及一第二處理# 吴、、且、一位準轉換模 + 弟-處理模組。弟—處理模組係由—第 私，並緩衝晝素資料訊號後輸出。 源供 二電源供電並與第-處理模組 由一第 在第二電社位㈣κ喊換模組係The condition number P ’ below is a simplified description. Only the single-single data signal P I 2 digital processing module u is powered by the digital power supply, and the pixel is poor. Zhao Wei h ^ - Di-Embroidery 1 series has a temporary register ill and the young buffer state register receives the primary signal SC shift and outputs 5 △ control signal SC and will control the output of the buffer - 112 - Synthetic wheel. . According to the control axis No. SC (4), the word p (1) is buffered (4) tfL No. P. The wheel is replaced by the analogy power supply + processing module 11 Data signal p. Analog processing 200905647 has a shifter 121, a converter 122, a second buffer 123, and a shifter 121 is electrically connected to the first buffer of the digital processing module 11 The converter 122 is electrically connected to the shifter 121 and the -,,, and the blister 123' multiplexer 124 are electrically connected to the second buffer 123. The 121 is based on the analog power source. Susu and improve the level of the data signal ρ to generate a transition state ^ redundant number SG1 ' and usually the transition state - a bit of the elementary data signal ρ on the real package makes Xiao # displacement 121, so If a plurality of pixel information numbers P are processed, a plurality of shifters 121 are used. The converter m receives a plurality of reference signals Ref from a resistor string, and converts the transition data signal s〇1 according to the reference signal Ref. a driving signal S02' and driving the circuit through the second buffer 123 and the multiplexer 124 to buffer the output The 1 series outputs a driving signal S02 to drive the pixels of the flat display panel, so that the liquid crystal molecules of the halogen are correspondingly actuated. *, ', However, due to the slow reaction time of the liquid crystal molecules, it is affected by the electric (four) of the reference signal Ref. Therefore, the analogy power supply VAd surface is larger; in addition, the 'digital processing chi-n material is more and more advanced, so the digital power supply VD ij can be smaller and smaller', thus causing the voltage difference between the analog power supply and the digital source VD In the above case, when the shifter (2) is engaged, if the gain value of the shifter 121 is designed; M, then it is easy to raise the position of the halogen data signal when the transfer state data signal P is used. If the gain meter is too large, the fortune will make the analog pumping current of the analog power supply VA too large. If the multiple information elements P are the same, then (four) several (four) Ϊ́2ι must be activated with the same time as 200105647 'There is a need to supply a very large amount of current'. This situation is likely to cause the supply of the overall power supply to be unbearable, and in severe cases, the internal components of the drive circuit 1 may be damaged. What is the object of the present invention is to provide a flat display device, a flat display panel, and a drive circuit that can solve the above problems - [Abstract] In view of the above problems, it is an object of the present invention to provide a smooth transition state. And the driving circuit, the flat display panel and the flat display device for reducing the current to be exchanged to protect the system power. The edge is that, in order to achieve the above object, a driving circuit according to the present invention receives at least one data signal, and the driving circuit includes a first A processing module, a quasi-conversion module and a second processing module. The first processing module is powered by a first power source and buffers the data signals and outputs the data. The level conversion module is powered by a second power source and electrically connected to the first processing module. The level conversion module increases the level of the data signal in the level of the second power source to output complementary data. A first data signal and a second data signal are converted to convert a first data signal and a second data signal to generate a first driving signal and a second driving signal, respectively. The second processing module is powered by a third power source and electrically connected to the level conversion module. The second processing module increases the level of the first driving signal to generate a third driving signal, and selects the second The driving signal or the third driving signal output, wherein the level of the second power source is between the levels of the first power source and the third power source. 200905647 In order to achieve the above object, according to one of the present invention - a pixel array and a driving circuit::, the panel system comprises a data signal, the driving circuit has - receiving at least one element group and a second processing #吴,, and A quasi-conversion mode + brother-processing module. The younger brother--the processing module is outputted by the first private, buffering the data signal. Source for two power supply and with the first-processing module by a second in the second electric community (four) κ shouting module system
St —第二資料訊號，並將第-資 弟二資料訊號轉換以分別產生一第 ： -弟二驅動職。第二處理模 ： 广 :::::rr連接，第二處理』二驅 戒或弟:驅動訊號輸出至晝素陣列，其中第二電源進 糸介於第一電源及第三電源之位準間。’、^ -金目的’依本發明之一種平面顯示農置係包含 旦素陣列、一光源以及一驅動電 過畫素陣列以顯示一影像’驅動電收至少：j ，第，路具有一第一處理模一;轉;2 :及-弟二處理模組。第一處理模組係由一第一電源供 ―並緩衝晝素㈣減後輸出。位準轉換触係由 2源供電並與第一處理模組電性連接，位準轉換模組係 2弟一電源之位準範圍内提高晝素資料訊號之位準以輸 出互補之一第—資料訊號及一第二資料訊號，並將第 相號及第二資料訊號轉換以分職生—第—驅動訊號 200905647 及一第二驅動訊號。第二處理模細係由一第三電源供電， 之位準以產生一第三驅動訊號’ c號輸出至晝素陣列，其中第 係介於弟-電狀第三電源之位準間。 早 板及==因Γ發明之平面顯示裝置、平面顯示面 ΐ = 3 加第二電源作為位準轉換模組之供 之門位準係介於第—電源及第三電源之位準 Γ而！^不僅可使位準轉換模組不需高電源之供 換，咅即提古圭去〜位皁範圍内就可順利作轉態切 二即“畫素貝料訊號之位準，甚至使用大 可起快速作動’並且除了不會有轉‘_ 穩定性。更可降低抽載電流量’進而保護整體電源之 【實施方式】 種參板:::::::佳實· - 2係示，本發明較佳實施例之平面顯示裝置 係且二4:面板3及一光源4。平面顯示面板3 面顯二ft?列:1以及一驅動電路32。光源4係與平 以顧- 才目對设置，並產生光線L穿過晝素陣列31 -二=本實施例之平面顯示裝置2財施上係為 、置’故平面顯示面板3係為—液日日日顯示面 11 200905647 板’而光源4於實施上係可為一背光模組。 言青參照圖3所示’本實施例之驅動電路32係接收複 數個晝素資料訊號p，並具有一第一處理模組321、一位 準轉換模組322以及一第二處理模組323 ;而各畫素資料 P於實施上係分別為-腕的資料訊號，且亦為:數位訊 號’故在此係以驅動電路32接收六個lbit之晝素資料訊 號P為例。本實施例之第一處理模組321 二 W供電，位準轉換模請係由一第二二電電二 二處理模組323係由一第三電源V3供電。本實施例之第 二電源V2之位準，於實施上係介於第一電源vi及第三電 源V3之位準之間，且第三電源V3之位準係大於第一電源 V1位準，例如第二電源V 2之位準其範圍係介於2 · 5伏特 至13伏特之間。St - the second information signal, and the conversion of the first - second data signal to generate a first: - brother two drivers. The second processing mode: wide:::::rr connection, the second processing" second drive or brother: the drive signal is output to the pixel array, wherein the second power supply is at the level of the first power source and the third power source between. ',^-金目' according to the present invention, a flat display farm system comprising a denier array, a light source and a driving electric pixel array to display an image 'drive electric charge at least: j, the first road has a first A processing module; turn; 2: and - brother two processing module. The first processing module is supplied by a first power source and buffered by the halogen (4). The level conversion contact system is powered by 2 sources and electrically connected to the first processing module, and the level conversion module is used to raise the level of the data signal in the level of the power source of the second brother to output one of the complementary ones. The information signal and a second data signal are converted to the first and second data signals to be divided into the secondary student-first driving signal 200105647 and a second driving signal. The second processing module is powered by a third power source, and the level is generated to generate a third driving signal 'c' output to the pixel array, wherein the second system is between the level of the third electrical source. Early board and == because of the invention of the flat display device, the flat display surface ΐ = 3 plus the second power supply as the level conversion module for the door position is between the first - power supply and the third power source ! ^ Not only can the level conversion module not need to be replaced by a high power supply, that is, it can be smoothly changed to the level of the liquid in the range of the liquid. Can be activated quickly 'and in addition to not turning '_ stability. Can reduce the amount of pumping current' and thus protect the overall power supply [Implementation] Seeding board::::::: Jiashi · - 2 shows The flat display device of the preferred embodiment of the present invention is a panel 4 and a light source 4. The flat display panel 3 has two ft columns: 1 and a driving circuit 32. The light source 4 is connected to the flat panel.目 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 平面 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 平面 = = = = = The light source 4 is implemented as a backlight module. The driving circuit 32 of the present embodiment receives a plurality of pixel data signals p and has a first processing module 321, a quasi-conversion module 322 and a second processing module 323; and each pixel data P is implemented as a wrist The material signal is also a digital signal. Therefore, the driver circuit 32 receives six lbits of the data signal P as an example. The first processing module 321 of the embodiment is powered by two bits, and the level conversion mode is requested. The second power supply 220 is powered by a third power supply V3. The second power supply V2 of the embodiment is implemented in the first power supply vi and the third power supply V3. Between the levels, and the level of the third power source V3 is greater than the level of the first power source V1, for example, the level of the second power source V 2 is between 7.5 volts and 13 volts.
於本實施例中，第一處理模組321係具有一移位暫存 器3211、一第一缓衝器3212及一第一多工器m3。 —移2暫存器32U係電性連接㈣ι“32ΐ2_ 多工益3213之間。第一多工器3213係接收一時脈控制 訊號SCC及各晝素資料訊號Ρ，並依據時脈控制訊號SCC ,&士 ^負極性輸出各晝素資料訊號P至移 位暫存器3211 ;例如·也卩士 王秒 時，則第—多工器321Λ控制减似為一低準位 制訊號SCC為-高準選擇以正極性輸出，當時脈控 負極性輸卜 ^時，則第—多工器切3係選— 極U極性之定義，則是以電壓值大於或小於 12 200905647 平面顯示面板3中之彩色濾光(color filter)基板的共同電壓 (⑶mmcm v〇itage)而言（圖未示）’當電壓值大於共同電壓則 為正極性，當電壓值小於共同電壓則為負極性，故倘若書 素資料訊號P之電壓值係大於共同電壓，則晝素資料訊號 P為正極性；倘若晝素資料訊號p之電壓值係小於共同電 [，則晝素資料訊號p為負極性；而在此係以第一多工器 3213依據時脈控制訊號scc為一低準位，而以正極性輪 出各晝素資料訊號P為例。 移位暫存器3211輸出一控制訊號SC至第一緩衝器 =12 γ並位移各晝素資料訊號p，而控制訊號sc係控制 第一緩衝器3212接收各晝素資料訊號P，第一緩衝器3212 係緩衝各晝素資料訊號p後輸出。本實施例之移位暫存器 3211係於實施上係為一雙向移位暫存器卬丨沿代⑷❹⑽丨让沧 代㈣如），第一緩衝器3212係為一行緩衝器（linebuffer)。 、位準轉換模組322係與第一處理模組321電性連接， 並具有複數個位移器3221及一轉換器3222。 。於本實施例中，位移器3221之數量於實施上係與驅 動電路32所接收之畫素資料訊號p的數量相同，意即一 個=移态3221係對應並接收一個lbit的晝素資料訊號p， =田位準轉換模組322接收六個lbit的晝素資料訊號p 牯，則位準轉換模組322具有六個位移器3221。 。月再參照圖4所示，圖4係圖3的其中之一位移器3221 之等致電路示意圖，而各位移器3221係與第一處理模組 321电性連接，並具有一第一輸入電晶體qi、一第二輸入 13 200905647 ::曰：Γ 一第一負載電晶體Q3以及-第二負載電晶體 二一輸入電晶體Q1之源極及第二輸入電晶體 連接一第四電源V4,第-負载電晶體Q3 之閘極係電性連接第-輸入電晶體Q1之没極 :體Q4、之閉極係電性連接第二輪入電晶體Q2J 係電性遠2晶體Q3之源極及第二負載電晶體Q4之源極 性連接第ί —電源V2,第—負載電晶體Q3之汲極係電 之電晶體Q2之没極，第二負載電晶體Q4 之第㉟電性連接第—輸人1晶體Q1之没極。本實施例 之第四：源V4於實施上係為一類比接地電源。 第二輪入電晶體Q1之閘極係接收晝素資料訊號p， 補^ J，人電晶體Q2之閘極係接收晝素資料訊號P之互 負載雷U日科位移器3221並藉由第一輪入電晶體Q1與第二 電晶體曰二Q4之配合’及第二輸入電晶體Q2與第-負載 素；料㈣之配合’以在第二電源V2之位準範圍内提高畫 出j訊P之位準，並於第二輸人電日日日體Q2之没極輸 料，卜及於第一輸入電晶體Q1之没極 及4 _欠一貝料訊號S12。本實施例之第一資料訊號S11 位貝料訊號S12於實施上係相互互補，並分別為一數 之黛二且在此則以位準轉換模組322係產生共六組成對 之弟一貧料訊號S11及第二資料訊號犯為例。 :再參照圖3所示，轉換器助係接收複數個參考 次二e/並與各位移器3221電性連接以接收六對的第— 〆孔號S11及第二貧料訊號Sl2，轉換器係依據參 14 200905647 考A號Ref以將此六對的第—資料^j %。 負科讯就S11及第二資料訊 號S12轉換以產生一弟一驅動訊 川。而轉換器迎係為一數H13或一弟二驅動訊號 數位類比轉換器（digital to ΠΓΓ.!813s14 係分別為一類比訊號，且具有一雷 例中，第-驅動訊號S13於實施=值。此外二於本實施 號S14為負極性，意即第—驅動訊麥^性*弟二驅動訊 共同電壓，第二驅動訊號su之電^之电壓值係大於 <兔壓值係小於共同雷壓； 且在此係以轉換器3222輸出第—驅動訊號阳為例。 由於位準轉換模組322藉由第二電源v 因第二電源V2之位準介於第一 私而又 位準之間，故位準轉換模組322只.·二電源V3之 二電源V2之間作切換，就可避免位-電源Μ及第 更能降低轉態時之抽載電流，進3221轉態失敗， 性。 進而保障整體電源的穩定 請參再· 3赫，於本實施例中 係與位準轉換模組322電性連接， 畏、、且323 323卜-第二緩衝器迎以及―第二多n回復電路 圖5係圖3中回復電路3231之—_立 323i係與位準轉換模組322 <轉換器—’回復電路 具有-推升器0PA及複數個電:° ·性連接，並 係具有-正輸入端η及一負輪入端Ι2，第升斋ΟΡΑ 一驅動訊號犯係分別輪人至推升器舰正 及負輸入端12’而推升器0ΡΑ及電阻器R1、R2== 15 200905647 二電源V2以將第/驅動。孔號$ 13推升來產生第三驅動訊 號S15。本實施例之餌復電路3231於實施上係一反相閉迴 3戶斤示’第二緩衝器3232係分別與轉換 路放大器。 請再參照： 器3222及回復$ 絡3231私性連接，並分別接收第二驅動 動訊?虎S15’苐二緩衝器3232係缓衝第 訊號S14及第多 二驅動訊號州及第二驅動訊號阳後輸出。而第二多工 哭在盥第二·绫衡益3232電性連接，並依據時脈控制 ;號_擇以奇，\偶數通道輪出第三驅_^^ 或以奇數或偶數通道第二驅動訊號S14至晝素陣列 31。本實施例之奇數通道與偶數通道，於實施上係分別為 正極性輸或負極性輸4，在此係以奇數通道為正極性給 出，而偶數通道為負極性輸出為例。 ] 路 在本實施例中’由於增加了第二電源V2及回復 咖，而第二電源、V2係作為位準轉換模組切之 且第二電源V2之位準係介於第—電源％及第 之位準之間’而回復電路3231則可推升第一— 以產生第三驅動訊號S15 ’因此可以較低的功率消= 升訊號之位準。此外，使第二驅動訊號sm ^推 號S15具有足夠能力可驅動晝素陣列，以提升整體—之口動;1 綜上所述，因依本發明之平面顯示裝置口= 板及其驅動電路’係增加第二電源作為位準轉換模= 電，且第二電源之位準係介於第1源及第三電 之間，此種方式不僅可使位準轉換模組不需高電源之= 16 200905647 應，而只需在第二電源之位準範圍内就可順利作轉態切 換，意即提高晝素資料訊號之位準，甚至使用大量的位準 轉換模組亦可一起快速作動，並且除了不會有轉態失敗的 問題產生外，更可降低抽載電流量，進而保護整體電源之 穩定性。 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範疇，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1為顯示習知之一種驅動電路之示意圖； 圖2為顯示依本發明較佳實施例之一種平面顯示裝置 之示意圖； 圖3為顯示依本發明較佳實施例之平面顯示裝置中驅 動電路之示意圖； 圖4為顯示依本發明較佳實施例之驅動電路中位移器 之示意圖；以及 圖5為顯示依本發明較佳實施例之驅動電路中回復電 路之示意圖。 【主要元件符號說明】 1、32 驅動電路 11 數位處理模組 111 暫存器 17 200905647 112 、 3212 第一缓衝器 12 類比處理模組 121 、 3221 位移器 122 、 3222 轉換器 123 、 3232 第二缓衝器 124 多工器 2 平面顯示裝置 3 平面顯示面板 31 晝素陣列 321 第一處理模組 3211 移位暫存器 3213 第一多工器 322 位準轉換模組 323 第二處理模組 3231 回復電路 3233 第二多工器 4 光源 11 正輸入端 12 負輸入端 L 光線 OPA 推升器 P 晝素資料訊號 P， 畫素資料訊號之互補訊號 Ql 第一輸入電晶體 18 200905647 Q2 第二輸入電晶體 Q3 第一負載電晶體 Q4 第二負載電晶體 R1、R2 電阻器 Ref 參考訊號 SC 控制訊號 see 時脈控制訊號 SOI 轉態資料訊號 S02 驅動訊號 Sll 第一資料訊號 S12 第二資料訊號 S13 第一驅動訊號 S14 第二驅動訊號 S15 苐三驅動訊號 VA 類比電源 VD 數位電源 VI 第一電源 V2 第二電源 V3 第三電源 V4 第四電源 19In the embodiment, the first processing module 321 has a shift register 3211, a first buffer 3212, and a first multiplexer m3. - Shift 2 register 32U is electrically connected (4) ι "32ΐ2_ 多工益3213. The first multiplexer 3213 receives a clock control signal SCC and each pixel data signal Ρ, and according to the clock control signal SCC, & 士^Negative output of each element data signal P to the shift register 3211; for example, also when the gentleman king seconds, the first multiplexer 321 Λ control minus a low level signal SCC is - Micro Motion selects the positive polarity output. When the pulse-controlled negative polarity is transferred, the first-multiplexer cuts the 3 series. The definition of the polarity U is based on the voltage value greater or less than 12 200905647. The common voltage of the color filter substrate ((3)mmcm v〇itage) (not shown) is positive when the voltage value is greater than the common voltage, and negative when the voltage value is less than the common voltage. If the voltage value of the data signal P is greater than the common voltage, the data signal P is positive; if the voltage value of the data signal p is less than the common electricity, the data signal p is negative; The first multiplexer 3213 is based on the clock control signal scc For example, the shift register 3211 outputs a control signal SC to the first buffer=12 γ and shifts each of the pixel data signals p, and is a low level. The control signal sc controls the first buffer 3212 to receive the respective pixel data signals P, and the first buffer 3212 buffers the respective data signals p. The shift register 3211 of the embodiment is implemented. The first buffer 3212 is a line buffer (linebuffer), and the level conversion module 322 is electrically connected to the first processing module 321 by a bidirectional shift register (4) ❹ (10) 丨 (4). The number of the shifters 3221 is the same as the number of the pixel data signals p received by the drive circuit 32, that is, the number of the shifters 3221 is the same as the number of the pixel data signals p received by the drive circuit 32. A level shifting 3221 corresponds to and receives a 1-bit pixel data signal p, and the field level conversion module 322 receives six 1-bit pixel data signals p 牯, and the level conversion module 322 has six shifters. 3221. Months are again shown in Figure 4, Figure 4 is in Figure 3 The circuit diagram of the shifter 3221 is electrically connected to the first processing module 321 and has a first input transistor qi and a second input 13 200905647 ::曰:Γ first The load transistor Q3 and the second load transistor are connected to the source of the transistor Q1 and the second input transistor is connected to a fourth power source V4, and the gate of the first load transistor Q3 is electrically connected to the first input power. The crystal Q1 is infinite pole: the body Q4, the closed pole is electrically connected to the second wheeled transistor Q2J is electrically far 2 the source of Q crystal Q3 and the source polarity of the second load transistor Q4 is connected ί - power supply V2, — The pole of the transistor Q2 of the load transistor Q3 is electrically connected, and the 35th of the second load transistor Q4 is electrically connected to the first pole of the crystal 1 of the input 1 crystal. Fourth of the embodiment: the source V4 is implemented as an analog grounding power source. The gate of the second round of the input transistor Q1 receives the halogen data signal p, complements the J, and the gate of the human crystal Q2 receives the mutual load of the elementary data signal P and the U-displacement shifter 3221 by the first The rotation of the transistor Q1 and the second transistor 曰2 Q4 'and the second input transistor Q2 and the first-loader; the material (4) cooperates to increase the level of the second power source V2 to draw the j signal P The level of the second input power, the Japanese body Q2, the immersive material, the first input transistor Q1, and the 4 _ owe a material signal S12. The first data signal S11 of the present embodiment is complementary to each other in the implementation, and is respectively one of the two. In this case, the level conversion module 322 is used to generate a total of six pairs of pairs. The material signal S11 and the second data signal are taken as examples. Referring again to FIG. 3, the converter assists receiving a plurality of reference times e/ and electrically connecting with each of the shifters 3221 to receive six pairs of the first pupil number S11 and the second poor signal S12, the converter According to the reference No. 14 200905647, the A number Ref is the first data of the six pairs. Negative Newsletter converts S11 and the second data signal S12 to generate a brother-in-one driver. The converter is greeted by a number H13 or a second driver signal digital analog converter (digital to ΠΓΓ.! 813s14 is a type of analog signal, and has a lightning example, the first drive signal S13 is implemented = value. In addition, the second implementation number S14 is negative polarity, which means that the first driving signal is the common voltage, and the voltage of the second driving signal su is greater than < the rabbit pressure value is smaller than the common lightning. In this case, the output of the first driving signal is performed by the converter 3222. Since the level conversion module 322 is in the first private level due to the second power source v, the level of the second power source V2 is Therefore, the position conversion module 322 only switches between the two power supply V3 and the power supply V2, so as to avoid the bit-power supply and the first can reduce the load current when the transition state, and the 3221 transition state fails. In order to ensure the stability of the overall power supply, please refer to the third level. In this embodiment, the system is electrically connected to the level conversion module 322, and the 323 323-second buffer and the second n reply circuit Figure 5 is the recovery circuit 3231 of Figure 3 - 立立323i and level conversion module 322 < Converter - 'Response circuit has - pusher 0PA and multiple electric: ° · Sexual connection, and has - positive input terminal η and a negative wheel end Ι 2, the first liter of fasting To the pusher ship positive and negative input terminal 12' and the pusher 0 ΡΑ and the resistor R1, R2 == 15 200905647 The second power supply V2 pushes the / drive. hole number $ 13 to generate the third drive signal S15. In the embodiment, the bait multiplexing circuit 3231 is implemented in an inverted phase, and the second buffer 3232 is respectively connected to the conversion path amplifier. Please refer to: the device 3222 and the reply to the network 3231 privately connected, and Receive the second driving motion separately? Tiger S15' 苐 2 buffer 3232 buffering signal S14 and the second and second driving signal state and the second driving signal yang output. The second multiplex is crying in the second 绫The balance 3232 is electrically connected and controlled according to the clock; the number is selected as odd, the even channel is rotated by the third drive _^^ or the odd or even channel second drive signal S14 is connected to the pixel array 31. This embodiment The odd-numbered channel and the even-numbered channel are respectively positive or negative polarity input 4, which is The odd channel is given as positive polarity, and the even channel is negative polarity output as an example.] In this embodiment, 'the second power supply V2 and the reply coffee are added, and the second power supply and V2 are used as the level conversion module. The second power source V2 is cut between the first power source and the first level, and the reply circuit 3231 can be boosted first to generate the third driving signal S15', so that the power can be lower. Eliminate the level of the rising signal. In addition, the second driving signal sm ^the number S15 has sufficient capacity to drive the pixel array to enhance the overall mouth movement; 1 in summary, according to the flat display according to the present invention The device port = the board and its driving circuit 'adds the second power source as the level conversion mode = electricity, and the level of the second power source is between the first source and the third power, which can not only make the level The conversion module does not need high power supply = 16 200905647 should, but only in the level of the second power supply can be smoothly switched, which means to improve the level of the data signal, even using a large number of levels The conversion module can also be activated quickly, and there is no State failure problems, but also can reduce the amount of current drawn carrier, so as to protect the stability of the overall power. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional driving circuit; FIG. 2 is a schematic view showing a flat display device according to a preferred embodiment of the present invention; FIG. 3 is a plan view showing a preferred embodiment of the present invention. 4 is a schematic diagram showing a shifter in a drive circuit according to a preferred embodiment of the present invention; and FIG. 5 is a schematic view showing a return circuit in a drive circuit in accordance with a preferred embodiment of the present invention. [Main component symbol description] 1, 32 drive circuit 11 digital processing module 111 register 17 200905647 112, 3212 first buffer 12 analog processing module 121, 3221 shifter 122, 3222 converter 123, 3232 second Buffer 124 multiplexer 2 flat display device 3 flat display panel 31 pixel array 321 first processing module 3211 shift register 3213 first multiplexer 322 level conversion module 323 second processing module 3231 Recovery circuit 3233 second multiplexer 4 light source 11 positive input terminal 12 negative input terminal L light OPA pusher P pixel data signal P, complementary signal of pixel data signal Ql first input transistor 18 200905647 Q2 second input Transistor Q3 First load transistor Q4 Second load transistor R1, R2 Resistor Ref Reference signal SC Control signal see Clock control signal SOI Transition data signal S02 Drive signal S11 First data signal S12 Second data signal S13 A drive signal S14 second drive signal S15 苐 three drive signal VA analog power supply VD digital power supply VI first The second power supply V2 V3 V4 third fourth power supply 19