TW200905647A - Driving circuit, flat display panel and flat display apparatus - Google Patents

Driving circuit, flat display panel and flat display apparatus Download PDF

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Publication number
TW200905647A
TW200905647A TW96126443A TW96126443A TW200905647A TW 200905647 A TW200905647 A TW 200905647A TW 96126443 A TW96126443 A TW 96126443A TW 96126443 A TW96126443 A TW 96126443A TW 200905647 A TW200905647 A TW 200905647A
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Taiwan
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signal
electrically
level
power source
driving
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TW96126443A
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Chinese (zh)
Inventor
Chin-Cheng Tsai
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Chi Mei Optoelectronics Corp
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Priority to TW96126443A priority Critical patent/TW200905647A/en
Publication of TW200905647A publication Critical patent/TW200905647A/en

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Abstract

A driving circuit receiving a plurality of pixel data signals includes a first processing module, a level converting module and a second processing module. The first processing module supplied by a first power buffers the pixel data signals to output. The level converting module supplied by a second power is electrically connected with the first processing module. The level converting module raises the level of the pixel data signals within level range of the second power to output a first data signal and a second data signal complementary to each other. The level converting module converts the first data signal and the second data signal to selectively output a first driving signal in positive polarity or a second driving signal in negative polarity. The second processing module supplied by a third power is electrically connected with the level converting module. The second processing module raises the level of the first driving signal to generate a third driving signal, and selects the second driving signal or the third driving signal to output. The level of the second power is between levels of the first power and the third power.

Description

200905647 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a driving circuit, a display panel, and a display device, and more particularly to a driving circuit, a flat display panel, and a flat display device. [Prior Art] With the advent of the digital era, the technology of flat display devices, such as liquid crystal display devices, has also grown rapidly and has become an indispensable electronic product. Therefore, the technical and functional requirements for flat display devices are also increasing. The use of a good driving circuit to drive liquid crystal molecules has become one of the key technologies for improving the planar display device. March] 丄 丄 , , , , , , , , 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习 习. The driving circuit 1 has a number 4 processing mode, and 11 and an analog processing module U to process a plurality of 昼素资李

The condition number P ’ below is a simplified description. Only the single-single data signal P I 2 digital processing module u is powered by the digital power supply, and the pixel is poor. Zhao Wei h ^ - Di-Embroidery 1 series has a temporary register ill and the young buffer state register receives the primary signal SC shift and outputs 5 △ control signal SC and will control the output of the buffer - 112 - Synthetic wheel. . According to the control axis No. SC (4), the word p (1) is buffered (4) tfL No. P. The wheel is replaced by the analogy power supply + processing module 11 Data signal p. Analog processing 200905647 has a shifter 121, a converter 122, a second buffer 123, and a shifter 121 is electrically connected to the first buffer of the digital processing module 11 The converter 122 is electrically connected to the shifter 121 and the -,,, and the blister 123' multiplexer 124 are electrically connected to the second buffer 123. The 121 is based on the analog power source. Susu and improve the level of the data signal ρ to generate a transition state ^ redundant number SG1 ' and usually the transition state - a bit of the elementary data signal ρ on the real package makes Xiao # displacement 121, so If a plurality of pixel information numbers P are processed, a plurality of shifters 121 are used. The converter m receives a plurality of reference signals Ref from a resistor string, and converts the transition data signal s〇1 according to the reference signal Ref. a driving signal S02' and driving the circuit through the second buffer 123 and the multiplexer 124 to buffer the output The 1 series outputs a driving signal S02 to drive the pixels of the flat display panel, so that the liquid crystal molecules of the halogen are correspondingly actuated. *, ', However, due to the slow reaction time of the liquid crystal molecules, it is affected by the electric (four) of the reference signal Ref. Therefore, the analogy power supply VAd surface is larger; in addition, the 'digital processing chi-n material is more and more advanced, so the digital power supply VD ij can be smaller and smaller', thus causing the voltage difference between the analog power supply and the digital source VD In the above case, when the shifter (2) is engaged, if the gain value of the shifter 121 is designed; M, then it is easy to raise the position of the halogen data signal when the transfer state data signal P is used. If the gain meter is too large, the fortune will make the analog pumping current of the analog power supply VA too large. If the multiple information elements P are the same, then (four) several (four) Ϊ́2ι must be activated with the same time as 200105647 'There is a need to supply a very large amount of current'. This situation is likely to cause the supply of the overall power supply to be unbearable, and in severe cases, the internal components of the drive circuit 1 may be damaged. What is the object of the present invention is to provide a flat display device, a flat display panel, and a drive circuit that can solve the above problems - [Abstract] In view of the above problems, it is an object of the present invention to provide a smooth transition state. And the driving circuit, the flat display panel and the flat display device for reducing the current to be exchanged to protect the system power. The edge is that, in order to achieve the above object, a driving circuit according to the present invention receives at least one data signal, and the driving circuit includes a first A processing module, a quasi-conversion module and a second processing module. The first processing module is powered by a first power source and buffers the data signals and outputs the data. The level conversion module is powered by a second power source and electrically connected to the first processing module. The level conversion module increases the level of the data signal in the level of the second power source to output complementary data. A first data signal and a second data signal are converted to convert a first data signal and a second data signal to generate a first driving signal and a second driving signal, respectively. The second processing module is powered by a third power source and electrically connected to the level conversion module. The second processing module increases the level of the first driving signal to generate a third driving signal, and selects the second The driving signal or the third driving signal output, wherein the level of the second power source is between the levels of the first power source and the third power source. 200905647 In order to achieve the above object, according to one of the present invention - a pixel array and a driving circuit::, the panel system comprises a data signal, the driving circuit has - receiving at least one element group and a second processing #吴,, and A quasi-conversion mode + brother-processing module. The younger brother--the processing module is outputted by the first private, buffering the data signal. Source for two power supply and with the first-processing module by a second in the second electric community (four) κ shouting module system

St - the second information signal, and the conversion of the first - second data signal to generate a first: - brother two drivers. The second processing mode: wide:::::rr connection, the second processing" second drive or brother: the drive signal is output to the pixel array, wherein the second power supply is at the level of the first power source and the third power source between. ',^-金目' according to the present invention, a flat display farm system comprising a denier array, a light source and a driving electric pixel array to display an image 'drive electric charge at least: j, the first road has a first A processing module; turn; 2: and - brother two processing module. The first processing module is supplied by a first power source and buffered by the halogen (4). The level conversion contact system is powered by 2 sources and electrically connected to the first processing module, and the level conversion module is used to raise the level of the data signal in the level of the power source of the second brother to output one of the complementary ones. The information signal and a second data signal are converted to the first and second data signals to be divided into the secondary student-first driving signal 200105647 and a second driving signal. The second processing module is powered by a third power source, and the level is generated to generate a third driving signal 'c' output to the pixel array, wherein the second system is between the level of the third electrical source. Early board and == because of the invention of the flat display device, the flat display surface ΐ = 3 plus the second power supply as the level conversion module for the door position is between the first - power supply and the third power source ! ^ Not only can the level conversion module not need to be replaced by a high power supply, that is, it can be smoothly changed to the level of the liquid in the range of the liquid. Can be activated quickly 'and in addition to not turning '_ stability. Can reduce the amount of pumping current' and thus protect the overall power supply [Implementation] Seeding board::::::: Jiashi · - 2 shows The flat display device of the preferred embodiment of the present invention is a panel 4 and a light source 4. The flat display panel 3 has two ft columns: 1 and a driving circuit 32. The light source 4 is connected to the flat panel.目 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 平面 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = 平面 = = = = = The light source 4 is implemented as a backlight module. The driving circuit 32 of the present embodiment receives a plurality of pixel data signals p and has a first processing module 321, a quasi-conversion module 322 and a second processing module 323; and each pixel data P is implemented as a wrist The material signal is also a digital signal. Therefore, the driver circuit 32 receives six lbits of the data signal P as an example. The first processing module 321 of the embodiment is powered by two bits, and the level conversion mode is requested. The second power supply 220 is powered by a third power supply V3. The second power supply V2 of the embodiment is implemented in the first power supply vi and the third power supply V3. Between the levels, and the level of the third power source V3 is greater than the level of the first power source V1, for example, the level of the second power source V 2 is between 7.5 volts and 13 volts.

In the embodiment, the first processing module 321 has a shift register 3211, a first buffer 3212, and a first multiplexer m3. - Shift 2 register 32U is electrically connected (4) ι "32ΐ2_ 多工益3213. The first multiplexer 3213 receives a clock control signal SCC and each pixel data signal Ρ, and according to the clock control signal SCC, & 士^Negative output of each element data signal P to the shift register 3211; for example, also when the gentleman king seconds, the first multiplexer 321 Λ control minus a low level signal SCC is - Micro Motion selects the positive polarity output. When the pulse-controlled negative polarity is transferred, the first-multiplexer cuts the 3 series. The definition of the polarity U is based on the voltage value greater or less than 12 200905647. The common voltage of the color filter substrate ((3)mmcm v〇itage) (not shown) is positive when the voltage value is greater than the common voltage, and negative when the voltage value is less than the common voltage. If the voltage value of the data signal P is greater than the common voltage, the data signal P is positive; if the voltage value of the data signal p is less than the common electricity, the data signal p is negative; The first multiplexer 3213 is based on the clock control signal scc For example, the shift register 3211 outputs a control signal SC to the first buffer=12 γ and shifts each of the pixel data signals p, and is a low level. The control signal sc controls the first buffer 3212 to receive the respective pixel data signals P, and the first buffer 3212 buffers the respective data signals p. The shift register 3211 of the embodiment is implemented. The first buffer 3212 is a line buffer (linebuffer), and the level conversion module 322 is electrically connected to the first processing module 321 by a bidirectional shift register (4) ❹ (10) 丨 (4). The number of the shifters 3221 is the same as the number of the pixel data signals p received by the drive circuit 32, that is, the number of the shifters 3221 is the same as the number of the pixel data signals p received by the drive circuit 32. A level shifting 3221 corresponds to and receives a 1-bit pixel data signal p, and the field level conversion module 322 receives six 1-bit pixel data signals p 牯, and the level conversion module 322 has six shifters. 3221. Months are again shown in Figure 4, Figure 4 is in Figure 3 The circuit diagram of the shifter 3221 is electrically connected to the first processing module 321 and has a first input transistor qi and a second input 13 200905647 ::曰:Γ first The load transistor Q3 and the second load transistor are connected to the source of the transistor Q1 and the second input transistor is connected to a fourth power source V4, and the gate of the first load transistor Q3 is electrically connected to the first input power. The crystal Q1 is infinite pole: the body Q4, the closed pole is electrically connected to the second wheeled transistor Q2J is electrically far 2 the source of Q crystal Q3 and the source polarity of the second load transistor Q4 is connected ί - power supply V2, — The pole of the transistor Q2 of the load transistor Q3 is electrically connected, and the 35th of the second load transistor Q4 is electrically connected to the first pole of the crystal 1 of the input 1 crystal. Fourth of the embodiment: the source V4 is implemented as an analog grounding power source. The gate of the second round of the input transistor Q1 receives the halogen data signal p, complements the J, and the gate of the human crystal Q2 receives the mutual load of the elementary data signal P and the U-displacement shifter 3221 by the first The rotation of the transistor Q1 and the second transistor 曰2 Q4 'and the second input transistor Q2 and the first-loader; the material (4) cooperates to increase the level of the second power source V2 to draw the j signal P The level of the second input power, the Japanese body Q2, the immersive material, the first input transistor Q1, and the 4 _ owe a material signal S12. The first data signal S11 of the present embodiment is complementary to each other in the implementation, and is respectively one of the two. In this case, the level conversion module 322 is used to generate a total of six pairs of pairs. The material signal S11 and the second data signal are taken as examples. Referring again to FIG. 3, the converter assists receiving a plurality of reference times e/ and electrically connecting with each of the shifters 3221 to receive six pairs of the first pupil number S11 and the second poor signal S12, the converter According to the reference No. 14 200905647, the A number Ref is the first data of the six pairs. Negative Newsletter converts S11 and the second data signal S12 to generate a brother-in-one driver. The converter is greeted by a number H13 or a second driver signal digital analog converter (digital to ΠΓΓ.! 813s14 is a type of analog signal, and has a lightning example, the first drive signal S13 is implemented = value. In addition, the second implementation number S14 is negative polarity, which means that the first driving signal is the common voltage, and the voltage of the second driving signal su is greater than < the rabbit pressure value is smaller than the common lightning. In this case, the output of the first driving signal is performed by the converter 3222. Since the level conversion module 322 is in the first private level due to the second power source v, the level of the second power source V2 is Therefore, the position conversion module 322 only switches between the two power supply V3 and the power supply V2, so as to avoid the bit-power supply and the first can reduce the load current when the transition state, and the 3221 transition state fails. In order to ensure the stability of the overall power supply, please refer to the third level. In this embodiment, the system is electrically connected to the level conversion module 322, and the 323 323-second buffer and the second n reply circuit Figure 5 is the recovery circuit 3231 of Figure 3 - 立立323i and level conversion module 322 < Converter - 'Response circuit has - pusher 0PA and multiple electric: ° · Sexual connection, and has - positive input terminal η and a negative wheel end Ι 2, the first liter of fasting To the pusher ship positive and negative input terminal 12' and the pusher 0 ΡΑ and the resistor R1, R2 == 15 200905647 The second power supply V2 pushes the / drive. hole number $ 13 to generate the third drive signal S15. In the embodiment, the bait multiplexing circuit 3231 is implemented in an inverted phase, and the second buffer 3232 is respectively connected to the conversion path amplifier. Please refer to: the device 3222 and the reply to the network 3231 privately connected, and Receive the second driving motion separately? Tiger S15' 苐 2 buffer 3232 buffering signal S14 and the second and second driving signal state and the second driving signal yang output. The second multiplex is crying in the second 绫The balance 3232 is electrically connected and controlled according to the clock; the number is selected as odd, the even channel is rotated by the third drive _^^ or the odd or even channel second drive signal S14 is connected to the pixel array 31. This embodiment The odd-numbered channel and the even-numbered channel are respectively positive or negative polarity input 4, which is The odd channel is given as positive polarity, and the even channel is negative polarity output as an example.] In this embodiment, 'the second power supply V2 and the reply coffee are added, and the second power supply and V2 are used as the level conversion module. The second power source V2 is cut between the first power source and the first level, and the reply circuit 3231 can be boosted first to generate the third driving signal S15', so that the power can be lower. Eliminate the level of the rising signal. In addition, the second driving signal sm ^the number S15 has sufficient capacity to drive the pixel array to enhance the overall mouth movement; 1 in summary, according to the flat display according to the present invention The device port = the board and its driving circuit 'adds the second power source as the level conversion mode = electricity, and the level of the second power source is between the first source and the third power, which can not only make the level The conversion module does not need high power supply = 16 200905647 should, but only in the level of the second power supply can be smoothly switched, which means to improve the level of the data signal, even using a large number of levels The conversion module can also be activated quickly, and there is no State failure problems, but also can reduce the amount of current drawn carrier, so as to protect the stability of the overall power. The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the present invention are intended to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional driving circuit; FIG. 2 is a schematic view showing a flat display device according to a preferred embodiment of the present invention; FIG. 3 is a plan view showing a preferred embodiment of the present invention. 4 is a schematic diagram showing a shifter in a drive circuit according to a preferred embodiment of the present invention; and FIG. 5 is a schematic view showing a return circuit in a drive circuit in accordance with a preferred embodiment of the present invention. [Main component symbol description] 1, 32 drive circuit 11 digital processing module 111 register 17 200905647 112, 3212 first buffer 12 analog processing module 121, 3221 shifter 122, 3222 converter 123, 3232 second Buffer 124 multiplexer 2 flat display device 3 flat display panel 31 pixel array 321 first processing module 3211 shift register 3213 first multiplexer 322 level conversion module 323 second processing module 3231 Recovery circuit 3233 second multiplexer 4 light source 11 positive input terminal 12 negative input terminal L light OPA pusher P pixel data signal P, complementary signal of pixel data signal Ql first input transistor 18 200905647 Q2 second input Transistor Q3 First load transistor Q4 Second load transistor R1, R2 Resistor Ref Reference signal SC Control signal see Clock control signal SOI Transition data signal S02 Drive signal S11 First data signal S12 Second data signal S13 A drive signal S14 second drive signal S15 苐 three drive signal VA analog power supply VD digital power supply VI first The second power supply V2 V3 V4 third fourth power supply 19

Claims (1)

  1. 200905647, the scope of application for patent: No., which drives a driving circuit, which receives a plurality of pixel data circuits, including: - the first processing module is powered by the - power supply, and buffers the rear information signals of the halogen data signals The - level conversion module is powered by the second power source and is connected to the first processing module. The level conversion module is used to raise the material in the level of the second power source (4). The position of Saki is to output: the first data signal and the second data signal, and convert the first data signal and the second data signal to select - positive polarity output - first - drive signal or a negative polarity outputting a first driving signal; and a middle module, which is powered by a third power source and electrically connected to the level=module, the second processing module is raised to generate a level And driving the third driving signal or the third driving signal output, wherein the level of the second source is between the first power source and the third power source. 2, 2 Please turn the _ circuit described in (4), where the full digit = «, the first - data signal and the second data signal system; 3, as in the patent application (four) 1 item drive circuit, which A 20 200905647 driving signal, the second driving signal and the third driving signal are respectively analog signals. 4. The driving circuit of claim 1, wherein the third power source has a level greater than a level of the first power source. 5. The driving circuit of claim 2, wherein the second power source has a level ranging from 2.5 volts to 13 volts. The driving circuit of the first aspect of the patent application, wherein the first processing module comprises: a clock control signal and the first multiplexer - the first multiplexer receives the signal "the field material" The control dragon selects 卩—positive or negative polarity to turn out the halogen data signals; a multiplexer is electrically connected and outputs
    The shift register is coupled to the first control signal and a first buffer, and the shift control signal controls the first number, and the first buffer is slowed down to the level conversion module. For example, the sixth aspect of the patent application scope is a bidirectional shift register. The driving circuit of the above-mentioned 6th, wherein the buffer circuit is a row of buffers. The above-mentioned ._circuit's -^ a plurality of shifters are respectively electrically connected to the first processing module to receive the pixel data signals by f, and in the level range of the second power source Enhancing the level of the data signals to output the complementary first-data signal and the second data signal; and - the converter is connected to the electrical signals of the shifter and the second data signal, And converting the first first bead signal to select to output the first driving signal with the positive polarity or output the second driving signal with the negative polarity. I. The driving circuit described in claim 9 (4), wherein the shifter system comprises: a first input transistor, wherein the gate receives the data signals; and a second input transistor, the gate system Receiving a complementary signal of the pixel data signals, wherein the first and the second input transistor are electrically connected to a fourth power source; the first load transistor is electrically connected to the gate And the second load transistor is electrically connected to the drain of the second input circuit 22 200905647 crystal, wherein the source of the first and second load transistors Electrically connecting the second power source, the drain of the first load transistor is electrically connected to the drain of the second input transistor to output the first data signal, and the drain of the second load transistor is electrically The first input transistor is connected to the drain of the first input transistor to output the second data signal. 11. The driving circuit of claim 9, wherein the converter is a digital analog converter. 12. The driving circuit of claim 1, wherein the second processing module comprises: a recovery circuit electrically powered by the third power source and electrically connected to the level conversion module, and having a The pusher receives the second power to push the first driving signal to generate the third driving signal. 13. The driving circuit of claim 12, wherein the recovery circuit is an inverted closed loop amplifier, wherein the second power source and the first driving signal are respectively input to one of the pusher positive inputs. Terminal and a negative input. 14. The driving circuit of claim 12, wherein the second processing module further comprises: 23 200905647 a second buffer electrically connected to the level conversion module and the recovery circuit, And respectively buffering the second driving signal and the third driving signal; and a second multiplexer electrically connected to the second buffer, and selecting to output the third driving signal or odd number in an odd or even channel Or the even channel outputs the second driving signal. 15. A flat display panel comprising: a pixel array; and a driving circuit for receiving a plurality of pixel data signals, the driving circuit having a first processing module, a quasi-conversion module, and a second processing The first processing module is powered by a first power supply and buffers the data signals, and the level conversion module is powered by a second power supply and the first processing module Electrically connecting, the level conversion module increases the level of the pixel data signals within the level of the second power source to output a complementary first signal and a second data signal, and The first data signal and the second data signal are converted to output a first driving signal with a positive polarity or a second driving signal with a negative polarity. The second processing module is powered by a third power source. The second processing module is configured to increase the level of the first driving signal to generate a third driving signal, and select the second driving signal or the third driving signal to output to the second driving signal. Day pixel array, wherein the level of the second power supply line between the first power source and 24200905647 between the level of the third power. 16 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 *Beeting Ten Table No. 17 18 19 2 The flat display panel described in Item 15 of the patent, the first drive signal and the second drive are respectively analog signals. The flat display panel of the above aspect, wherein the level of the second power source is greater than the level of the first power source. , = please (4) 15 of the flat _ (four) board, Yizhong ^ brother a power supply standard _ between 2.5 volts to 13 volts 20, the range of the plane display panel mentioned in item 15, I child A processing module includes a ································································································· a data signal; a shift register is electrically connected to the first multiplexer, a control signal, and receives and shifts the data signals; '25 200905647 and a first buffer, Is electrically connected to the shift register, wherein the control signal controls the first buffer to receive the data signals, and the first buffer buffers the data signals and outputs the data to the level Conversion module. 21. The flat display panel of claim 20, wherein the register is a bidirectional shift register. 22. The flat display panel of claim 20, wherein the first buffer is a row of buffers. The flat display panel of claim 15, wherein the level conversion module comprises: a plurality of shifters electrically connected to the first processing module to respectively receive the pixels And the information signal is updated to the level of the second data source to output the complementary first data signal and the second data signal; and a converter and the like The shifter is electrically connected to receive the first data signal and the second data signal, and converts the first data signal and the second data signal to select to output the first driving signal or the negative polarity with the positive polarity The second driving signal is output. 24. The flat display panel of claim 23, wherein 26 200905647 the shifter comprises: a first input transistor, the gate receiving the pixel data signals; and a second input power a crystal, the gate receiving a complementary signal of the halogen data signals, wherein the first and second input transistors are electrically connected to a fourth power source; a first load transistor, the gate thereof Electrically connecting the drain of the first input transistor; and a second load transistor, the gate of which is electrically connected to the drain of the second input transistor, wherein the first and the second load are electrically The source of the crystal is electrically connected to the second power source, and the drain of the first load transistor is electrically connected to the drain of the second input transistor to output the first data signal, and the second load transistor is The drain is electrically connected to the drain of the first input transistor to output the second data signal. 25. The flat display panel of claim 23, wherein the converter is a digital analog converter. The flat display panel of claim 15, wherein the second processing module comprises: a reply circuit electrically powered by the third power source and electrically connected to the level conversion module, and having a pusher that receives the second power to push the first drive signal to generate the third 27 200905647 drive signal. The flat display panel of claim 26, wherein the recovery circuit is an inverted closed loop amplifier, wherein the second power source and the first driving signal are respectively input to one of the pushers Input and a negative input. The flat display panel of claim 26, wherein the second processing module further comprises: a second buffer electrically connected to the level conversion module and the recovery circuit to Buffering the second driving signal and the third driving signal respectively; and a second multiplexer electrically connected to the second buffer, and selecting to output the third driving signal or odd number in an odd or even channel Or the even channel outputs the second driving signal. 29. A flat display device comprising: a pixel array; a light source for generating light passing through the pixel array to display an image; and a driving circuit for receiving a plurality of pixel data signals, the driving circuit comprising a first processing module, a quasi-conversion module, and a second processing module, wherein the first processing module is powered by a first power source, and buffers the pixel data signals for output, and the level conversion 28 200905647 The die button is powered by a second power source and connected to the first +: the level conversion module is in the second power source: two! : mention = equal to the level of the data signal to turn out a second material signal and a second data signal, and converting the fourth η: second data signal to select a positive-emission rain-driving first-drive signal or a negative polarity output-the second processing module The third processing module is configured to generate a third driving signal, and the third driving signal or the third driving signal is output to the third driving signal. The gui == the level of the second power source is between The level between the first power and the second power source. 30 31. If you apply for the flat display device of the full-length 29th rhyme, the elementary data signal, the first data signal and the system-number call. The flat display device of the invention of claim 29, wherein the first drive signal, the second drive signal and the third drive signal are respectively analog signals. The planar display device of claim 29, wherein the level of the third power source is greater than the level of the first power source. The flat display device of claim 29, wherein the second power source has a level range of between 2.5 volts and 13 volts. 34. The flat display device of claim 29, wherein the first processing module comprises: a first multiplexer that receives a clock control signal and the pixel data signals, according to the time The pulse control signal is selected to output the halogen data signals by a positive polarity or a negative polarity; a shift register is electrically connected to the first multiplexer, and outputs a control signal, and receives and shifts And the first buffer is electrically connected to the shift register, wherein the control signal controls the first buffer to receive the pixel data signal, the first buffer The device buffers the halogen data signals and outputs the signals to the level conversion module. 35. The flat display device of claim 34, wherein the register is a bidirectional shift register. The flat display device of claim 34, wherein the first buffer is a row of buffers. 37. The flat display device of claim 29, wherein 30 200905647 the level conversion module comprises: a plurality of shifters electrically connected to the first processing module to respectively receive the same a data signal that increases the level of the pixel data signals within the level of the second power source to output the complementary first data signal and the second data signal; and a converter The shifters are electrically connected to receive the first data signal and the second data signal, and convert the first data signal and the second data signal to output the first driving signal or the negative polarity The second driving signal is output. 38. The flat display device of claim 37, wherein the shifter comprises: a first input transistor, the gate receiving the halogen data signal; and a second input transistor; The gate receives the complementary signal of the halogen data signals, wherein the first and the second input transistors are electrically connected to a fourth power source; and the first load transistor has a gate current The first input transistor is connected to the drain of the first input transistor; and a second load transistor is electrically connected to the drain of the second input transistor, wherein the first and second load transistors are sourced The pole is electrically connected to the second power source, and the drain of the first load transistor is electrically connected to the drain of the second input transistor to output the first data signal, and the second load transistor is connected to the drain The electrical connection 31 200905647 is connected to the drain of the first input transistor to output the second data signal. 39. The flat display device of claim 37, wherein the converter is a digital analog converter. 40. The flat display device of claim 29, wherein the second processing module comprises: a reply circuit electrically powered by the third power source and electrically connected to the level conversion module, and having a pusher that receives the second power to push the first drive signal to generate the third drive signal. The flat display device of claim 40, wherein the recovery circuit is an inverted closed loop amplifier, wherein the second power source and the first driving signal are respectively input to one of the pushers Input and a negative input. The flat display device of claim 40, wherein the second processing module further comprises: a second buffer electrically connected to the level conversion module and the recovery circuit to respectively Buffering the second driving signal and the third driving signal; and a second multiplexer electrically connected to the second buffer, and selecting 200905647 to output the third driving signal in an odd or even channel or The odd or even channel outputs the second drive signal. The flat display device of claim 29, further comprising a flat display panel, the flat display panel being disposed opposite the light source and having the pixel array and the driving circuit.
TW96126443A 2007-07-19 2007-07-19 Driving circuit, flat display panel and flat display apparatus TW200905647A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702189A (en) * 2014-11-26 2016-06-22 群创光电股份有限公司 Scanning driver circuit and display panel employing same
TWI552129B (en) * 2014-11-26 2016-10-01 群創光電股份有限公司 Scan driver and display using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702189A (en) * 2014-11-26 2016-06-22 群创光电股份有限公司 Scanning driver circuit and display panel employing same
TWI552129B (en) * 2014-11-26 2016-10-01 群創光電股份有限公司 Scan driver and display using the same

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