CN105702189B - Scan drive circuit and the display panel for applying it - Google Patents
Scan drive circuit and the display panel for applying it Download PDFInfo
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- CN105702189B CN105702189B CN201410696717.4A CN201410696717A CN105702189B CN 105702189 B CN105702189 B CN 105702189B CN 201410696717 A CN201410696717 A CN 201410696717A CN 105702189 B CN105702189 B CN 105702189B
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Abstract
The present invention proposes a kind of scan drive circuit and the display panel using it.Scan drive circuit includes multistage first driving unit.Multistage first driving unit is controlled by the first initial signal, clock signal and an at least selection signal, and wherein the first driving unit of i-stage includes a shift register and a de-multiplexer.Shift register generates scanning signal according to clock signal and trigger signal.De-multiplexer is according to an at least selection signal, by scanning signal selectively output to multiple scan lines.Wherein the trigger signal of the 1st grade of the first driving unit is the first initial signal, and the trigger signal of the first driving unit of (i+1) grade is the scanning signal of the first driving unit of i-stage.
Description
Technical field
The invention relates to a kind of scan drive circuit and using its display panel, and in particular to a kind of benefit
With the scan drive circuit of de-multiplexer.
Background technique
With development in science and technology, display panel has been widely used in various electronic device at present, such as mobile phone,
TV, computer screen etc..In response to the high-res demand of display panel, usually with scan drive circuit cooperation data-driven electricity
Road, the image information of entire picture is written.On the other hand, in order to save external printed circuit board cost, using on panel
Thin film transistor (TFT) (Thin Film Transistor, TFT), by the partial scan driving circuit to drive scan line, in
When thin film transistor (TFT) array makes, it is formed on the substrate of display panel together, this technology can be described as GOP (Gate on
Panel) the display panel of technology.In this way, external scan driving circuit complexity and volume can be simplified, while panel can be reduced
Production cost.And area occupied by scan drive circuit how is effectively reduced, become one of the project that current industry is endeavoured.
Summary of the invention
The present invention proposes its display panel of a kind of scan drive circuit and application, and especially a kind of utilizes de-multiplexer
Scan drive circuit.
According to the first aspect of the invention, a kind of scan drive circuit is proposed.Scan drive circuit includes that multistage first is driven
Moving cell.Multistage first driving unit is controlled by the first initial signal, clock signal and an at least selection signal, wherein i-stage
First driving unit includes a shift register and a de-multiplexer.Shift register is according to clock signal and trigger signal
Generate scanning signal.De-multiplexer is according to an at least selection signal, by scanning signal selectively output to multiple scan lines.Wherein
The trigger signal of 1st grade of the first driving unit is the first initial signal, and the trigger signal of the first driving unit of (i+1) grade is
The scanning signal of i the first driving unit of grade.
According to the second aspect of the invention, a kind of display panel, including thin-film transistor array base-plate, the first display are proposed
Region and scan drive circuit.First display area is formed on thin-film transistor array base-plate, and the first display area includes
Multiple first row pixel circuits.Scan drive circuit includes multistage first driving unit.Multistage first driving unit is controlled by the
One initial signal, clock signal and an at least selection signal, wherein the first driving unit of i-stage include a shift register and
One de-multiplexer.Shift register generates scanning signal according to clock signal and trigger signal.De-multiplexer is according at least one
Selection signal, by scanning signal selectively output to one of multiple scan lines, each scanning line driving first row pixel circuit.
Wherein the trigger signal of the 1st grade of the first driving unit is the first initial signal, the trigger signal of the first driving unit of (i+1) grade
It is the scanning signal of the first driving unit of i-stage.
Detailed description of the invention
For the above objects, features and advantages of the present invention can be clearer and more comprehensible, below in conjunction with attached drawing to tool of the invention
Body embodiment elaborates, in which:
Figure 1A is painted the schematic diagram of known display panel.
Figure 1B is painted the signal timing diagram of known display panel.
Fig. 2 is painted the schematic diagram according to first embodiment of the invention display panel.
Fig. 3 is painted the circuit framework figure according to de-multiplexer in first embodiment of the invention display panel.
Fig. 4 A is painted according to the signal timing diagram in first embodiment of the invention display panel.
Fig. 4 B is painted the signal timing diagram of progressive scan.
Fig. 5 is painted the schematic diagram according to first embodiment of the invention write-in picture data.
Fig. 6 is painted the schematic diagram according to second embodiment of the invention display panel.
Fig. 7 is painted the schematic diagram according to second embodiment of the invention write-in picture data.
Fig. 8 is painted a kind of schematic diagram of external control circuit.
Fig. 9 A is painted the schematic diagram according to third embodiment of the invention display panel.
Fig. 9 B is painted the schematic diagram according to fourth embodiment of the invention display panel.
Figure 10 A and Figure 10 B are painted the schematic diagram according to de-multiplexer used in fourth embodiment of the invention.
Figure 11 is painted according to the signal timing diagram in fourth embodiment of the invention display panel.
Figure 12 is painted the circuit framework figure of shift register.
Component label instructions in figure:
2,6,9: display panel
20,60,90: thin-film transistor array base-plate
21,61,91: scan drive circuit
22,62,92: the first display area
62 ': the second display area
80: memory unit
82: comparing unit
84: control unit
C1: capacitor
C (1), C (2): thermal compensation signal
Com (1)~Com (2n): compensating line
CKV: clock signal
Data bus: data/address bus
DM (1), DM (2), DM ' (1), DM ' (2), DMc (1), DMc (2): de-multiplexer
F01~F04, F11~F20: picture
R (1)~R (2n): first row pixel circuit
R (h+1)~R (h+2n): secondary series pixel circuit
S (1), S (2), S ' (1), S ' (2): scanning signal
Scan (1)~Scan (2n): scan line
Selector, Sel1, nSel1, Sel2, nSel2, Sel3, nSel3, Sel4, nSel14: selection signal
SD (1), SD (2), SD ' (1), SD ' (2): the first driving circuit
SR (1), SR (2), SR ' (1), SR ' (2), SRc (1), SRc (2): shift register
STV: initial signal
STV1: the first initial signal
STV2: the second initial signal
STVc: compensation initial signal
T1~T8, T11~T16: transistor
VGL: blanking voltage current potential
Specific embodiment
The schematic diagram of known display panel is painted please also refer to Figure 1A and Figure 1B, Figure 1A, Figure 1B is painted known display surface
The timing control figure of plate.Display panel 1 includes M column pixel circuit (ROW) R (1)~R (M), such as is for resolution
The display panel 1 of 1280x960, M are equal to 960.The scan drive circuit of display panel 1 includes M shift register (Shift
Register, SR) SR (1)~SR (M), M shift register be controlled by identical clock signal CKV, the 1st grade of shift LD
Device SR (1) receives the first initial signal STV1 to determine the time for starting to be scanned.Since M shift register SR goes here and there each other
Connection, when occurring clock signal CKV positive edge, the pulse meeting level-one level-one of initial signal STV shifts down, can refer to Figure 1B and draws
Scanning signal Scan (1)~Scan (M) that each shift register SR (the 1)~SR (M) shown is exported.Scanning signal Scan
(i) column pixel circuit R (i) is driven, so that the i-th column of display panel 1 can accept data driver and (for simplicity, not draw
It is shown in figure) data that are written.As shown in Figure 1B, display panel 1 is that image data is written in a manner of scanning by column, when sweeping
After the M column for having retouched a picture (frame), initial signal STV is triggered, again to re-start scanning by column.
The scan drive circuit as depicted in Figure 1A has all needed a corresponding displacement for each column pixel circuit
Register, and these shift registers can be formed in the TFT substrate of display panel 1 with GOP technology, or are present in grid collection
At in circuit drives element (gate driver IC), the occupied circuit layout of scan drive circuit will lead to by this method
(layout) area is too big.Following embodiment separately proposes a kind of scan drive circuit that circuit layout area can be effectively reduced.
Fig. 2 is painted the schematic diagram according to first embodiment of the invention display panel.Display panel 2 includes thin film transistor (TFT) battle array
Column substrate 20, scan drive circuit 21 and the first display area 22.First display area 22 is formed in thin film transistor (TFT) array
On substrate 20, including multiple first row pixel circuit R (1), R (2) ....Scan drive circuit 21 is formed in thin film transistor (TFT) battle array
On column substrate 20, including multistage the first driving unit SD (1), SD (2) ..., be controlled by the first initial signal STV1, clock pulse letter
A number CKV and at least selection signal Selector.Wherein the first driving unit SD (i) of i-stage includes a shift register SR (i)
And de-multiplexer (De-multiplexer, DEMUX) DM (i).Shift register SR (i) according to clock signal CKV and
Trigger signal generates scanning signal S (i).De-multiplexer DM (i) is according to an at least selection signal Selector, by scanning signal S
(i) selectivity is exported to one of multiple scan line Scan, each scan line Scan driving first row pixel circuit R.Wherein the 1st
The trigger signal of the first driving unit SD (1) of grade is the first initial signal STV1, (i+1) grade the first driving unit SD (i+1)
Trigger signal be the first driving unit SD (i) of i-stage scanning signal S (i), i is positive integer more than or equal to 1.In detail
It is described as follows.
In the embodiment of the present invention, driving circuit 21 is realized with thin film transistor (TFT) (TFT) using GOP technology, will be scanned
Driving circuit 21 is formed on thin-film transistor array base-plate 20 or driving circuit 21 is located at grid integrated circuits driving element
In (gate driver IC).21 received signal of scan drive circuit, including clock signal CKV, the first initial signal
STV1, selection signal Selector, can come from the printed circuit board other than thin-film transistor array base-plate 20, such as by specific
Drive integrated circult provide.
Below as explanation by taking the 1st grade of first driving unit SD (1) as an example.1st grade of first driving unit SD (1) can be only
Cooperate 1 de-multiplexer DM (1) using 1 shift register SR (1), drives n scan line Scan (1)~Scan to generate
(n) signal.N scan line Scan (1)~Scan (n) can be used to drive n column pixel circuit R of the first display area 22
(1)~R (n).De-multiplexer DM (1) is selectively to be exported scanning signal S (1) according to an at least selection signal Selector
To scan line Scan (1)~Scan (n), by taking n=4 as an example, de-multiplexer DM (1) can be according to an at least selection signal Selector
(such as selected is the 2nd article of scan line) exports scanning signal S (1) to scan line Scan (2), and other are non-selected
3 scan line Scan (1), Scan (3) and Scan (4) can then give a blanking voltage current potential VGL, so may make column picture
Plain circuit R (2) is written into data, and the switch keeping off state of column pixel circuit R (1), R (3) and R (4) are without being written into
Data.
Fig. 3 is painted a kind of circuit framework figure of achievable de-multiplexer DM (1).It is the de-multiplexer using 1 pair 4 in this
(n=4), de-multiplexer DM (1) includes 8 TFT T1~T8, according to 8 selection signals Sel1, nSel1, Sel2, nSel2,
Sel3, nSel3, Sel4, nSel4, to scan line Scan (1)~Scan (4), selectivity exports scanning signal S (1) and cuts respectively
Only one of voltage potential VGL.Wherein selection signal nSel1 is the inversion signal of selection signal Sel1, remaining and so on.
When selection signal Sel1 is logic high potential, scan line Scan (1) exports scanning signal S (1), and when selection signal Sel1 is
When logic low potential, scan line Scan (1) exports blanking voltage current potential VGL.As shown in figure 3, each scan line can be individual
Control output, it is independent each other, blanking voltage can be also exported simultaneously to whole scan lines.Via appropriately designed outside
Control circuit to generate selection signal Sel1, nSel1, Sel2, nSel2, Sel3, nSel3, Sel4, nSel4, can complete
User's control mode to be designed.
The quantity of selection signal Selector is relevant to the scan line quantity n of the first driving unit SD (1) output, when first
The scan line quantity n that driving unit SD (1) need to drive is more, and the quantity of selection signal Selector also just increases therewith, with energy
It is enough to make a choice from n scan line.Above-mentioned example is the mode that one kind can be able to achieve (1) de-multiplexer DM, however not
It is limited to this, for one 1 pair 4 of de-multiplexer, selection signal can be 2,4 or 8, and end view de-multiplexer DM is practical
The function and design limitation that need to complete and determine.
Referring to FIG. 2, the 1st grade of first driving unit SD (1) as described above generates n scan line Scan (1)~Scan (n)
Driving signal, the 2nd grade of first driving unit SD (2) can also be also responsible for generate n scan line Scan (n+1)~Scan
The scan line quantity of the driving signal of (2n), the first driving unit outputs certainly at different levels can also be different, only when the first driving is single
When the series of member increases, if the scan line quantity of output at different levels is identical, it is easier to complete on hardware Winding Design, timing control
System is relatively easy to design.If the scan line quantity of the first driving unit outputs at different levels is all n, for needing to export the scanning of M item
The scan drive circuit 21 of line is needed using the first driving unit SD (i) of (M/n) grade, and (M/n) a shift register can be used only
SR(i)。
Shift register SR (1) the 2nd grade of first driving unit SD (2) of series connection in 1st grade of first driving unit SD (1)
Shift register SR (2) in the middle, similarly, shift register SR (2) series connection the 3rd in the 2nd grade of first driving unit SD (2)
Shift register SR (3) in the first driving unit SD (3) of grade.The trigger signal of i.e. the 1st grade first driving unit SD (1) is
First initial signal STV1, and the trigger signal of the first driving unit of (i+1) grade is the scanning letter of the first driving unit of i-stage
Number S (i).
Fig. 4 A is painted according to the signal timing diagram in first embodiment of the invention display panel.For simplified illustration and clearly
Chu's explanation, is as explanation by taking n=2 as an example in Figure 4 A, i.e. each first driving unit SD (i) is all the solution using 1 pair 2
Multiplexer DM (i), selection signal Selector include Sel1, Sel2, nSel1, nSel2.In this example, the first display area 22 has
2m column pixel circuit R (1)~R (2m), scan drive circuit 21 include m grade the first driving unit SD (1)~SD (m).
Due to using 1 couple 2 of de-multiplexer DM (i), 2 can be divided into for the writing process of an image (frame)
Stage (Phase).(Phase 1) selection signal Sel1 maintains logic high potential in the first stage, and selection signal Sel2 is then maintained
Logic low potential, therefore for de-multiplexer DM (i) at different levels, state is all scanning signal S (i) output that will be inputted
To its 1st output connecting pin.As shown in Figure 4 A, after triggering the first initial signal STV1, via concatenated shift register
SR (1)~SR (m) gradually can drive scan line Scan (1), and Scan (3), Scan (5) ..., Scan (2m-1), data are driven at this time
Dynamic device need to cooperate the corresponding driving data D of output1,D3,D5,…,D2m-1To data/address bus.
Logic low potential is maintained in second stage (Phase 2) selection signal Sel1, selection signal Sel2 then maintains logic
High potential, the state of de-multiplexer DM (i) at different levels is all that the scanning signal S (i) of input terminal is output to its 2nd output at this time
Pin.The first initial signal STV1 is triggered again, similarly via concatenated shift register SR (1)~SR (m), can gradually be driven
Dynamic scan line Scan (2), Scan (4), Scan (6) ..., Scan (2m), data driver need to cooperate the corresponding drive of output at this time
Dynamic data D2,D4,D6,…,D2mTo data/address bus.
In the above example, (1) Scan, Scan (2) ..., Scan (2m) respectively drive the 1st column of display panel 2, the 2nd
Column ..., 2m column therefore using the scan drive circuit 21 such as above-mentioned first embodiment be first write-in surprise when picture be written
The pixel data of ordered series of numbers, then the pixel data of even column is written.
Fig. 5 is painted the schematic diagram of write-in picture data, and to keep diagram clearer, example depicted in Fig. 5 is with n=3
As explanation.Picture F01 is previous picture (headstock towards a left side), when current picture (as shown in F04, headstock towards the right side) is written,
It is divided into 3 stages (because n=3).(Phase 1) sequentially scans the 1st, 4,7 ... column (picture F02), second-order in the first stage
Section (Phase 2) sequentially scans 2,5,8 ... column (picture F03), and the phase III (Phase 3) sequentially scans the 3rd, 6,9 ... column (pictures
Face F04), 3 the first initial signal STV1 need to be triggered altogether, complete one picture of write-in.
It is worth noting that, this case invention is not limited to above-mentioned column interlacing mode, can be believed according to different control
Number or be different hardware connection mode, and change the scanning mode of picture, such as can change as progressive scan.With n=2,
Display panel 2 shares 2m scan line and illustrates as an example, and two kinds of explanation may be by the way of below.A kind of mode is by
The output of 1 grade of de-multiplexer DM (1) is connected to the scan line Scan (1) and Scan (m+1) of display panel 2, the 2nd grade of de-multiplexer DM
(2) output is connected to the scan line Scan (2) and Scan (m+2) of display panel 2, remaining and so on, then the write-in of data is suitable
Sequence can change into D1,D2,D3,D4…,D2m.Another way is to change selection signal Selector, please refers to Fig. 4 B, is painted
The signal timing diagram of progressive scan, selection signal Sel1 and selection signal Sel2 be all with clock signal CKV identical frequency, and
And each other be phase phase difference 180 degree signal, the mode of connection maintain it is identical as script, so in a week of clock signal CKV
In phase, the 1st grade of first driving unit SD (1) can sequentially scan Scan (1) and Scan (2), in the next of clock signal CKV
In period, the 2nd grade of first driving unit SD (2) can sequentially scan Scan (3) and Scan (4) (can change external control electricity
Clock signal CKV frequency caused by road is identical to maintain picture update rate), the write sequence of such data can also be changed into
D1,D2,D3,D4…,D2m。
Above-mentioned first way need to change hardware connection mode, when m value is big, the output of a de-multiplexer
End, which need to be connected to, is separated by two very remote scan lines, and such winding mode is less easily realized.And the second way, it need to be with higher
Frequency is frequently changed selection signal, will lead to additional power consumption.Therefore, the scan drive circuit of this exposure and viewing area
When the scan line connection in domain, though can there are different connection type and control mode, however following explanation, all use aforementioned first
It is to be carried out in a manner of every the scanning of n row when the mode of embodiment is as explanation, i.e. write-in picture.
Such as the scan drive circuit of above-described embodiment, due to using a shift register in the first driving units at different levels
Multi-strip scanning line is driven with a multiplexer is unified, therefore the quantity that TFT is used can be reduced, is reduced occupied by scan drive circuit
Area.The circuit framework figure of the shift register as depicted in Figure 12, a shift register can be substantially estimated as using 7
TFT.In the framework of Figure 1A, every 4 scan lines need to use 4 shift registers, need 28 TFT altogether.It compares down, the frame of Fig. 2
In structure (by taking n=4 as an example), every 4 scan lines using 1 shift register (7 TFT) and 1 de-multiplexer (8 TFT,
See Fig. 3), it is only necessary to 15 TFT.Hardware is added to put into effect border area reckoning around line width, if using low temperature polycrystalline silicon (Low
Temperature Poly-silicon, LTPS) TFT, entire area shared by scan drive circuit can save to 83%, and if
Be using indium gallium zinc oxide (IGZO) TFT, because the single area of IGZO TFT is big compared with LTPS TFT, once saving TFT makes
Number, entire area shared by scan drive circuit can more be saved to 70%.Comparison result is arranged into such as lower section table one.
Table one
The area for saving GOP scan drive circuit is conducive to design narrow side frame panel, and energy band is more preferably regarded to user
Feel experience.Circuit area is saved, the size and cost of grid integrated circuits driving element can be also reduced.In addition to this, as aforementioned
Timing control mode, selection signal Selector can maintain same logic level in each stage (Phase), such as
This can reduce the switching times of selection signal Selector, avoid unnecessary power consumption.
Further, since the multi-strip scanning line that is exported of de-multiplexer can be with unit control, therefore it can be via appropriately designed outer
Portion's control circuit can more achieve the effect that further to save power consumption.Fig. 8 is painted a kind of schematic diagram of external control circuit,
External control circuit includes storage unit 80, comparing unit 82 and control unit 84.Storage unit 80 is, for example, memory, storage
Deposit previous picture Y (N-1).Current picture Y (N) and previous picture Y (N-1) are compared by comparing unit 82, relatively more single
Member 82 can more be compared each column, the pixel for the current picture Y (N) of determination and previous picture Y (N-1) which having arrange
It is identical.Such as the pixel of current picture Y (N) pth column is identical with previous picture Y (N-1), then current picture is without to the
P column carry out write activity again, and it is more to control corresponding solution that control unit 84 can export corresponding selection signal Selector
Work device will not arrange pth in current picture Y (N) and write again so that scan line Scan (p) maintains stopping potential VGL
Enter.Since leakage rate of IGZO TFT when closing is low compared with LTPSTFT and a-Si TFT, it is easier to keep the data of previous picture,
Such practice is started without corresponding transistor especially suitable for IGZO panel, for the column pixel that no change has taken place, and energy
Further decrease power consumption.And do not limited in implementation and use control circuit, it can also be obtained by computer through software operation
The difference of picture Y (N) and previous picture Y (N-1) at present.
Above-mentioned first embodiment to whole picture by arrange it is staggered in a manner of scan, as shown in figure 5, being transformed by picture F01
When picture F04, it is possible to discomfort slightly can be caused for the vision perception of the mankind, perceive the conversion between picture.Following reality
It applies example and separately proposes a kind of scan drive circuit that can lower human vision sense of discomfort.
Fig. 6 is painted the schematic diagram according to second embodiment of the invention display panel.Exist with the difference of aforementioned first embodiment,
Display panel 6 further includes the second display area 62 ' and the first display area 62 and is similarly formed in thin-film transistor array base-plate 60
On, the first display area 62 includes h first row pixel circuit R (1)~R (h), and the second display area 62 ' includes multiple second
Column pixel circuit R (h+1), R (h+2) ....Scan drive circuit 61 further includes multistage the second driving unit SD ' (1), SD '
(2) ..., it is controlled by the second initial signal STV2, clock signal CKV and at least a selection signal Selector, wherein j-th stage
Two driving units SD ' (j) include shift register SR ' (j) and Xie work device DM ' (j).Shift register SR ' (j) basis
Clock signal CKV and trigger signal generate scanning signal S ' (j).De-multiplexer DM ' (j) is according to an at least selection signal
Scanning signal S ' (j) selectively output to multiple scan line Scan, each scan line Scan is driven secondary series picture by Selector
One of plain circuit R.Wherein the trigger signal of the 1st grade of second driving unit SD ' (1) is the second initial signal STV2, (j+
1) trigger signal of the second driving unit of grade SD ' (j+1) is scanning signal S ' (j) of the second driving unit of j-th stage SD ' (j), j
For the positive integer more than or equal to 1.
As previously mentioned, the scan line that each de-multiplexer is exported can be with column pixel circuit continuous in driving panel, also
The mode of jumper connection can be used, drive multiple column pixel circuits with spacing.Coiling difficulty when entity design is contemplated, this
Embodiment is to drive on display panel continuous column pixel circuit as explanation.Similarly, the first display area in this embodiment
First row pixel circuit R (1) in 62, R (2) ... it succeeds one another and is set on thin-film transistor array base-plate 60, second is aobvious
Show the secondary series pixel circuit R (h+1) in region 62 ', R (h+2) ... it succeeds one another and is set to thin-film transistor array base-plate
On 60.It is not limited to this in implementation, such as the first display area 62 also may include odd-numbered column pixel circuit, second is aobvious
Show that region 62 ' includes even-numbered column pixel circuit.This embodiment is only as the example for being easier to completion hardware coiling, also
That is, the first display area 62 and the second display area 62 ' respectively represent a lateral block of display panel 6.
From fig. 6, it can be seen that multistage the second driving unit SD ' (1), SD ' (2) ... and the first driving unit SD of multistage
(1), the framework of (2) SD ... is similar, the difference is that the trigger signal of the 1st grade of first driving unit SD (1) is the first initial signal
STV1, and the trigger signal of the 1st grade of second driving unit SD ' (1) is the second initial signal STV2.Therefore, the first display area
62 timing control is identical as aforementioned first embodiment, is not repeating in this.And in the scanning for completing the first display area 62
Later, the second initial signal STV2 is triggered, to be similar to the scanning mode of the first display area 62, completes the second display area
62 ' scanning.
Fig. 7 is painted the schematic diagram according to second embodiment of the invention write-in picture data.In order to clearly illustrate scanning sequency,
In Fig. 7, display panel is divided into 3 display areas as explanation, it is therefore desirable to have the first initial signal STV1, the second starting
Signal STV2, third initial signal STV3.And driving unit at different levels is then the de-multiplexer (n=3) using 1 pair 3.Picture
F11 is previous picture (headstock towards a left side), when current picture (as shown in F20, headstock towards the right side) is written, is divided into 3 viewing areas
Domain is successively written.One of the tripartite above picture is written first, is similar to first embodiment, point 3 stages trigger 3 the firsts
Beginning signal STV1, first stage sequentially scan the 1st, 4,7 ... column (picture F12), and second stage, which sequentially scans 2,5,8 ... column, (draws
Face F13), the phase III sequentially scans the 3rd, 6,9 ... column (picture F14).It is then written to the one third in picture center, triggering 3
Secondary second initial signal STV2, point 3 stages by arrange it is staggered in a manner of scan (picture F15, F16, F17).It is ultimately written under picture
The one third of side, triggers 3 third initial signal STV3, point 3 stages by arrange it is staggered in a manner of scan (picture F18, F19,
F20), whole picture is so completed.
According to the picture scanning mode of above-mentioned second embodiment, arranged respectively since whole picture is divided into multiple blocks
Interlacing can reduce whole picture and carry out column interlacing bring ghost or sense of discomfort.No matter it is worth noting that, solution
The solution multiplexing ratio (n) of multiplexer is how many, no matter panel is also divided into several display areas, spends required for a picture
Sweep time be all it is identical, for the display panel for thering is M to arrange, be equally to need to spend M clock cycle to scan, changed
It is only the sequence of scanning, therefore does not will cause the extra burden of sweep time.
For display device, in order to enable the brightness of display can and panel identical as the result desired by driving circuit it is equal
Even degree is considered, it usually needs setting compensation circuit.Especially for Organic Light Emitting Diode (Organic Light
Emitting Diode, OLED) panel.This is because the process variation of interelement, may cause critical voltage (Vth) not identical,
It causes the electric current for flowing through transistor even if giving identical driving voltage still not identical, and makes brightness inconsistent.This exposure
A kind of scan drive circuit and display panel that can be adapted for comprising compensation function is more proposed below.
For oled panel, one of compensation way is to penetrate to give control signal appropriate, so that the drive of OLED
Streaming current can not be influenced by critical voltage variation, and compensation process can divide into reset phase (Reset), data write phase
(Program) and light emitting phase (Emission).
Fig. 9 A is painted the schematic diagram according to third embodiment of the invention display panel.For the sake of asking diagram clear, Fig. 9 A is only
When being painted about compensation is applied to, the part newly-increased compared to first embodiment.With first embodiment the difference is that, scanning drive
Dynamic circuit 91 further includes Multilevel compensating driving unit CD (1), CD (2) ..., is controlled by a compensation initial signal STVc, clock pulse letter
A number CKV and at least selection signal Selector.Wherein kth grade compensation drive unit CD (k) includes a shift register SRc
(k) and a de-multiplexer DMc (k).Shift register SRc (k) generates a compensation according to clock signal CKV and trigger signal
Signal C (k).De-multiplexer DMc (k) is according to an at least selection signal Selector, extremely by thermal compensation signal C (k) selectively output
Multiple compensating line Com.Each compensating line Com is for compensating one of first row pixel circuit R.Wherein the 1st grade of compensation driving is single
The trigger signal of first CD (1) is compensation initial signal STVc, and the trigger signal of (k+1) grade compensation drive unit CD (k+1) is
The thermal compensation signal C (k) of kth grade compensation drive unit CD (k), k are the positive integer more than or equal to 1.
Display panel 9 is, for example, oled panel.Compensating line Com (1), Com (2) ... e.g. for controlling first row picture
Plain circuit R (1), R (2) ... in the reset control signal RST of reset phase, or control first row pixel circuit R (1), R
(2) ... in the LED control signal EM of light emitting phase.As shown in Figure 9 A, it compensates in the framework and first embodiment of part only
Framework comprising turntable driving is similar, is equally using de-multiplexer, to reduce required shift register quantity.And the 1st grade
De-multiplexer DMc (1) and the de-multiplexer DM in the 1st grade of first driving unit SD (1) in compensation drive unit CD (1)
(1), used selection signal Selector also can be sent out the 1st article of scanning of compensation with identical, for example by Com (1)
After the reset signal of line, the scanning signal of the 1st article of scan line Scan (1) is sent out by Scan (1), so that image data is written
First row pixel circuit R (1).
This exposure is following separately to propose a kind of display that can further reduce shift register used in compensation part
Panel.In following embodiment, for multiple column pixel circuits of display panel, a compensating control signal can be shared, such as can
2 column pixel circuits are regarded as a frequency band (band), identical compensating control signal is given.
Fig. 9 B is painted the schematic diagram according to fourth embodiment of the invention display panel.It is with 1 pair 3 of de-multiplexer in Fig. 9 B
Illustrate as an example, and 2 column pixel circuits are regarded as a frequency band, for example, column pixel circuit R (1) and R (4) is regarded
Make a frequency band.It is worth noting that, the de-multiplexer DMc (1) in the 1st grade of compensation drive unit CD (1) is couple to 6 benefits
Repay line Com (1)~Com (6), however the selection signal Selector and de-multiplexer DM (1) of de-multiplexer DMc (1) and DM (2)
Control signal it is identical.
Figure 10 A and Figure 10 B are painted the schematic diagram according to de-multiplexer used in fourth embodiment of the invention.De-multiplexer
DM (1) and the control mode of de-multiplexer DM (2) are similar with previous embodiment, repeat no more in this.De-multiplexer DMc (1) is then
It is when selection signal Sel1 is logic high potential, by scanning signal C (1) output to compensating line Com (1) and compensating line Com
(4), when selection signal Sel2 is logic high potential, by scanning signal C (1) output to compensating line Com (2) and compensating line
Com (5), when selection signal Sel3 is logic high potential, by scanning signal C (1) output to compensating line Com (3) and compensation
Line Com (6).
In fourth embodiment, due to by common 1 thermal compensation signal of 2 column pixel circuits, for 6 column pixels
Circuit R (1)~R (6), shift register number needed for turntable driving part is 2, and the displacement needed for compensating part is posted
Storage number only needs 1.Quantity needed for shift register can not only be reduced and can achieve the effect that reduce circuit area, more
Due to compensating multiple column pixel circuits jointly, each column pixel circuit is enabled to have longer compensation time, therefore energy
Obtain more preferably compensation effect.
Figure 11 is painted according to the signal timing diagram in fourth embodiment of the invention display panel.In Figure 11, thermal compensation signal C
(1) be, for example, compensated stage reset control signal RST.(selection signal Sel1 is logic high potential) in the first stage, first will
Thermal compensation signal C (1) output after the completion of resetting, then scanning signal S (1) is exported and is extremely scanned to compensating line Com (1) and Com (4)
Scanning signal S (2) are exported to scan line Scan (4) again later, complete first row pixel circuit R (1) and R by line Scan (1)
(4) resetting and scanning.Similarly, it sequentially completes in second stage (selection signal Sel2 is logic high potential) to first row picture
The resetting and scanning of plain circuit R (2) and R (5) are sequentially completed in the phase III (selection signal Sel3 be logic high potential) to the
The resetting and scanning of one column pixel circuit R (3) and R (6).
Scan drive circuit of the present invention, due to being selectively output to a scanning signal using de-multiplexer
Multi-strip scanning line, quantity needed for can be effectively reduced shift register, reduce on panel with TFT implementation driving circuit or
Occupied area in grid integrated circuits driving element can be widely applied for various different display panels, especially favorably
In the design of narrow side frame panel.
Furthermore the time needed for such scan drive circuit not will increase scan-image picture is able to maintain identical
Picture update rate.And controlled via wiring appropriate, the received selection signal of de-multiplexer institute can't continually switch bounce,
It can be avoided unnecessary power consumption.And for the TFT with low drain electrical property, due to can effectively store pixel data,
The method for more proposing to generate control de-multiplexer selection signal in a manner of comparing image frame, is disappeared with further saving power
Consumption.
In addition to this, more consider the picture effect that human vision is perceived, propose to be suitable for for display panel being divided into
Different blocks, the circuit framework and driving method being sequentially scanned to different blocks respectively are reducing scan drive circuit
While area, the pleasant ornamental experience of user can be also brought.
This exposure is separately proposed scan drive circuit applying the compensation method in the explicit module of Organic Light Emitting Diode, mended
It repays in control also with the framework of de-multiplexer to reduce the quantity used needed for shift register.In addition, more by multiple column
The circuit compensation signal of pixel shares, further to reduce the quantity of shift register, while but also each column pixel
Circuit can have the longer compensation time, to obtain more preferably compensation effect.
Although the present invention is disclosed as above with preferred embodiment, however, it is not to limit the invention, any this field skill
Art personnel, without departing from the spirit and scope of the present invention, when can make a little modification and perfect therefore of the invention protection model
It encloses to work as and subject to the definition of the claims.
Claims (18)
1. a kind of scan drive circuit, comprising:
Multistage first driving unit, is controlled by one first initial signal, a clock signal and an at least selection signal, wherein this is more
Grade the first driving unit include:
One shift register, the shift register generate scan signal according to the clock signal and a trigger signal；And
One de-multiplexer, the de-multiplexer are swept according to an at least selection signal, by the scanning signal selectively output to multiple
Retouch line；And
Multilevel compensating driving unit is controlled by a compensation initial signal, the clock signal and an at least selection signal, wherein should
Multilevel compensating driving unit includes:
One shift register, the shift register generate a thermal compensation signal according to the clock signal and a trigger signal；And
One de-multiplexer, the de-multiplexer is according to an at least selection signal, by the thermal compensation signal selectively output to multiple benefits
Repay line；
Wherein the trigger signal of the 1st grade of the first driving unit is first initial signal, the touching of the first driving unit of (i+1) grade
Signalling is the scanning signal of the first driving unit of i-stage, and i is the positive integer more than or equal to 1, the 1st grade of compensation drive unit
Trigger signal be the compensation initial signal, the trigger signal of (k+1) grade compensation drive unit is kth grade compensation drive unit
Thermal compensation signal, k is positive integer more than or equal to 1, and respectively the wherein level-one of the first driving unit of this grade is exported multiple
Scan line quantity is less than multiple compensating line quantity that the wherein level-one of respectively this grade of compensation drive unit is exported.
2. scan drive circuit as described in claim 1, which is characterized in that the de-multiplexer of i-stage is according at least one choosing
Signal is selected, one of the scanning signal and a blanking voltage current potential are selectively exported respectively to each multiple scan line.
3. scan drive circuit as claimed in claim 2, which is characterized in that an at least selection signal is drawn now according to one
The comparison result of face and a previous picture and determine.
4. scan drive circuit as described in claim 1, which is characterized in that respectively the output of the first driving unit of this grade is multiple
Scan line quantity is identical, and the quantity of an at least selection signal is relevant to multiple scanning of respectively the first driving unit of this grade output
Line number amount.
5. scan drive circuit as described in claim 1, further includes:
Multistage second driving unit, is controlled by one second initial signal, the clock signal and an at least selection signal, wherein should
Multistage second driving unit includes:
One shift register, the shift register generate scan signal according to the clock signal and a trigger signal；And
One de-multiplexer, the de-multiplexer are swept according to an at least selection signal, by the scanning signal selectively output to multiple
Retouch line；
Wherein the trigger signal of the 1st grade of the second driving unit is second initial signal, the touching of the second driving unit of (j+1) grade
Signalling is the scanning signal of the second driving unit of j-th stage, and j is the positive integer more than or equal to 1.
6. scan drive circuit as claimed in claim 5, which is characterized in that respectively the output of the second driving unit of this grade is multiple
Scan line quantity is identical, and identical as multiple scan line quantity of respectively the first driving unit of this grade output, at least one choosing
The quantity for selecting signal is relevant to multiple scan line quantity of respectively the first driving unit of this grade output.
7. scan drive circuit as described in claim 1, which is characterized in that the de-multiplexer of the kth grade compensation drive unit
According to an at least selection signal, the thermal compensation signal and a blanking voltage current potential are selectively exported respectively to each multiple compensating line
One of them.
8. a kind of display panel, comprising:
One thin-film transistor array base-plate；
One first display area, including multiple first row pixel circuits；And
One scan drive circuit, comprising:
Multistage first driving unit, is controlled by one first initial signal, a clock signal and an at least selection signal, wherein this is more
Grade the first driving unit include:
One shift register, the shift register generate scan signal according to the clock signal and a trigger signal；And
One de-multiplexer, the de-multiplexer are swept according to an at least selection signal, by the scanning signal selectively output to multiple
Retouch one of line, each multiple multiple first row pixel circuit of scanning line driving；And
Multilevel compensating driving unit is controlled by a compensation initial signal, the clock signal and an at least selection signal, wherein should
Multilevel compensating driving unit includes:
One shift register, the shift register generate a thermal compensation signal according to the clock signal and a trigger signal；And
One de-multiplexer, the de-multiplexer is according to an at least selection signal, by the thermal compensation signal selectively output to multiple benefits
Repay line；
Wherein the trigger signal of the 1st grade of the first driving unit is first initial signal, the touching of the first driving unit of (i+1) grade
Signalling is the scanning signal of the first driving unit of i-stage, and i is the positive integer more than or equal to 1, the 1st grade of compensation drive unit
Trigger signal be the compensation initial signal, the trigger signal of (k+1) grade compensation drive unit is kth grade compensation drive unit
Thermal compensation signal, k is positive integer more than or equal to 1, and respectively the wherein level-one of the first driving unit of this grade is exported multiple
Scan line quantity is less than multiple compensating line quantity that the wherein level-one of respectively this grade of compensation drive unit is exported.
9. display panel as claimed in claim 8, which is characterized in that the de-multiplexer of the i-stage is according at least one selection
Signal selectively exports one of the scanning signal and a blanking voltage current potential to each multiple scan line respectively.
10. display panel as claimed in claim 9, which is characterized in that an at least selection signal is according to a present picture
And one previous picture comparison result and determine.
11. display panel as claimed in claim 8, which is characterized in that respectively first driving unit of grade exports multiple scanning
The quantity of line is identical, and the quantity of an at least selection signal is relevant to respectively the first driving unit of this grade and exports multiple scan line
Quantity.
12. display panel as claimed in claim 8, which is characterized in that multiple scanning of the first driving unit of i-stage output
Line is to drive multiple continuous first row pixel circuits in first display area.
13. display panel as claimed in claim 8, further includes:
One second display area, including multiple secondary series pixel circuits；
Wherein the scan drive circuit further includes multistage second driving unit, is controlled by one second initial signal, the clock signal
And an at least selection signal, wherein second driving unit of multistage include:
One shift register, the shift register generate scan signal according to the clock signal and a trigger signal；And
One de-multiplexer, the de-multiplexer are swept according to an at least selection signal, by the scanning signal selectively output to multiple
Retouch one of line, each multiple multiple secondary series pixel circuit of scanning line driving；
Wherein the trigger signal of the 1st grade of the second driving unit is second initial signal, the touching of the second driving unit of (j+1) grade
Signalling is the scanning signal of the second driving unit of j-th stage, and j is the positive integer more than or equal to 1.
14. display panel as claimed in claim 13, which is characterized in that respectively multiple the sweeping of the second driving unit of this grade output
Retouch that line number amount is identical, and identical as multiple scan line quantity of respectively the first driving unit of this grade output, at least one selection
The quantity of signal is relevant to multiple scan line quantity of respectively the first driving unit of this grade output.
15. display panel as claimed in claim 13, which is characterized in that multiple first row pixel circuit succeeds one another setting
The thin film transistor (TFT) array base is set on the thin-film transistor array base-plate, multiple secondary series pixel circuit succeeds one another
On plate.
16. display panel as claimed in claim 8, which is characterized in that respectively this grade of compensation drive unit exports each multiple
Compensating line is for compensating one of multiple first row pixel circuit.
17. display panel as claimed in claim 8, which is characterized in that respectively this grade of compensation drive unit exports each multiple
Compensating line is to be used for while compensating multiple first row pixel circuit at least the two therein.
18. display panel as claimed in claim 8, which is characterized in that the display panel is an Organic Light Emitting Diode
(OLED) panel.
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| CN105976759B (en) * | 2016-07-29 | 2019-09-06 | 京东方科技集团股份有限公司 | Driving circuit, display panel, display equipment and driving method |
| CN106297629B (en) * | 2016-08-22 | 2018-06-15 | 武汉华星光电技术有限公司 | Scan drive circuit and flat display apparatus with the circuit |
| CN107632474A (en) * | 2017-10-19 | 2018-01-26 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN108122529B (en) * | 2018-01-25 | 2021-08-17 | 京东方科技集团股份有限公司 | Gate driving unit, driving method thereof and gate driving circuit |
| US10533563B2 (en) * | 2018-02-13 | 2020-01-14 | Quanta Computer Inc. | Management of multiple fan modules |
| CN110782833B (en) * | 2018-07-30 | 2021-09-21 | 成都京东方光电科技有限公司 | Display panel and display device |
| CN111243522A (en) * | 2018-11-29 | 2020-06-05 | 上海和辉光电有限公司 | Display device and driving method thereof |
| CN109410867B (en) * | 2018-12-05 | 2020-10-16 | 惠科股份有限公司 | Display panel, driving method and display device |
| CN110264939A (en) * | 2019-06-27 | 2019-09-20 | 京东方科技集团股份有限公司 | Shift register cell, gate driving circuit and display control method |
| CN111354319A (en) * | 2020-04-26 | 2020-06-30 | 福州京东方光电科技有限公司 | Display module and display device |
| CN111710301A (en) * | 2020-07-13 | 2020-09-25 | 京东方科技集团股份有限公司 | Display panel, preparation method and repair method thereof, and display device |
| CN113035110B (en) * | 2021-03-25 | 2022-01-14 | 惠科股份有限公司 | Gate drive circuit and display device |
| CN113920946B (en) * | 2021-10-18 | 2023-02-28 | 京东方科技集团股份有限公司 | Gate driver, driving method thereof and display device |
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| TW200830247A (en) * | 2007-01-09 | 2008-07-16 | Denmos Technology Inc | Gate driver |
| TW200905647A (en) * | 2007-07-19 | 2009-02-01 | Chi Mei Optoelectronics Corp | Driving circuit, flat display panel and flat display apparatus |
| CA2637343A1 (en) * | 2008-07-29 | 2010-01-29 | Ignis Innovation Inc. | Improving the display source driver |
| US8325127B2 (en) * | 2010-06-25 | 2012-12-04 | Au Optronics Corporation | Shift register and architecture of same on a display panel |
| TWI476742B (en) * | 2010-12-06 | 2015-03-11 | Au Optronics Corp | Multiplex driving circuit |
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