CN110288942B - Display panel and display device - Google Patents
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- CN110288942B CN110288942B CN201910579417.0A CN201910579417A CN110288942B CN 110288942 B CN110288942 B CN 110288942B CN 201910579417 A CN201910579417 A CN 201910579417A CN 110288942 B CN110288942 B CN 110288942B
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- 238000012360 testing method Methods 0.000 claims description 14
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- 238000005516 engineering process Methods 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention discloses a display panel and a display device, wherein first shift registers in a light-emitting control circuit are grouped, each first register group is electrically connected with a plurality of adjacent light-emitting control signal lines, and different first frame starting signal ends and different first clock control signal ends are respectively arranged on each first register group, so that the first register groups can be independently controlled to drive the electrically connected light-emitting control signal lines. When the display panel displays in the subareas, part of the first register groups work independently to enable the corresponding areas to carry out display driving, and the areas corresponding to the rest of the first register groups are not enabled to carry out display driving, so that the power consumption can be reduced. When the display panel displays the whole display, the first register groups work sequentially to carry out the line-by-line display driving on the light-emitting control signal lines in the display panel, so that the display panel can realize the function of whole display.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. The Gate Driver on Array (GOA) technology integrates a Thin Film Transistor (TFT) Gate switch Circuit on an Array substrate of a display panel to form a scan drive for the display panel, so that a wiring space of a binding (Bonding) region and a Fan-out (Fan-out) region of a Gate Integrated Circuit (IC) can be omitted, and thus, not only can the product cost be reduced in two aspects of material cost and preparation process, but also the display panel can be designed to be symmetrical at two sides and to be beautiful with a narrow frame.
At present, a general driving control circuit is composed of a plurality of cascaded shift registers, each shift register is correspondingly connected with a driving signal line, scanning signals are sequentially input to the connected driving signal lines from top to bottom through each shift register to perform progressive scanning, and meanwhile, a source driving circuit loads corresponding data signals to each data line to complete displaying of a picture. However, when the display panel only needs to display a part of the contents such as time, calendar, weather, etc., the driving control circuit needs to perform display driving by scanning each driving signal line in the display panel line by line to enable the display panel to display the contents, which results in increased power consumption.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for reducing the power consumption of the display panel.
An embodiment of the present invention provides a display panel, including: a plurality of light emission control signal lines, and a light emission control circuit having a plurality of first shift registers; the first shift register is divided into M first register groups which are sequentially arranged, and each first register group is correspondingly and electrically connected with a plurality of adjacent light-emitting control signal wires; each first shift register in each first register group is arranged in a cascade mode, and each first shift register is electrically connected with at least one light-emitting control signal line; each first register group is correspondingly connected with different first frame starting signal ends and different first clock control signal ends respectively; m is an integer greater than 1;
when the display panel displays in a subarea mode, in one frame of scanning time, part of the M first register groups are used for independently working under the control of signals of a first frame starting signal end and a first clock control signal end which are electrically connected, and driving light-emitting control signal lines which are electrically connected line by line; except for the partial first register groups, signals of first frame starting signal ends electrically connected with the rest first register groups are different from signals of first frame starting signal ends electrically connected with the partial first register groups, and the time sequence of the signals of the first clock control signal ends electrically connected with each first register group is the same;
when the display panel displays the whole, in the scanning time of one frame, each first register group is used for working sequentially under the control of signals of a first frame starting signal end and a first clock control signal end which are electrically connected and driving light-emitting control signal lines in the display panel line by line; the time sequence of signals of the first clock control signal end electrically connected with each first register group is the same, and except the first register group, the time sequence of signals of the first frame start signal end electrically connected with other first register groups is the same as the time sequence of signals output by the last stage first shift register in the last adjacent first register group.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, when the display panel is subjected to a factory test, in the scanning time of one frame, each of the first register groups is configured to simultaneously operate under the control of signals of a first frame start signal end and a first clock control signal end that are electrically connected, and drive light-emitting control signal lines that are electrically connected row by row; the time sequence of signals of a first clock control signal end electrically connected with each first register group is the same, and the time sequence of signals of a first frame start signal end electrically connected with each first register group is the same.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the display panel is divided into a first area and a second area; m is 2, wherein a 1 st one of the 2 first register groups is used to drive a light emission control signal line located in the first region; the 2 nd first register group is used for driving a light-emitting control signal line in the second area; or the like, or, alternatively,
the display panel is divided into a first area, a second area and a third area; m-3, wherein a 1 st one of the 3 first register groups is used to drive a light emission control signal line located in the first region; the 2 nd first register group is used for driving a light-emitting control signal line in the second area; the 3 rd first register group is used for driving a light emission control signal line located in the third area.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the first shift register includes a plurality of P-type transistors;
when the display panel displays in a subarea mode, a first frame starting signal end electrically connected with the partial first register group correspondingly loads a pulse signal with a low potential effective pulse signal; except for the partial first register groups, the first frame starting signal ends electrically connected with the rest first register groups are loaded with fixed high-potential signals.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the first shift register includes a plurality of N-type transistors;
when the display panel displays in a subarea mode, a first frame starting signal end electrically connected with the partial first register group correspondingly loads an effective pulse signal which is a high-potential pulse signal; except for the part of the first register groups, the first frame starting signal ends electrically connected with the other first register groups are loaded with fixed low-potential signals.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, each of the first shift registers includes a left first shift register and a right first shift register respectively disposed at two ends of a same light emission control signal line; when the display panel displays in whole or in regions, the left first shift register and the right first shift register which are positioned at two ends of the same light-emitting control signal line work simultaneously when the first shift register works; when the display panel is subjected to factory test, when the first shift register works, the left first shift register and the right first shift register which are positioned at two ends of the same light-emitting control signal line are selected to work.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the display panel further includes a plurality of gate signal lines and a gate driving circuit; the grid driving circuit is provided with a plurality of second shift registers which are arranged in a cascade mode; each second shift register is electrically connected with at least one grid signal line; the first second shift register is electrically connected with a second frame starting signal end; each second shift register is electrically connected with the same second clock control signal end;
and in one frame of scanning time, each second shift register is used for sequentially working under the control of signals of a second frame starting signal end and a second clock control signal end which are electrically connected and driving the electrically connected grid signal lines line by line.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, each of the second shift registers includes a left second shift register and a right second shift register respectively disposed at two ends of the same gate signal line; when the display panel displays in whole or in regions, the left second shift register and the right second shift register which are positioned at two ends of the same grid signal line work simultaneously when the second shift register works; when the display panel is subjected to factory test, when the second shift register works, the left second shift register and the right second shift register which are positioned at two ends of the same grid signal line are selected to work.
In a possible implementation manner, in the display panel provided in the embodiment of the present invention, the display panel further includes a plurality of data signal lines, and a source driving circuit electrically connected to the plurality of data signal lines;
when the display panel displays in a subarea mode, in a frame scanning time, the source electrode driving circuit is used for loading effective data signals to the plurality of data signal lines which are electrically connected only when the partial first register groups work; and when the rest of the first register groups work, loading a fixed low-potential signal to the plurality of electrically connected data signal lines.
On the other hand, the embodiment of the invention also provides a display device, which comprises the display panel provided by the embodiment of the invention.
The invention has the following beneficial effects:
in the display panel and the display device provided by the embodiments of the present invention, the first shift registers in the light emission control circuit are grouped, the first shift registers in each first register group are arranged in a cascade manner, each first register group is electrically connected to a plurality of adjacent light emission control signal lines, and different first frame start signal ends and different first clock control signal ends are respectively arranged for each first register group, so that each first register group can be independently controlled to drive the electrically connected light emission control signal lines.
When the display panel displays in the subareas, signals of each first frame starting signal end and the first clock control signal end are set to enable part of the first register groups to work independently, so that the areas corresponding to the working first register groups are subjected to display driving, signals of the first frame starting signal ends electrically connected with the rest of the first register groups are different from signals of the first frame starting signal ends electrically connected with the part of the first register groups, the time sequence of the signals of the first clock control signal ends electrically connected with each first register group is the same, and the areas corresponding to the rest of the first register groups are not subjected to display driving, so that the power consumption can be reduced. When the display panel displays the whole display, the signals of each first frame starting signal end and the first clock control signal end are set to enable each first register group to work sequentially, and the light-emitting control signal lines in the display panel are driven to display line by line, so that the display panel can realize the function of whole display.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 2 is a second schematic structural diagram of a display panel according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a second schematic diagram of a shift register according to an embodiment of the present invention;
FIG. 5 is a timing diagram of a circuit according to an embodiment of the present invention;
FIG. 6 is a second timing diagram of the circuit according to the embodiment of the present invention;
FIG. 7 is a timing diagram illustrating a partition operation according to an embodiment of the present invention;
FIG. 8 is a timing diagram illustrating overall operation of the first embodiment of the present invention;
FIG. 9 is a timing diagram of factory testing according to an embodiment of the present invention;
fig. 10 is a third schematic structural diagram of a display panel according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, specific embodiments of a display panel and a display device according to an embodiment of the present invention are described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only for illustrating and explaining the present invention and are not to be used for limiting the present invention. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
An embodiment of the present invention provides a display panel, as shown in fig. 1 and 2, the display panel includes: a plurality of light emission control signal lines EMIT, and a light emission control circuit VSR _ EMIT having a plurality of first shift registers; the first shift register is divided into M first register groups VSR _ EMIT _ M (M is an integer which is greater than or equal to 1 and less than or equal to M), wherein M is 2 in the figure 1, and M is 3 in the figure 2, and each first register group VSR _ EMIT _ M is correspondingly and electrically connected with a plurality of adjacent light-emitting control signal lines EMIT; each first shift register in each first register group VSR _ EMIT _ m is cascade-connected, and each first shift register is electrically connected to at least one light-emitting control signal line EMIT; and each of the first register groups VSR _ EMIT _ m is correspondingly connected to a different first frame start signal terminal stv1_ m and a different first clock control signal terminal ckv1_ m, respectively; m is an integer greater than 1;
when the display panel displays in a subarea mode, in one frame of scanning time, part of the M first register groups are used for independently working under the control of signals of a first frame starting signal end and a first clock control signal end which are electrically connected, and driving light-emitting control signal lines which are electrically connected line by line; except for part of the first register groups, signals of first frame start signal ends electrically connected with the other first register groups are different from signals of first frame start signal ends electrically connected with the part of the first register groups, the time sequence of the signals of a first clock control signal end stv1_ m electrically connected with each first register group VSR _ EMIT _ m is the same, namely the time sequence of the signals of ck1_ m is the same, and the time sequence of the signals of ckb1_ m is the same;
when the display panel displays the whole, in one frame of scanning time, each first register group VSR _ EMIT _ m is used for sequentially working under the control of signals of a first frame start signal end stv1_ m and a first clock control signal end ckv1_ m which are electrically connected, and driving a light-emitting control signal line EMIT in the display panel line by line; the timing of the signals of the first clock control signal terminal stv1_ m electrically connected to each first register group VSR _ EMIT _ m is the same, that is, the timing of the signals of ck1_ m is the same, and the timing of the signals of ckb1_ m is the same; besides the first register group, the timing sequence of the signal at the first start signal end stv1_ m of the first frame electrically connected to the other first register groups is the same as the timing sequence of the signal output by the last stage of the first shift register in the last adjacent first register group.
Specifically, in the display panel provided in the embodiment of the present invention, the first shift registers in the light emission control circuit are grouped, the first shift registers in each first register group are arranged in a cascade manner, and each first register group is electrically connected to a plurality of adjacent light emission control signal lines, and different first frame start signal ends and different first clock control signal ends are respectively arranged for each first register group, so that the electrically connected light emission control signal lines can be independently controlled to be driven by each first register group. When the display panel displays in the subareas, signals of each first frame starting signal end and the first clock control signal end are set to enable part of the first register groups to work independently, so that the areas corresponding to the working first register groups are subjected to display driving, signals of the first frame starting signal ends electrically connected with the rest of the first register groups are different from signals of the first frame starting signal ends electrically connected with the part of the first register groups, the time sequence of the signals of the first clock control signal ends electrically connected with each first register group is the same, and the areas corresponding to the rest of the first register groups are not subjected to display driving, so that the power consumption can be reduced. When the display panel displays the whole display, the signals of each first frame starting signal end and the first clock control signal end are set to enable each first register group to work sequentially, and the driving signal lines in the display panel are driven to display line by line, so that the display panel can realize the function of whole display.
Optionally, in the display panel provided in the embodiment of the present invention, when the display panel is subjected to a factory test, in a frame scanning time, each first register group VSR _ EMIT _ m is configured to operate simultaneously under the control of signals of the electrically connected first frame start signal terminal stv1_ m and the first clock control signal terminal ckv1_ m, and drive the electrically connected light-emitting control signal lines EMIT line by line; the timings of the signals of the first clock control signal terminal ckv1_ m electrically connected to each first register group VSR _ EMIT _ m are the same, and the timings of the signals of the first frame start signal terminal stv1_ m electrically connected to each first register group VSR _ EMIT _ m are the same.
Specifically, before the display panel leaves a factory, a pressure test is performed, and effective signals are loaded to all the light-emitting control signal lines EMIT through the light-emitting control circuit VSR _ EMIT, so that the transistors connected to the light-emitting control signal lines EMIT are enabled at a high voltage, and thus, the defect states in the transistors can be repaired, the off-state voltage is reduced, and the generation of bright spots is reduced as much as possible after the display panel is shipped. When the display panel is tested in a factory, the first register sets VSR _ EMIT _ m can be controlled to work simultaneously, so as to improve the working efficiency.
In a specific implementation, the display panel provided in the embodiment of the present invention may be an electroluminescent display panel. In an electroluminescent display panel, a plurality of electroluminescent diodes and a pixel driving circuit connected to each of the electroluminescent diodes are generally provided. A light emission control transistor for controlling light emission of the organic light emitting diode and a scan control transistor for controlling input of a data signal are provided in a general pixel driving circuit. The driving start signal output by the light-emitting control circuit VSR _ EMIT is transmitted to the light-emitting control transistor through the light-emitting control signal line EMIT, so as to control the light-emitting control transistor to be started, and control the driving transistor to drive the electroluminescent diode to EMIT light, so that the display panel realizes the display function. The driving closing signal output by the light-emitting control circuit VSR _ EMIT is used for controlling the light-emitting control transistor to be closed so as to prevent the driving transistor from driving the electroluminescent diode to EMIT light, so that the display panel does not need to display, and the power consumption is further reduced. Therefore, when the display is carried out in the divided areas, the first register group which works independently can control the light-emitting control transistor of the corresponding area to be turned on so as to realize the display function. And the rest first register groups do not output the driving starting signal, so that the display of the corresponding area is not luminous, and the power consumption of the display panel can be saved. In practical applications, the specific structure of the pixel driving circuit may be the same as that of the pixel driving circuit having the light emitting control transistor and the scanning control transistor in the prior art, and will not be described herein again.
In a specific implementation manner, in the display panel provided in the embodiment of the present invention, the cascade relationship of each first shift register in each first register group is: the input signal end of the first-stage first shift register is connected with the corresponding first frame starting signal end; except the first stage of first shift register, the input signal ends of the other first shift registers of each stage are respectively connected with the output signal end of the first shift register of the previous stage adjacent to the input signal end of the first shift register of the previous stage.
In a specific implementation, in the display panel provided in the embodiment of the present invention, as shown in fig. 3 and 4, the first shift register may include: a first switch transistor M1, a second switch transistor M2, a third switch transistor M3, a fourth switch transistor M4, a fifth switch transistor M5, a sixth switch transistor M6, a seventh switch transistor M7, an eighth switch transistor M8, a first capacitor C1 and a second capacitor C2. A control electrode of the first switching transistor M1 is connected to the first clock signal terminal CK, a first electrode of the first switching transistor M1 is connected to the input signal terminal In, and a second electrode of the first switching transistor M1 is connected to the first node N1. A control electrode of the second switching transistor M2 is connected to the first clock signal terminal CK, a first electrode of the second switching transistor M2 is connected to the first reference voltage signal terminal vref1, and a second electrode of the second switching transistor M2 is connected to the second node N2. A control electrode of the third switching transistor M3 is connected to the first reference voltage signal terminal vref1, a first electrode of the third switching transistor M3 is connected to the first node N1, and a second electrode of the third switching transistor M3 is connected to the third node N3. A control electrode of the fourth switching transistor M4 is connected to the first node N1, a first electrode of the fourth switching transistor M4 is connected to the first clock signal terminal CK, and a second electrode of the fourth switching transistor M4 is connected to the second node N2.
A control electrode of the fifth switching transistor M5 is connected to the second clock signal terminal CKB, a first electrode of the fifth switching transistor M5 is connected to the second electrode of the sixth switching transistor M6, and a second electrode of the fifth switching transistor M5 is connected to the first node N1. A control electrode of the sixth switching transistor M6 is connected to the second node N2, and a first electrode of the sixth switching transistor M6 is connected to the second reference voltage signal terminal vref 2. A control electrode of the seventh switching transistor M7 is connected to the third node N3, a first electrode of the seventh switching transistor M7 is connected to the second clock signal terminal CKB, and a second electrode of the seventh switching transistor M7 is connected to the output signal terminal Out of the first shift register unit. A control electrode of the eighth switching transistor M8 is connected to the second node N2, a first electrode of the eighth switching transistor M8 is connected to the second reference voltage signal terminal vref2, and a second electrode of the eighth switching transistor M8 is connected to the output signal terminal Out of the first shift register unit. A first terminal of the first capacitor C1 is connected to the third node N3, and a second terminal of the first capacitor C1 is connected to the output signal terminal Out of the first shift register unit. A first terminal of the second capacitor C2 is connected to the second node N2, and a second terminal of the second capacitor C2 is connected to the second reference voltage signal terminal vref 2. The specific structure of the first shift register provided in the embodiment of the present invention is merely illustrated, and in the implementation, the specific structure of the first shift register is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.
In a specific implementation manner, in the display panel provided in the embodiment of the present invention, as shown in fig. 3, each of the switch transistors may be a P-type transistor, and the P-type transistor is turned on under the control of a low-level signal and turned off under the control of a high-level signal. Alternatively, as shown in fig. 4, each of the switching transistors may be an N-type transistor, and the N-type transistor may be turned on by a high-potential signal and turned off by a low-potential signal. The control electrode of each switching transistor is a gate electrode thereof, and depending on the type of each switching transistor, the first electrode is a source electrode thereof and the second electrode is a drain electrode thereof, or the first electrode is a drain electrode thereof and the second electrode is a source electrode thereof, which are not distinguished herein.
In practical applications, a timing chart of a circuit corresponding to the first shift register shown In fig. 3 is shown In fig. 5, an input signal end In corresponds to a pulse signal In with a low potential of an effective pulse signal, a first clock signal end CK corresponds to a clock signal CK, a second clock signal end CKB corresponds to a clock signal CKB, and an output signal end Out corresponds to an output driving signal Out. At this time, the valid clock signals of the clock signals ck and ckb in one clock cycle are low-level signals in one clock cycle, and the low-level signals in one clock cycle are used for generating low-level signals serving as driving-on signals in the driving signals out. However, when the signal corresponding to the input signal terminal In is the fixed high signal, the seventh transistor M7 is not turned on, so that the output driving signal out always keeps outputting the fixed high signal.
Fig. 6 shows a timing chart of a circuit corresponding to the first shift register shown In fig. 4, where an input signal terminal In corresponds to a pulse signal In whose effective pulse signal is at a high level, a first clock signal terminal CK corresponds to a clock signal CK, a second clock signal terminal CKB corresponds to a clock signal CKB, and an output signal terminal Out corresponds to an output driving signal Out. At this time, the effective clock signals of the clock signals ck and ckb in one clock cycle are high level signals in one clock cycle, and the high level signals in one clock cycle are used for generating the high level signals as the driving start signals in the driving signal out. However, when the signal corresponding to the input signal terminal In is the fixed low signal, the seventh transistor M7 is not turned on, so that the output driving signal out always keeps outputting the fixed low signal. The working processes of the two first shift registers are substantially the same as those in the prior art, and it should be understood by those skilled in the art that the working processes are not described herein again, nor should they be construed as limitations to the present invention.
In practical implementation, when the structure of the first shift register in the display panel provided by the embodiment of the present invention is as shown in fig. 3 or fig. 4, and with reference to fig. 1 and fig. 2, the first clock control signal terminal ckv1_ m corresponding to one first register group VSR _ EMIT _ m may include two first clock control sub-signal terminals: ck1_ m and ckb1_ m. The connection relationship between the first clock signal terminal of each first shift register in the first register group VSR _ EMIT _ m and the corresponding first clock control sub-signal terminal may be: the first clock signal terminal CK of the first shift register of the 2c-1 th stage and the second clock signal terminal CKB of the first shift register of the 2c stage are both connected to the same first clock control sub-signal terminal CK1_ m, the second clock signal terminal CKB of the first shift register of the 2c-1 th stage and the first clock signal terminal CK of the first shift register of the 2c stage are both connected to the same first clock control sub-signal terminal CKB1_ m, and c is a positive integer.
In a specific implementation, in the display panel provided in the embodiment of the present invention, as shown in fig. 3, the first shift register includes a plurality of P-type transistors, and in order to enable the first shift register in the first register group to sequentially implement the shift output operation, as shown in fig. 5, the first frame start signal end electrically connected to the first register group may load the pulse signal in with the effective pulse signal at the low potential. And, the first clock control sub-signal terminal electrically connected to the first register group can load the clock signals ck and ckb, respectively. However, in order to prevent the first shift register in the first register group from outputting the driving turn-on signal, the first frame start signal terminal electrically connected to the first register group may be loaded with a fixed high signal to prevent the P-type transistor in the shift register from turning on. Therefore, in the specific implementation, during the display in the sub-region, the first frame start signal end electrically connected to the first register group in the working part can correspondingly load the pulse signal with the effective pulse signal as the low potential, so that the first register group in the working part can work normally to drive the light-emitting control signal line. The first frame start signal ends electrically connected with the rest of the first register groups except for part of the first register groups can be loaded with fixed high-potential signals, and the first clock control signal ends electrically connected with the rest of the first register groups are loaded with signals identical to the first clock control signal ends electrically connected with the working part of the first register groups, so that the rest of the first register groups can avoid driving the light-emitting control signal lines while reducing the interference among the first clock control signal lines.
In a specific implementation, in the display panel provided in the embodiment of the present invention, as shown in fig. 4, the first shift register includes a plurality of N-type transistors, and in order to enable the first shift register in the first register group to sequentially implement the shift output operation, as shown in fig. 6, the first frame start signal end electrically connected to the first register group may be loaded with the pulse signal in whose effective pulse signal is a high potential. And, the first clock control sub-signal terminal electrically connected to the first register group can load the clock signals ck and ckb, respectively. However, in order to prevent the first shift register in the first register group from outputting the driving turn-on signal, the first start-of-frame signal terminal electrically connected to the register group may be loaded with a fixed low-level signal to prevent the N-type transistor in the first shift register from turning on. Therefore, in the specific implementation, when the display is performed in the divided regions, the first frame start signal end electrically connected to a part of the first register groups can correspondingly load the pulse signal with the high potential as the effective pulse signal, so that the part of the first register groups can normally work to drive the light-emitting control signal lines. Except for part of the first register groups, the first frame start signal ends electrically connected with the other first register groups can all load fixed low-potential signals, and meanwhile, the first clock control signal ends electrically connected with the other first register groups load signals identical to the first clock control signal ends electrically connected with the working part of the first register groups, so that the rest part of the first register groups can avoid driving the light-emitting control signal lines while reducing the interference among the first clock control signal lines.
In practical implementation, in the display panel provided in the embodiment of the present invention, the first shift register may be divided into 2 first register groups arranged in sequence, that is, M is 2, so that the display panel may be driven and displayed in two regions. Alternatively, the first shift register may be divided into 3 first register groups arranged in sequence, that is, M is 3, so that the display panel may be driven and displayed in three regions. Of course, the first shift register may be divided into 4 or 5 … first register groups arranged in sequence, so that the display panel may be driven and displayed in a plurality of regions. In practical applications, the value of M needs to be designed and determined according to practical application environments, and is not limited herein.
The following describes a display panel provided in an embodiment of the present invention, with M ═ 2 and M ═ 3 as examples. In the following, the first shift register includes P-type transistors as an example.
The first embodiment,
Taking M as an example of 2, a display panel is generally provided with pixels for display, and light emission control signal lines extend in the row direction of the pixels. In specific implementation, as shown in fig. 1, in the display panel provided in the embodiment of the present invention, the display panel may be divided into two regions, which are respectively: a first area aa _1 and a second area aa _ 2. The 1 st first register group VSR _ EMIT _1 of the 2 first register groups is used to drive the light emission control signal line EMIT located in the first area aa _1, so that the light emission control signal line EMIT in the first area aa _1 may be driven. The 2 nd first register set VSR _ EMIT _2 is used to drive the light emission control signal line EMIT in the second area aa _2, so that the light emission control signal line EMIT in the second area aa _2 can be driven.
In a specific implementation, in the display panel provided in the embodiment of the present invention, each first shift register may include a left first shift register and a right first shift register respectively disposed at two ends of a same light emission control signal line emit; and when the display panel displays in whole or in regions, when the first shift register works, the left first shift register and the right first shift register at two ends of the same light-emitting control signal line emit work simultaneously, so that the display panel can realize the function of bilateral driving. When the display panel is subjected to factory test, when the first shift register works, the left first shift register and the right first shift register at two ends of the same light-emitting control signal line emit are selected to work, so that the full-screen driving effect is achieved, and meanwhile, the service life of the first shift register at the non-working side can be prolonged. Specifically, as shown in fig. 1, taking the first shift register SR1_1 as an example, the first shift register SR1_1 includes a left first shift register SR1_1a and a right first shift register SR1_1b located on the emission control signal line emit that drives the pixels of the same row. The specific configuration of the remaining first shift registers can refer to the configuration of the first shift register SR1_1, which is not described herein.
In practical implementation, when the display panel provided by the embodiment of the present invention displays in a sub-area, wherein when the first area aa _1 is displayed and the second area aa _2 is not displayed, the first frame start signal end stv1_1 may correspond to the signal stv1 in fig. 7. The first clock control sub-signal terminals ck1_1, ckb1_1 may correspond to ck1, ckb1 in fig. 7, respectively. Thus, the 1 st first register group VSR _ EMIT _1 in the light emission control circuit can be operated under the control of the signals of the first frame start signal terminal stv1_1 and the first clock control signal terminal (including the first clock control sub-signal terminals ck1_1 and ckb1_1) electrically connected thereto to output the driving signal to drive the light emission control signal line in the first area aa _1, so that the electroluminescent diode in the first area aa _1 EMITs light, thereby realizing the display function. The first frame start signal terminal stv1_2 corresponding to the 2 nd first register group VSR _ EMIT _2 may be loaded with a high signal corresponding to stv2 in fig. 7, and the first clock control sub signal terminals ck1_2 and ckb1_2 may correspond to ck2 and ckb2 in fig. 7, respectively. So as not to output the driving signal under the control of the signals of the first frame start signal terminal stv1_2 and the clock control signal terminal (including the clock control sub signal terminals ck _2 and ckb _2) electrically connected thereto, so as to avoid the electroluminescent diode in the second area aa _2 from emitting light, thereby avoiding the display in the second area aa _2 and further reducing the power consumption of the display panel. When the first area aa _1 is not displayed and the second area aa _2 is displayed, the operation principle of the display panel is substantially the same as that described above, and the detailed description thereof is omitted. During the entire display, the 1 st first register set VSR _ EMIT _1 and the 2 nd first register set VSR _ EMIT _2 sequentially operate to drive the light emission control signal lines in the display panel line by line. At this time, the first frame start signal terminals stv1_1 and stv1_2 may correspond to the signals stv1 and stv2 in fig. 8, respectively. The first clocking sub-signal terminals ck1_1, ckb1_1, ck1_2, ckb1_2 may correspond to ck1, ckb1, ck2, ckb2 in fig. 8, respectively. In a factory test, the 1 st first register group VSR _1 and the 2 nd first register group VSR _2 operate simultaneously to drive the light emission control signal lines in the display panel line by line. At this time, the first frame start signal terminals stv1_1 and stv1_2 may correspond to the signals stv1 and stv2 in fig. 9, respectively. The first clock control sub-signal terminals ck _1, ckb _1, ck _2, ckb _2 may correspond to ck1, ckb1, ck2, ckb2 in fig. 8, respectively.
Example II,
Taking M ═ 3 as an example, in a specific implementation, in the display panel provided in the embodiment of the present invention, as shown in fig. 2, the display panel may be divided into three regions, which are: a first area aa _1, a second area aa _2, and a third area aa _ 3. The 1 st first register group VSR _ EMIT _1 of the 3 first register groups is used to drive the light emission control signal line EMIT located in the first area aa _1, so that the light emission control signal line EMIT in the first area aa _1 may be driven. The 2 nd first register set VSR _ EMIT _2 is used to drive the light emission control signal line EMIT in the second area aa _2, so that the light emission control signal line EMIT in the second area aa _2 can be driven. The 3 rd first register set VSR _ EMIT _3 is used to drive the light emission control signal line EMIT located in the third area a _3 so that the light emission control signal line EMIT in the third area aa _3 can be driven.
In a specific implementation, in the display panel provided in the embodiment of the present invention, each first shift register may include a left first shift register and a right first shift register respectively disposed at two ends of a same light emission control signal line emit; and when the display panel displays in whole or in regions, when the first shift register works, the left first shift register and the right first shift register at two ends of the same light-emitting control signal line emit work simultaneously, so that the display panel can realize the function of bilateral driving. When the display panel is subjected to factory test, when the first shift register works, the left first shift register and the right first shift register at two ends of the same light-emitting control signal line emit are selected to work, so that the full-screen driving effect is achieved, and meanwhile, the service life of the first shift register at the non-working side can be prolonged. Specifically, as shown in fig. 2, taking the first shift register SR1_1 as an example, the first shift register SR1_1 includes a left first shift register SR1_1a and a right first shift register SR1_1b located on the emission control signal line emit that drives the pixels of the same row. The specific configuration of the remaining first shift registers can refer to the configuration of the first shift register SR1_1, which is not described herein.
The driving method for the split area display, the full screen display and the factory test is similar to the embodiment and will not be described in detail here.
Further, in a specific implementation, in the display panel provided in the embodiment of the present invention, as shown in fig. 10, the display panel may further include a plurality of GATE signal lines GATE and a GATE driving circuit VSR _ GATE; the GATE driving circuit VSR _ GATE has a plurality of second shift registers SR _ n arranged in cascade; each second shift register SR _ n is electrically connected with at least one grid signal line gate; the first second shift register is electrically connected to a second frame start signal terminal stv 2; each second shift register SR _ n is electrically connected to the same second clock control signal terminal ckv 2;
during one frame scanning time, each of the second shift registers SR _ n is configured to sequentially operate under the control of signals of the electrically connected second frame start signal terminal stv2 and the second clock control signal terminal ckv2, and drive the electrically connected gate signal lines gate row by row.
Specifically, a driving turn-on signal output by the GATE driving circuit VSR _ GATE is transmitted to the scan control transistor through the GATE signal line GATE, and controls the scan control transistor to be turned on and off. The driving starting signal is used for controlling the scanning control transistor to be started, and the driving stopping signal is used for controlling the scanning control transistor to be stopped.
Specifically, in the display panel provided by the embodiment of the invention, the GATE driving circuits VSR _ GATE are not grouped, and only one set of the second clock control signal terminal ckv2 and the second frame start signal terminal stv2 is adopted, so that the wiring can be saved. In the case of the divided display, the whole display, or the factory test, the second shift registers SR _ n in the GATE driving circuits VSR _ GATE are sequentially operated. When the display is carried out in the subarea display mode, the non-display area is controlled to EMIT no light through the light-emitting control circuit VSR _ EMIT, so that the grid driving circuits VSR _ GATE are prevented from being grouped, and the narrow frame design is influenced by increasing the wiring.
Further, similarly, in the display panel provided in the embodiment of the present invention, as shown in fig. 10, the GATE driving circuit VSR _ GATE may also implement a driving function in a bilateral driving manner, and specifically, each of the second shift registers may include a left second shift register SR _ na and a right second shift register SR _ nb respectively disposed at two ends of the same GATE signal line GATE; and when the display panel displays in whole or in regions, the left second shift register and the right second shift register which are positioned at two ends of the same grid signal line work simultaneously when the second shift register works, so that the display panel can realize the function of bilateral driving. When the display panel is tested in a factory, when the second shift register works, the left second shift register and the right second shift register which are positioned at two ends of the same grid signal line are selected to work, so that the full-screen driving effect is achieved, and meanwhile, the service life of the non-working second shift register can be prolonged.
In practical application, when the scan control transistor is turned on, the source driving circuit in the display panel loads corresponding display signals to the data lines, so that the display panel displays one picture. The working process of the source driving circuit can be the same as that of the prior art, and is not described herein. Therefore, in the display panel provided in the embodiment of the present invention, the display panel may further include a plurality of data signal lines, and a source driving circuit electrically connected to the plurality of data signal lines;
when the display panel displays in a subarea mode, in a frame scanning time, the source electrode driving circuit is used for loading effective data signals to a plurality of electrically connected data signal lines only when a part of the first register groups work; when the rest of the first register groups work, a fixed low-potential signal is loaded on a plurality of data signal lines which are electrically connected, so that the power consumption can be saved.
Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention. The display device can be implemented by referring to the above embodiments of the display panel, and repeated descriptions are omitted.
In the display panel and the display device provided by the embodiments of the present invention, the first shift registers in the light-emitting control circuit are grouped, the first shift registers in each first register group are arranged in a cascade manner, and each first register group is electrically connected to a plurality of adjacent light-emitting control signal lines, and different first frame start signal ends and different first clock control signal ends are respectively arranged for each first register group, so that each first register group can be independently controlled to drive the electrically connected light-emitting control signal lines. When the display panel displays in the subareas, signals of each first frame starting signal end and the first clock control signal end are set to enable part of the first register groups to work independently, so that the areas corresponding to the working first register groups are subjected to display driving, signals of the first frame starting signal ends electrically connected with the rest of the first register groups are different from signals of the first frame starting signal ends electrically connected with the part of the first register groups, the time sequence of the signals of the first clock control signal ends electrically connected with each first register group is the same, and the areas corresponding to the rest of the first register groups are not subjected to display driving, so that the power consumption can be reduced. When the display panel displays the whole display, the signals of each first frame starting signal end and the first clock control signal end are set to enable each first register group to work sequentially, and the light-emitting control signal lines in the display panel are driven to display line by line, so that the display panel can realize the function of whole display.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A display panel, comprising: a plurality of light emission control signal lines, and a light emission control circuit having a plurality of first shift registers; the first shift register is divided into M first register groups which are sequentially arranged, and each first register group is correspondingly and electrically connected with a plurality of adjacent light-emitting control signal wires; each first shift register in each first register group is arranged in a cascade mode, and each first shift register is electrically connected with at least one light-emitting control signal line; each first register group is correspondingly connected with different first frame starting signal ends and different first clock control signal ends respectively; m is an integer greater than 1;
when the display panel displays in a subarea mode, in one frame of scanning time, part of the M first register groups are used for independently working under the control of signals of a first frame starting signal end and a first clock control signal end which are electrically connected, and driving light-emitting control signal lines which are electrically connected line by line; except for the partial first register groups, signals of first frame starting signal ends electrically connected with the rest first register groups are different from signals of first frame starting signal ends electrically connected with the partial first register groups, and the time sequence of the signals of the first clock control signal ends electrically connected with each first register group is the same;
when the display panel displays the whole, in the scanning time of one frame, each first register group is used for working sequentially under the control of signals of a first frame starting signal end and a first clock control signal end which are electrically connected and driving light-emitting control signal lines in the display panel line by line; the time sequence of signals of a first clock control signal end electrically connected with each first register group is the same, and except for the first register group, the time sequence of signals of a first frame starting signal end electrically connected with other first register groups is the same as the time sequence of signals output by a last stage first shift register in the last adjacent first register group;
the display panel also comprises a plurality of grid signal lines and a grid driving circuit; the grid driving circuit is provided with a plurality of second shift registers which are arranged in a cascade mode; each second shift register is electrically connected with at least one grid signal line; the first second shift register is electrically connected with a second frame starting signal end; each second shift register is electrically connected with the same second clock control signal end;
and in one frame of scanning time, each second shift register is used for sequentially working under the control of signals of a second frame starting signal end and a second clock control signal end which are electrically connected and driving the electrically connected grid signal lines line by line.
2. The display panel according to claim 1, wherein each of the first register groups is configured to operate simultaneously under control of signals of a first frame start signal terminal and a first clock control signal terminal which are electrically connected, and drive light emission control signal lines line by line, within the one-frame scanning time, at the time of a factory test of the display panel; the time sequence of signals of a first clock control signal end electrically connected with each first register group is the same, and the time sequence of signals of a first frame start signal end electrically connected with each first register group is the same.
3. The display panel according to claim 1, wherein the display panel is divided into a first region and a second region; m is 2, wherein a 1 st one of the 2 first register groups is used to drive a light emission control signal line located in the first region; the 2 nd first register group is used for driving a light-emitting control signal line in the second area; or the like, or, alternatively,
the display panel is divided into a first area, a second area and a third area; m-3, wherein a 1 st one of the 3 first register groups is used to drive a light emission control signal line located in the first region; the 2 nd first register group is used for driving a light-emitting control signal line in the second area; the 3 rd first register group is used for driving a light emission control signal line located in the third area.
4. The display panel according to claim 1, wherein the first shift register includes a plurality of P-type transistors;
when the display panel displays in a subarea mode, a first frame starting signal end electrically connected with the partial first register group correspondingly loads a pulse signal with a low potential effective pulse signal; except for the partial first register groups, the first frame starting signal ends electrically connected with the rest first register groups are loaded with fixed high-potential signals.
5. The display panel according to claim 1, wherein the first shift register includes a plurality of N-type transistors;
when the display panel displays in a subarea mode, a first frame starting signal end electrically connected with the partial first register group correspondingly loads an effective pulse signal which is a high-potential pulse signal; except for the part of the first register groups, the first frame starting signal ends electrically connected with the other first register groups are loaded with fixed low-potential signals.
6. The display panel according to any one of claims 1 to 5, wherein each of the first shift registers includes a left side first shift register and a right side first shift register respectively provided at both ends of the same light emission control signal line; when the display panel displays in whole or in regions, the left first shift register and the right first shift register which are positioned at two ends of the same light-emitting control signal line work simultaneously when the first shift register works; when the display panel is subjected to factory test, when the first shift register works, the left first shift register and the right first shift register which are positioned at two ends of the same light-emitting control signal line are selected to work.
7. The display panel according to claim 1, wherein each of the second shift registers includes a left second shift register and a right second shift register respectively disposed at both ends of the same gate signal line; when the display panel displays in whole or in regions, the left second shift register and the right second shift register which are positioned at two ends of the same grid signal line work simultaneously when the second shift register works; when the display panel is subjected to factory test, when the second shift register works, the left second shift register and the right second shift register which are positioned at two ends of the same grid signal line are selected to work.
8. The display panel according to claim 1, further comprising a plurality of data signal lines, and a source driving circuit electrically connected to the plurality of data signal lines;
when the display panel displays in a subarea mode, in a frame scanning time, the source electrode driving circuit is used for loading effective data signals to the plurality of data signal lines which are electrically connected only when the partial first register groups work; and when the rest of the first register groups work, loading a fixed low-potential signal to the plurality of electrically connected data signal lines.
9. A display device characterized by comprising the display panel according to any one of claims 1 to 8.
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| EP4018429A1 (en) * | 2019-10-31 | 2022-06-29 | Google LLC | Technique for partial area display |
| TWI723780B (en) * | 2020-02-19 | 2021-04-01 | 友達光電股份有限公司 | Driving method for partial displaying |
| CN111402806B (en) * | 2020-04-26 | 2021-08-27 | 京东方科技集团股份有限公司 | Driving circuit, driving method thereof and display panel |
| CN111710286B (en) * | 2020-06-30 | 2023-01-24 | 上海中航光电子有限公司 | Display panel, driving control method thereof and display device |
| CN112863448A (en) * | 2021-01-11 | 2021-05-28 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| TWI831179B (en) * | 2022-04-13 | 2024-02-01 | 友達光電股份有限公司 | Display panel and method of driving pixel thereof |
| CN115311976A (en) * | 2022-08-09 | 2022-11-08 | 信利(仁寿)高端显示科技有限公司 | STV control-based partition grid scanning method and display panel |
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Effective date of registration: 20211021 Address after: No.8 liufangyuan Road, Dongyi Industrial Park, Donghu New Technology Development Zone, Wuhan, Hubei Province Patentee after: WUHAN TIANMA MICROELECTRONICS Co.,Ltd. Patentee after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch Address before: Room 509, building 1, 6111 Longdong Avenue, Pudong New Area, Shanghai 201201 Patentee before: SHANGHAI TIANMA AM-OLED Co.,Ltd. |