CN105372891A - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN105372891A CN105372891A CN201510887454.XA CN201510887454A CN105372891A CN 105372891 A CN105372891 A CN 105372891A CN 201510887454 A CN201510887454 A CN 201510887454A CN 105372891 A CN105372891 A CN 105372891A
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- 239000000758 substrate Substances 0.000 title abstract description 5
- 230000008878 coupling Effects 0.000 abstract description 2
- 238000010168 coupling process Methods 0.000 abstract description 2
- 238000005859 coupling reaction Methods 0.000 abstract description 2
- 241001270131 Agaricus moelleri Species 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention has described a kind of array base plate and display device, the said array base plate includes the pixel array, is formed by a plurality of pixel units in m lines x n matrix arrangement; a plurality of gate lines extending in a row direction, a plurality of data lines and scan lines extending in a column direction, the scan lines being connected to one of the gate lines and insulated from the remaining gate lines; a first wiring area or a second wiring area is arranged between two adjacent columns of pixel units, and the first wiring area and the second wiring area are alternately arranged along the row direction; two data lines are arranged in each first wiring area, and at most one scanning line is arranged in each second wiring area. The array substrate provided by the invention can increase the distance between the scanning line and the data line, reduce the voltage coupling on the data line and solve the problem that partial pixels of the display device are over-bright in medium and low gray scales.
Description
Technical field
The present invention relates to thin film transistor (TFT) (ThinFilmTransistor, TFT) display technique field, particularly relate to a kind of array base palte and comprise the display device of this array base palte.
Background technology
Array base palte, is also called TFT substrate, has the features such as volume is little, low in energy consumption, occupies leading position in current field of display.
Current TFT substrate comprises pel array, and pel array comprises the pixel cell of multiple array arrangement, arranges TFT switch and pixel electrode in each pixel cell.The function of TFT switch is a three-terminal switch pipe, and one end is grid, corresponding gate line; One end is source electrode, respective data lines; One end is drain electrode, respective pixel electrode.Array base palte also comprises gate driver circuit and data drive circuit, and gate driver circuit inputs sweep signal to gate line, and data drive circuit is to data line input data signal.Gate driver circuit and data drive circuit are arranged on the region beyond pel array.
Fig. 1 is the vertical view of a kind of array base palte in prior art.As Fig. 1, array base palte 1 comprises pel array 2, many gate lines 4 and a plurality of data lines 3.Gate line 4 and data line 3 need to be connected to driving chip 6, and driving chip 6 provides drive singal for gate line 4 and data line 3.Gate line 4 is connected to driving chip 6 by gate line connecting portion 4-1, and gate line connecting portion 4-1 is arranged on the both sides of pel array 2, and therefore gate line connecting portion 4-1 occupies a part of region on array base palte 1, causes the frame of array base palte 1 wider.
Summary of the invention
In view of this, the invention provides a kind of array base palte and comprise the display device of this array base palte.
The invention provides a kind of array base palte, comprising: pel array, described pel array comprises multiple pixel cell, described pixel cell with m capable × n row matrix-style arrangement, m and n is positive integer;
Described array base palte also comprises many gate lines extended in the row direction, many data lines along column direction extension and sweep trace, and sweep trace is connected with in gate line and insulate with remaining gate line;
First cabling district and the second cabling district are the first cabling district or the second cabling district between adjacent two row pixel cells, and the alternately arrangement in the row direction of the first cabling district and the second cabling district; Be provided with two data lines in each first cabling district, in each second cabling district, be provided with a sweep trace at the most.
The present invention also provides a kind of display device, comprising: array base palte provided by the present invention.
Compared with prior art, the present invention at least has one of following outstanding advantage: not only narrow frame; And sweep trace and data line be arranged in parallel and be provided with pixel cell between sweep trace and data line, decrease interference therebetween, namely reduce voltage couples on data line, solve display device in low GTG time there is the situation that partial pixel is excessively bright.
Accompanying drawing explanation
Fig. 1 is the vertical view of a kind of array base palte in prior art;
Fig. 2 is the vertical view of a kind of array base palte in the present invention;
Fig. 3 is the vertical view of another array base palte in the present invention;
Fig. 4 is the vertical view of another array base palte in the present invention;
Fig. 5 is a kind of vertical view of pixel cell;
Fig. 6 is the cut-open view along AA ' line and BB ' line in Fig. 5;
Fig. 7 is the vertical view of another pixel cell;
Fig. 8 is the cut-open view along CC ' line and DD ' line in Fig. 7;
Fig. 9 is the vertical view of another pixel cell;
Figure 10 is the cut-open view along EE ' line and FF ' line in Fig. 9;
Figure 11 is the vertical view of another array base palte in the present invention;
Figure 12 is the cut-open view along GG ' line in Figure 11;
Figure 13 is the vertical view of another array base palte in the present invention;
Figure 14 is the cut-open view along HH ' line in Figure 13;
Figure 15 is the another kind of cut-open view along EE ' line and FF ' line in Fig. 9;
Figure 16 is the vertical view of another pixel cell;
Figure 17 is the cut-open view along II ' line and JJ ' line in Figure 16;
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and below in conjunction with drawings and Examples, the present invention will be further described.
It should be noted that, set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public embodiment.
Fig. 2 is the schematic diagram of a kind of array base palte in the present invention.Please refer to Fig. 2, array base palte 100 comprises pel array 110, and pel array 110 comprises multiple pixel cell 111.It should be noted that, pixel cell 111 comprises the structure such as thin film transistor (TFT), pixel electrode of grid, source electrode, drain electrode composition, in order to illustrative simplicity, outstanding content of the present invention, the sketch commonly used with this area in fig. 2 illustrates the structure such as thin film transistor (TFT), pixel electrode in each pixel cell.Multiple pixel cell 111 with m capable × n row matrix-style arrangement, m and n is positive integer.
Array base palte 100 also comprise many in the row direction X extend gate line 10 and many along column direction Y extend data lines 20, gate line 10 and data line 20 are for driving pixel cell 111.Array base palte 100 also comprises many sweep traces 30 extended along column direction Y.Sweep trace 30 is connected with in gate line 10, insulate with remaining gate line 10.It should be noted that, in the present invention, described line direction X and column direction Y is orthogonal, but the present invention does not limit this.
Array base palte 100 also comprises the first cabling district 120 and the second cabling district 130, be the first cabling district 120 or the second cabling district 130 between adjacent two row pixel cells 111, described first cabling district 120 and the second cabling district 130 are along line direction X alternately arrangement, two data lines 20 are provided with in each first cabling district 120, every bar data line 20 is all adjacent, and a namely nearest row pixel cell 111 connects.A sweep trace 30 is provided with in each second cabling district 130.
In the present invention, the situation of quantity more than the quantity of sweep trace 30 in the second cabling district 130 is worked as in existence, please refer to Fig. 3, the difference of Fig. 3 and Fig. 2 is, when the quantity in the second cabling district 130 is more than the quantity of sweep trace 30, in part second cabling district 130-1, sweep trace is not set, is therefore provided with a sweep trace 30 at the most in the second cabling district 130 in the present invention.
In the present invention, array base palte 100 also comprises dummy line (dummy line).As Fig. 4, with m=5, n=14 for example, 5 gate lines 10 and 5 sweep traces 30 are comprised in pel array 100,6 the second cabling districts 130, wherein arrange a sweep trace 30 in 5 the second cabling districts 130, therefore unnecessary go out a second cabling district 130-2 sweep trace is not set.When the second cabling district 130-2 does not arrange sweep trace, there is data line 20 to affect the imbalance of pixel cell 111, in order to avoid this impact, a dummy line 50 can be set in the second cabling district 130-2, in order to balance the capacitance coupling effect that pixel electrode is subject to, improve display quality.The set-up mode of dummy line 50 is identical with sweep trace 30, be and extend along column direction Y, but dummy line 50 is not connected with gate line 10 in fact, unsettled setting also can access the voltage of 1/2V.The the second cabling district 130 arranging sweep trace 30 and the second cabling district 130-2 arranging dummy line 50 can combination in any distributions.
In the present invention, there is the situation that the quantity working as the second cabling district 130 is less than the quantity of sweep trace 30, unnecessary sweep trace 30 can be arranged on the one or both sides of pel array 110.
In the present invention, be the first cabling district between preferred first row pixel cell and secondary series pixel cell, if when n is odd number, the n-th row pixel cell arranges separately a data lines 20.When being the second cabling district between first row pixel cell and secondary series pixel cell, need for first row and/or the n-th row pixel cell arrange separately a data lines 20.
Please continue to refer to Fig. 4, in the present invention, first substrate 100 is also provided with data drive circuit 140 and scan drive circuit 150, every bar data line 20 is connected to data drive circuit 140, and data drive circuit 140 provides data-signal for data line 20; Every bar gate line 10 is connected to described scan drive circuit 150 by sweep trace 30, and scan drive circuit 150 provides sweep signal for gate line 10.Data drive circuit 140 and scan drive circuit 150 are all arranged on the same side of pel array 110.
In the present invention, sweep trace 30 has two kinds with the connected mode of gate line 10:
In the first connected mode, can in the preparation process of array base palte 100, use with photoetching or mask (mask), gate line 10 is made in same rete with the part cabling of sweep trace 30 with identical material, in coupling part, sweep trace 30 connects with crossing realization of in gate line 10; At insulated part, sweep trace 30 uses bridge and all the other gate lines 10 to insulate, or gate line 10 uses bridge and all the other sweep traces 30 to insulate.
In order to the relation in the present invention on array base palte 100 between each rete is clearly described, the structure of concrete pixel cell is illustrated in Fig. 5, there is in pixel cell 111 gate line 10 be connected with grid 15, the data line 20 be connected with source electrode 12, the pixel electrode 13 be connected with drain electrode 11, sweep trace 30.Sweep trace 30 comprises multistage scanning cabling portion 31 and multiple scanning bridge 32, and scanning bridge 32 comprises scanning connecting hole 33 and scanning connecting portion 34.Pixel cell 111 also comprises public electrode, because with the inventive point of the present embodiment without direct relation, therefore not shown.
Please refer to Fig. 6, it should be noted that, in order to clearly illustrate that different rete is at the position relationship at diverse location place, Fig. 6 is divided into two parts, and wherein Part I is the cut-open view along AA ' line in Fig. 5; Part II is the cut-open view along BB ' line in Fig. 5.
Please continue to refer to Fig. 6, array base palte 100 comprises source electrode 11, drain electrode 12, grid 15, pixel electrode 13, gate line 10 and gate insulator 50.Sweep trace 30 comprises multistage scanning cabling portion 31 and multiple scanning bridge 32, scanning cabling portion 31 and the different layer of scanning bridge 32, scanning bridge 32 comprises scanning connecting hole 33 and scanning connecting portion 34, scanning cabling portion 31 and the same layer of gate line 10, scanning connecting portion 34 and the same layer of data line 20.Adjacent two sections of scanning cabling portions 31, in the position needing to insulate with gate line 10, are connected with two scanning connecting holes 33 by scanning connecting portion 34, thus avoid realize crossing with gate line 10 to insulate by sweep trace 30.Meanwhile, formed because the multistage scanning cabling portion 31 of sweep trace 30 and multiple scanning bridge 32 can utilize existing rete to etch, this technical scheme can be realized when not increasing mask.
At sweep trace 30 with the first connected mode of institute's gate line 10, please refer to Fig. 7, Fig. 7 is the vertical view of another pixel cell, the difference of Fig. 7 and Fig. 5 is, gate line 10 arranges multiple grid cabling portion 11 and multiple grid bridge 12, and grid bridge 12 comprises grid connecting hole 13 and grid connecting portion 14.
Please refer to Fig. 8, Fig. 8 is divided into two parts, and wherein Part I is the cut-open view along CC ' line in Fig. 7; Part II is the cut-open view along DD ' line in Fig. 7.Grid cabling portion 11 and the different layer of grid bridge 12, grid bridge 12 comprises grid connecting hole 13 and grid connecting portion 14, grid cabling portion 11 and the same layer of sweep trace 30, grid connecting portion 14 and the same layer of data line 20.At sweep trace 30 in the position needing to insulate with gate line 10, gate line 10 realizes insulating with sweep trace 30 by grid bridge 12.
Sweep trace 30 with the second connected mode of institute's gate line 10 is: sweep trace 30 rete with the different layer of described gate line 10 and therebetween arranges via hole, and sweep trace 30 is connected with in gate line 10 by described via hole.Embodiment is as follows:
Fig. 9 is the vertical view of another pixel cell, with reference to figure 9, has the gate line 10 be connected with grid 15 in pixel cell 111, the data line 20 be connected with source electrode 12, the pixel electrode 13 be connected with drain electrode 11 and sweep trace 30.Wherein, sweep trace 30 is connected with a gate line 10 by via hole 40.
Please refer to Figure 10, Figure 10 is divided into two parts, and wherein Part I is the cut-open view along EE ' line in Fig. 9; Part II is the cut-open view along FF ' line in Fig. 9.Sweep trace 30 and data line 20 are arranged on same rete, have via hole 40 in gate insulator 50, and sweep trace 30 is connected with in gate line 10 by via hole 40, insulate with all the other gate lines.
Figure 11 is the vertical view of another array base palte in the present invention, when sweep trace 30 is arranged on same rete with data line 20, sweep trace 30 and data line 20 all extend along column direction Y in pel array 110 region, there is not crossing problem, but sweep trace 30 and data line 20 need to be connected to data drive circuit 140 and scan drive circuit 150 respectively, in region A between pel array 110 and data drive circuit 140 and scan drive circuit 150, there is the problem that data drive circuit 140 and scan drive circuit 150 intersect.In order to solve this technical matters, need sweep trace 30 in the A of region, to be arranged on different rete from data line 20.Data line 20 comprises the first data wire part 20-1, the second data wire part 20-2 and data line thread-changing hole 21, and data line thread-changing hole 21 connects a data wire part 20-1 and the second data wire part 20-2.First data wire part 20-1 extends along column direction Y in pel array 110 region, and the first data wire part 20-1 and sweep trace 30 are arranged on same rete.
Please refer to Figure 12, Figure 12 is the cut-open view along GG ' line in Figure 11, second data wire part 20-2 and gate line 10 are arranged on same rete, setting data line thread-changing hole 21 in gate insulator 50, and data line thread-changing hole 21 connects a data wire part 20-1 and the second data wire part 20-2.In the A of region, sweep trace 30 and the different layer of data line 20, avoid crossing.
In the present embodiment, data line 20 can also be kept to be arranged on same rete, sweep trace 30 thread-changing in the A of region, to gate line 10 place rete, is avoided crossing with data line 20.Please refer to Figure 13, the difference of Figure 13 and Figure 11 is, sweep trace 30 comprises the first sweep trace portion 30-1, the second sweep trace portion 30-2 and sweep trace thread-changing hole 31.First sweep trace portion 30-1 extends along column direction Y in pel array 110 region, and the first sweep trace portion 30-1 data line 20 is arranged on same rete.
Please refer to Figure 14, Figure 14 is the cut-open view along HH ' line in Figure 13, second sweep trace portion 30-2 and gate line 10 are arranged on same rete, arrange sweep trace thread-changing hole 31, first sweep trace portion 30-1 in gate insulator 50 to be connected by described sweep trace thread-changing hole 31 with described second sweep trace portion 30-2.In the A of region, sweep trace 30 and the different layer of data line 20, avoid crossing.
Sweep trace 30 is with the second connected mode of institute's gate line 10, and array base palte 100 can also comprise touch control electrode and touch control electrode lead-in wire, is integrated into by touch function in array base palte 100, can the thickness of thinning module entirety.
Be divided into two parts with reference to Figure 15, Figure 15, wherein Part I is the cut-open view along EE ' line in Fig. 9; Part II is the cut-open view along FF ' line in Fig. 9.In Figure 15, array base palte 100 also comprises touch control electrode 14 and touch control electrode lead-in wire 16, and touch control electrode 14 is connected with the driver element be arranged on array base palte by touch control electrode lead-in wire 16.In this case sweep trace 30 and touch control electrode can be gone between and 16 use and be produced on same layer with photoetching or mask (mask), sweep trace 30 is connected by via hole 40 with in gate line 10.
Array base palte 100 in above embodiment can use amorphous silicon (a-Si), oxide (IndiumGalliumZincOxide, IGZO) or low temperature polycrystalline silicon (LowTemperaturePoly-Silicon, LTPS) make thin film transistor switch (TFT switch).When using low temperature polycrystalline silicon (LTPS) to make TFT switch, as shown in figure 16, pixel cell 111 comprises light shield layer 17 to the structure of pixel cell 111, grid 15, sweep trace 30, gate line 10.Figure 17 is the cut-open view along II ' line and JJ ' line in Figure 16, and array base palte 100 also comprises light shield layer 17, grid 15, source electrode 12, drain electrode 11, because other retes or structure and point of the present invention are without direct relation, therefore not shown.The material of light shield layer 17 is such as molybdenum aluminium alloy, chromium metal, molybdenum or other have the material of shade function and conduction property simultaneously, described sweep trace 30 can be arranged with layer with described light shield layer 17, uses same metal level to utilize same mask etching to be formed.Described sweep trace 30 is connected by via hole 40 with in described gate line 10.
The present invention also provides a kind of display device comprising above-mentioned array base palte 100.Display device can comprise: liquid crystal panel, LCD TV, mobile phone, computer etc.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should be considered as belonging to protection scope of the present invention.
Claims (11)
1. an array base palte, is characterized in that, comprising:
Pel array, described pel array comprises multiple pixel cell, described pixel cell with m capable × n row matrix-style arrangement, m and n is positive integer;
Many the gate lines extended in the row direction,
Many the data lines along column direction extension and sweep trace,
Described sweep trace is connected with in described gate line and insulate with gate line described in all the other,
First cabling district and the second cabling district are the first cabling district or the second cabling district between adjacent two row pixel cells,
Described first cabling district and the second cabling district be alternately arrangement in the row direction;
Be provided with two described data lines in each first cabling district, in each second cabling district, be provided with a described sweep trace at the most.
2. array base palte as claimed in claim 1, it is characterized in that, described array base palte also comprises dummy line, and described second cabling district comprises a described sweep trace or at the most a described dummy line at the most, and described dummy line and described gate line insulate.
3. array base palte as claimed in claim 1, it is characterized in that, described array base palte also comprises data drive circuit and scan drive circuit, described data drive circuit provides data-signal for described data line, described scan drive circuit is by described sweep trace for described gate line provides sweep signal, and described data drive circuit and described scan drive circuit are arranged on the same side of described pel array.
4. array base palte as claimed in claim 1, it is characterized in that, described sweep trace comprises:
Multistage scanning cabling portion and the multiple scanning bridge with the different layer in described scanning cabling portion,
Described scanning bridge connects two sections of adjacent described scanning cabling portions,
Described scanning cabling portion and the same layer of described gate line.
5. array base palte as claimed in claim 1, it is characterized in that, described gate line comprises:
Multistage grid cabling portion and the multiple grid bridge with the different layer in described grid cabling portion,
Described grid bridge connects two sections of adjacent described grid cabling portions,
Described grid cabling portion and the same layer of described sweep trace.
6. array base palte as claimed in claim 1, it is characterized in that, described array base palte also comprises via hole, and described sweep trace is connected with in described gate line by described via hole.
7. array base palte as claimed in claim 6, is characterized in that,
Each described sweep trace comprises the first sweep trace portion, the second sweep trace portion and sweep trace thread-changing hole,
Described first sweep trace portion is with the described second different layer in sweep trace portion and be connected by described sweep trace thread-changing hole,
Described first sweep trace portion and the same layer of described data line.
8. array base palte as claimed in claim 6, is characterized in that,
Each described data line comprises the first data wire part, the second data wire part and data line thread-changing hole,
Described first data wire part is with the different layer of described second data wire part and be connected by described data line thread-changing hole,
Described first data wire part and the same layer of described sweep trace.
9. array base palte as claimed in claim 6, it is characterized in that, described array base palte also comprises light shield layer, described sweep trace and the same layer of described light shield layer.
10. array base palte as claimed in claim 6, is characterized in that, described array base palte also comprises touch control electrode and touch control electrode lead-in wire, and described sweep trace and described touch control electrode go between same layer.
11. 1 kinds of display device, is characterized in that, comprising: the array base palte as described in any one of claim 1 to 10.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510887454.XA CN105372891B (en) | 2015-12-04 | 2015-12-04 | Array substrate and display device |
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| CN201510887454.XA CN105372891B (en) | 2015-12-04 | 2015-12-04 | Array substrate and display device |
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| CN105372891B CN105372891B (en) | 2019-03-08 |
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| CN106783895A (en) * | 2017-03-16 | 2017-05-31 | 厦门天马微电子有限公司 | Array base palte and its manufacture method and display device |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090135125A1 (en) * | 2007-11-23 | 2009-05-28 | June Ho Park | Liquid crystal display device |
| CN102385200A (en) * | 2010-08-27 | 2012-03-21 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and liquid crystal display panel |
| CN102819157A (en) * | 2012-08-06 | 2012-12-12 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display device |
| US20130093657A1 (en) * | 2011-10-12 | 2013-04-18 | Min-Chul Song | Liquid crystal display having minimized bezel area |
| CN103217843A (en) * | 2013-03-25 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal panel |
| CN104360558A (en) * | 2014-12-08 | 2015-02-18 | 重庆京东方光电科技有限公司 | Array substrate, display panel and display device |
| CN105047122A (en) * | 2015-09-08 | 2015-11-11 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
-
2015
- 2015-12-04 CN CN201510887454.XA patent/CN105372891B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090135125A1 (en) * | 2007-11-23 | 2009-05-28 | June Ho Park | Liquid crystal display device |
| CN102385200A (en) * | 2010-08-27 | 2012-03-21 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and liquid crystal display panel |
| US20130093657A1 (en) * | 2011-10-12 | 2013-04-18 | Min-Chul Song | Liquid crystal display having minimized bezel area |
| CN102819157A (en) * | 2012-08-06 | 2012-12-12 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and display device |
| CN103217843A (en) * | 2013-03-25 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal panel |
| CN104360558A (en) * | 2014-12-08 | 2015-02-18 | 重庆京东方光电科技有限公司 | Array substrate, display panel and display device |
| CN105047122A (en) * | 2015-09-08 | 2015-11-11 | 京东方科技集团股份有限公司 | Array substrate, display panel and display device |
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