CN111243486A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN111243486A CN111243486A CN202010156953.2A CN202010156953A CN111243486A CN 111243486 A CN111243486 A CN 111243486A CN 202010156953 A CN202010156953 A CN 202010156953A CN 111243486 A CN111243486 A CN 111243486A
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- goa unit
- array substrate
- area
- fan
- unit circuit
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- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application provides an array substrate and a display panel, wherein the array substrate comprises a plurality of scanning lines and a plurality of data lines which are arranged corresponding to a display area, a fan-out area and a binding area, the fan-out area and the binding area correspond to a non-display area, the binding area is positioned on one side of the display area, and the fan-out area is positioned between the binding area and the display area; a plurality of levels of GOA unit circuits which are arranged at intervals are arranged in the fan-out area along the direction of the scanning line; the plurality of data lines extend from the display area to the fan-out area and extend to the binding area through the gap between two adjacent GOA unit circuits; and the plurality of scanning lines are electrically connected with the GOA unit circuit through connecting wires arranged in the display area. This application is through setting up GOA unit circuit in the direction of following the scanning line in display panel, adopts the two-stage simultaneously GOA unit circuit drive corresponds the sub-pixel unit of line, increases GOA unit circuit's width to reduce GOA unit circuit's height, and then reduce display panel's width.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In recent years, the market share of large-screen smart phones is gradually increased according to market demands, and high-resolution and ultra-narrow frames become a market trend, wherein the demand of a spliced screen is more inevitable for the narrow-side width.
Three narrow products and one wide product can be used for three-edge splicing, the frame of a GOA large-size product with the width smaller than 1mm is about to become the leading technology in the future, however, as the resolution becomes higher, how to realize the large size needing splicing becomes a design difficulty.
Disclosure of Invention
The application provides an array substrate and a display panel, which are used for realizing narrow-frame or frameless design.
In order to realize the functions, the technical scheme provided by the application is as follows:
an array substrate comprises a plurality of scanning lines and a plurality of data lines which are arranged corresponding to a display area, a fan-out area and a binding area, wherein the fan-out area and the binding area correspond to a non-display area;
a plurality of levels of GOA unit circuits which are arranged at intervals are arranged in the fan-out area along the direction of the scanning line;
the plurality of data lines extend from the display area to the fan-out area and extend to the binding area through a gap between two adjacent GOA unit circuits;
and the plurality of scanning lines are electrically connected with the GOA unit circuit through connecting wires arranged in the display area.
In the array substrate of the application, many the scanning line with many the data line will array substrate divides into a plurality of pixel, pixel includes the sub-pixel unit, wherein, every two-stage GOA unit circuit is connected to one the scanning line, and two-stage GOA unit circuit is used for driving the sub-pixel unit that corresponds the line.
In the array substrate of the present application, the widths of the two GOA unit circuits are equal to the widths of the corresponding 3 consecutive sub-pixels.
In the array substrate of the present application, the width of the GOA unit circuit is greater than the width of the sub-pixel unit along the scanning line direction.
In the array substrate, the connecting wires are arranged at the gaps between the two adjacent sub-pixel units.
In the array substrate, the connecting wires and the data lines are arranged in parallel on the same layer.
In the array substrate, the scanning line with it is provided with the grid insulation layer to connect to walk to be provided with the via hole on the grid insulation layer, it passes through to connect to walk the line the via hole is connected with corresponding the scanning line.
In the array substrate, the array substrate comprises N scanning lines and two repeated GOA unit circuit groups, wherein each GOA unit circuit group comprises N-level GOA unit circuits;
the N-th-level GOA unit circuit in the first group of GOA unit circuit groups and the N-th-level GOA unit circuit in the second group of GOA unit circuit groups are connected to the same scanning line, wherein N is a positive integer, and N is a positive integer which is greater than or equal to 1 and less than or equal to N.
The application also provides a display panel, which comprises the array substrate.
Has the advantages that: this application is through setting up GOA unit circuit in the direction of following the scanning line in array substrate, adopts the two-stage simultaneously GOA unit circuit drive corresponds the sub-pixel unit of line, when increasing GOA unit circuit width, can become the height that reduces GOA unit circuit mutually, and then has reduced display panel's width to can realize display panel's narrow frame or no frame design.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a top view of an array substrate of the present application;
fig. 2 is a top view of an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
In the prior art, when a large-size display panel is manufactured, because the width of the display panel is larger than the effective exposure size of one photomask plate, a plurality of photomask plates are required to be spliced to realize the manufacturing, and therefore, the manufacturing cost is increased. Based on this, the application provides an array substrate and a display panel, can solve the defect of complaining on.
Referring to fig. 1, a top view of an array substrate of the present application is shown.
In the present application, the array substrate includes a plurality of scan lines 10 and a plurality of data lines 20 corresponding to the display area 100, and includes a fan-out area 300 and a bonding area 400 corresponding to the non-display area 200, the bonding area 400 is located on one side of the display area 100, the fan-out area 300 is located between the bonding area 400 and the display area 100.
In the fan-out area 300, a plurality of stages of GOA unit circuits 30 are arranged at intervals along the direction of the scan line 10.
The plurality of data lines 20 extend from the display area 100 to the fan-out area 300, and extend to the bonding area 400 through a gap between two adjacent GOA unit circuits 30.
The data lines 20 are spaced apart in the fan-out area 400.
The plurality of scan lines 10 are electrically connected to the GOA unit circuits 30 through connecting traces 40 arranged in the display area 100.
This application is through setting up GOA unit circuit 30 in the direction of scanning line in array substrate, be about to GOA unit circuit 30 sets up the one end along the line of data line 20 in array substrate, for example array substrate's bottom, thereby makes the width of display panel both sides reduces, and then realizes display panel's narrow frame or no frame design.
The technical solution of the present application will now be described with reference to specific embodiments.
Example one
Referring to fig. 2, a top view of an array substrate according to an embodiment of the present disclosure is shown.
In this embodiment, the array substrate includes a plurality of scan lines 10 and a plurality of data lines 20 disposed corresponding to the display area 100, and a fan-out area 300 and a bonding area 400 corresponding to the non-display area 200.
The binding region 400 is located at one side of the display region 100, and the fan-out region 300 is located between the binding region 400 and the display region 100.
In the fan-out area 300, a plurality of stages of GOA unit circuits 30 are arranged at intervals along the direction of the scan line 10.
The plurality of data lines 20 extend from the display area 100 to the fan-out area 300, and extend to the bonding area 400 through a gap between two adjacent GOA unit circuits 30.
The plurality of scan lines 10 are electrically connected to the GOA unit circuits 30 through connecting traces 40 arranged in the display area 100.
In this embodiment, the scan lines 10, the data lines 20, and the connecting traces 40 are all made of a conductive material such as silver or copper.
In the present embodiment, the array substrate is divided into a plurality of pixel units by the plurality of scan lines 10 and the plurality of data lines 20, and the pixel units include sub-pixel units 50.
The sub-pixel unit 50 is connected to the adjacent data line 20.
The adjacent sub-pixel units 50 are connected to different data lines 20.
The sub-pixel unit 50 includes any one of a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit.
Each two levels of the GOA unit circuits 30 are connected to one of the scan lines 10, and the two levels of the GOA unit circuits 30 are used for driving the sub-pixel units 50 in a corresponding row.
In this embodiment, the width of the two GOA unit circuits 30 is equal to the width of the corresponding 3 consecutive sub-pixel units 50 on the display substrate.
The 3 sub-pixel units 50 are red sub-pixel units, green sub-pixel units, and blue sub-pixel arrangements, and it should be noted that the present embodiment does not limit the types and arrangements of the sub-pixel units 50, and the example of the present embodiment is only for illustration.
In the present embodiment, the width of the GOA unit circuit 30 along the direction of the scan line 10 is greater than the width of the sub-pixel unit 50.
In this embodiment, the connecting trace 40 is disposed at a gap between two adjacent sub-pixel units 50.
In this embodiment, the connecting trace 40 and the data line 20 are disposed in the same layer and in parallel.
In this embodiment, a gate insulating layer is disposed between the scan line 10 and the connection trace 40, a via hole is disposed on the gate insulating layer, and the connection trace 40 is connected to the corresponding scan line 10 through the via hole.
In this embodiment, the array substrate includes a substrate, a gate insulating layer, and a connection trace, which are stacked in sequence.
The gate insulating layer is patterned to form a first via hole located above the gate, and the connecting wire is in contact with the gate through the first via hole.
The patterning process includes, but is not limited to, a masking and etching process.
In this embodiment, the array substrate includes N scan lines 10 and two repeated sets of the GOA unit circuits, and each set of the GOA unit circuits includes N levels of the GOA unit circuits 30.
The nth-level GOA unit circuit 30 in the first group of GOA unit circuits and the nth-level GOA unit circuit 30 in the second group of GOA unit circuits are connected to the same scan line 10.
Wherein N is a positive integer, and N is a positive integer greater than or equal to 1 and less than or equal to N.
In this embodiment, in the fan-out area 300, one data line 30 is disposed between two adjacent GOA unit circuits 30, or two data lines 30 are disposed, which is not limited in this embodiment.
Further, at least one data line 20 is disposed between two adjacent GOA unit circuits 30 in the fan-out area 300.
In the present embodiment, the GOA unit circuits 30 are arranged in the display panel along the direction of the scan line, two levels of the GOA unit circuits 30 are used for driving the sub-pixel units 50 in the corresponding row, and meanwhile, the widths of the two GOA unit circuits 30 are equal to the widths of the corresponding 3 consecutive sub-pixel units 50, so that the width of the GOA unit circuit 30 is increased, the height of the GOA unit circuit 30 is reduced, and the width of the side of the display panel is reduced.
The present application provides a display panel, where the display panel includes the array substrate according to the first embodiment, and a specific structure of the array substrate is described in the foregoing embodiments, and is not described herein again.
In the present application, the width of the side edge of the display panel is less than 1 mm.
The application provides an array substrate and a display panel, wherein the array substrate comprises a plurality of scanning lines and a plurality of data lines which are arranged corresponding to a display area, a fan-out area and a binding area, the fan-out area and the binding area correspond to a non-display area, the binding area is positioned on one side of the display area, and the fan-out area is positioned between the binding area and the display area; a plurality of levels of GOA unit circuits which are arranged at intervals are arranged in the fan-out area along the direction of the scanning line; the plurality of data lines extend from the display area to the fan-out area and extend to the binding area through the gap between two adjacent GOA unit circuits; and the plurality of scanning lines are electrically connected with the GOA unit circuit through connecting wires arranged in the display area.
This application is through setting up GOA unit circuit in the direction of following the scanning line in array substrate, be about it GOA unit circuit sets up data line one end along the line in the array substrate, for example display panel's bottom, thereby makes the width of display panel both sides reduces, adopts the two-stage simultaneously GOA unit circuit drive corresponds the sub-pixel unit of line, thereby increases GOA unit circuit's width can become like this and reduce GOA unit circuit's height, and then realizes display panel's narrow frame or no frame design.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. The array substrate is characterized by comprising a plurality of scanning lines and a plurality of data lines which are arranged corresponding to a display area, a fan-out area and a binding area, wherein the fan-out area and the binding area correspond to a non-display area;
a plurality of levels of GOA unit circuits which are arranged at intervals are arranged in the fan-out area along the direction of the scanning line;
the plurality of data lines extend from the display area to the fan-out area and extend to the binding area through a gap between two adjacent GOA unit circuits;
and the plurality of scanning lines are electrically connected with the GOA unit circuit through connecting wires arranged in the display area.
2. The array substrate of claim 1, wherein the plurality of scan lines and the plurality of data lines divide the array substrate into a plurality of pixel units, the pixel units comprise sub-pixel units, wherein each two levels of the GOA unit circuits are connected to one scan line, and the two levels of the GOA unit circuits are used for driving the sub-pixel units in a corresponding row.
3. The array substrate of claim 2, wherein the two GOA unit circuits have a width equal to that of the corresponding 3 consecutive sub-pixels on the display substrate.
4. The array substrate of claim 2, wherein the width of the GOA unit circuit is greater than the width of the sub-pixel unit along the scan line direction.
5. The array substrate according to claim 2, wherein the connecting trace is disposed at a gap between two adjacent sub-pixel units.
6. The array substrate of claim 1, wherein the connection traces are disposed in parallel and at the same layer as the data lines.
7. The array substrate according to claim 6, wherein a gate insulating layer is disposed between the scan lines and the connecting traces, and vias are disposed on the gate insulating layer, and the connecting traces are connected to the corresponding scan lines through the vias.
8. The array substrate of claim 1, wherein the array substrate comprises N scan lines and two repeated sets of the GOA unit circuits, each set of the GOA unit circuits comprising N levels of the GOA unit circuits;
the N-th-level GOA unit circuit in the first group of GOA unit circuit groups and the N-th-level GOA unit circuit in the second group of GOA unit circuit groups are connected to the same scanning line, wherein N is a positive integer, and N is a positive integer which is greater than or equal to 1 and less than or equal to N.
9. The array substrate as claimed in claim 1, wherein at least one data line is disposed between two adjacent GOA unit circuits in the fan-out region.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010156953.2A CN111243486A (en) | 2020-03-09 | 2020-03-09 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010156953.2A CN111243486A (en) | 2020-03-09 | 2020-03-09 | Array substrate and display panel |
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| CN111243486A true CN111243486A (en) | 2020-06-05 |
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| CN202010156953.2A Pending CN111243486A (en) | 2020-03-09 | 2020-03-09 | Array substrate and display panel |
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| CN111798765A (en) * | 2020-07-08 | 2020-10-20 | Tcl华星光电技术有限公司 | Preparation method of display panel and display device |
| CN111798755A (en) * | 2020-07-07 | 2020-10-20 | Tcl华星光电技术有限公司 | Display panel |
| CN112967667A (en) * | 2021-02-25 | 2021-06-15 | Tcl华星光电技术有限公司 | Display panel, driving method thereof and display device |
| CN113327516A (en) * | 2021-05-31 | 2021-08-31 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN113421896A (en) * | 2021-06-03 | 2021-09-21 | 武汉天马微电子有限公司 | Display panel and display device |
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