CN114512057A

CN114512057A - Display panel

Info

Publication number: CN114512057A
Application number: CN202210121625.8A
Authority: CN
Inventors: 许作远
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2022-02-09
Filing date: 2022-02-09
Publication date: 2022-05-17
Anticipated expiration: 2042-02-09
Also published as: CN114512057B

Abstract

The application discloses a display panel, which is provided with a display area and a non-display area arranged around the display area; the display panel comprises a substrate positioned in the display area and the non-display area, and a driving chip and a switching circuit board which are arranged on the substrate positioned in the non-display area; the substrate positioned in the non-display area comprises a first wiring group and a second wiring group which are arranged at intervals; the first routing group is directly electrically connected with the driving chip, and the second routing group is electrically connected with the driving chip through the switching circuit board. The problem that the line width of the line that walks that this application can avoid the wiring space limited to cause increases and adjacent walk and interfere mutually between the line is favorable to improving signal transmission's stability.

Description

Display panel

Technical Field

The application relates to the technical field of display, in particular to a display panel.

Background

With the technical development of the full-screen display, the screen occupation ratio of the display screen is continuously improved at present, and the lower frame of the display is smaller and smaller.

There are various ways to implement a narrow bezel in the prior art, and fig. 1 and 2 are one of many ways to implement a narrow bezel for an exemplary display panel. In the display panel 1 ' shown in fig. 1 and 2, a fan-out region 2 ' is provided with a plurality of fan-out wirings 3 ' and a plurality of Gate Driver On Array (GOA) wirings 4 ' located at two sides of the plurality of fan-out wirings 3 ', a driving chip (IC)5 ' includes a plurality of output terminals, and signal lines of a display region 6 ' are electrically connected with the output terminals through the fan-out wirings 3 ' and the GOA wirings 4 '; wherein, some fan-out wires of the fan-out wires 3 ' extend through two sides of the driving chip 5 ' to be connected with the corresponding output terminals, so that the position of the driving chip 5 ' can be integrally moved upwards, thereby realizing a narrow frame.

However, since the partial fan-out trace 3 'occupies the space on both sides of the driver chip 5', the arrangement space of the GOA trace 4 'is compressed, which results in the too thin line width and the increased impedance of the GOA trace 4', and the GOA trace 4 'interferes with the adjacent fan-out trace 3' (as shown in the dashed line frame a), which affects the stability of the electrical signal.

Therefore, improvements in the existing display panel are required to solve the above problems.

Disclosure of Invention

The application provides a display panel can avoid the limited problem of walking the line width small impedance increase and adjacent line of walking of causing of wiring space and interfering mutually between the line, is favorable to improving signal of telecommunication transmission's stability.

The application provides a display panel, which is provided with a display area and a non-display area arranged around the display area;

the display panel comprises a substrate positioned in the display area and the non-display area, and a driving chip and a switching circuit board which are arranged on the substrate positioned in the non-display area;

the substrate positioned in the non-display area comprises a first wiring group and a second wiring group which are arranged at intervals; the first routing group is directly electrically connected with the driving chip, and the second routing group is electrically connected with the driving chip through the switching circuit board.

Optionally, the non-display area includes a routing area disposed adjacent to the display area in a first direction and a binding area located on a side of the routing area away from the display area; the binding area comprises a first sub-binding area arranged close to the wiring area and a second sub-binding area arranged at an interval with the first sub-binding area;

the first routing group is located in the routing area, and one end, far away from the display area, of the first routing group extends to the first sub-binding area; the second routing group is located in the routing area, and one end, far away from the display area, of the second routing group extends to the second sub-binding area;

the driving chip is located in the first sub-bonding area and electrically connected with the first routing group located in the first sub-bonding area; the switching circuit board is electrically connected with the driving chip and the second routing group located in the second sub-binding area respectively.

Optionally, the first sub-bonding area includes a first edge close to the routing area, and a second edge and a third edge that are adjacent to and opposite to two ends of the first edge; the second sub-bonding region is located at a side of the second edge far away from the third edge and/or at a side of the third edge far away from the second edge.

Optionally, the first routing group includes a plurality of first routings arranged at intervals in sequence, and the second routing group includes a plurality of second routings arranged at intervals in sequence;

at least one first wire part of the plurality of first wires, which is close to the second wire group, is located on one side of the second edge, which is far away from the third edge, and/or is located on one side of the third edge, which is far away from the second edge.

Optionally, the binding region further includes a third sub-binding region located on a side of the first sub-binding region away from the wiring region; the transit circuit board is partially positioned in the second sub-binding area and partially positioned in the third sub-binding area;

the switching circuit board located in the third sub-bonding area is electrically connected with the driving chip, and the switching circuit board located in the second sub-bonding area is electrically connected with the second routing group located in the second sub-bonding area.

Optionally, the second sub-bonding region and the third sub-bonding region are disposed at an interval in a second direction, and the second direction is perpendicular to the first direction.

Optionally, the substrate further includes a first pad group and a second pad group located in the first sub-bonding region, a third pad group located in the second sub-bonding region, a fourth pad group located in the third sub-bonding region, and a first connecting wire group connecting the second pad group and the fourth pad group; the first wiring group is connected with the first pad group, and the second wiring group is connected with the third pad group;

the driving chip is connected with the first pad group and the second pad group in a binding mode; the switching circuit board is respectively bound and connected with the third pad group and the fourth pad group, and a second connection wiring group for connecting the third pad group and the fourth pad group is arranged in the switching circuit.

Optionally, the adapter circuit board comprises a flexible circuit board; the substrate further comprises a fifth pad group located in the first sub-bonding region and a sixth pad group located in the third sub-bonding region and electrically connected to the fifth pad group correspondingly;

the drive chip is further connected with the fifth gasket group in a binding mode, and the flexible circuit board is further connected with the sixth gasket group in a binding mode.

Optionally, the first pad group and the second pad group are oppositely disposed in the first direction, and the second pad group is disposed near the fourth pad group.

Optionally, the substrate includes a plurality of data lines and a plurality of scan lines in the display area; the first routing group is electrically connected to the plurality of data lines, and the second routing group is electrically connected to the plurality of scan lines.

According to the display panel, the wiring on the substrate is divided into the first wiring group and the second wiring group, wherein the first wiring group is directly and electrically connected with the driving chip, the second wiring group is connected to the driving chip through the switching circuit board in a switching mode, the second wiring group and the first wiring group are prevented from being directly and electrically connected with the driving chip with limited peripheral space, and therefore wiring space limitation of the second wiring group and the first wiring group is avoided, and multiple wirings with reasonable line width and space are formed; therefore, this application both can avoid walking the line impedance increase, also can avoid adjacent walk between the line interference of each other, especially can avoid being located the line of drive chip side because of the less impedance increase of the less impedance of line width that the space restriction caused and walk the less mutual interference's of interval problem between the line, be favorable to improving electrical signal transmission's stability.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of an exemplary display panel.

Fig. 2 is a partially enlarged view of the region B in fig. 1.

Fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.

Fig. 4 is a partially enlarged view of the region C in fig. 3.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically, electrically or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.

As shown in fig. 3 and 4, the present embodiment provides a display panel 1, the display panel 1 has a display area 5 and a non-display area 6 disposed around the display area 5, and the display panel 1 includes a substrate 2 located in the display area 5 and the non-display area 6, and a driver chip 3 and a relay circuit board 4 bonded (bonded) on the substrate 2 located in the non-display area 6. The substrate 2 positioned in the non-display area 6 comprises a first wiring group 11 and a second wiring group 12 which are arranged at intervals; the first wire group 11 is directly electrically connected to the driving chip 3, and the second wire group 12 is electrically connected to the driving chip 3 through the adapting circuit board 4.

Specifically, the non-display area 6 includes a routing area (e.g., a fan-out area) 7 disposed adjacent to the display area 5 in a first direction (e.g., a vertical direction) and a binding area 8 located on a side of the routing area 7 away from the display area 5. The binding region 8 includes a first sub-binding region 9 disposed adjacent to the routing region 7 and a second sub-binding region 10 disposed apart from the first sub-binding region 9. The first wiring group 11 is located in the wiring area 7, and one end far away from the display area 5 extends to the first sub-binding area 9; the second wire group 12 is located in the wire area 7, and an end far away from the display area 5 extends to the second sub-bonding area 10.

Specifically, the driving chip (IC)3 is located in the first sub-bonding region 9 and electrically connected to the first wire group 11 located in the first sub-bonding region 9; the adapting circuit board 4 is located between the driving chip 3 and the second wire group 12 and is electrically connected to the driving chip 3 and the second wire group 12 located in the second sub-bonding region 10, respectively, so that the second wire group 12 is electrically connected to the driving chip 3. It is understood that the second wire group 12 in the embodiment of the present application does not extend directly to the first sub-bonding region 9 to connect with the driving chip 3, but is connected with the driving chip 3 indirectly through the via circuit board 4. Because the second sub-bonding area 10 and the first sub-bonding area 9 are arranged at an interval, the distance between the second wire group 12 and the first wire group 11 can be increased by adjusting the position of the second sub-bonding area 10, and meanwhile, the wiring space of the first wire group 11 at two sides of the driving chip 3 is also increased, so that the problem that the wire width of the wires is limited or signal interference is generated due to too small distance between the wires is avoided.

In one embodiment, the substrate 2 further includes a plurality of data lines (not shown) located in the display region 5 and extending along a first direction, a plurality of scan lines (not shown) located in the display region 5 and extending along a second direction (perpendicular to the first direction, for example, a horizontal direction), and GOA circuits 13 located in the non-display region 6 and located at two sides of the display region 5 in the second direction. In the embodiment of the present application, the first routing group 11 is a fan-out routing line correspondingly connected to a plurality of data lines of the display area 5, and is configured to transmit data signals to the data lines; the second wire group 12 is a GOA wire electrically connected to a plurality of scan lines of the display area 5 for providing scan signals to the scan lines. Specifically, one end of the first wire group 11 away from the first sub-bonding region 9 extends to the display region 5 to be connected to the corresponding data line, and one end of the second wire group 12 away from the second sub-bonding region 10 extends to be connected to the corresponding GOA circuit 13.

It is understood that, in the above embodiment, the number of the GOA circuits 13 is 2, and correspondingly, the number of the second sub-bonding regions 10 and the number of the second routing groups 12 are also 2, and the two second routing groups 12 are located on two sides of the first routing group 11 in the second direction and are electrically connected to the two GOA circuits 13 in a one-to-one correspondence manner. Of course, in other embodiments, the number of the GOA circuits 13 may also be 1, that is, the GOA circuits 13 are disposed on any side of the display area 5 in the second direction; correspondingly, the number of the second sub-bonding regions 10 and the second routing groups 12 is also 1, and the second sub-bonding regions and the second routing groups are correspondingly electrically connected to the GOA circuit 13.

Specifically, the first sub-bonding area 9 includes a first side 14 close to the routing area 7, and a second side 15 and a third side 16 adjacent to and opposite to both ends of the first side 14. The second sub-binding region 10 is located at a side of the second edge 15 remote from the third edge 16 and/or at a side of the third edge 16 remote from the second edge 15. It can be understood that, when the number of the second routing groups 12 is 2, and two second routing groups 12 are respectively disposed at two sides of the first routing group 11, two second sub-binding regions 10 are respectively located at one side of the second edge 15 away from the third edge 16 and one side of the third edge 16 away from the second edge 15; when the number of the second routing group 12 is 1, the second sub-binding region 10 is located on the side of the second edge 15 away from the third edge 16 or on the side of the third edge 16 away from the second edge 15.

Specifically, the first routing line group 11 includes a plurality of first routing lines 17 sequentially arranged at intervals, and the second routing line group 12 includes a plurality of second routing lines 18 sequentially arranged at intervals. The part of the second wires 18 close to the second sub-bonding area 10 is located on one side of the second edge 15 away from the third edge 16 and/or on one side of the third edge 16 away from the second edge 15; at least one first trace 17 of the plurality of first traces 17 that is close to the second trace group 12 is partially located on a side of the second side 15 away from the third side 16 and/or on a side of the third side 16 away from the second side 15.

It is understood that the second routing group 12 is disposed corresponding to the second sub-bonding region 10, so that the position of the second routing group 12 is related to the position of the second sub-bonding region 10. When the number of the second routing lines 12 is 2, the plurality of second routing lines 18 in the second routing line group 12 disposed close to the second edge 15 are located on a side of the second edge 15 away from the third edge 16, and the plurality of second routing lines 18 in the second routing line group 12 disposed close to the third edge 16 are located on a side of the third edge 16 away from the third edge 16. When the number of the second routing lines 12 is 1 and the second sub-bonding region 10 is located on a side of the second edge 15 away from the third edge 16, the plurality of second routing lines 18 in the second routing line 12 are located on a side of the second edge 15 away from the third edge 16. When the number of the second routing line group 12 is 1 and the second sub-bonding region 10 is located on a side of the third edge 16 away from the second edge 15, the plurality of second routing lines 18 in the second routing line group 12 are located on a side of the third edge 16 away from the second edge 15.

Specifically, in order to implement a narrow bezel, in the embodiment of the present application, the position of the driving chip 3 (the first sub-bonding region 9) is moved toward a direction close to the display region 5, so as to compress a space between the display region 5 and the bonding region 8, so that at least one first trace 17 located at an outer position in the first trace group 11 extends from the trace region 7 to a side surface of the driving chip 3 (the first sub-bonding region 9) first, and then extends to the first sub-bonding region 9 to be electrically connected to the driving chip 3, so that a part of the at least one first trace 17 is located at the side surface of the driving chip 3 (the first sub-bonding region 9) (a side of the second side 15 away from the third side 16 and/or a side of the third side 16 away from the second side 15).

Specifically, the binding region 8 further includes a third sub-binding region 19 located on a side of the first sub-binding region 9 away from the routing region 7; the transit circuit board 4 is partially located in the second sub-bonding area 10 and partially located in the third sub-bonding area 19; the through circuit board 4 located in the third sub-bonding region 19 is electrically connected to the driving chip 3, and the through circuit board 4 located in the second sub-bonding region 10 is electrically connected to the second wire group 12 located in the second sub-bonding region 10. It is understood that the adapting circuit board 4 may be located on the substrate 2 as a whole, or may be located on the substrate 2 partially, and is not limited herein.

Specifically, the second sub-bundled region 10 and the third sub-bundled region 19 are arranged at intervals in the second direction. In a specific embodiment, two second sub-binding regions 10 are symmetrically disposed at both sides of the third sub-binding region 19. Because the second sub-bonding region 10 and the third sub-bonding region 19 are arranged close to the edge (cutting line) of the substrate 2, the second sub-bonding region 10 and the third sub-bonding region 19 are arranged at intervals along the second direction, which is beneficial to the structural design of the transfer circuit board 4 to be more regular, thereby being beneficial to the bonding operation to be more convenient and being beneficial to the improvement of the bonding effect.

Specifically, the substrate 2 includes a first pad group 20 and a second pad group 21 located in the first sub-bonding region 9, a third pad group 22 located in the second sub-bonding region 10, a fourth pad group 23 located in the third sub-bonding region 19, and a first connecting wiring group 24 connecting the second pad group 21 and the fourth pad group 23; the first wiring group 11 is connected to the first pad group 20, and the second wiring group 12 is connected to the third pad group 22; the driving chip 3 is connected with the first pad group 20 and the second pad group 21 in a binding manner; the adapting circuit board 4 is respectively bound and connected with the third pad group 22 and the fourth pad group 23, and a second connecting wiring group 25 connected with the third pad group 22 and the fourth pad group 23 is arranged in the adapting circuit.

It is understood that the second wire group 12 is electrically connected to the driving chip 3 through the second connecting wire group 25 in the through circuit and the first connecting wire group 24 connecting the second pad group 21 and the fourth pad group 23.

It should be noted that each pad group includes a plurality of pads arranged at intervals, the number of pads in the first pad group 20 is the same as the number of first traces 17 in the first trace group 11, the number of pads in the second pad group 21 is the same as the number of pads in the third pad group 22, and the number of pads is the same as the number of second traces 18 in the second trace group 12. The number of traces in the first connecting trace group 24 and the second connecting trace group 25 is the same, and the number of pads in the second pad group 21 is the same.

Specifically, the driving chip 3 includes a first output terminal group (not shown in the figure) and a second output terminal group (not shown in the figure) corresponding to the first pad group 20 and the second pad group 21, and when binding, the first output terminal group is correspondingly bound and connected to the first pad group 20, and the second output terminal group is correspondingly bound and connected to the second pad group 21. Certainly, the adapter circuit board 4 is provided with a pad group corresponding to and bonded with the third pad group 22 and the fourth pad group 23, which is not described in detail herein.

Specifically, the first pad group 20 and the second pad group 21 are oppositely arranged in the first direction, and the second pad group 21 is arranged close to the fourth pad group 23, so that the configuration is more convenient for the adapter circuit board 4 to be electrically connected with the driving chip 3.

Specifically, the adapting Circuit board 4 may be a Flexible Printed Circuit (FPC); correspondingly, the base board 2 further includes a fifth pad group 26 located in the first sub-bonding area 9, a sixth pad group 27 located in the third sub-bonding area 19, and a third connecting wire group (not shown in the figure) connecting the fifth pad group 26 and the sixth pad group 27; the driving chip 3 is also bound and connected with the fifth pad group 26, and the through circuit board 4 is also bound and connected with the sixth pad group 27.

Specifically, the portion of the adapting circuit board 4 away from the binding region 8 is electrically connected with the external circuit board. It is understood that the driving chip 3 further includes an input terminal group corresponding to the fifth pad group 26, and the relay circuit board 4 is electrically connected to the input terminal group of the driving chip 3 through the fifth pad group 26, the third connecting wire group and the sixth pad group 27, and is used for transmitting electrical signals to the driving chip 3.

It can be understood that the function of the relay circuit board 4 in the embodiment of the present application is two, one is to connect the second wire group 12 and the driving chip 3, and the other is to transmit an electrical signal to the driving chip 3.

In the embodiment of the application, on the basis of realizing the narrow lower frame, the second wire group 12 (e.g., GOA wires) is switched to the driver chip 3 through the switching circuit board 4 (e.g., FPC), so as to avoid directly extending the second wire group 12 and the first wire group 11 together to the first sub-bonding region 9 to connect with the driver chip 3, thereby avoiding the limitation of the wiring space of the second wire group 12 and the first wire group 11, being beneficial to forming a plurality of wires (such as the first wire 17 and the second wire 18) with reasonable line width and spacing in the wire area 7, avoiding the increase of the wire impedance and the interference between the adjacent wires, particularly, the problems of small line width, increased impedance and mutual interference between the wires caused by limited space of the wires on the side surface of the driving chip 3 can be avoided, and the stability of electric signal transmission in the wire routing area 7 can be improved.

The embodiment of the present application further provides a display panel, which is different from the above embodiments in that the first routing group and the second routing group are electrically connected to the plurality of data lines in the display area correspondingly. It is understood that the first wire group and the second wire group have the same function and are used for transmitting data signals.

It should be noted that, in other embodiments, the first routing line group and the second routing line group may also correspond to other signal lines in the display area, and are not limited to the specific examples described in the foregoing embodiments.

In the embodiment of the application, on the basis of realizing the narrow lower frame, the routing in the routing area is divided into a first routing group and a second routing group, wherein the first routing group directly extends to a first sub-binding area provided with a driving chip, and the second routing group is switched to the driving chip through a switching circuit board (such as an FPC), so that the second routing group and the first routing group are prevented from directly extending to the first sub-binding area together to be connected with the driving chip, and therefore, the limitation of the routing space of the second routing group and the first routing group is avoided, and the formation of a plurality of routing (such as the first routing and the second routing) with reasonable line width and spacing in the routing area is facilitated; therefore, the embodiment of the application can avoid the increase of the impedance of the wires, can also avoid the mutual interference between the adjacent wires, especially can avoid the problems that the wires on the side face of the driving chip have small impedance increase of the line width due to the limited space and the mutual interference between the wires has small space, and is favorable for improving the stability of the electric signal transmission of the wire routing area.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel provided by the embodiment of the present application is described in detail above, and a specific example is applied to illustrate the principle and the implementation manner of the present application, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel characterized by having a display area and a non-display area provided around the display area;

2. The display panel according to claim 1, wherein the non-display region includes a wiring region provided adjacent to the display region in a first direction and a binding region located on a side of the wiring region away from the display region; the binding area comprises a first sub-binding area arranged close to the wiring area and a second sub-binding area arranged at an interval with the first sub-binding area;

3. The display panel according to claim 2, wherein the first sub-bonding region comprises a first edge near the routing region, and a second edge and a third edge adjacent to and opposite to two ends of the first edge; the second sub-bonding region is located at a side of the second edge far away from the third edge and/or at a side of the third edge far away from the second edge.

4. The display panel according to claim 3, wherein the first trace group includes a plurality of first traces arranged at intervals in sequence, and the second trace group includes a plurality of second traces arranged at intervals in sequence;

5. The display panel according to claim 2, wherein the bonding region further comprises a third sub-bonding region located on a side of the first sub-bonding region away from the routing region; the transit circuit board is partially positioned in the second sub-binding area and partially positioned in the third sub-binding area;

6. The display panel according to claim 5, wherein the second sub-bonding region and the third sub-bonding region are disposed at a distance from each other in a second direction, and the second direction is perpendicular to the first direction.

7. The display panel according to claim 5, wherein the substrate further comprises a first pad group and a second pad group located in the first sub-bonding area, a third pad group located in the second sub-bonding area, a fourth pad group located in the third sub-bonding area, and a first connection wiring group connecting the second pad group and the fourth pad group; the first wiring group is connected with the first pad group, and the second wiring group is connected with the third pad group;

the driving chip is connected with the first pad group and the second pad group in a binding mode; the switching circuit board is respectively connected with the third gasket group and the fourth gasket group in a binding mode, and a second connecting wiring group connected with the third gasket group and the fourth gasket group is arranged in the switching circuit.

8. The display panel according to claim 7, wherein the relay circuit board comprises a flexible circuit board; the substrate further comprises a fifth pad group located in the first sub-bonding region and a sixth pad group located in the third sub-bonding region and electrically connected to the fifth pad group correspondingly;

9. The display panel according to claim 7, wherein the first pad group and the second pad group are disposed opposite to each other in the first direction, and wherein the second pad group is disposed adjacent to the fourth pad group.

10. The display panel according to claim 1, wherein the substrate includes a plurality of data lines and a plurality of scan lines in the display region; the first routing group is electrically connected to the plurality of data lines, and the second routing group is electrically connected to the plurality of scan lines.