CN206331214U - A kind of array base palte and display device - Google Patents
A kind of array base palte and display device Download PDFInfo
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- CN206331214U CN206331214U CN201621110569.4U CN201621110569U CN206331214U CN 206331214 U CN206331214 U CN 206331214U CN 201621110569 U CN201621110569 U CN 201621110569U CN 206331214 U CN206331214 U CN 206331214U
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- line
- array base
- base palte
- underlay substrate
- gate
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Abstract
The utility model provides a kind of array base palte and display device, and the array base palte includes：Including underlay substrate and a plurality of gate line being arranged on the underlay substrate, each the gate line includes Part I line and Part II line, the Part I line intersects and connected with corresponding Part II line, the Part I line is used to connect thin film transistor (TFT), and the Part II line is used to connect gate drivers.In the utility model, gate line is no longer a horizontal line, form is more flexible, so as to which gate drivers to be arranged to the side identical or relative with source electrode driver, i.e. the left and right sides of array base palte can be not provided with gate drivers, so as to which the frame that may be such that the display device comprising the array base palte diminishes, narrow frame is advantageously implemented.
Description
Technical field
The utility model is related to display technology field, more particularly to a kind of array base palte and display device.
Background technology
In existing liquid crystal display device, source electrode driver (Source IC) generally is set in the side of array base palte, i.e.,
DP sides, gate drivers (Gate IC or GOA), i.e. GP sides or GPO sides are set in one or both sides normal thereto.It is above-mentioned to set
Meter causes the left and right sides or side of existing liquid crystal display device to include gate drivers so that the frame of liquid crystal display device
It is relatively thick, it is unfavorable for realizing narrow frame.
Utility model content
In view of this, the utility model provides a kind of array base palte and display device, is filled with solving existing liquid crystal display
Put the problem of being unfavorable for realizing narrow frame.
In order to solve the above technical problems, the utility model provides a kind of array base palte, including underlay substrate and it is arranged at
A plurality of gate line on the underlay substrate, each gate line includes Part I line and Part II line, and described the
A part of line intersects and connected with corresponding Part II line, and the Part I line is used to connect thin film transistor (TFT), and described the
Two partial lines are used to connect gate drivers.
Preferably, the array base palte also includes：It is arranged at a plurality of data lines on the underlay substrate, described first
Separated time and the data wire transposition insulator are set.
Preferably, orthographic projection of the Part II line with the data wire on the underlay substrate be not overlapping.
Preferably, the Part II line be arranged in parallel with the data wire.
Preferably, in a plurality of Part II line, the Part II line of intermediate region is connected to away from the grid
The Part I line of driver side, from intermediate region to the direction of both sides, the length of the Part II line is successively
Successively decrease.
Preferably, the region division of the Part II line will be set for left field and right side area, wherein, even number
The corresponding Part II line of row Part I line is respectively positioned on left field, the corresponding Part II of odd-numbered line Part I line
Line is respectively positioned on right side area.
Preferably, the underlay substrate includes the first area close to the first side of the underlay substrate, described first
Region is non-display area, for setting the gate drivers.
Preferably, at least two jiaos of the underlay substrate are acute angle or obtuse angle.
Preferably, the Part II line is set with the data wire with layer with material.
The utility model also provides a kind of display device, including above-mentioned array base palte.
Above-mentioned technical proposal of the present utility model has the beneficial effect that：
Each gate line include with the Part I line and Part II line that intersect and be connected, Part I line be used for it is thin
Film transistor is connected, and Part II line is used to be connected with gate drivers, and Part II line can receive grid from gate drivers
Scanning signal, and by gated sweep signal transmission to Part I line, and it is transferred to corresponding film crystal from Part I line
The gate electrode of pipe, so as to realize the function of normal gate line.In addition, gate line is no longer a parallel lines, form is cleverer
It is living, so as to which gate drivers are arranged at and source electrode driver identical side or relative side, i.e. array base palte
The left and right sides can be not provided with gate drivers, so as to may be such that the frame of the display device comprising the array base palte diminishes, have
Beneficial to realizing narrow frame.
Brief description of the drawings
Fig. 1 is the structural representation of the array base palte of the utility model embodiment one；
Fig. 2 is the damaged one jiao schematic diagram of the array base palte of the utility model embodiment one；
Fig. 3 is the structural representation of the array base palte of the utility model embodiment two；
Fig. 4 is the gate line of the embodiment of the utility model one and the structural representation of data wire；
Fig. 5 is the structural representation of the GOA circuits of the embodiment of the utility model one；
Fig. 6 be Fig. 5 in GOA circuits cascade connection structural representation.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.With
Lower embodiment is used to illustrate the utility model, but is not limited to scope of the present utility model.
To solve the problem of existing liquid crystal display device is unfavorable for realizing narrow frame, the utility model embodiment provides one
Kind of array base palte, including underlay substrate and a plurality of gate line that is arranged on the underlay substrate, each gate line
Including Part I line and Part II line, the Part I line intersects and connected with corresponding Part II line, and described
A part of line is used to connect thin film transistor (TFT), and the Part II line is used to connect gate drivers.
In the utility model embodiment, each gate line includes the Part I line and Part II with intersecting and being connected
Line, Part I line is used to be connected with thin film transistor (TFT), and Part II line is used to be connected with gate drivers, and Part II line can
Grid scanning signal is received from gate drivers, and by gated sweep signal transmission to Part I line, and from Part I line
The gate electrode of corresponding thin film transistor (TFT) is transferred to, so as to realize the function of normal gate line.
In addition, gate line is no longer a parallel lines, form is more flexible, so as to which gate drivers are arranged at and source
Driver identical side or the left and right sides of relative side, i.e. array base palte can be not provided with gate drivers, from
And may be such that the frame of the display device comprising the array base palte diminishes, it is advantageously implemented narrow frame.
Array base palte in the utility model embodiment can also include：It is arranged at many datas on the underlay substrate
Line.
Preferably, the Part I line and the data wire transposition insulator are set.
In some embodiments of the present utility model, the Part II line is with the data wire on the underlay substrate
Orthographic projection it is not overlapping.For example, the Part II line be arranged in parallel or is arranged substantially in parallel with the data wire.Now, institute
Stating Part II line can be with the data line bit in same layer, it is of course also possible to be located at different layers.
In other embodiments of the present utility model, the Part II line is with the data wire in the underlay substrate
On orthographic projection can also be overlapping, certainly, now, the Part II line and the data line bit are in different layers.
In a preferred embodiment of the present utility model, the data wire is parallel with the Part II line, and extension side
To for longitudinal direction, the Part I line and the data wire are vertically insulated arranged in a crossed manner, the bearing of trend of the Part I line
For transverse direction.
Certainly, in some other embodiment of the present utility model, data wire, Part I line and Part II line also may be used
Think other bearing of trends.
In some embodiments of the utility model embodiment, the underlay substrate can be included close to the underlay substrate
First side first area, the first area be non-display area, for setting the gate drivers.
Preferably, source electrode driver can also be arranged in the first area, or, it is disposed in proximity to the substrate base
In the second area of the second side of plate, the second side is the side relative with the first side, i.e., by raster data model
Device is arranged at can be not provided with grid with source electrode driver identical side or relative side, the left and right sides of array base palte
Driver, so as to may be such that the frame of the display device comprising the array base palte diminishes, is advantageously implemented narrow frame.
Under normal circumstances, the first area for setting gate drivers is usually the upside or downside of underlay substrate.
Fig. 1 is refer to, Fig. 1 is the structural representation of the array base palte of the utility model embodiment one, the utility model reality
Applying the array base palte of example includes underlay substrate 101 and a plurality of gate line 102 being arranged on the underlay substrate 101 and a plurality of
Data wire (not shown), each gate line 102 includes the Part I line 1021 and Part II line for intersecting and connecting
1022, the Part I line 1021 and the data wire square crossing insulation set, the Part II line 1022 with it is described
Data wire be arranged in parallel, and the Part I line 1021 is used to be connected with thin film transistor (TFT), and the Part II line 1022 is used for
Connect gate drivers (i.e. GOA1-GOA28 in Fig. 1).
In the utility model embodiment, the bearing of trend of data wire is longitudinal direction, the extension side of the Part I line 1021
Arranged in a crossed manner with data wire to for transverse direction, the bearing of trend of the Part II line 1022 is longitudinal direction, parallel with data wire to set
Put.
From figure 1 it appears that in the utility model embodiment, underlay substrate 101 longitudinal side (upside or under
Side) set source electrode driver, meanwhile, by gate drivers be arranged at underlay substrate 101 be used for the source electrode driver is set
Side (in the present embodiment be downside).
Certainly, in other embodiments, gate drivers can also be arranged to the described for setting of underlay substrate 101
The relative side in the side of source electrode driver (i.e. upside).
That is, certain side (upside or downside) that can be on the longitudinal direction of underlay substrate sets gate drivers, from without
The one or both sides (i.e. left side or right side) being arranged at gate drivers on the horizontal direction of underlay substrate are needed, bag is may be such that
The frame of the display device of the array base palte of the embodiment containing the utility model diminishes, and is advantageously implemented narrow frame.
In the utility model embodiment, the Part II line 1022 of a plurality of gate line 102 on the underlay substrate 101
Length is differed.
Certainly, can also be by the length of a plurality of Part II line 1022 in some other embodiment of the present utility model
It is designed as identical so that the overall length of each gate line 102 is identical, and resistance is also identical, so that the letter of each gate line 102
Number transmission time is also identical.
In the utility model embodiment, in a plurality of Part II line 1022, the Part II line of intermediate region is connected to far
From the Part I line 1021 of gate drivers side, from intermediate region to the direction of both sides, the length of Part II line 1022
Successively decrease successively.
In the utility model embodiment, the region division of the Part II line 1022 will be set for left field and right side
Region, wherein, the corresponding Part II line 1022 of even number line Part I line 1021 is respectively positioned on left field, odd-numbered line
The corresponding Part II line 1022 of a part of line 1021 is respectively positioned on right side area.And, in the left field, from left side to the right
On the direction of side extension, the numbering of the corresponding gate line of the Part II line 1022 diminishes successively, in the left and right side region,
From the direction that right side extends to the left, the numbering of the corresponding gate line of the Part II line 1022 diminishes successively.That is, first
The Part II line 1022 of bar gate line is located at intermediate region, be the 2nd successively to the left, 4,6 ... the second of 28 articles of gate lines
Partial line 1022 is the 3rd successively to the right, the Part II line 1022 of 5,7 ... 27 articles of gate lines.From figure 1 it appears that
The distribution of whole Part II line 1022 is triangular in shape.
Certainly, in some other embodiment of the present utility model, the Part II line 1022 can also set for other
Put mode.
The design of gate line in above-described embodiment so that a certain angle breakage (refer to when the upside of array base palte
Fig. 2) or when the angle of upside two is damaged, though positioned at some Part I line parts against wear of array base palte upper-side area,
The display of whole display device is not interfered with.
Furthermore it is also possible to which by the upside of array base palte, one or two angle is cut or rounding, to form irregular array
Substrate.
Fig. 3 is refer to, Fig. 3 is the structural representation of the gate line of the utility model embodiment two, the utility model implementation
Example and the difference of the embodiment shown in Fig. 1 are：Underlay substrate 101 in the utility model embodiment is non-rectangle substrate base
Plate.Two angles of the upside of underlay substrate 101 are acute angle or obtuse angle.
The underlay substrate 101 includes the first area 1011 close to the first side of the underlay substrate 101, described the
One side is parallel with the bearing of trend of the Part I line 1021, and the first area 1011 is non-display area, for setting
Put the gate drivers.
The underlay substrate 101 also includes the second area 1012 close to the second side of the underlay substrate 102, described
Second side is relative with the first side, and the second area 1012 is trapezoid area.
It is less than positioned at the length of the Part I line 1021 of the second area 1012 and is located at the underlay substrate 101
Other regions the Part I line 1021 length.
In the second area 1012, on the direction away from the first area 1011, the Part I line 1021
Length be gradually reduced.
The not traditional rectangle of array base palte in the utility model embodiment, so that liquid crystal display device
Shape more flexibility.
In above-described embodiment embodiment, it is preferable that refer to Fig. 4, Part II line 1022 and the data wire 103 of gate line
Set with layer with material, the Part II line 1022 can be formed with the data wire 103 by patterning processes successively, so as to save
Save manufacture craft.In addition, Part II line 1022 is connected by via 1023 with corresponding Part I line 1021, so that by grid
The signal transmission of driver is to Part I line 1021.
Fig. 5 is refer to, Fig. 5 is the structural representation of the GOA circuits of the embodiment of the utility model one, the gate drivers bag
Thin film transistor (TFT) M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11 and electric capacity C1 are included, wherein, M1 effect is PU preliminary fillings
Electricity, M2 effect is that PU resets, and M3 effect is PU bootstrappings and GOA outputs, and M4 effect is that GOA is put in Blanking Area
Electricity, M5 effect is PD chargings, and M6 effect is PD electric discharges, and M8 effect is PD_CN electric discharges, and M9 effect is PD_CN chargings,
M10 effect is nonselection mode PU noise reductions, and M11 effect is nonselection mode OUTPUT noise reductions, and C1 effect is to stablize PU
Current potential, aids in noise reduction.
It refer to Fig. 6, Fig. 6 is the cascade connection structural representation of the GOA circuits in Fig. 5.
The operation principle of above-mentioned GOA circuits is as follows：
Stage one：Charging stage
OUTPUT (n-2) inputs open M1 to INPUT (n), and PU is charged to VGH.M6 and M8, PD_CN quilt are opened simultaneously
0V or so is pulled low to, PD is pulled low to -8V or so.
Stage two：The output stage
Before the output stage starts, PU has been pulled up to VGH, now because CLK from VGL is changed into VGH, in electric capacity C1 work
Under, PU points are booted to the current potential higher than VGH, three M3 is substantially more opened, CLK signal is exported to OUTPUT.
INPUT (n+2) receives OUTPUT (n) signals, and (n+2) unit enters the charging stage.Now M6＆M8 is opened also more fully, PD_
CN is further pulled low to -4V or so, PD holdings -8V.
Stage three：Discharge regime
CLK is changed into after low level, and the output stage terminates, but now PU is still VGH, and M3 remains unchanged opening, OUTPUT current potential quilts
It is pulled low to VGL.Now M6＆M8 is still opened, and PD_CN returns back to 0V or so, PD holdings -8V.
Stage four：Reseting stage
OUTPUT (n+2) inputs are opened to RESET (n), M2, and PU current potentials are reduced to VGL.Now M6＆M8 is turned off, and VDD leads to
M9＆M5 is crossed by PD voltage boosts to VGH, M10 and M11, PU and OUTPUT electric discharges is opened.
Stage five：The holding stage
During nonselection mode, PU keeps low potential, and M6＆M8 is persistently turned off, and PD keeps high potential, and M10 and M11 are opened, held
Continue for PU and OUTPUT electric discharges.
The utility model embodiment also provides a kind of display device, including above-mentioned array base palte.
In some embodiments of the present utility model, the display device also includes：Gate drivers, are arranged at the lining
The first area of the first side of the close underlay substrate of substrate.
The above is preferred embodiment of the present utility model, it is noted that for the ordinary skill of the art
For personnel, on the premise of principle described in the utility model is not departed from, some improvements and modifications can also be made, these improvement
Protection domain of the present utility model is also should be regarded as with retouching.
Claims (9)
1. a kind of array base palte, it is characterised in that including underlay substrate and a plurality of grid being arranged on the underlay substrate
Line, each gate line includes Part I line and Part II line, the Part I line and corresponding Part II
Line intersects and connected, and the Part I line is used to connect thin film transistor (TFT), and the Part II line is used to connect raster data model
Device；
The array base palte also includes：It is arranged at a plurality of data lines on the underlay substrate, the Part I line and described
Data wire transposition insulator is set.
2. array base palte according to claim 1, it is characterised in that the Part II line is with the data wire described
Orthographic projection on underlay substrate is not overlapping.
3. array base palte according to claim 2, it is characterised in that the Part II line is parallel with the data wire to be set
Put.
4. array base palte according to claim 1, it is characterised in that in a plurality of Part II line, intermediate region
The Part II line is connected to the Part I line away from the gate drivers side, from intermediate region to both sides
Direction, the length of the Part II line is successively decreased successively.
5. array base palte according to claim 4, it is characterised in that be by the region division for setting the Part II line
Left field and right side area, wherein, the corresponding Part II line of even number line Part I line is respectively positioned on left field, and is strange
The corresponding Part II line of several rows of Part I lines is respectively positioned on right side area.
6. array base palte according to claim 1, it is characterised in that the underlay substrate is included close to the underlay substrate
First side first area, the first area be non-display area, for setting the gate drivers.
7. array base palte according to claim 1, it is characterised in that at least two jiaos of the underlay substrate be acute angle or
Obtuse angle.
8. the array base palte according to Claims 2 or 3, it is characterised in that the Part II line and the data wire are same
Layer is set with material.
9. a kind of display device, it is characterised in that including the array base palte as described in claim any one of 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621110569.4U CN206331214U (en) | 2016-10-10 | 2016-10-10 | A kind of array base palte and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621110569.4U CN206331214U (en) | 2016-10-10 | 2016-10-10 | A kind of array base palte and display device |
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| Publication Number | Publication Date |
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| CN206331214U true CN206331214U (en) | 2017-07-14 |
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| CN201621110569.4U Active CN206331214U (en) | 2016-10-10 | 2016-10-10 | A kind of array base palte and display device |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108037618A (en) * | 2018-01-02 | 2018-05-15 | 厦门天马微电子有限公司 | A kind of backlight module and liquid crystal display device |
| CN108153012A (en) * | 2018-01-10 | 2018-06-12 | 广东欧珀移动通信有限公司 | Display screen, the processing method of display screen and electronic equipment |
| CN109192121A (en) * | 2018-09-28 | 2019-01-11 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111243486A (en) * | 2020-03-09 | 2020-06-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| CN111583849A (en) * | 2020-05-19 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112255852A (en) * | 2020-10-23 | 2021-01-22 | 深圳市华星光电半导体显示技术有限公司 | Display device and light-emitting panel |
| CN112820246A (en) * | 2021-01-04 | 2021-05-18 | Tcl华星光电技术有限公司 | TFT array substrate |
| WO2021203563A1 (en) * | 2020-04-08 | 2021-10-14 | Tcl华星光电技术有限公司 | Display panel |
| US11404449B2 (en) | 2020-04-08 | 2022-08-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel |
-
2016
- 2016-10-10 CN CN201621110569.4U patent/CN206331214U/en active Active
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108037618A (en) * | 2018-01-02 | 2018-05-15 | 厦门天马微电子有限公司 | A kind of backlight module and liquid crystal display device |
| CN108153012A (en) * | 2018-01-10 | 2018-06-12 | 广东欧珀移动通信有限公司 | Display screen, the processing method of display screen and electronic equipment |
| CN109192121A (en) * | 2018-09-28 | 2019-01-11 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109192121B (en) * | 2018-09-28 | 2021-09-28 | 武汉天马微电子有限公司 | Display panel and display device |
| CN111243486A (en) * | 2020-03-09 | 2020-06-05 | Tcl华星光电技术有限公司 | Array substrate and display panel |
| WO2021203563A1 (en) * | 2020-04-08 | 2021-10-14 | Tcl华星光电技术有限公司 | Display panel |
| US11404449B2 (en) | 2020-04-08 | 2022-08-02 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel |
| CN111583849A (en) * | 2020-05-19 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112255852A (en) * | 2020-10-23 | 2021-01-22 | 深圳市华星光电半导体显示技术有限公司 | Display device and light-emitting panel |
| CN112820246A (en) * | 2021-01-04 | 2021-05-18 | Tcl华星光电技术有限公司 | TFT array substrate |
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