CN112863448A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN112863448A CN112863448A CN202110031710.0A CN202110031710A CN112863448A CN 112863448 A CN112863448 A CN 112863448A CN 202110031710 A CN202110031710 A CN 202110031710A CN 112863448 A CN112863448 A CN 112863448A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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Abstract
The application provides a display panel and display device, display panel includes display area and frame district, and the frame district sets up around the display area, and the display area includes the pixel circuit that a plurality of arrays were arranged, and the frame district includes drive circuit system, and drive circuit system includes first grid drive circuit and first light control circuit. The first grid drive circuit unit is coupled to the pixel circuit in a bilateral drive mode; the first light-emitting control circuit unit is coupled to the pixel circuits in a manner of driving the corresponding pixel circuits in one row on a single side or in a manner of driving the corresponding pixel circuits in multiple rows on a double side. The display panel and the display device have a narrow frame effect.
Description
Technical Field
The application relates to the technical field of display panels, in particular to a display panel and a display device.
Background
An organic light emitting diode display panel (OLED) is a self-luminous display device, which does not require a separate light source and has a small thickness and weight, unlike a Liquid Crystal Display (LCD), and in addition, attracts attention as a next-generation display device of a portable electronic display since it exhibits high quality characteristics such as low power consumption, high brightness, and short response time.
An AMOLED panel based on a low-temperature polysilicon technology has the advantages that a Thin Film Transistor (Transistor or TFT for short) of a driving panel has high mobility, so that the integration of a GOA circuit is facilitated, however, a P-type low-temperature polysilicon TFT (holes are majority carriers) has a fatal weakness that leakage current is high, and particularly Flicker (Flicker) is serious in low-frequency display; the N-type metal oxide TFT (electron is a majority carrier) can just make up the deficiency of low-temperature polysilicon, and the N-type metal oxide TFT and the electron are combined to fully utilize the respective advantages of the low-temperature polysilicon. Therefore, a pixel driving circuit having P-type TFTs and N-type TFTs has been developed on the AMOLED panel, and for example, one pixel driving circuit includes N-type switching control TFTs, P-type switching control TFTs, and P-type emission control TFTs.
As shown in fig. 1, this, however, complicates the driving circuitry of the pixel circuit of the AMOLED panel, and requires a conventional gate driving circuit to generate a gate driving signal to drive the P-type switching control TFT and the N-type switching control TFT, and a light Emission control circuit to provide a light Emission control signal (EM signal), by which a duty driving method can be implemented. As shown in fig. 1, the display panel includes a display area AA and a frame area BB, the first frame area BB1 includes a first conventional gate driving circuit (GOA circuit) 21N, a second conventional gate driving circuit 22P and a light emission control driving circuit 23E, and the second frame area BB2 also includes the first conventional gate driving circuit (GOA circuit) 21N, the second conventional gate driving circuit 22P and the light emission control driving circuit 23E.
As shown in fig. 1, the conventional gate driving circuit and the light-emitting driving control circuit are both driven in a manner of bilateral driving corresponding to one row of pixel circuits, which results in that the conventional gate driving circuit unit and the light-emitting driving control circuit unit occupy too much width on the layout of the layout, resulting in an increase in the frame of the AMOLED panel.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can realize the narrow frame of an AMOLED panel when various driving circuits in a frame area provide various driving signals.
The application provides a display panel, including display area and frame district, the frame district centers on the display area sets up, the display area includes the pixel circuit that a plurality of arrays were arranged, the frame district includes drive circuit system, drive circuit system includes:
the first grid driving circuit comprises a plurality of first grid driving circuit units which are arranged in a cascade mode, the first grid driving circuit is used for generating a first grid driving signal, and the first grid driving circuit units are coupled to the pixel circuit in a bilateral driving mode;
a first light emission control circuit including a plurality of cascade-arranged first light emission control circuit units for generating a first light emission control signal, the first light emission control circuit units being coupled to the pixel circuits in such a manner that the pixel circuits corresponding to one row are driven on one side or the pixel circuits corresponding to a plurality of rows are driven on two sides.
In the display panel of the application, the frame area comprises a first frame area and a second frame area which are opposite and positioned at two sides of the display area;
the first grid driving circuit is arranged in the first frame area and the second frame area;
the first light emission control circuit is disposed in at least one area of the first and second bezel areas, and is coupled to the pixel circuits of a corresponding row by bilaterally driving the corresponding rows of the pixel circuits when the first light emission control circuit is disposed in the first and second bezel areas.
In the display panel of the present application, the driving circuit system further includes a second gate driving circuit, where the second gate driving circuit includes a plurality of second gate driving circuit units arranged in a cascade manner, the second gate driving circuit units are configured to generate a second gate driving signal, the second gate driving circuit is disposed in at least one region of the first frame region and the second frame region, and the second gate driving circuit is coupled to the pixel circuits in the corresponding row;
the pixel circuit comprises at least one N-type switch control TFT, at least one P-type switch control TFT and at least one P-type light-emitting control TFT;
the first gate driving circuit unit is coupled to the corresponding N-type switch control TFT in the pixel circuit of the corresponding row;
the second gate driving circuit unit is coupled to the corresponding P-type switch control TFT in the pixel circuit of the corresponding row;
the first light emission control circuit unit is coupled to the corresponding P-type light emission control TFT in the pixel circuit of the corresponding row.
In the display panel of the present application, the first light emission control circuit is disposed in the first frame region, and the second gate driving circuit is disposed in the second frame region;
the second grid drive circuit unit is coupled to the pixel circuits in a mode of driving the pixel circuits in a corresponding row in a single side mode;
the first light emitting control circuit unit is coupled to the pixel circuits in a manner of unilaterally driving the pixel circuits in a corresponding row.
In the display panel of the present application, the first light emission control circuit is disposed in the first frame region and the second frame region;
the second grid driving circuit is arranged in the first frame area and the second frame area;
the width of the first light-emitting control circuit unit or/and the second grid drive circuit unit on the layout is smaller than that of the first grid drive circuit unit on the layout.
In the display panel of the present application, the second gate driving circuit unit is coupled to the pixel circuits by bilateral driving corresponding rows of the pixel circuits; or/and
the first light emission control circuit unit is coupled to the pixel circuits by bilaterally driving corresponding rows of the pixel circuits.
In the display panel of the application, the frame area comprises a first frame area and a second frame area which are opposite and positioned at two sides of the display area;
the first light-emitting control circuit is arranged in the first frame area and the second frame area and is coupled to the pixel circuits of the corresponding row in a mode of bilateral driving the pixel circuits of the corresponding rows;
the driving circuit system further includes a second light-emitting control circuit, the second light-emitting control circuit includes a plurality of second light-emitting control circuit units arranged in a cascade manner, the second light-emitting control circuit is disposed in the first frame region and the second frame region, the second light-emitting control circuit units are coupled to the pixel circuits in a manner of bilateral driving corresponding to a plurality of rows of the pixel circuits, and the second light-emitting control circuit is configured to generate a second gate driving signal.
In the display panel of the present application, the widths of the first light-emitting control circuit unit and the second light-emitting control circuit unit on the layout are smaller than the width of the first gate driving circuit unit on the layout.
In the display panel of the present application, the pixel circuit includes at least one N-type switching control TFT, at least one P-type emission control TFT;
the first gate driving circuit unit is coupled to the corresponding P-type switch control TFT in the corresponding row of the pixel circuits;
the first light emission control circuit unit is coupled to corresponding P-type light emission control TFTs in corresponding rows of the pixel circuits;
the second light emission control circuit unit is coupled to the corresponding N-type switch control TFTs in the corresponding rows of the pixel circuits.
The application also provides a display device which comprises any one of the display panels.
The beneficial effect of this application does: by selectively and optimally setting the second gate driving circuit or/and the first light-emitting control circuit, even including the second light-emitting control circuit, the frame width of the AMOLED panel is reduced, and the AMOLED panel has a narrow frame effect.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a prior art display panel driving circuitry provided herein;
FIG. 2 is a schematic diagram of a pixel circuit of a display panel according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a driving timing sequence of a pixel circuit of a display panel according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of a display panel driving circuit system according to an embodiment of the present application;
fig. 5 is a schematic diagram of a display panel driving circuit system according to an embodiment of the present application;
fig. 6 is a schematic diagram of a display panel driving circuit system according to an embodiment of the present application;
FIG. 7 is a diagram illustrating a display panel driving circuit system according to an embodiment of the present application;
fig. 8 is a schematic diagram of a display panel driving circuit system according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 2, a pixel circuit of an AMOLED panel is illustrated in an embodiment of the present application. The pixel circuit 11 includes a first driving transistor T1 (referred to as a first transistor or a first TFT), a first data transfer transistor T2 (referred to as a second transistor or a second TFT), a first compensation transistor T3 (referred to as a third transistor or a third TFT), a first initialization transistor T4 (referred to as a fourth transistor or a fourth TFT), a first light emission control transistor T5 (referred to as a fifth transistor or a fifth TFT), a second light emission control transistor T6 (referred to as a sixth transistor or a sixth TFT), a first bypass transistor T7 (referred to as a seventh transistor or a seventh TFT), and a storage capacitor C1. The following illustrates more detailed connections and driving relationships of embodiments of the present application. A source and a drain of the third transistor T3 are respectively connected to a point of a gate Q1 and a point of a drain B1 of the first transistor T1, one end of a source and a drain of the fourth transistor T4 are connected to an initialization signal input terminal, the other end of the fourth transistor T4 is connected to a point of a gate Q1 of the first transistor T1, one end of a source and a drain of the seventh transistor T7 are connected to the initialization signal input terminal, the other end of the seventh transistor T1 is connected to an anode of the pixel D1, one end of a source and a drain of the second transistor T2 are connected to the first Data signal input terminal Data1, the other end of the second transistor T3684 is connected to a point of a source a1 of the first transistor T1, one end of a source and a drain of the fifth transistor T5 is connected to an input terminal of the first power supply voltage Vdd, the other end of the second transistor T1 is connected to a point of a source a1, one end of a source and a drain of the sixth transistor T6 is connected to a point of a drain B58; the whole circuit has a structure of 7T 1C. The pixel D1 also includes a cathode opposite the anode that is coupled to a cathode signal VSS.
Specifically, as shown in fig. 3, which illustrates the light emitting driving timing of the pixel circuit, the operation of the pixel circuit is divided into an initialization phase t1, a compensation phase t2, and a light emitting phase t 3.
In the initialization stage T1, since the first gate driving signal Scan1 is inputted, the fourth transistor T4 is turned on at this stage, the point Q1 of the gate of the first transistor T1 is written into the signal VI at the initialization signal input terminal, and the first transistor T1 is turned on.
In the compensation phase T2, due to the input of the second gate driving signal Scan2 and the third gate driving signal Scan3, the second transistor T2 is turned on, the signal Data1 at the first Data signal input terminal is written into a point a1, since the storage capacitor C1 holds the voltage at the point Q1, the first transistor T1 is still in AN on state, and at the same time the third transistor T3 is turned on, so the signal Data1 at the first Data signal input terminal is written into a point Q1, the voltage at the point Q1 is raised from a low potential to a critical value voltage which just turns on the first transistor T1, and then the voltage is held by the storage capacitor C1, at which time the seventh transistor T7 is turned on, and the signal at the initialization signal input terminal initializes the anode AN1 of the first light emitting pixel D1.
In the light emitting period T3, the first transistor T1 is still in an on state, the fifth transistor T5 and the sixth transistor T6 are turned on in the first pixel driving circuit 11 due to the input of the light emitting control signal EM, so that the light emitting pixel D1 emits light, the voltage stability of the point Q1 determines the light emitting stability of the first light emitting pixel D1 due to the input of the light emitting control signal EM, the third transistor T3 may be an oxide transistor, and the influence of the point B1 on the voltage of the point Q1 is reduced as much as possible by using the low leakage current characteristic of the oxide transistor; the point Q1 is also connected to the source of the fourth transistor T4, and the fourth transistor T4 may be an oxide transistor, which utilizes the low leakage current characteristic of the oxide transistor to minimize the influence of the signal at the initialization signal input terminal on the voltage at the point Q1. The third transistor T3 and the fourth transistor T4 are transistors of oxide semiconductors, and the voltage stability of the Q1 point can be increased by using the low leakage current characteristics of the oxide transistors, so that the light emitting stability of the light emitting pixel D1 is improved, and the display panel 100 has a more stable display effect.
Specifically, among the 7 transistors, T1, T2, T5, T6, and T7 are P-type transistors, and T3 and T4 are N-type transistors. In detail, among the 7 transistors, T1, T2, T5, T6, and T7 are polysilicon transistors, and T3 and T4 are metal oxide transistors.
In the present application, the Transistor and the TFT are both Thin Film transistors (Thin Film transistors)
In the above embodiment, the pixel circuit of the AMOLED panel is exemplified by the pixel circuit of 7T1C, but the pixel circuit of the AMOLED panel is not limited thereto, and for example, the pixel circuit may be the pixel circuit of 7T2C, and may be the pixel circuit of 5T1C, as long as the pixel circuit includes at least one N-type switch control TFT, at least one P-type switch control TFT, and at least one P-type emission control TFT. In fig. 2, the fifth transistor T5 and the sixth transistor T6 are P-type light emission control TFTs, the second transistor T2 and the seventh transistor T7 are P-type switching control TFTs, and the third transistor T3 and the fourth transistor T4 are N-type switching control TFTs.
The following describes an exemplary embodiment of a driving circuit system for providing a driving signal of an N-type switching control TFT, a driving signal of a P-type switching control TFT, and a driving signal of a P-type emission control TFT to a pixel circuit of an AMOLED panel according to the present application.
Example one
Referring to fig. 4 to 8, an embodiment of the present application provides a display panel 100, where the display panel 100 includes a display area AA and a frame area BB, the frame area BB is disposed around the display area AA, the display area AA includes a plurality of pixel circuits 11 arranged in an array, the frame area BB includes a driving circuit system 230, and the driving circuit system 230 includes a first gate driving circuit (21N or 51P) and a first light emitting control circuit (23E or 53E).
The first gate driving circuit (21N or 51P) comprises a plurality of first gate driving circuit units which are arranged in a cascade mode, the first gate driving circuit units are used for generating first gate driving signals, and the first gate driving circuit units are coupled to the pixel circuits in a bilateral driving mode.
The first light emission control circuit (23E or 53E) comprises a plurality of first light emission control circuit units which are arranged in a cascade mode, the first light emission control circuit units are used for generating first light emission control signals, and the first light emission control circuit units are coupled to the pixel circuits in a mode of driving the pixel circuits corresponding to one row in a single-side mode or driving the pixel circuits corresponding to a plurality of rows in a double-side mode.
Specifically, the double-side driving means a mode of simultaneously transmitting corresponding driving signals from both ends of the wire, and the single-side driving means a mode of transmitting corresponding driving signals from one end of the wire. The manner of driving the corresponding one row of pixel circuits in a single side is a manner of transmitting a driving signal from one end of the corresponding one row of pixel circuits, and the manner of driving the corresponding multiple rows of pixel circuits in a double side is a manner of transmitting the driving signal from both ends of at least two rows of wirings of the corresponding at least two rows of pixel circuits at the same time.
In the embodiment of the application, the first light emitting control circuit unit is coupled to the pixel circuits in a manner of driving the corresponding pixel circuits in one row in a single-sided manner or driving the corresponding pixel circuits in multiple rows in a double-sided manner, so that the frame width of the AMOLED panel can be reduced, and the effect of a narrow frame is achieved.
Example two
Referring to fig. 4, the second embodiment of the present application is further described in detail based on the first embodiment.
The display panel 100 includes a display area AA and a frame area BB, and the frame area BB includes a first frame area BB1 and a second frame area BB2 located at two opposite sides of the display area.
The driving circuit system 230 further includes a second gate driving circuit 22P, the second gate driving circuit 22P includes a plurality of second gate driving circuit units arranged in a cascade, the second gate driving circuit units are configured to generate a second gate driving signal, the second gate driving circuit 22P is disposed in one of the first frame area BB1 and the second frame area BB2, and the second gate driving circuit 22P is coupled to the pixel circuits in the corresponding row.
Specifically, the first gate driving circuit 21N is disposed in the first frame region and the second frame region; the first light emission control circuit 23E is provided in the first frame area BB1, and the second gate driver circuit 22P is provided in the second frame area BB 2. The second gate driving circuit 22P and the first light-emitting control circuit 23E are not disposed in the same region of the first frame region BB1 and the second frame region BB2, for example, if the first light-emitting control circuit 23E is disposed in the second frame region BB2, the second gate driving circuit 22P is disposed in the first frame region BB 1.
The first gate driving circuit unit is coupled to the pixel circuits in the opposite row in a bilateral driving manner, and at this time, optionally, the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to one row of pixel circuits, or the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to at least two rows of pixel circuits. Preferably, the first gate driving circuit unit may be coupled to the pixel circuits by bilateral driving corresponding to a row of the pixel circuits, so as to provide the pixel circuits with more excellent driving capability.
Specifically, the second gate driving circuit unit is coupled to the pixel circuits by one-side driving the corresponding row of pixel circuits. The first light emitting control circuit unit is coupled to the pixel circuits in a manner of unilaterally driving the corresponding row of pixel circuits. The first gate driving circuit, the second gate driving circuit and the first light emitting control circuit all include a plurality of circuit units arranged in a cascade, and each circuit unit can provide corresponding driving signals required by all rows of pixels of the display panel 100.
The pixel circuit comprises at least one N-type switch control transistor, at least one P-type switch control TFT and at least one P-type light-emitting control TFT; the first grid drive circuit unit is coupled to the corresponding N-type switch control TFT in the pixel circuit of the corresponding row; the second grid drive circuit unit is coupled to the corresponding P-type switch control TFT in the pixel circuit of the corresponding row; the first light emission control circuit unit is coupled to the corresponding P-type light emission control TFT in the pixel circuit of the corresponding row.
When the driving circuitry 230 in the present embodiment corresponds to the pixel circuit in fig. 2, the first gate driving circuit 21N may be provided with a first gate signal Scan1 for controlling the on and off states of the N-type fourth transistor T4 (switching transistor); the second gate driving circuit 22P provides a second gate driving signal Scan2 for controlling the on and off states of the P-type second transistor T2 (switching transistor); the first light emission control circuit 23E supplies a first light emission control signal EM for controlling on and off states of the fifth transistor T5 and the sixth transistor T6 (light emission control transistors) of the P-type.
In the embodiment of the present application, the first light-emitting control circuit 23E is disposed in the first frame area BB1, the second gate driving circuit 22P is disposed in the second frame area BB2, the second gate driving circuit unit is coupled to the pixel circuits in a manner of driving a corresponding row of pixel circuits on a single side, and the first light-emitting control circuit unit is coupled to the pixel circuits in a manner of driving a corresponding row of pixel circuits on a single side, so that the number of circuits of the driving circuit system 230 in the first frame area BB1 and the second frame area BB2 is reduced, the frame width of the AMOLED panel can be reduced, and the effect of a narrow frame is achieved.
EXAMPLE III
Referring to fig. 5, a third embodiment of the present application is described in further detail based on the first embodiment.
The display panel 100 includes a display area AA and a frame area BB, and the frame area BB includes a first frame area BB1 and a second frame area BB2 located at two opposite sides of the display area.
The driving circuit system 230 further includes a second gate driving circuit 22P, the second gate driving circuit 22P includes a plurality of second gate driving circuit units arranged in a cascade, the second gate driving circuit units are configured to generate a second gate driving signal, the second gate driving circuit 22P is disposed in the first frame area BB1 and the second frame area BB2, and the second gate driving circuit 22P is coupled to the pixel circuits in the same corresponding row.
Specifically, the first gate driving circuit 21N is disposed in the first frame region and the second frame region; the first light emission control circuit 23E is provided in the first frame area BB1 and the second frame area BB2, and the second gate drive circuit 22P is provided in the first frame area BB1 and the second frame area BB 2. The width of the first light-emitting control circuit unit on the layout is smaller than that of the first gate drive circuit unit on the layout.
The first gate driving circuit unit is coupled to the pixel circuits in the opposite row in a bilateral driving manner, and at this time, optionally, the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to one row of pixel circuits, or the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to at least two rows of pixel circuits. Preferably, the first gate driving circuit unit may be coupled to the pixel circuits by bilateral driving corresponding to a row of the pixel circuits, so as to provide the pixel circuits with more excellent driving capability.
Specifically, the second gate driving circuit unit is coupled to the pixel circuits in a manner of bilateral driving corresponding to a row of pixel circuits; the first light emission control circuit unit is coupled to the pixel circuits in a manner of bilateral driving of the corresponding rows of pixel circuits. Here, a plurality of rows refers to two or more rows of pixel circuits.
When the first light emission control circuit unit is coupled to the pixel circuits by bilaterally driving the pixel circuits corresponding to two or more rows, the first light emission control circuit unit has a longer length in the first frame area BB1 and the second frame area BB2 at the left and right ends of the pixel circuits of a row than at the left and right ends of the pixel circuits of a row (e.g., at the left and right ends in fig. 5), and the first light emission control circuit unit can be set to have a longer length in the layout of the layout (layout design), and thus to have a narrower width in the layout of the layout (layout design). Note that, the longitudinal direction here refers to a direction parallel to the extending direction of the first gate driver circuit 21N or a direction perpendicular to the driving signal line 12; the width direction means a direction perpendicular to the extending direction of the first gate driver circuit 21N or parallel to the driving signal line 12, or a side width direction of the first frame region BB 1.
The pixel circuit comprises at least one N-type switch control transistor, at least one P-type switch control TFT and at least one P-type light-emitting control TFT; the first grid drive circuit unit is coupled to the corresponding N-type switch control TFT in the pixel circuit of the corresponding row; the second grid drive circuit unit is coupled to the corresponding P-type switch control TFT in the pixel circuit of the corresponding row; the first light emission control circuit unit is coupled to the corresponding P-type light emission control TFT in the pixel circuit of the corresponding row.
When the driving circuitry 230 in the present embodiment corresponds to the pixel circuit in fig. 2, the first gate driving circuit 21N may be provided with a first gate signal Scan1 for controlling the on and off states of the N-type fourth transistor T4 (switching transistor); the second gate driving circuit 22P provides a second gate driving signal Scan2 for controlling the on and off states of the P-type second transistor T2 (switching transistor); the first light emission control circuit 23E supplies a first light emission control signal EM for controlling on and off states of the fifth transistor T5 and the sixth transistor T6 (light emission control transistors) of the P-type.
In the embodiment of the application, the first light-emitting control circuit units are coupled to the pixel circuits in a manner of double-side driving corresponding to multiple rows of pixel circuits, so that the width of the first light-emitting control circuit units in the first frame area BB1 and the second frame area BB2 is reduced, the frame width of the AMOLED panel can be reduced, and the effect of a narrow frame is achieved.
Example four
Referring to fig. 6, a fourth embodiment of the present application is further described in detail based on the first embodiment.
The display panel 100 includes a display area AA and a frame area BB, and the frame area BB includes a first frame area BB1 and a second frame area BB2 located at two opposite sides of the display area.
The driving circuit system 230 further includes a second gate driving circuit 22P, the second gate driving circuit 22P includes a plurality of second gate driving circuit units arranged in a cascade, the second gate driving circuit units are configured to generate a second gate driving signal, the second gate driving circuit 22P is disposed in the first frame area BB1 and the second frame area BB2, and the second gate driving circuit 22P is coupled to the pixel circuits in the same corresponding row.
Specifically, the first gate driving circuit 21N is disposed in the first frame region and the second frame region; the first light emission control circuit 23E is provided in the first frame area BB1 and the second frame area BB2, and the second gate drive circuit 22P is provided in the first frame area BB1 and the second frame area BB 2. The width of the second gate driving circuit unit on the layout is smaller than that of the first gate driving circuit unit on the layout.
The first gate driving circuit unit is coupled to the pixel circuits in the opposite row in a bilateral driving manner, and at this time, optionally, the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to one row of pixel circuits, or the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to at least two rows of pixel circuits. Preferably, the first gate driving circuit unit may be coupled to the pixel circuits by bilateral driving corresponding to a row of the pixel circuits, so as to provide the pixel circuits with more excellent driving capability.
Specifically, the second gate driving circuit unit is coupled to the pixel circuits in a manner of bilateral driving corresponding to multiple rows of pixel circuits; the first light emitting control circuit unit is coupled to the pixel circuits in a manner of bilateral driving of the corresponding row of pixel circuits. Here, a plurality of rows refers to two or more rows of pixel circuits.
When the second gate driving circuit unit is coupled to the pixel circuits by bilateral driving corresponding to two or more rows of pixel circuits, the second gate driving circuit unit has a longer length in the first frame area BB1 and the second frame area BB2 at the left and right ends of the rows of pixel circuits than at the left and right ends of one row of pixel circuits (e.g., the left and right ends in fig. 5), and the second gate driving circuit unit may be set to have a longer length in the layout (layout design), and thus have a narrower width in the layout (layout design). Note that, the longitudinal direction here refers to a direction parallel to the extending direction of the first gate driver circuit 21N or a direction perpendicular to the driving signal line 12; the width direction means a direction perpendicular to the extending direction of the first gate driver circuit 21N or parallel to the driving signal line 12, or a side width direction of the first frame region BB 1.
The pixel circuit comprises at least one N-type switch control transistor, at least one P-type switch control TFT and at least one P-type light-emitting control TFT; the first grid drive circuit unit is coupled to the corresponding N-type switch control TFT in the pixel circuit of the corresponding row; the second grid drive circuit unit is coupled to the corresponding P-type switch control TFT in the pixel circuit of the corresponding row; the first light emission control circuit unit is coupled to the corresponding P-type light emission control TFT in the pixel circuit of the corresponding row.
When the driving circuitry 230 in the present embodiment corresponds to the pixel circuit in fig. 2, the first gate driving circuit 21N may be provided with a first gate signal Scan1 for controlling the on and off states of the N-type fourth transistor T4 (switching transistor); the second gate driving circuit 22P provides a second gate driving signal Scan2 for controlling the on and off states of the P-type second transistor T2 (switching transistor); the first light emission control circuit 23E supplies a first light emission control signal EM for controlling on and off states of the fifth transistor T5 and the sixth transistor T6 (light emission control transistors) of the P-type.
In the embodiment of the application, the second gate driving circuit units are coupled to the pixel circuits in a manner of double-side driving corresponding to multiple rows of pixel circuits, so that the widths of the second gate driving circuit units in the first frame area BB1 and the second frame area BB2 are reduced, the frame width of the AMOLED panel can be reduced, and the effect of a narrow frame is achieved.
EXAMPLE five
Referring to fig. 7, a fifth embodiment of the present application is further described in detail based on the first embodiment.
The display panel 100 includes a display area AA and a frame area BB, and the frame area BB includes a first frame area BB1 and a second frame area BB2 located at two opposite sides of the display area.
The driving circuit system 230 further includes a second gate driving circuit 22P, the second gate driving circuit 22P includes a plurality of second gate driving circuit units arranged in a cascade, the second gate driving circuit units are configured to generate a second gate driving signal, the second gate driving circuit 22P is disposed in the first frame area BB1 and the second frame area BB2, and the second gate driving circuit 22P is coupled to the pixel circuits in the same corresponding row.
Specifically, the first gate driving circuit 21N is disposed in the first frame region and the second frame region; the first light emission control circuit 23E is provided in the first frame area BB1 and the second frame area BB2, and the second gate drive circuit 22P is provided in the first frame area BB1 and the second frame area BB 2. The width of the first light-emitting control circuit unit and the second grid driving circuit unit on the layout is smaller than that of the first grid driving circuit unit on the layout.
The first gate driving circuit unit is coupled to the pixel circuits in the opposite row in a bilateral driving manner, and at this time, optionally, the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to one row of pixel circuits, or the first gate driving circuit unit may be coupled to the pixel circuits in a manner of bilateral driving corresponding to at least two rows of pixel circuits. Preferably, the first gate driving circuit unit may be coupled to the pixel circuits by bilateral driving corresponding to a row of the pixel circuits, so as to provide the pixel circuits with more excellent driving capability.
Specifically, the second gate driving circuit unit is coupled to the pixel circuits in a manner of bilateral driving corresponding to multiple rows of pixel circuits; the first light emission control circuit unit is also coupled to the pixel circuits by bilaterally driving the corresponding rows of the pixel circuits. Here, a plurality of rows refers to two or more rows of pixel circuits.
When the second gate driving circuit unit and the first light emission control circuit unit are coupled to the pixel circuits respectively in a manner of bilateral driving corresponding to two or more rows of pixel circuits, the second gate driving circuit unit and the first light emission control circuit unit have longer lengths in the first frame area BB1 and the second frame area BB2 at the left and right ends of a row of pixel circuits than in the left and right ends (e.g., the left and right ends in fig. 5) of a row of pixel circuits, and the second gate driving circuit unit and the first light emission control circuit unit may be set to have longer lengths in the layout (layout design), thereby having a narrower width in the layout (layout design). Note that, the longitudinal direction here refers to a direction parallel to the extending direction of the first gate driver circuit 21N or a direction perpendicular to the driving signal line 12; the width direction means a direction perpendicular to the extending direction of the first gate driver circuit 21N or parallel to the driving signal line 12, or a side width direction of the first frame region BB 1.
The pixel circuit comprises at least one N-type switch control transistor, at least one P-type switch control TFT and at least one P-type light-emitting control TFT; the first grid drive circuit unit is coupled to the corresponding N-type switch control TFT in the pixel circuit of the corresponding row; the second grid drive circuit unit is coupled to the corresponding P-type switch control TFT in the pixel circuit of the corresponding row; the first light emission control circuit unit is coupled to the corresponding P-type light emission control TFT in the pixel circuit of the corresponding row.
When the driving circuitry 230 in the present embodiment corresponds to the pixel circuit in fig. 2, the first gate driving circuit 21N may be provided with a first gate signal Scan1 for controlling the on and off states of the N-type fourth transistor T4 (switching transistor); the second gate driving circuit 22P provides a second gate driving signal Scan2 for controlling the on and off states of the P-type second transistor T2 (switching transistor); the first light emission control circuit 23E supplies a first light emission control signal EM for controlling on and off states of the fifth transistor T5 and the sixth transistor T6 (light emission control transistors) of the P-type.
In the embodiment of the application, the second gate driving circuit unit is coupled to the pixel circuits in a manner of bilateral driving corresponding to multiple rows of pixel circuits, and the first light-emitting control circuit unit is also coupled to the pixel circuits in a manner of bilateral driving corresponding to multiple rows of pixel circuits, so that the widths of the second gate driving circuit unit and the first light-emitting control circuit unit in the first frame area BB1 and the second frame area BB2 are reduced, the frame width of the AMOLED panel can be reduced, and the effect of a narrow frame is achieved.
EXAMPLE six
Referring to fig. 8, a fifth embodiment of the present application is further described in detail based on the first embodiment.
The display panel 100 includes a display area AA and a frame area BB, and the frame area BB includes a first frame area BB1 and a second frame area BB2 located at two opposite sides of the display area.
The first gate driving circuit unit is disposed in the first frame area BB1 and the second frame area BB2, and is coupled to the pixel circuits in the opposite row in a bilateral driving manner, where optionally the first gate driving circuit unit may be coupled to the pixel circuits in a manner that the bilateral driving corresponds to one row of pixel circuits, or the first gate driving circuit unit may be coupled to the pixel circuits in a manner that the bilateral driving corresponds to at least two rows of pixel circuits. Preferably, the first gate driving circuit unit may be coupled to the pixel circuits by bilateral driving corresponding to a row of the pixel circuits, so as to provide the pixel circuits with more excellent driving capability.
The first light emission control circuit 53E is provided in the first frame area BB1 and the second frame area BB2, and the first light emission control circuit 53E is coupled to the pixel circuits of the corresponding row by double-side driving the corresponding rows of pixel circuits. Here, a plurality of rows refers to two or more rows of pixel circuits.
The driving circuit system 230 further includes a second light-emitting control circuit 52E, the second light-emitting control circuit 52E includes a plurality of second light-emitting control circuit units arranged in a cascade, the second light-emitting control circuit 52E is disposed in the first frame area BB1 and the second frame area BB2, the second light-emitting control circuit units are coupled to the pixel circuits by double-side driving corresponding to the plurality of rows of pixel circuits, and the second light-emitting control circuit is configured to generate a second gate driving signal. Here, a plurality of rows refers to two or more rows of pixel circuits.
Further, the width of the first light-emitting control circuit unit and the second light-emitting control circuit unit on the layout is smaller than the width of the first gate drive circuit unit on the layout.
When the first light-emitting control circuit unit and the second light-emitting control circuit unit are coupled to the pixel circuits respectively in a manner of bilateral driving corresponding to two or more rows of pixel circuits, the first light-emitting control circuit unit and the second light-emitting control circuit unit have longer lengths in the first frame area BB1 and the second frame area BB2 at the left and right ends of a row of pixel circuits than at the left and right ends (e.g., the left and right ends in fig. 5) of a row of pixel circuits, and the first light-emitting control circuit unit and the second light-emitting control circuit unit can be set to have longer lengths in the layout (layout design), so that the first light-emitting control circuit unit and the second light-emitting control circuit unit have a narrower width in the layout (layout). Note that, the longitudinal direction here refers to a direction parallel to the extending direction of the first gate driver circuit 21N or a direction perpendicular to the driving signal line 12; the width direction means a direction perpendicular to the extending direction of the first gate driver circuit 21N or parallel to the driving signal line 12, or a side width direction of the first frame region BB 1.
The pixel circuit comprises at least one N-type switch control TFT, at least one P-type switch control TFT and at least one P-type light-emitting control TFT; the first grid driving circuit unit is coupled to the corresponding P-type switch control TFT in the pixel circuit of the corresponding row; the first light emission control circuit unit is coupled to the corresponding P-type light emission control TFTs in the corresponding plurality of rows of pixel circuits; the second light emission control circuit unit is coupled to the corresponding N-type switching control TFT in the corresponding plurality of rows of pixel circuits.
When the driving circuit system 230 in the present embodiment corresponds to the pixel circuit in fig. 2, the second light-emitting control circuit 52E may be provided with a second gate signal Scan1 (the second gate driving signal Scan1 in the present embodiment) for controlling the on and off states of the N-type fourth transistor T4 (switching transistor); the first gate driving circuit 51P provides a first gate driving signal Scan2 (Scan 2 in the present embodiment) for controlling the on and off states of the P-type second transistor T2 (switching transistor); the first light emission control circuit 53E supplies a first light emission control signal EM for controlling on and off states of the fifth transistor T5 and the sixth transistor T6 (light emission control transistors) of the P-type.
This embodiment is different from the second to fifth embodiments in various aspects. In the present embodiment, the second gate driving signal is generated by the second light emitting control circuit, and the second gate driving signal can be used to control the on and off states of the N-type fourth transistor T4, because the EM signal has a long on time, and can be provided instead of the conventional gate driving circuit. Meanwhile, the first light-emitting control circuit unit and the second light-emitting control circuit unit can be driven in a mode of bilateral driving of multiple rows of pixel circuits, so that the first light-emitting control circuit unit and the second light-emitting control circuit unit can have narrower width in layout (layout design), the display panel 100 can have narrower width, and the beneficial effect of a narrow frame is achieved.
The present application further provides a display device, which includes any one of the display panels 100, and the display device may further optionally include other structures or components such as a protection structure.
The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel, comprising a display area and a frame area, wherein the frame area surrounds the display area, the display area includes a plurality of pixel circuits arranged in an array, the frame area includes a driving circuit system, and the driving circuit system includes:
the first grid driving circuit comprises a plurality of first grid driving circuit units which are arranged in a cascade mode, the first grid driving circuit is used for generating a first grid driving signal, and the first grid driving circuit units are coupled to the pixel circuit in a bilateral driving mode;
a first light emission control circuit including a plurality of cascade-arranged first light emission control circuit units for generating a first light emission control signal, the first light emission control circuit units being coupled to the pixel circuits in such a manner that the pixel circuits corresponding to one row are driven on one side or the pixel circuits corresponding to a plurality of rows are driven on two sides.
2. The display panel of claim 1,
the frame area comprises a first frame area and a second frame area which are opposite and positioned at two sides of the display area;
the first grid driving circuit is arranged in the first frame area and the second frame area;
the first light emission control circuit is disposed in at least one area of the first and second bezel areas, and is coupled to the pixel circuits of a corresponding row by bilaterally driving the corresponding rows of the pixel circuits when the first light emission control circuit is disposed in the first and second bezel areas.
3. The display panel of claim 2,
the driving circuit system further comprises a second gate driving circuit, the second gate driving circuit comprises a plurality of second gate driving circuit units which are arranged in a cascade mode, the second gate driving circuit units are used for generating second gate driving signals, the second gate driving circuit is arranged in at least one area of the first frame area and the second frame area, and the second gate driving circuit is coupled to the pixel circuits in the corresponding row;
the pixel circuit comprises at least one N-type switch control TFT, at least one P-type switch control TFT and at least one P-type light-emitting control TFT;
the first gate driving circuit unit is coupled to the corresponding N-type switch control TFT in the pixel circuit of the corresponding row;
the second gate driving circuit unit is coupled to the corresponding P-type switch control TFT in the pixel circuit of the corresponding row;
the first light emission control circuit unit is coupled to the corresponding P-type light emission control TFT in the pixel circuit of the corresponding row.
4. The display panel of claim 3,
the first light-emitting control circuit is arranged in the first frame area, and the second gate drive circuit is arranged in the second frame area;
the second grid drive circuit unit is coupled to the pixel circuits in a mode of driving the pixel circuits in a corresponding row in a single side mode;
the first light emitting control circuit unit is coupled to the pixel circuits in a manner of unilaterally driving the pixel circuits in a corresponding row.
5. The display panel of claim 3,
the first light-emitting control circuit is arranged in the first frame area and the second frame area;
the second grid driving circuit is arranged in the first frame area and the second frame area;
the width of the first light-emitting control circuit unit or/and the second grid drive circuit unit on the layout is smaller than that of the first grid drive circuit unit on the layout.
6. The display panel of claim 5,
the second grid driving circuit unit is coupled to the pixel circuits in a mode of bilateral driving corresponding to a plurality of rows of the pixel circuits; or/and
the first light emission control circuit unit is coupled to the pixel circuits by bilaterally driving corresponding rows of the pixel circuits.
7. The display panel of claim 1,
the frame area comprises a first frame area and a second frame area which are opposite and positioned at two sides of the display area;
the first light-emitting control circuit is arranged in the first frame area and the second frame area and is coupled to the pixel circuits of the corresponding row in a mode of bilateral driving the pixel circuits of the corresponding rows;
the driving circuit system further includes a second light-emitting control circuit, the second light-emitting control circuit includes a plurality of second light-emitting control circuit units arranged in a cascade manner, the second light-emitting control circuit is disposed in the first frame region and the second frame region, the second light-emitting control circuit units are coupled to the pixel circuits in a manner of bilateral driving corresponding to a plurality of rows of the pixel circuits, and the second light-emitting control circuit is configured to generate a second gate driving signal.
8. The display panel of claim 7,
the width of the first light-emitting control circuit unit and the second light-emitting control circuit unit on the layout is smaller than that of the first gate drive circuit unit on the layout.
9. The display panel of claim 8,
the pixel circuit comprises at least one N-type switch control TFT, at least one P-type switch control TFT and at least one P-type light-emitting control TFT;
the first gate driving circuit unit is coupled to the corresponding P-type switch control TFT in the corresponding row of the pixel circuits;
the first light emission control circuit unit is coupled to corresponding P-type light emission control TFTs in corresponding rows of the pixel circuits;
the second light emission control circuit unit is coupled to the corresponding N-type switch control TFTs in the corresponding rows of the pixel circuits.
10. A display device comprising the display panel according to any one of claims 1 to 9.
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