CN116312707A

CN116312707A - Shift register unit and driving method thereof, panel driving circuit and display device

Info

Publication number: CN116312707A
Application number: CN202310288617.7A
Authority: CN
Inventors: 吴鹏
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2023-03-21
Filing date: 2023-03-21
Publication date: 2023-06-23

Abstract

The disclosure provides a shift register unit, a driving method thereof, a panel driving circuit and a display device, and belongs to the technical field of display. The shift register unit includes an input circuit, an output circuit, and a compensation circuit. The input circuit is capable of charging the pull-up node based on an input signal provided by the input signal terminal. The output circuit is capable of transmitting the clock signal supplied from the clock signal terminal to the output signal terminal based on the potential of the pull-up node. The compensation circuit can control the output signal end to be conducted with the input signal end based on the potential of the pull-up node and the clock signal so as to compensate the input signal provided by the input signal end based on the clock signal transmitted to the output signal end. In this way, the voltage difference between the input signal end and the pull-up node can be reduced in the stage that the pull-up node is pulled up by the bootstrap of the capacitor in the output circuit, namely the source-drain voltage difference of the transistor in the input circuit is reduced. Further, the occurrence of negative drift in characteristics of transistors in the input circuit can be avoided.

Description

Shift register unit and driving method thereof, panel driving circuit and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a shift register unit, a driving method thereof, a panel driving circuit and a display device.

Background

With the progress of display technology, array substrate row driving (gate driver on array, GOA) technology is often adopted to integrate gate driving circuits on an array substrate in a display device, so as to facilitate the design of a narrow frame of the display device. The gate driving circuit is also called a GOA circuit.

In the related art, the GOA circuit generally includes: a plurality of cascaded shift register cells (also referred to as GOA cells). The GOA unit comprises: an input circuit and an output circuit. The input circuit is respectively coupled with the input signal end and the pull-up node; the output circuit is coupled to the pull-up node, the clock signal terminal and the output signal terminal, respectively. The input circuit is used for charging the pull-up node under the control of the input signal end. The output circuit is used for controlling the clock signal end to output a clock signal to the output signal end under the control of the potential of the pull-up node. And the output circuit can bootstrap and raise the potential of the pull-up node through the capacitor included in the output circuit, so that the clock signal can be conveniently transmitted to the output signal end.

However, on the basis of raising the potential bootstrap of the pull-up node, the source-drain voltage difference of the transistor in the input circuit is increased, and unavoidable negative drift occurs.

Disclosure of Invention

A shift register unit, a driving method thereof, a panel driving circuit and a display device are provided, which can solve the problem that the source-drain voltage difference of a transistor in an input circuit is increased and unavoidable negative drift occurs on the basis of bootstrapping and lifting the potential of a pull-up node in the related art. The technical scheme is as follows:

in one aspect, there is provided a shift register unit including:

the input circuit is respectively coupled with the input signal end and the pull-up node and is used for controlling the on-off of the input signal end and the pull-up node based on an input signal provided by the input signal end;

the output circuit is respectively coupled with the pull-up node, the clock signal end and the output signal end and is used for controlling the on-off of the clock signal end and the output signal end based on the potential of the pull-up node;

and the compensation circuit is respectively coupled with the pull-up node, the clock signal end, the output signal end and the input signal end and is used for controlling the on-off of the output signal end and the input signal end based on the potential of the pull-up node and the clock signal provided by the clock signal end.

Optionally, the compensation circuit includes:

the first compensation sub-circuit is respectively coupled with the pull-up node, the clock signal end and the control node and is used for controlling the on-off of the clock signal end and the control node based on the potential of the pull-up node;

and the second compensation sub-circuit is respectively coupled with the control node, the output signal end and the input signal end and is used for controlling the on-off of the output signal end and the input signal end based on the potential of the control node.

Optionally, the first compensation sub-circuit includes: a first transistor;

the gate of the first transistor is coupled to the pull-up node, the first pole of the first transistor is coupled to the clock signal terminal, and the second pole of the first transistor is coupled to the control node.

Optionally, the second compensation sub-circuit includes: a second transistor;

the gate of the second transistor is coupled to the control node, the first pole of the second transistor is coupled to the output signal terminal, and the second pole of the second transistor is coupled to the input signal terminal.

Optionally, the output signal terminal includes: the cascade output end is used for being coupled with a next-stage shift register unit, and the driving output end is used for being coupled with a pixel; the output circuit includes:

The first output sub-circuit is respectively coupled with the pull-up node, the clock signal end and the cascade output end and is used for controlling the on-off of the clock signal end and the cascade output end based on the potential of the pull-up node;

the second output sub-circuit is respectively coupled with the pull-up node, the clock signal end and the driving output end and is used for controlling the on-off of the clock signal end and the driving output end based on the potential of the pull-up node;

the compensation circuit is coupled with a cascade output end included in the output signal end and used for controlling on-off of the cascade output end and the input signal end based on the potential of the pull-up node and the clock signal.

Optionally, the first output sub-circuit includes: a third transistor; the second output sub-circuit includes: a fourth transistor and a storage capacitor;

a gate of the third transistor is coupled to the pull-up node, a first pole of the third transistor is coupled to the clock signal terminal, and a second pole of the third transistor is coupled to the cascade output terminal;

the grid electrode of the fourth transistor is coupled with the pull-up node, the first electrode of the fourth transistor is coupled with the clock signal end, and the second electrode of the fourth transistor is coupled with the driving output end;

One end of the storage capacitor is coupled with the pull-up node, and the other end of the storage capacitor is coupled with the driving output end.

Optionally, the shift register unit further includes:

the reset circuit is respectively coupled with a total reset signal end, a first reset signal end, a second reset signal end, a first pull-down power end, a second pull-down power end, the pull-up node and the driving output end, and is used for controlling the on-off of the first pull-down power end and the pull-up node based on the total reset signal provided by the total reset signal end, controlling the on-off of the first pull-down power end and the pull-up node based on the first reset signal provided by the first reset signal end, and controlling the on-off of the second pull-down power end and the driving output end based on the second reset signal provided by the second reset signal end;

the pull-down control circuits are respectively coupled with a pull-up power supply end, the input signal end, the pull-up node, the first pull-down power supply end and the pull-down node, and are used for controlling the on-off of the pull-up power supply end and the pull-down node based on a pull-up power supply signal provided by the pull-up power supply end and controlling the on-off of the first pull-down power supply end and the pull-down node based on the input signal and the potential of the pull-up node;

And at least one pull-down circuit corresponding to the pull-down control circuits one by one, wherein each pull-down circuit is respectively coupled with the pull-down node, the first pull-down power end, the second pull-down power end, the pull-up node, the cascade output end and the driving output end, and is used for controlling the on-off of the first pull-down power end and the pull-up node, controlling the on-off of the first pull-down power end and the cascade output end and controlling the on-off of the second pull-down power end and the driving output end based on the potential of the pull-down node.

Optionally, the reset circuit includes: a fifth transistor, a sixth transistor, and a seventh transistor; the pull-down control circuit includes: an eighth transistor, a ninth transistor, and a tenth transistor; the pull-down circuit includes: an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the input circuit includes: a fourteenth transistor;

the grid electrode of the fifth transistor is coupled with the total reset signal end, the first electrode of the fifth transistor is coupled with the first pull-down power end, and the second electrode of the fifth transistor is coupled with the pull-up node;

A gate of the sixth transistor is coupled to the first reset signal terminal, a first pole of the sixth transistor is coupled to the first pull-down power terminal, and a second pole of the sixth transistor is coupled to the pull-up node;

a gate of the seventh transistor is coupled to the second reset signal terminal, a first pole of the seventh transistor is coupled to the second pull-down power terminal, and a second pole of the seventh transistor is coupled to the driving output terminal;

the grid electrode and the first electrode of the eighth transistor are both coupled with the pull-up power supply end, and the second electrode of the eighth transistor is coupled with the pull-down node;

a gate of the ninth transistor is coupled to the input signal terminal, a first pole of the ninth transistor is coupled to the first pull-down power supply terminal, and a second pole of the ninth transistor is coupled to the pull-down node;

a gate of the tenth transistor is coupled to the pull-up node, a first pole of the tenth transistor is coupled to the first pull-down power supply terminal, and a second pole of the tenth transistor is coupled to the pull-down node;

a gate of the eleventh transistor is coupled to the pull-down node, a first pole of the eleventh transistor is coupled to the first pull-down power supply terminal, and a second pole of the eleventh transistor is coupled to the pull-up node;

A gate of the twelfth transistor is coupled to the pull-down node, a first pole of the twelfth transistor is coupled to the first pull-down power supply terminal or the second pull-down power supply terminal, and a second pole of the twelfth transistor is coupled to the cascade output terminal;

a gate of the thirteenth transistor is coupled to the pull-down node, a first pole of the thirteenth transistor is coupled to the second pull-down power supply terminal, and a second pole of the thirteenth transistor is coupled to the drive output terminal;

the gate and the first pole of the fourteenth transistor are both coupled to the input signal terminal, and the second pole of the fourteenth transistor is coupled to the pull-up node.

In another aspect, there is provided a driving method of a shift register unit for driving the shift register unit as described in the above aspect, the method comprising:

in the input stage, the potential of an input signal provided by an input signal end is a first potential, the potential of a clock signal provided by a clock signal end is a second potential, an input circuit controls the input signal end to be conducted with a pull-up node based on the input signal, an output circuit controls the clock signal end to be conducted with an output signal end based on the potential of the pull-up node, and a compensation circuit controls the output signal end to be decoupled from the input signal end based on the potential of the pull-up node and the clock signal;

And in the output stage, the potential of the clock signal jumps from the second potential to the first potential, the potential of the pull-up node is kept at the first potential, the output circuit controls the clock signal end to be conducted with the output signal end based on the potential of the pull-up node, and the compensation circuit controls the output signal end to be conducted with the input signal end based on the potential of the pull-up node and the clock signal.

In still another aspect, there is provided a panel driving circuit including: at least two cascaded shift register units as described in the above aspect.

In still another aspect, there is provided a display device including: a display panel, and a panel driving circuit as described in the above further aspect;

the display panel comprises a plurality of pixels, and the panel driving circuit is coupled with the pixels and used for transmitting light-emitting driving signals to the pixels so as to drive the pixels to emit light.

In summary, the beneficial effects brought by the technical solution provided by the embodiments of the present disclosure at least may include:

a shift register unit, a driving method thereof, a panel driving circuit, and a display device are provided. The shift register unit includes an input circuit, an output circuit, and a compensation circuit. The input circuit is capable of charging the pull-up node based on an input signal provided by the input signal terminal. The output circuit is capable of transmitting the clock signal supplied from the clock signal terminal to the output signal terminal based on the potential of the pull-up node. The compensation circuit can control the output signal end to be conducted with the input signal end based on the potential of the pull-up node and the clock signal so as to compensate the input signal provided by the input signal end based on the clock signal transmitted to the output signal end. In this way, the voltage difference between the input signal end and the pull-up node can be reduced in the stage that the pull-up node is pulled up by the bootstrap of the capacitor in the output circuit, namely the source-drain voltage difference of the transistor in the input circuit is reduced. Further, the occurrence of negative drift in characteristics of transistors in the input circuit can be avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic diagram of a shift register unit in the related art;

FIG. 2 is a timing diagram of signals coupled to a shift register unit provided on the basis of FIG. 1;

FIG. 3 is a graph of characteristics of a transistor provided on the basis of FIG. 1;

fig. 4 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a structure of a shift register unit according to another embodiment of the present disclosure;

fig. 9 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure;

FIG. 10 is a signal timing diagram of a shift register unit according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a panel driving circuit according to an embodiment of the present disclosure;

fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.

The transistors employed in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices of the same characteristics, and the transistors employed in the embodiments of the present disclosure are primarily switching transistors according to their role in the circuit. Since the source and drain of the switching transistor employed herein are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first pole and the drain is referred to as a second pole. The middle terminal of the transistor is defined as a control electrode according to the form in the figure, and may be called a gate electrode, a signal input signal terminal as a source electrode, and a signal output terminal as a drain electrode. In addition, the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor that is turned on when the gate is at a low level, turned off when the gate is at a high level, and an N-type switching transistor that is turned on when the gate is at a high level, and turned off when the gate is at a low level. Further, the plurality of signals in the various embodiments of the present disclosure each correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has 2 state quantities, and do not represent that the first potential or the second potential has a specific value in the whole text.

Currently, referring to fig. 1, an input circuit in a goa unit may include an input transistor T1 with a gate source (i.e., a gate g and a source s) connected, and an output circuit may include an output transistor T2 and a storage capacitor Cst. The gate g and source s of the INPUT transistor T1 may be both coupled to the INPUT signal terminal INPUT, and the drain may be coupled to the pull-up node PU. The gate g of the output transistor T2 may be coupled to the pull-up node PU, the source s may be coupled to the clock signal terminal CLK, and the drain d may be coupled to the output signal terminal OUT. The storage capacitor Cst is connected in series between the gate g and the drain d of the output transistor T2. In addition, fig. 1 also shows two reset transistors T3 and T4 included in the GOA unit, wherein gates g of the reset transistors T3 and T4 are coupled to the reset signal terminal RST, sources s of the reset transistors T3 and T4 are coupled to the pull-down power supply terminal VSS, and drains d of the reset transistors T3 and T4 are coupled to the pull-up node PU and the output signal terminal OUT, respectively.

Also, taking the example that the transistors are all N-type transistors, fig. 2 is combined: first, in the INPUT stage T1, the INPUT signal terminal INPUT may provide the INPUT signal of the high voltage VGH, so that the INPUT transistor T1 is turned on, and the INPUT signal terminal INPUT transmits the INPUT signal of the high voltage VGH to the pull-up node PU to precharge the pull-up node PU. At this time, the clock signal terminal CLK may provide a clock signal of the low potential VGL. Then, in the output stage T2, after the precharge of the pull-up node PU is completed, the output transistor T2 may be turned on. At this time, the INPUT signal terminal INPUT may provide the INPUT signal of the low voltage VGL, so that the INPUT transistor T1 is turned off. And, the clock signal terminal CLK may provide a clock signal of a high potential VGH, which may be transmitted to the output signal terminal OUT through the output transistor T2. In addition, in the output stage T2, the storage capacitor Cst may further raise the potential of the pull-up node PU by bootstrap, and may generally be raised to approximately 2VGH, so that the output transistor T2 is fully turned on. Assuming VGH is 32 volts (V), the potential of the pull-up node PU is pulled up to about 64V by bootstrap. If the low voltage VGL of the input signal is-10V, it is known that the voltage of the pull-up node PU is bootstrapped, and the source-drain voltage difference Vds of the input transistor T1 is as high as 74V (64- (-10) =74). In addition, fig. 2 further illustrates a reset stage T3 after the output stage T2, in the reset stage T3, the reset signal terminal RST may provide a reset signal of the high potential VGH, so that the reset transistors T3 and T4 are turned on, and the pull-down power supply terminal VSS may transmit a pull-down power supply signal of the low potential VGL to the pull-up node PU and the output signal terminal OUT, respectively, so as to implement the reset of the pull-up node PU and the output signal terminal OUT.

In the test, it is found that the invasion of water vapor and the higher Vds differential pressure can cause negative drift of the characteristics of the input transistor T1 in the input circuit in the high-temperature high-humidity operation experiment. As shown in fig. 3, when the gate-source voltage difference Vgs of the input transistor T1 is 0V, the leakage current of the input transistor T1 increases exponentially, so that the input transistor T1 is electrically conductive. Furthermore, leakage occurs at the pull-up node PU, and the potential of the pull-up node PU cannot be maintained, so that the output transistor T2 cannot normally output a clock signal, and the GOA unit fails to operate, so that the display device has a problem of Abnormal Display (AD) failure. The abscissa in fig. 3 refers to the gate-source voltage difference Vgs in V; the ordinate indicates the drain current Id in amperes (A).

In the related art, attempts have been made to reduce the source-drain voltage difference Vds of the input transistor T1 by reducing VGH and VGL, thereby improving the negative drift phenomenon of the characteristics of the input transistor T1, solving the above-mentioned AD defect problem, and improving the product life. However, decreasing VGH will undoubtedly affect the charging rate. On the one hand, the bad phenomenon of uneven display (mura) is easy to occur under certain pictures with larger load (namely heavy load); on the other hand, the limit of the working life or the Margin (Margin) is also reduced. In view of the above problems, the embodiments of the present disclosure provide a method for reducing the voltage difference Vds of a transistor in an input circuit without changing the VGH and VGL settings, thereby improving the negative drift phenomenon of the transistor and ensuring that the display device can normally display a picture.

Fig. 4 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure. As shown in fig. 4, the shift register unit includes: an input circuit 01, an output circuit 02 and a compensation circuit 03.

The INPUT circuit 01 is coupled to the INPUT signal INPUT and the pull-up node PU, respectively, and the INPUT circuit 01 is configured to control on/off of the INPUT signal INPUT and the pull-up node PU based on an INPUT signal provided by the INPUT signal INPUT.

For example, the INPUT circuit 01 may control the INPUT signal INPUT to be turned on with the pull-up node PU when the INPUT signal INPUT provides the first potential. At this time, the INPUT signal provided by the INPUT signal terminal INPUT can be transmitted to the pull-up node PU. And, the INPUT circuit 01 may control the INPUT signal terminal INPUT to be decoupled from the pull-up node PU when the potential of the INPUT signal provided by the INPUT signal terminal INPUT is the second potential.

Alternatively, in an embodiment of the present disclosure, the first potential may be an active potential and the second potential may be an inactive potential. The first potential may be a high potential, and the second potential may be a low potential, that is, the first potential is larger than the second potential. The transistors in the circuit corresponding to the potential may be N-type transistors. If the transistors in the circuit are P-type transistors, the first potential may be low and the second potential may be high, i.e., the first potential is smaller than the second potential. The following examples are not repeated.

The output circuit 02 is coupled to the pull-up node PU, the clock signal terminal CLK, and the output signal terminal OUT, respectively. The output circuit 02 is used for controlling the on-off of the clock signal terminal CLK and the output signal terminal OUT based on the potential of the pull-up node PU.

For example, the output circuit 02 may control the clock signal terminal CLK to be conductive with the output signal terminal OUT when the potential of the pull-up node PU is the first potential. At this time, the clock signal provided by the clock signal terminal CLK can be transmitted to the output signal terminal OUT. And, the output circuit 02 may be decoupled from the control clock signal terminal CLK and the output signal terminal OUT when the potential of the pull-up node PU is the second potential.

The compensation circuit 03 is coupled to the pull-up node PU, the clock signal terminal CLK, the output signal terminal OUT, and the INPUT signal terminal INPUT, respectively. The compensation circuit 03 is configured to control on-off of the output signal terminal OUT and the INPUT signal terminal INPUT based on the potential of the pull-up node PU and a clock signal provided by the clock signal terminal CLK.

For example, when the potential of the pull-up node PU and the potential of the clock signal provided by the clock signal terminal CLK are both the first potentials, the compensation circuit 03 controls the output signal terminal OUT to be conductive to the INPUT signal terminal INPUT, and at this time, the clock signal transmitted to the output signal terminal OUT by the output circuit 02 may be further feedback-transmitted to the INPUT signal terminal INPUT. And, the compensation circuit 03 may control the output signal terminal OUT to be decoupled from the INPUT signal terminal INPUT when the potential of the pull-up node PU and/or the potential of the clock signal provided by the clock signal terminal CLK is the second potential.

When the clock signal has the first potential (i.e., the high potential VGH), the potential of the pull-up node PU is pulled up to approximately 2VGH by bootstrap as described in the above embodiments. At this time, by setting the compensation circuit 03 to feed back the clock signal of the high potential VGH to the INPUT signal terminal INPUT, the potential of the INPUT signal supplied from the INPUT signal terminal INPUT can be compensated to VGH. In this way, the source-drain voltage difference Vds of the transistor in the input circuit 01 can be reduced. On the basis of the structure shown in fig. 1, vds can be reduced from 2VGH-VGL in the related art to 2 VGH-vgh=vgh, i.e., to only one VGH. Furthermore, the characteristic negative drift of the transistor in the input circuit 01 can be improved, the electric leakage of the pull-up node PU is avoided, the better potential stability of the pull-up node PU is ensured, the output circuit 02 is ensured to reliably output a required clock signal to the output signal end OUT based on the potential of the pull-up node PU, and the AD bad phenomenon of the display device is improved.

In summary, the embodiments of the present disclosure provide a shift register unit. The shift register unit includes an input circuit, an output circuit, and a compensation circuit. The input circuit is capable of charging the pull-up node based on an input signal provided by the input signal terminal. The output circuit is capable of transmitting the clock signal supplied from the clock signal terminal to the output signal terminal based on the potential of the pull-up node. The compensation circuit can control the output signal end to be conducted with the input signal end based on the potential of the pull-up node and the clock signal so as to compensate the input signal provided by the input signal end based on the clock signal transmitted to the output signal end. In this way, the voltage difference between the input signal end and the pull-up node can be reduced in the stage that the pull-up node is pulled up by the bootstrap of the capacitor in the output circuit, namely the source-drain voltage difference of the transistor in the input circuit is reduced. Furthermore, the transistors in the input circuit can be prevented from negative drift.

On the basis of avoiding negative drift of transistors in an input circuit, electric leakage of a pull-up node can be avoided, and the potential of the pull-up node is ensured to be kept stable. Accordingly, the output circuit can reliably transmit clock signals to the output signal end based on the potential of the pull-up node, and the display device can reliably display pictures.

Fig. 5 is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 5, the output signal terminal OUT may include: a cascade output out_c and a driving output OUT1.

Wherein the cascade output out_c may be used for coupling with a shift register unit of a next stage. For example, the cascade output out_c of the shift register unit of the current stage may be coupled with the INPUT signal INPUT of the shift register unit of the next stage of the cascade. Accordingly, the clock signal transmitted to the cascade output terminal out_c may be used as an input signal of the next stage shift register unit to drive the next stage shift register unit to operate. The cascade output out_c may also be referred to as a shift output.

The driving output OUT1 may be used to couple with a pixel. For example, the driving output terminal OUT1 may be coupled to the pixel through a Gate line Gate. Accordingly, the clock signal transmitted to the driving output terminal OUT1 can be transmitted to the pixel as the gate driving signal to drive the pixel to emit light. The driving circuit including the shift register unit may be referred to as a gate driving circuit. Of course, in some embodiments, the driving output OUT1 may also be coupled to the pixel through the light emitting control line EM, and on the basis of this, the clock signal transmitted to the driving output OUT1 may be transmitted to the pixel as the light emitting control signal. The embodiment of the present disclosure does not limit the signal line connecting the driving output terminal OUT1 and the pixel.

By dividing the output signal terminal OUT into the cascade output terminal out_c and the driving output terminal OUT1 to cascade the shift register unit and the driving pixel to emit light, respectively, the cascade and the driving can be made not to interfere with each other, and not only the reliable operation of the shift register unit but also the reliable driving of the pixel to emit light can be ensured.

And, at the output signal terminal OUT may include: as can be seen with continued reference to fig. 5, on the basis of the cascade output terminal out_c and the driving output terminal OUT1, the output circuit 02 may include: a first output sub-circuit 021 and a second output sub-circuit 022.

The first output sub-circuit 021 may be coupled to the pull-up node PU, the clock signal terminal CLK, and the cascade output terminal out_c, respectively. The first output sub-circuit 021 may be used for controlling the on-off of the clock signal terminal CLK and the cascade output terminal out_c based on the potential of the pull-up node PU.

For example, the first output sub-circuit 021 may control the clock signal terminal CLK to be conducted with the cascade output terminal out_c when the potential of the pull-up node PU is the first potential. At this time, the clock signal provided by the clock signal terminal CLK may be transmitted to the cascade output terminal out_c, and transmitted to the cascade next stage shift register unit through the cascade output terminal out_c, for driving the next stage shift register unit to operate reliably. And, the first output sub-circuit 021 may control the clock signal terminal CLK to be decoupled from the cascade output terminal out_c when the potential of the pull-up node PU is the second potential.

The second output sub-circuit 022 may be coupled with the pull-up node PU, the clock signal terminal CLK, and the driving output terminal OUT1, respectively. The second output sub-circuit 022 may be used to control the on-off of the clock signal terminal CLK and the driving output terminal OUT1 based on the potential of the pull-up node PU.

For example, the second output sub-circuit 022 may control the clock signal terminal CLK to be turned on with the driving output terminal OUT1 when the potential of the pull-up node PU is the first potential. At this time, the clock signal provided from the clock signal terminal CLK may be transmitted to the driving output terminal OUT1 and transmitted to the pixel through the driving output terminal OUT1 for driving the pixel to emit light. And, the second output sub-circuit 022 may control the clock signal terminal CLK to be decoupled from the driving output terminal OUT1 when the potential of the pull-up node PU is the second potential.

As described in the above embodiments, with continued reference to fig. 5, the compensation circuit 03 described in the embodiment of the present disclosure may be coupled to the cascade output terminal out_c included in the output signal terminal OUT. Correspondingly, the compensation circuit 03 may be configured to control on-off of the cascade output terminal out_c and the INPUT signal terminal INPUT based on the potential and the clock signal of the pull-up node PU, so as to compensate the INPUT signal provided by the INPUT signal terminal INPUT based on the clock signal transmitted from the first output sub-circuit 021 to the cascade output terminal out_c. In this way, the output of the row driving output terminal OUT1 of the previous stage is not affected. Of course, in some embodiments, the compensation circuit 03 may be coupled to the driving output terminal OUT1 included in the output signal terminal OUT, and control the on-off of the driving output terminal OUT1 and the INPUT signal terminal INPUT based on the potential of the pull-up node PU and the clock signal.

Optionally, fig. 6 is a schematic structural diagram of another shift register unit provided in an embodiment of the disclosure. As shown in fig. 6, the compensation circuit 03 may include: a first compensation sub-circuit 031 and a second compensation sub-circuit 032.

The first compensation sub-circuit 031 may be coupled to the pull-up node PU, the clock signal terminal CLK, and the control node V1, respectively. The first compensation sub-circuit 031 may be configured to control the on/off of the clock signal terminal CLK and the control node V1 based on the potential of the pull-up node PU.

For example, the first compensation sub-circuit 031 may be configured to conduct the control clock signal terminal CLK with the control node V1 when the potential of the pull-up node PU is the first potential, and at this time, the clock signal provided by the clock signal terminal CLK may be transmitted to the control node V1. And, the first compensation sub-circuit 031 can disconnect the control clock signal terminal CLK from the control node V1 when the potential of the pull-up node PU is the second potential.

The second compensation sub-circuit 032 may be coupled to the control node V1, the output signal terminal OUT, and the INPUT signal terminal INPUT, respectively. The second compensation sub-circuit 032 may be configured to control on-off of the output signal terminal OUT and the INPUT signal terminal INPUT based on the potential of the control node V1.

For example, the second control sub-circuit 032 may control the output signal terminal OUT to be conductive to the INPUT signal terminal INPUT when the potential of the control node V1 is the first potential, and at this time, the signal transmitted to the output signal terminal OUT by the output circuit 02 may be feedback-transmitted to the INPUT signal terminal INPUT. Since the first compensation sub-circuit 031 transmits the clock signal to the control node V1 and the output circuit 02 transmits the clock signal to the output signal terminal OUT when the potential of the pull-up node PU is the first potential, the second control sub-circuit 032 transmits the clock signal of the first potential to the INPUT signal terminal INPUT when both the potential of the pull-up node PU and the potential of the clock signal are the first potentials, thereby realizing the compensation of the potential of the INPUT signal provided by the INPUT signal terminal INPUT. And, the second control sub-circuit 032 may control the output signal terminal OUT to be decoupled from the INPUT signal terminal INPUT when the potential of the control node V1 is the second potential.

It should be noted that, based on the structure shown in fig. 5, as can be seen in conjunction with fig. 6, the second compensation sub-circuit 032 may be coupled to the cascade output terminal out_c included in the output signal terminal OUT and the cascade output terminal out_c in the driving output terminal OUT 1. Correspondingly, the second compensation sub-circuit 032 may be configured to control the on-off of the cascade output terminal out_c and the INPUT signal terminal INPUT based on the potential of the control node V1.

Optionally, fig. 7 is a schematic structural diagram of still another shift register unit provided in an embodiment of the disclosure. As shown in fig. 7, the shift register unit may further include: a reset circuit 04, at least one pull-down control circuit 05, and at least one pull-down circuit 06 in one-to-one correspondence with the at least one pull-down control circuit 05.

The reset circuit 04 may be coupled to the total reset signal terminal tgoa_rst, the first reset signal terminal rst_1, the second reset signal terminal rst_2, the first pull-down power supply terminal LVGL, the second pull-down power supply terminal VGL, the pull-up node PU, and the driving output terminal OUT1, respectively. The reset circuit 04 may be configured to control on-off of the first pull-down power supply terminal LVGL and the pull-up node PU based on a total reset signal provided by the total reset signal terminal tgoa_rst, control on-off of the first pull-down power supply terminal LVGL and the pull-up node PU based on a first reset signal provided by the first reset signal terminal rst_1, and control on-off of the second pull-down power supply terminal VGL and the driving output terminal OUT1 based on a second reset signal provided by the second reset signal terminal rst_2.

For example, the reset circuit 04 may control the first pull-down power supply terminal LVGL to be turned on with the pull-up node PU when the potential of the total reset signal provided by the total reset signal terminal tgoa_rst is the first potential. At this time, the first pull-down power signal provided by the first pull-down power terminal LVGL may be transmitted to the pull-up node PU to reset the pull-up node PU. And, the reset circuit 04 may control the first pull-down power supply terminal LVGL to be decoupled from the pull-up node PU when the potential of the total reset signal provided by the total reset signal terminal tgoa_rst is the second potential. Similarly, the reset circuit 04 may control the first pull-down power supply terminal LVGL to be turned on with the pull-up node PU when the first reset signal provided by the first reset signal terminal rst_1 has the first potential. At this time, the first pull-down power signal provided by the first pull-down power terminal LVGL may be transmitted to the pull-up node PU to reset the pull-up node PU. And, the reset circuit 04 may control the first pull-down power supply terminal LVGL to be decoupled from the pull-up node PU when the potential of the first reset signal provided by the first reset signal terminal rst_1 is the second potential. The reset circuit 04 may control the second pull-down power supply terminal VGL to be turned on with the driving output terminal OUT1 when the potential of the second reset signal supplied from the second reset signal terminal rst_2 is the first potential. At this time, the second pull-down power signal provided from the second pull-down power terminal VGL may be transmitted to the driving output terminal OUT1 to reset the driving output terminal OUT 1. And, the reset circuit 04 may control the second pull-down power supply terminal VGL to be decoupled from the driving output terminal OUT1 when the potential of the second reset signal supplied from the second reset signal terminal rst_2 is the second potential.

Alternatively, the potential of the first pull-down power supply signal and the potential of the second pull-down power supply signal may be both the second potential, and the potential of the first pull-down power supply signal may be smaller than the potential of the second pull-down power supply signal.

Each of the pull-down control circuits 05 may be coupled to the pull-up power supply terminal VDD, the INPUT signal terminal INPUT, the pull-up node PU, the first pull-down power supply terminal LVGL, and the pull-down node PD, respectively. Each pull-down control circuit 05 may be configured to control on-off of the pull-up power supply terminal VDD and the pull-down node PD based on a pull-up power supply signal provided by the pull-up power supply terminal VDD, and control on-off of the first pull-down power supply terminal LVGL and the pull-down node PD based on an input signal and a potential of the pull-up node PU.

For example, each of the pull-down control circuits 05 may control the pull-up power supply terminal VDD to be turned on with the pull-down node PD when the potential of the pull-up power supply signal supplied from the pull-up power supply terminal VDD is the first potential. At this time, the pull-up power signal provided from the pull-up power terminal VDD may be transmitted to the pull-down node PD. And, each of the pull-down control circuits 05 may control the pull-up power supply terminal VDD to be decoupled from the pull-down node PD when the potential of the pull-up power supply signal supplied from the pull-up power supply terminal VDD is the second potential. Similarly, each pull-down control circuit 05 may control the first pull-down power source terminal LVGL to be turned on with the pull-down node PD when the input signal has the first potential. At this time, the first pull-down power signal provided by the first pull-down power terminal LVGL may be transmitted to the pull-down node PD. And, each pull-down control circuit 05 may control the first pull-down power supply terminal LVGL to be decoupled from the pull-down node PD when the potential of the input signal is the second potential. Each pull-down control circuit 05 may control the first pull-down power source terminal LVGL to be turned on with the pull-down node PD when the potential of the pull-up node PU is the first potential. At this time, the first pull-down power signal provided by the first pull-down power terminal LVGL may be transmitted to the pull-down node PD. And, each pull-down control circuit 05 may control the first pull-down power source terminal LVGL to be decoupled from the pull-down node PD when the potential of the pull-up node PU is the second potential.

Each of the pull-down circuits 06 may be coupled to the pull-down node PD, the first pull-down power supply terminal LVGL, the second pull-down power supply terminal VGL, the pull-up node PU, the cascade output terminal out_c, and the driving output terminal OUT1, respectively. Each pull-down circuit 06 may be configured to control on/off of the first pull-down power supply terminal LVGL and the pull-up node PU, control on/off of the first pull-down power supply terminal LVGL and the cascade output terminal out_c, and control on/off of the second pull-down power supply terminal VGL and the driving output terminal OUT1 based on the potential of the pull-down node PD.

For example, each pull-down circuit 06 may control the first pull-down power supply terminal LVGL to be turned on with the pull-up node PU, control the first pull-down power supply terminal LVGL to be turned on with the cascade output terminal out_c, and control the second pull-down power supply terminal VGL to be turned on with the driving output terminal OUT1 when the potential of the pull-down node PD is the first potential. At this time, the first pull-down power signal provided from the first pull-down power terminal LVGL may be transmitted to the pull-up node PU and the cascade output terminal out_c, and the second pull-down power signal provided from the second pull-down power terminal VGL may be transmitted to the driving output terminal OUT1. And, each pull-down circuit 06 may control the first pull-down power supply terminal LVGL to be decoupled from the pull-up node PU, control the first pull-down power supply terminal LVGL to be decoupled from the cascade output terminal out_c, and control the second pull-down power supply terminal VGL to be decoupled from the driving output terminal OUT1 when the potential of the pull-down node PD is the second potential.

Alternatively, fig. 7 schematically shows two pull-down control circuits 05 and two pull-down circuits 06 in a one-to-one correspondence. And for distinction, the pull-up power terminals VDD coupled to the two pull-down control circuits 05 are respectively identified as vdd_a and vdd_b, and the coupled pull-down nodes PD are respectively identified as pd_a and pd_b. The pull-up power signal provided by the pull-up power terminal vdd_a and the pull-up power signal provided by the pull-up power terminal vdd_b may be exactly opposite, i.e., different in potential during the same period. In this way, each of the pull-down control circuits 05 and each of the pull-down circuits 06 can be made to operate alternately in time periods, ensuring a longer operating life of the shift register unit.

Optionally, fig. 8 is a schematic structural diagram of still another shift register unit provided in an embodiment of the disclosure. As shown in fig. 8, the first compensation sub-circuit 031 may include: a first transistor M1.

The gate of the first transistor M1 may be coupled to the pull-up node PU, the first pole of the first transistor M1 may be coupled to the clock signal terminal CLK, and the second pole of the first transistor M1 may be coupled to the control node V1.

Optionally, as can be seen with continued reference to fig. 8, the second compensation sub-circuit 032 may include: and a second transistor M2.

The gate of the second transistor M2 may be coupled to the control node V1, the first pole of the second transistor M2 may be coupled to the output signal terminal OUT, and the second pole of the second transistor M2 may be coupled to the INPUT signal terminal INPUT. In connection with fig. 7, here a first pole of the second transistor M2 may be coupled to a cascade output terminal out_c included in the output signal terminal OUT.

Alternatively, as can be seen with continued reference to fig. 8, the first output subcircuit 021 may include: and a third transistor M3. The second output sub-circuit 022 may include: a fourth transistor M4 and a storage capacitor C1.

The gate of the third transistor M3 may be coupled to the pull-up node PU, the first pole of the third transistor M3 may be coupled to the clock signal terminal CLK, and the second pole of the third transistor M3 may be coupled to the cascade output terminal out_c.

The gate of the fourth transistor M4 may be coupled to the pull-up node PU, the first pole of the fourth transistor M4 may be coupled to the clock signal terminal CLK, and the second pole of the fourth transistor M4 may be coupled to the driving output terminal OUT 1.

One end of the storage capacitor C1 may be coupled to the pull-up node PU, and the other end of the storage capacitor C1 may be coupled to the driving output terminal OUT 1.

Alternatively, as can be seen with continued reference to fig. 8, the reset circuit 04 may include: a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The pull-down control circuit 05 may include: an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The pull-down circuit 06 may include: an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13.

The gate of the fifth transistor M5 may be coupled to the total reset signal terminal tgoa_rst, the first pole of the fifth transistor M5 may be coupled to the first pull-down power terminal LVGL, and the second pole of the fifth transistor M5 may be coupled to the pull-up node PU.

The gate of the sixth transistor M6 may be coupled to the first reset signal terminal rst_1, the first pole of the sixth transistor M6 may be coupled to the first pull-down power terminal LVGL, and the second pole of the sixth transistor M6 may be coupled to the pull-up node PU.

A gate of the seventh transistor M7 may be coupled to the second reset signal terminal rst_2, a first pole of the seventh transistor M7 may be coupled to the second pull-down power terminal VGL, and a second pole of the seventh transistor M7 may be coupled to the driving output terminal OUT 1.

The gate and the first pole of the eighth transistor M8 may be both coupled to the pull-up power supply terminal VDD, and the second pole of the eighth transistor M8 may be coupled to the pull-down node PD.

A gate of the ninth transistor M9 may be coupled to the INPUT signal terminal INPUT, a first pole of the ninth transistor M9 may be coupled to the first pull-down power supply terminal LVGL, and a second pole of the ninth transistor M9 may be coupled to the pull-down node PD.

The gate of the tenth transistor M10 may be coupled to the pull-up node PU, the first pole of the tenth transistor M10 may be coupled to the first pull-down power supply terminal LVGL, and the second pole of the tenth transistor M10 may be coupled to the pull-down node PD.

The gate of the eleventh transistor M11 is coupled to the pull-down node PD, the first pole of the eleventh transistor M11 is coupled to the first pull-down power supply terminal LVGL, and the second pole of the eleventh transistor M11 is coupled to the pull-up node PU.

A gate of the twelfth transistor M12 may be coupled to the pull-down node PD, a first pole of the twelfth transistor M12 may be coupled to the first pull-down power supply terminal LVGL or the second pull-down power supply terminal VGL, and a second pole of the twelfth transistor M12 may be coupled to the cascade output terminal out_c.

For example, as shown in fig. 8, a pull-down circuit 06 includes a twelfth transistor m12_a having a first pole coupled to the first pull-down power supply terminal LVGL; the other pull-down circuit 06 includes a twelfth transistor m12_b having a first pole coupled to the second pull-down power terminal VGL.

A gate of the thirteenth transistor M13 may be coupled to the pull-down node PD, a first pole of the thirteenth transistor M13 may be coupled to the second pull-down power terminal VGL, and a second pole of the thirteenth transistor M13 may be coupled to the driving output terminal OUT 1.

Alternatively, as can be seen with continued reference to fig. 8, the input circuit 01 may include: fourteenth transistor M14.

The gate and the first pole of the fourteenth transistor M14 may be both coupled to the INPUT signal terminal INPUT, and the second pole of the fourteenth transistor M14 may be coupled to the pull-up node PU. As can be seen from this, the input circuit 01 according to the embodiment of the present disclosure includes the transistor connected to the gate source according to the embodiment.

Fig. 8 is a distinction, in which, of the two pull-down control circuits 05, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10 included in one pull-down control circuit 05 are respectively identified as m8_ A, M9_a and m10_a; the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 included in the other pull-down control circuit 05 are respectively identified as m8_ B, M9_b and m10_b. And, of the two pull-down circuits 06, an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13 included in one pull-down circuit 06 are respectively identified as m11_ A, M12_a and m13_a; the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 included in the other pull-down circuit 06 are respectively identified as m11_ B, M12_b and m13_b.

Optionally, the shift register unit protected by the embodiments of the present disclosure may include transistors that are all N-type transistors. On this basis, as described in the above embodiment, the first potential (i.e., the effective potential) may be a high potential, and the second potential (i.e., the ineffective potential) may be a low potential. The embodiment of the present disclosure mainly resides in the arrangement of the first transistor M1 and the second transistor M2. In addition, in addition to the 20T1C (i.e., 20 transistors and 1 capacitor) structure shown in fig. 8, the shift register unit according to the embodiment of the present disclosure may have other structures, such as 14T1C, but it is sufficient to include the fourteenth transistor M14, the first transistor M1 and the second transistor M2.

Fig. 9 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure, which may be used to drive the shift register unit shown in any one of fig. 4 to 8. As shown in fig. 9, the method includes:

step 901, in the input stage, the potential of the input signal provided by the input signal end is a first potential, the potential of the clock signal provided by the clock signal end is a second potential, the input circuit controls the input signal end to be conducted with the pull-up node based on the input signal, the output circuit controls the clock signal end to be conducted with the output signal end based on the potential of the pull-up node, and the compensation circuit controls the output signal end to be decoupled from the input signal end based on the potential of the pull-up node and the clock signal.

In step 902, in the output stage, the potential of the clock signal jumps from the second potential to the first potential, the potential of the pull-up node is kept at the first potential, the output circuit controls the clock signal terminal to be conducted with the output signal terminal based on the potential of the pull-up node, and the compensation circuit controls the output signal terminal to be conducted with the input signal terminal based on the potential of the pull-up node and the clock signal.

Alternatively, taking the structure shown in fig. 8, and the included transistors are N-type transistors, the first potential is a high potential VGH, and the second potential is a low potential VGL as an example, the working principle of the shift register unit provided in the embodiment of the disclosure is described as follows:

Fig. 10 provides a timing diagram of the operation of a shift register cell. As shown in fig. 10, first, in the INPUT stage t1, the INPUT signal provided by the INPUT signal terminal INPUT is at a high level, and the clock signal provided by the clock signal terminal CLK is at a low level. Accordingly, the fourteenth transistor M14 may be turned on. Further, an input signal of a high potential can be transmitted to the pull-up node PU through the fourteenth transistor M14, precharging the pull-up node PU, and also charging the storage capacitor C1. Accordingly, the third transistor M3, the fourth transistor M4 and the first transistor M1 are all turned on. The clock signal of the low potential may be transmitted to the cascade output terminal out_c through the third transistor M3, may be transmitted to the driving output terminal OUT1 through the fourth transistor M4, and may be transmitted to the control node V1 through the first transistor M1. Accordingly, the second transistor M2 may be turned off.

Next, in the output stage t2 after the input stage t1, the potential of the clock signal provided at this time by the clock signal terminal CLK may jump to a high potential. And, under the bootstrap action of the storage capacitor C1, the potential of the pull-up node PU can be further pulled up. As described in the above embodiment, the potential of the pull-up node PU may be pulled up to 2VGH. Accordingly, the third transistor M3, the fourth transistor M4, and the first transistor M1 may be further fully turned on. The clock signal of the high potential may be transmitted to the cascade output terminal out_c through the third transistor M3, may be transmitted to the driving output terminal OUT1 through the fourth transistor M4, and may be transmitted to the control node V1 through the first transistor M1. Accordingly, the second transistor M2 may be turned on. The clock signal of the high potential transmitted to the cascade output terminal out_c may be transmitted to the INPUT signal terminal INPUT through the second transistor M2, thereby implementing the compensation charging of the INPUT signal terminal INPUT such that the gate and source of the fourteenth transistor M14 are both close to VGH in potential. On this basis, even if the potential of the pull-up node PU is bootstrap-pulled up to 2VGH, i.e., the potential of the drain of the fourteenth transistor M14 is 2VGH, the source-drain voltage difference Vds of the fourteenth transistor M14 can be reduced to one VGH (i.e., 2 VGH-vgh=vgh). Compared with the prior art, the source-drain voltage difference Vds of the transistors in the input circuit is 2VGH-VGL, so that the source-drain voltage difference Vds can be greatly reduced. Further, the negative drift phenomenon of the characteristics of the fourteenth transistor M14 can be improved, and the potential leakage of the pull-up node PU can be avoided, i.e., the potential of the pull-up node PU can be ensured to be kept stable.

In addition, in the input stage t1 and the output stage t2, the potential of the total reset signal provided by the total reset signal terminal tgoa_rst, the potential of the first reset signal provided by the first reset signal terminal rst_1 and the potential of the second reset signal provided by the second reset signal terminal rst_2 may be both low, so that the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all turned off, the first pull-down power supply terminal LVGL is prevented from transmitting the first pull-down power supply signal of the low potential to the pull-up node PU, and the second pull-down power supply terminal VGL is prevented from transmitting the second pull-down power supply signal of the low potential to the driving output terminal OUT 1. In addition, since the potential of the pull-up node PU and the potential of the input signal are both high, the ninth transistor M9 and the tenth transistor M10 can be turned on, so that the first pull-down power source terminal LVGL transmits the first pull-down power source signal with low potential to the pull-down node PD. Accordingly, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 may be turned off to prevent the first pull-down power supply terminal LVGL from transmitting the first pull-down power supply signal of the low potential to the pull-up node PU and the cascade output terminal out_c, and to prevent the second pull-down power supply terminal VGL from transmitting the second pull-down power supply signal of the low potential to the driving output terminal OUT 1.

After the input stage t1 and the output stage t2, a reset stage may be further included. In the reset phase, first, the potential of the total reset signal provided by the total reset signal terminal tgoa_rst, the potential of the first reset signal provided by the first reset signal terminal rst_1 and the potential of the second reset signal provided by the second reset signal terminal rst_2 may be both high, so that the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are all controlled to be turned on, so that the first pull-down power supply terminal LVGL transmits a first pull-down power supply signal of a low potential to the pull-up node PU, and the second pull-down power supply terminal VGL transmits a second pull-down power supply signal of a low potential to the driving output terminal OUT 1. In addition, in the reset phase, the potential of the INPUT signal provided by the INPUT signal terminal INPUT may be low, and in combination with the potential of the pull-up node PU being low, both the ninth transistor M9 and the tenth transistor M10 may be turned off. Further, a pull-down power signal of high potential supplied from the pull-up power terminal VDD may be transmitted to the pull-down node PD through the turned-on eighth transistor M8. Accordingly, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 may be turned on such that the first pull-down power supply terminal LVGL may transmit the first pull-down power supply signal of the low potential to the pull-up node PU and the cascade output terminal out_c, and such that the second pull-down power supply terminal VGL may transmit the second pull-down power supply signal of the low potential to the driving output terminal OUT 1. Thereby achieving reliable reset of the pull-up node PU, the cascade output out_c and the drive output OUT 1.

In summary, the embodiments of the present disclosure provide a driving method of a shift register unit. In the method, in an input stage, an input circuit can control an input signal end to be conducted with a pull-up node based on an input signal, an output circuit can control a clock signal end to be conducted with an output signal end based on the potential of the pull-up node, and a compensation circuit can control the output signal end to be decoupled from the input signal end based on the potential of the pull-up node and the clock signal. In the output stage, the output circuit can control the conduction of the clock signal end and the output signal end based on the potential of the pull-up node, and the compensation circuit can control the conduction of the output signal end and the input signal end based on the potential of the pull-up node and the clock signal. In this way, the voltage difference between the input signal end and the pull-up node can be reduced in the stage that the pull-up node is pulled up by the bootstrap of the capacitor in the output circuit, namely the source-drain voltage difference of the transistor in the input circuit is reduced. Furthermore, the transistors in the input circuit can be prevented from negative drift.

Fig. 11 is a schematic structural diagram of a panel driving circuit according to an embodiment of the present disclosure. As shown in fig. 11, the panel driving circuit includes: at least two shift register units 00 as shown in any one of fig. 4 to 8.

Alternatively, taking the structure shown in fig. 8 as an example, in the embodiment of the present disclosure, the cascade output terminal out_c of the shift register unit 00 of the current stage may be cascaded with the INPUT signal terminal INPUT of the shift register unit 00 of the next stage; the driving output OUT1 of the current stage shift register unit 00 may be coupled to a pixel. For the first stage shift register unit 00, the INPUT signal terminal INPUT may be coupled to the on signal terminal STV to receive the on INPUT signal provided by the on signal terminal STV, thereby implementing a cascade output.

For example, as described in the above embodiments, the driving output terminal OUT1 of the current stage shift register unit 00 may be coupled to the Gate line Gate to be indirectly coupled to the pixel through the Gate line Gate. On this basis, the panel driving circuit may also be referred to as a gate driving circuit. Of course, in some other embodiments, the driving output OUT1 of the current stage shift register unit 00 may also be coupled to the pixel through the light emitting control line EM. On this basis, the panel driving circuit may also be referred to as a light emitting driving circuit.

Fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 12, the display device includes: a display panel 100, and a panel driving circuit 000 as shown in fig. 11.

The display panel 100 includes a plurality of pixels P1, and the panel driving circuit 000 may be coupled to the plurality of pixels P1 and configured to transmit a light emission driving signal to the plurality of pixels P1 to drive the plurality of pixels P1 to emit light.

For example, assuming that the panel driving circuit 000 is a Gate driving circuit as described in the above embodiments, the panel driving circuit 000 may be coupled to the plurality of pixels P1 through the plurality of Gate lines Gate as shown in fig. 12 and used to transmit a Gate driving signal (which is one of light emission driving signals) to the plurality of pixels P1 to drive the plurality of pixels P1 to emit light.

Alternatively, the display device may be: an organic light-emitting diode (OLED) display device, electronic paper, mobile phone, tablet computer, television, display, notebook computer, navigator, or any other product or component having a display function.

It is to be understood that the terminology used in the description of the embodiments of the disclosure is for the purpose of describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed.

"connected" or "coupled" refers to electrical connections. "and/or" means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working processes of the gate driving circuit, the shift register unit, each circuit and each sub-circuit described above may refer to corresponding processes in the method embodiments, and are not described herein again.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims

1. A shift register unit, characterized in that the shift register unit comprises:

2. The shift register unit according to claim 1, wherein the compensation circuit comprises:

3. The shift register unit of claim 2, wherein the first compensation sub-circuit comprises: a first transistor;

4. The shift register unit of claim 2, wherein the second compensation sub-circuit comprises: a second transistor;

5. A shift register unit as claimed in any one of claims 1 to 4, in which the output signal terminal comprises: the cascade output end is used for being coupled with a next-stage shift register unit, and the driving output end is used for being coupled with a pixel; the output circuit includes:

6. The shift register cell of claim 5, wherein the first output sub-circuit comprises: a third transistor; the second output sub-circuit includes: a fourth transistor and a storage capacitor;

7. The shift register unit of claim 5, wherein the shift register unit further comprises:

8. The shift register unit according to claim 7, wherein the reset circuit comprises: a fifth transistor, a sixth transistor, and a seventh transistor; the pull-down control circuit includes: an eighth transistor, a ninth transistor, and a tenth transistor; the pull-down circuit includes: an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the input circuit includes: a fourteenth transistor;

9. A driving method of a shift register unit, characterized by driving a shift register unit according to any one of claims 1 to 8, the method comprising:

10. A panel drive circuit, the panel drive circuit comprising: at least two cascaded shift register cells according to any of claims 1 to 8.

11. A display device, characterized in that the display device comprises: a display panel, and the panel driving circuit according to claim 10;