CN117809550A

CN117809550A - Shift register unit and driving method thereof, light-emitting driving circuit and display device

Info

Publication number: CN117809550A
Application number: CN202410009714.2A
Authority: CN
Inventors: 韩承佑; 李卓; 冯煊; 张慧; 刘立伟; 杨明; 张定昌; 玄明花
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2024-01-02
Filing date: 2024-01-02
Publication date: 2024-04-02

Abstract

A shift register unit, a driving method thereof, a light-emitting driving circuit and a display device are provided, and belong to the technical field of display. In the shift register unit, the input circuit can respectively control the potentials of two pull-up nodes under the control of signal ends such as a first clock end, a second clock end, a first power end, a second power end, a starting end, a pull-down end and the like. The pull-down circuit can control the potential of the pull-down node under the control of the potentials of the two pull-up nodes, the third clock end, the first reset end, the second reset end and other signal ends. The output circuit can control the pull-up end to transmit pull-up signals to the output end under the potential control of the two pull-up nodes, and can control the pull-down end to transmit pull-down signals to the output end under the potential control of the pull-down nodes. Therefore, the problem of poor output stability caused by the characteristic deviation of the transistors in each circuit can be avoided by flexibly setting the signals provided by each signal terminal so as to reliably adjust the output signals.

Description

Shift register unit and driving method thereof, light-emitting driving circuit and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a shift register unit, a driving method thereof, a light-emitting driving circuit and a display device.

Background

The light-emitting driving circuit is coupled with the pixel circuits in the display panel and is used for providing a light-emitting control signal for the pixel circuits to drive the coupled light-emitting elements to emit light.

In the related art, an array substrate row driving (gate drive on array, GOA) technology is often used to integrate a light Emitting (EM) driving circuit on a display panel, so as to facilitate the design of a narrow frame of the display device. That is, as with the gate driving circuit, the current light emitting driving circuit generally includes a plurality of EM GOA cells, abbreviated as EOA cells (also referred to as shift register cells) in cascade. Also, EOA cells in light emitting driving circuits typically include N-type transistors made of multiple oxide (oxide) materials or P-type transistors made of multiple polysilicon (Poly-Si) materials.

However, the characteristics (e.g., threshold voltage) of transistors in EOA cells included in current light emitting driving circuits are easily shifted due to material characteristics. In this way, the output stability of the light-emitting driving circuit is poor.

Disclosure of Invention

A shift register unit, a driving method thereof, a light-emitting driving circuit and a display device are provided, which can solve the problem of poor output stability of the light-emitting driving circuit in the related art. The technical scheme is as follows:

in one aspect, there is provided a shift register unit including:

the input circuit is respectively coupled with a first clock end, a second clock end, a first power end, a second power end, a starting end, a pull-down end, a first pull-up node and a second pull-up node, and is used for controlling the on-off of the starting end and the first pull-up node in response to a first clock signal provided by the first clock end, controlling the on-off of the pull-down end and the first pull-up node in response to a second power signal provided by the second power end, regulating the potential of the first pull-up node based on a first power signal provided by the first power end, controlling the on-off of the starting end and the second pull-up node in response to a second clock signal provided by the second clock end, controlling the on-off of the pull-down end and the second pull-up node in response to the first power signal, and regulating the potential of the second pull-up node based on the second power signal;

The pull-down circuit is respectively coupled with a third clock end, the first pull-up node, the second pull-up node, the pull-down end, a first reset end, a second reset end and the pull-down node, and is used for controlling the on-off of the third clock end and the pull-down node in response to a third clock signal provided by the third clock end, a first reset signal provided by the first reset end and a second reset signal provided by the second reset end, controlling the on-off of the pull-down end and the pull-down node in response to the potential of the first pull-up node, and controlling the on-off of the pull-down end and the pull-down node in response to the potential of the second pull-up node;

and the output circuit is respectively coupled with the first pull-up node, the second pull-up node, the pull-down node, the pull-up end, the pull-down end and the output end, and is used for controlling the on-off of the pull-up end and the output end in response to the potential of the first pull-up node, controlling the on-off of the pull-up end and the output end in response to the potential of the second pull-up node and controlling the on-off of the pull-down end and the output end in response to the potential of the pull-down node.

Optionally, the input circuit includes:

the first input sub-circuit is respectively coupled with the first clock end, the first power end, the second power end, the starting end, the pull-down end and the first pull-up node, and is used for controlling the on-off of the starting end and the first pull-up node in response to the first clock signal, controlling the on-off of the pull-down end and the first pull-up node in response to the second power signal and regulating the potential of the first pull-up node based on the first power signal;

and the second input sub-circuit is respectively coupled with the second clock end, the first power end, the second power end, the starting end, the pull-down end and the second pull-up node, and is used for controlling the on-off of the starting end and the second pull-up node in response to the second clock signal, controlling the on-off of the pull-down end and the second pull-up node in response to the first power signal and regulating the potential of the second pull-up node based on the second power signal.

Optionally, the first input sub-circuit includes: a first transistor, a second transistor, and a first capacitor;

the grid electrode of the first transistor is coupled with the first clock end, the first pole of the first transistor is coupled with the starting end, and the second pole of the first transistor is coupled with the first pull-up node;

The grid electrode of the second transistor is coupled with the second power supply end, the first electrode of the second transistor is coupled with the pull-down end, and the second electrode of the second transistor is coupled with the first pull-up node;

the first end of the first capacitor is coupled to the first power supply terminal, and the second end of the first capacitor is coupled to the first pull-up node.

Optionally, the second input sub-circuit includes: a third transistor, a fourth transistor, and a second capacitor;

a gate of the third transistor is coupled to the second clock terminal, a first pole of the third transistor is coupled to the start terminal, and a second pole of the third transistor is coupled to the second pull-up node;

a gate of the fourth transistor is coupled to the first power supply terminal, a first pole of the fourth transistor is coupled to the pull-down terminal, and a second pole of the fourth transistor is coupled to the second pull-up node;

the first end of the second capacitor is coupled to the second power supply terminal, and the second end of the second capacitor is coupled to the second pull-up node.

Optionally, the pull-down circuit includes:

a pull-down control sub-circuit coupled to the third clock terminal, the first reset terminal, the second reset terminal, the pull-down terminal, and a pull-down control node, respectively, for controlling on-off of the pull-down terminal and the pull-down control node in response to the first reset signal and the second reset signal, and adjusting a potential of the pull-down control node based on the third clock signal;

And the pull-down sub-circuit is respectively coupled with the pull-down control node, the third clock end, the first pull-up node, the second pull-up node, the pull-down node and the pull-down end, and is used for controlling the on-off of the third clock end and the pull-down node in response to the potential of the pull-down control node, controlling the on-off of the pull-down end and the pull-down node in response to the potential of the first pull-up node and controlling the on-off of the pull-down end and the pull-down node in response to the potential of the second pull-up node.

Optionally, the pull-down control sub-circuit includes: a fifth transistor, a sixth transistor, and a third capacitor;

a gate of the fifth transistor is coupled to the first reset terminal, a first pole of the fifth transistor is coupled to the pull-down terminal, and a second pole of the fifth transistor is coupled to the pull-down control node;

a gate of the sixth transistor is coupled to the second reset terminal, a first pole of the sixth transistor is coupled to the pull-down terminal, and a second pole of the sixth transistor is coupled to the pull-down control node;

the first end of the third capacitor is coupled with the third clock end, and the second end of the third capacitor is coupled with the pull-down control node.

Optionally, the pull-down sub-circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor;

a gate of the seventh transistor is coupled to the pull-down control node, a first pole of the seventh transistor is coupled to the third clock terminal, and a second pole of the seventh transistor is coupled to the pull-down node;

a gate of the eighth transistor is coupled to the first pull-up node, a first pole of the eighth transistor is coupled to the pull-down terminal, and a second pole of the eighth transistor is coupled to the pull-down node;

the gate of the ninth transistor is coupled to the second pull-up node, the first pole of the ninth transistor is coupled to the pull-down terminal, and the second pole of the ninth transistor is coupled to the pull-down node.

Optionally, the output circuit includes:

the first output subcircuit is respectively coupled with the first pull-up node, the pull-up end and the output end and is used for responding to the potential of the first pull-up node to control the on-off of the pull-up end and the output end;

the second output subcircuit is respectively coupled with the second pull-up node, the pull-up end and the output end and is used for responding to the potential of the second pull-up node to control the on-off of the pull-up end and the output end;

And the third output subcircuit is respectively coupled with the pull-down node, the pull-down end and the output end and is used for responding to the potential of the pull-down node to control the on-off of the pull-down end and the output end.

Optionally, the first output sub-circuit includes: a tenth transistor and a fourth capacitor; the second output sub-circuit includes: an eleventh transistor and a fifth capacitor; the third output sub-circuit includes: a twelfth transistor and a sixth capacitor;

a gate of the tenth transistor is coupled to the first pull-up node, a first pole of the tenth transistor is coupled to the pull-up terminal, and a second pole of the tenth transistor is coupled to the output terminal;

a first end of the fourth capacitor is coupled with the first pull-up node, and a second end of the fourth capacitor is coupled with the output end;

a gate of the eleventh transistor is coupled to the second pull-up node, a first pole of the eleventh transistor is coupled to the pull-up terminal, and a second pole of the eleventh transistor is coupled to the output terminal;

a first end of the fifth capacitor is coupled with the second pull-up node, and a second end of the fifth capacitor is coupled with the output end;

A gate of the twelfth transistor is coupled to the pull-down node, a first pole of the twelfth transistor is coupled to the pull-down terminal, and a second pole of the twelfth transistor is coupled to the output terminal;

the first end of the sixth capacitor is coupled to the pull-down node, and the second end of the sixth capacitor is coupled to the pull-down terminal.

Optionally, the twelfth transistor includes: two transistors connected in series between the output terminal and the pull-down terminal; the shift register unit further includes:

and the anti-leakage circuit is respectively coupled with the first pull-up node, the second pull-up node, the pull-up end and a series node of two transistors connected in series in the twelfth transistor, and is used for controlling the on-off of the pull-up end and the series node in response to the potential of the first pull-up node and controlling the on-off of the pull-up end and the series node in response to the potential of the second pull-up node.

Optionally, the anti-leakage circuit includes: a thirteenth transistor and a fourteenth transistor;

a gate of the thirteenth transistor is coupled to the first pull-up node, a first pole of the thirteenth transistor is coupled to the pull-up terminal, and a second pole of the thirteenth transistor is coupled to the series node;

The gate of the fourteenth transistor is coupled to the second pull-up node, the first pole of the fourteenth transistor is coupled to the pull-up terminal, and the second pole of the fourteenth transistor is coupled to the series node.

Optionally, the output terminal is configured to be coupled to a light emission control terminal of the pixel circuit;

and, each transistor in the shift register unit includes: an N-type oxide transistor.

In another aspect, there is provided a driving method of a shift register unit for driving the shift register unit as described in the above aspect, the method comprising:

the first stage, the potential of the first power signal provided by the first power end and the potential of the first clock signal provided by the first clock end are both first potentials, and the potential of the second power signal provided by the second power end and the potential of the second clock signal provided by the second clock end are both second potentials; the input circuit controls the starting end to be conducted with a first pull-up node in response to the first clock signal, and controls the pull-down end to be conducted with a second pull-up node in response to the first power signal, and the potential of the starting signal provided by the starting end is a first potential; the pull-down circuit responds to the potential of the first pull-up node to control the pull-down end to be conducted with the pull-down node; the output circuit responds to the potential of the first pull-up node to control the pull-up end to be conducted with the output end;

A second stage, wherein the potential of the second power supply signal and the potential of the second clock signal are the first potential, and the potential of the first power supply signal and the potential of the first time signal are the second potential; the input circuit controls the starting end to be conducted with the second pull-up node in response to the second clock signal, and controls the pull-down end to be conducted with the first pull-up node in response to the second power signal, and the potential of the starting signal is a second potential; the pull-down circuit responds to a third clock signal provided by a third clock end to control the third clock end to be conducted with the pull-down node, and the potential of the third clock signal is a first potential; the output circuit responds to the potential of the pull-down node to control the pull-down end to be conducted with the output end.

In still another aspect, there is provided a light emission driving circuit including: at least two cascaded shift register units as described in the above aspect.

In still another aspect, there is provided a display device including: a display panel, and a light-emitting drive circuit as described in the above further aspect; the display panel includes a plurality of pixels; the pixel includes a pixel circuit and a light emitting element;

The light-emitting driving circuit is coupled with the pixel circuit and is used for transmitting a light-emitting driving signal for the pixel circuit;

the pixel circuit is also coupled to the light emitting element and is configured to drive the light emitting element to emit light in response to the light emission control signal.

In summary, the beneficial effects brought by the technical solution provided by the embodiments of the present disclosure at least may include:

a shift register unit, a driving method thereof, a light emitting driving circuit, and a display device are provided. In the shift register unit, the input circuit can respectively control the potentials of two pull-up nodes under the control of signal ends such as a first clock end, a second clock end, a first power end, a second power end, a starting end, a pull-down end and the like. The pull-down circuit can control the potential of the pull-down node under the control of the potentials of the two pull-up nodes, the third clock end, the first reset end, the second reset end and other signal ends. The output circuit can control the pull-up end to transmit pull-up signals to the output end under the potential control of the two pull-up nodes, and can control the pull-down end to transmit pull-down signals to the output end under the potential control of the pull-down nodes. Therefore, the problem of poor output stability caused by the characteristic deviation of the transistors in each circuit can be avoided by flexibly setting the signals provided by each signal terminal so as to reliably adjust the output signals.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a shift register unit according to another embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of a shift register unit according to an embodiment of the disclosure;

fig. 6 is a schematic circuit diagram of another shift register unit according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of signal timing of a pixel circuit according to an embodiment of the disclosure;

Fig. 9 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure;

fig. 10 is a schematic signal timing diagram of a shift register unit according to an embodiment of the disclosure;

fig. 11 is an equivalent circuit diagram of the shift register unit shown in fig. 6 in a first stage;

fig. 12 is an equivalent circuit diagram of the shift register unit shown in fig. 6 in a second stage;

fig. 13 is an equivalent circuit diagram of the shift register unit shown in fig. 6 at a third stage;

fig. 14 is an equivalent circuit diagram of the shift register unit shown in fig. 6 at a fourth stage;

fig. 15 is an equivalent circuit diagram of the shift register unit shown in fig. 6 at a fifth stage;

fig. 16 is an equivalent circuit diagram of the shift register unit shown in fig. 6 at a sixth stage;

fig. 17 is an equivalent circuit diagram of the shift register unit shown in fig. 6 at an eleventh stage;

fig. 18 is an equivalent circuit diagram of the shift register unit shown in fig. 6 at a twelfth stage;

FIG. 19 is a schematic diagram illustrating a signal timing simulation of a shift register unit according to an embodiment of the present disclosure;

fig. 20 is a schematic diagram of a structure of a light-emitting driving circuit according to an embodiment of the present disclosure;

fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

For the purposes of clarity, technical solutions and advantages of the present disclosure, the following further details the embodiments of the present disclosure with reference to the accompanying drawings.

The transistors employed in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices of the same characteristics, and the transistors employed in the embodiments of the present disclosure are primarily switching transistors according to their role in the circuit. Since the source and drain of the switching transistor employed herein are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first pole and the drain is referred to as a second pole. The middle terminal of the transistor is defined as a control electrode according to the form in the figure, and may be called a gate electrode, a signal input terminal as a source electrode, and a signal output terminal as a drain electrode. In addition, the switching transistor used in the embodiments of the present disclosure may include any one of a P-type switching transistor that is turned on when the gate is at a low level, turned off when the gate is at a high level, and an N-type switching transistor that is turned on when the gate is at a high level, and turned off when the gate is at a low level. Further, the plurality of signals in the various embodiments of the present disclosure each correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has 2 state quantities, and do not represent that the first potential or the second potential has a specific value in the whole text.

Fig. 1 is a schematic structural diagram of a shift register unit according to an embodiment of the present disclosure. As shown in fig. 1, the shift register unit includes: an input circuit 01, a pull-down circuit 02 and an output circuit 03.

The input circuit 01 is coupled to the first clock terminal p_eck1, the second clock terminal p_eck2, the first power terminal VDD1, the second power terminal VDD2, the start terminal ESTV, the pull-down terminal VGL, the first pull-up node PU1 and the second pull-up node PU2, respectively. The input circuit 01 is configured to control on/off of the start end escv and the first pull-up node PU1 in response to a first clock signal provided by the first clock end p_eck1, control on/off of the pull-down end VGL and the first pull-up node PU1 in response to a second power signal provided by the second power end VDD2, adjust a potential of the first pull-up node PU1 based on the first power signal provided by the first power end VDD1, control on/off of the start end escv and the second pull-up node PU2 in response to a second clock signal provided by the second clock end p_eck2, control on/off of the pull-down end VGL and the second pull-up node PU2 in response to the first power signal, and adjust a potential of the second pull-up node PU2 based on the second power signal.

For example, the input circuit 01 can control the start end escv to be turned on with the first pull-up node PU1 when the first clock signal provided by the first clock end p_eck1 has the first potential, so that the start signal provided by the start end escv is transmitted to the first pull-up node PU1. And, the input circuit 01 is capable of controlling the start end ESTV to be decoupled from the first pull-up node PU1 when the potential of the first clock signal is the second potential. Similarly, when the potential of the second power signal provided by the second power terminal VDD2 is the first potential, the input circuit 01 can control the pull-down terminal VGL to be conducted with the first pull-up node PU1, so that the pull-down signal provided by the pull-down terminal VGL is transmitted to the first pull-up node PU1. And, the input circuit 01 is capable of controlling the pull-down terminal VGL to be decoupled from the first pull-up node PU1 when the potential of the second power signal is the second potential. In addition, the input circuit 01 is also capable of adjusting the potential of the first pull-up node PU1 based on the first power signal provided by the first power terminal VDD1 through the coupling.

For example, the input circuit 01 can control the start end escv to be turned on with the second pull-up node PU2 when the potential of the second clock signal provided by the second clock end p_eck2 is the first potential, so that the start signal is transmitted to the second pull-up node PU2. And, the input circuit 01 is capable of controlling the start end ESTV to be decoupled from the second pull-up node PU2 when the potential of the second clock signal is the second potential. Similarly, when the potential of the first power signal is the first potential, the input circuit 01 can control the pull-down terminal VGL to be conducted with the second pull-up node PU2, so that the pull-down signal is transmitted to the second pull-up node PU2. And, the input circuit 01 is capable of controlling the pull-down terminal VGL to be decoupled from the second pull-up node PU2 when the potential of the first power signal is the second potential. The input circuit 01 is also capable of adjusting the potential of the second pull-up node PU2 based on the second power supply signal by coupling.

Alternatively, in an embodiment of the present disclosure, the first potential may be an active potential and the second potential may be an inactive potential. The first potential may be a high potential, and the second potential may be a low potential, that is, the first potential is larger than the second potential. The transistors in the circuit corresponding to the potential may be N-type transistors. If the transistors in the circuit are P-type transistors, the first potential may be low and the second potential may be high, i.e., the first potential is smaller than the second potential.

With continued reference to fig. 1, the pull-down circuit 02 is coupled to the third clock terminal ECK, the first pull-up node PU1, the second pull-up node PU2, the pull-down terminal VGL, the first reset terminal R1, the second reset terminal R2, and the pull-down node PD, respectively. The pull-down circuit 02 is configured to control on-off of the third clock terminal ECK and the pull-down node PD in response to a third clock signal provided by the third clock terminal ECK, a first reset signal provided by the first reset terminal R1, and a second reset signal provided by the second reset terminal R2, control on-off of the pull-down terminal VGL and the pull-down node PD in response to a potential of the first pull-up node PU1, and control on-off of the pull-down terminal VGL and the pull-down node PD in response to a potential of the second pull-up node PU 2.

For example, the pull-down circuit 02 may control the third clock terminal ECK to be in conduction with the pull-down node PD when the potential of the third clock signal provided by the third clock terminal ECK is the first potential, and the potential of the first reset signal provided by the first reset terminal R1 and the potential of the second reset signal provided by the second reset terminal R2 are the second potential, so that the third clock terminal ECK is in conduction with the pull-down node PD. And, the pull-down circuit 02 can control the third clock terminal ECK to be decoupled from the pull-down node PD when the potential of the third clock signal is the second potential and the potential of the first reset signal and/or the potential of the second reset signal is the first potential. Similarly, the pull-down circuit 02 can control the pull-down terminal VGL to be connected to the pull-down node PD when the potential of the first pull-up node PU1 is the first potential, so that the pull-down signal is transmitted to the pull-down node PD. And, the pull-down circuit 02 can control the pull-down terminal VGL to be decoupled from the pull-down node PD when the potential of the first pull-up node PU1 is the second potential. And, the pull-down circuit 02 can control the pull-down terminal VGL to be conducted with the pull-down node PD when the potential of the second pull-up node PU2 is the first potential, so that the pull-down signal is transmitted to the pull-down node PD. And, the pull-down circuit 02 can control the pull-down terminal VGL to be decoupled from the pull-down node PD when the potential of the second pull-up node PU2 is the second potential.

Optionally, the display device includes N shift register units in cascade. The first reset terminal R1 may be coupled with a first pull-up node PU1 (n-1) of a cascaded upper stage shift register unit; the second reset terminal R2 may be coupled to a second pull-up node PU2 (n-1) of the cascaded last stage shift register unit. Wherein N is an integer greater than 1; n is greater than 0 and less than or equal to N.

The output circuit 03 is coupled to the first pull-up node PU1, the second pull-up node PU2, the pull-down node PD, the pull-up terminal VGH, the pull-down terminal VGL, and the output terminal Eout, respectively. The output circuit 03 is configured to control on/off of the pull-up terminal VGH and the output terminal Eout in response to the potential of the first pull-up node PU1, control on/off of the pull-up terminal VGH and the output terminal Eout in response to the potential of the second pull-up node PU2, and control on/off of the pull-down terminal VGL and the output terminal Eout in response to the potential of the pull-down node PD.

For example, the output circuit 03 can control the pull-up terminal VGH to be conducted with the output terminal Eout when the potential of the first pull-up node PU1 is the first potential, so that the pull-up signal provided by the pull-up terminal VGH is transmitted to the output terminal Eout. And, the output circuit 03 can control the pull-up terminal VGH to be decoupled from the output terminal Eout when the potential of the first pull-up node PU1 is the second potential. Similarly, when the potential of the second pull-up node PU2 is the first potential, the output circuit 03 can control the pull-up terminal VGH to be connected to the output terminal Eout, so that the pull-up signal is transmitted to the output terminal Eout. And, the output circuit 03 can control the pull-up terminal VGH to be decoupled from the output terminal Eout when the potential of the second pull-up node PU2 is the second potential. And, the output circuit 03 can control the pull-down terminal VGL to be conducted with the output terminal Eout when the potential of the pull-down node PD is the first potential, so that the pull-down signal is transmitted to the output terminal Eout. And, the output circuit 03 can control the pull-down terminal VGL to be decoupled from the output terminal Eout when the potential of the pull-down node PD is the second potential.

In summary, the embodiments of the present disclosure provide a shift register unit. The shift register unit includes an input circuit, a pull-down circuit, and an output circuit. The input circuit can respectively control the electric potentials of the two pull-up nodes under the control of signals provided by signal ends such as a first clock end, a second clock end, a first power end, a second power end, a starting end, a pull-down end and the like. The pull-down circuit can control the potential of the pull-down node under the control of the potentials of the two pull-up nodes and signals provided by signal ends such as the third clock end, the first reset end, the second reset end and the like. The output circuit can control the pull-up end to transmit pull-up signals to the output end under the potential control of the two pull-up nodes, and can control the pull-down end to transmit pull-down signals to the output end under the potential control of the pull-down nodes. Therefore, the problem of poor output stability caused by the characteristic deviation of the transistors in each circuit can be avoided by flexibly setting the signals provided by each signal terminal so as to reliably adjust the output signals.

Fig. 2 is a schematic diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 2, the input circuit 01 may include: a first input sub-circuit 011 and a second input sub-circuit 012. That is, the shift register unit provided by the embodiments of the present disclosure may be a dual input structure.

The first input sub-circuit 011 may be coupled to the first clock terminal p_eck1, the first power terminal VDD1, the second power terminal VDD2, the start terminal ESTV, the pull-down terminal VGL and the first pull-up node PU1, respectively. The first input sub-circuit 011 may be configured to control the on-off of the start end escv and the first pull-up node PU1 in response to the first clock signal, control the on-off of the pull-down end VGL and the first pull-up node PU1 in response to the second power signal, and adjust the potential of the first pull-up node PU1 based on the first power signal.

For example, the first input sub-circuit 011 can control the start end ESTV to be conducted with the first pull-up node PU1 when the first clock signal has the first potential, so that the start signal is transmitted to the first pull-up node PU1. And, the first input sub-circuit 011 can control the start-end ESTV to be decoupled from the first pull-up node PU1 when the potential of the first clock signal is the second potential. Similarly, the first input sub-circuit 011 can control the pull-down terminal VGL to be conducted with the first pull-up node PU1 when the potential of the second power signal is the first potential, so that the pull-down signal is transmitted to the first pull-up node PU1. And, the first input sub-circuit 011 can control the pull-down terminal VGL to be decoupled from the first pull-up node PU1 when the potential of the second power signal is the second potential. In addition, the first input sub-circuit 011 is also capable of adjusting the potential of the first pull-up node PU1 based on the first power supply signal by coupling.

The second input sub-circuit 012 may be coupled to the second clock terminal p_eck2, the first power terminal VDD1, the second power terminal VDD2, the start terminal ESTV, the pull-down terminal VGL, and the second pull-up node PU2, respectively. The second input subcircuit 012 may be used to control the on-off of the start end ESTV and the second pull-up node PU2 in response to the second clock signal, control the on-off of the pull-down end VGL and the second pull-up node PU2 in response to the first power signal, and adjust the potential of the second pull-up node PU2 based on the second power signal.

For example, the second input sub-circuit 012 can control the start end escv to be conducted with the second pull-up node PU2 when the potential of the second clock signal is the first potential, so that the start signal is transmitted to the second pull-up node PU2. And, the second input sub-circuit 012 can control the start end escv to be decoupled from the second pull-up node PU2 when the potential of the second clock signal is the second potential. Similarly, the second input sub-circuit 012 can control the pull-down terminal VGL to be conducted with the second pull-up node PU2 when the potential of the first power signal is the first potential, so that the pull-down signal is transmitted to the second pull-up node PU2. And, the second input sub-circuit 012 can control the pull-down terminal VGL to be decoupled from the second pull-up node PU2 when the potential of the first power signal is the second potential. The second input subcircuit 012 is also able to adjust the potential of the second pull-up node PU2 based on the second power supply signal by way of coupling.

Fig. 3 is a schematic structural diagram of another shift register unit according to an embodiment of the present disclosure. As shown in fig. 3, the pull-down circuit 02 may include: a pull-down control sub-circuit 021 and a pull-down sub-circuit 022.

The pull-down control sub-circuit 021 may be coupled to the third clock terminal ECK, the first reset terminal R1, the second reset terminal R2, the pull-down terminal VGL, and the pull-down control node pd_c, respectively. The pull-down control sub-circuit 021 may be used to control the on-off of the pull-down terminal VGL and the pull-down control node pd_c in response to the first reset signal and the second reset signal, and adjust the potential of the pull-down control node pd_c based on the third clock signal.

For example, the pull-down control sub-circuit 021 can control the pull-down terminal VGL to be conductive to the pull-down control node pd_c when the potential of the first reset signal and/or the potential of the second reset signal is the first potential, so that the pull-down signal is transmitted to the pull-down control node pd_c. And, the pull-down control sub-circuit 021 can control the pull-down terminal VGL to be decoupled from the pull-down control node pd_c when the potential of the first reset signal and the potential of the second reset signal are both the second potentials. In addition, the pull-down control sub-circuit 021 can also adjust the potential of the pull-down control node pd_c based on the third clock signal by the coupling action.

The pull-down sub-circuit 022 may be coupled to the pull-down control node pd_c, the third clock terminal ECK, the first pull-up node PU1, the second pull-up node PU2, the pull-down node PD, and the pull-down terminal VGL, respectively. The pull-down sub-circuit 022 may be configured to control the on-off of the third clock terminal ECK and the pull-down node PD in response to the potential of the pull-down control node pd_c, control the on-off of the pull-down terminal VGL and the pull-down node PD in response to the potential of the first pull-up node PU1, and control the on-off of the pull-down terminal VGL and the pull-down node PD in response to the potential of the second pull-up node PU 2.

For example, the pull-down sub-circuit 022 may control the third clock terminal ECK to be conductive with the pull-down node PD when the potential of the pull-down control node pd_c is the first potential, so that the third clock signal is transmitted to the pull-down node PD. And, the pull-down sub-circuit 022 may control the third clock terminal ECK to be decoupled from the pull-down node PD when the potential of the pull-down control node pd_c is the second potential. Similarly, the pull-down sub-circuit 022 may control the pull-down terminal VGL to be turned on with the pull-down node PD when the potential of the first pull-up node PU1 is the first potential, so that the pull-down signal is transmitted to the pull-down node PD. And, the pull-down sub-circuit 022 may control the pull-down terminal VGL to be decoupled from the pull-down node PD when the potential of the first pull-up node PU1 is the second potential. And, the pull-down sub-circuit 022 may control the pull-down terminal VGL to be conducted with the pull-down node PD when the potential of the second pull-up node PU2 is the first potential, so that the pull-down signal is transmitted to the pull-down node PD. And, the pull-down sub-circuit 022 may control the pull-down terminal VGL to be decoupled from the pull-down node PD when the potential of the second pull-up node PU2 is the second potential.

Fig. 4 is a schematic structural diagram of still another shift register unit according to an embodiment of the present disclosure. As shown in fig. 4, the output circuit 03 may include: a first output sub-circuit 031, a second output sub-circuit 032, and a third output sub-circuit 033.

The first output sub-circuit 031 may be coupled to the first pull-up node PU1, the pull-up terminal VGH, and the output terminal Eout, respectively. The first output sub-circuit 031 may be configured to control the on/off of the pull-up terminal VGH and the output terminal Eout in response to the potential of the first pull-up node PU 1.

For example, the first output sub-circuit 031 can control the pull-up terminal VGH to be conducted with the output terminal Eout when the potential of the first pull-up node PU1 is the first potential, so that the pull-up signal is transmitted to the output terminal Eout. And, the first output sub-circuit 031 can control the pull-up terminal VGH to be decoupled from the output terminal Eout when the potential of the first pull-up node PU1 is the second potential.

The second output sub-circuit 032 may be coupled to the second pull-up node PU2, the pull-up terminal VGH, and the output terminal Eout, respectively. The second output sub-circuit 032 may be used to control the on-off of the pull-up terminal VGH and the output terminal Eout in response to the potential of the second pull-up node PU 2.

For example, the second output sub-circuit 032 can control the pull-up terminal VGH to be conducted with the output terminal Eout when the potential of the second pull-up node PU2 is the first potential, so that the pull-up signal is transmitted to the output terminal Eout. And, the second output sub-circuit 032 can control the pull-up terminal VGH to be decoupled from the output terminal Eout when the potential of the second pull-up node PU2 is the second potential.

The third output sub-circuit 033 may be coupled to the pull-down node PD, the pull-down terminal VGL, and the output terminal Eout, respectively. The third output sub-circuit 033 may be used to control the on-off of the pull-down terminal VGL and the output terminal Eout in response to the potential of the pull-down node PD.

For example, the third output sub-circuit 033 can control the pull-down terminal VGL to be conducted with the output terminal Eout when the potential of the pull-down node PD is the first potential, so that the pull-down signal is transmitted to the output terminal Eout. And, the third output sub-circuit 033 can control the pull-down terminal VGL to be decoupled from the output terminal Eout when the potential of the pull-down node PD is the second potential.

Fig. 5 shows a schematic circuit structure of a shift register unit according to an embodiment of the disclosure on the basis of fig. 4. As shown in fig. 5, the first input sub-circuit 011 may include: a first transistor M1, a second transistor M2 and a first capacitor C1.

The gate of the first transistor M1 may be coupled to the first clock terminal p_eck1, the first pole of the first transistor M1 may be coupled to the start terminal escv, and the second pole of the first transistor M1 may be coupled to the first pull-up node PU 1.

The gate of the second transistor M2 may be coupled to the second power terminal VDD2, the first pole of the second transistor M2 may be coupled to the pull-down terminal VGL, and the second pole of the second transistor M2 may be coupled to the first pull-up node PU 1.

A first terminal of the first capacitor C1 may be coupled to the first power terminal VDD1, and a second terminal of the first capacitor C1 may be coupled to the first pull-up node PU 1.

Optionally, as can be seen with continued reference to fig. 5, the second input subcircuit 012 may include: a third transistor M3, a fourth transistor M4 and a second capacitor C2.

The gate of the third transistor M3 may be coupled to the second clock terminal p_eck2, the first pole of the third transistor M3 may be coupled to the start terminal escv, and the second pole of the third transistor M3 may be coupled to the second pull-up node PU 2.

The gate of the fourth transistor M4 may be coupled to the first power terminal VDD1, the first pole of the fourth transistor M4 may be coupled to the pull-down terminal VGL, and the second pole of the fourth transistor M4 may be coupled to the second pull-up node PU 2.

The first terminal of the second capacitor C2 may be coupled to the second power terminal VDD2, and the second terminal of the second capacitor C2 may be coupled to the second pull-up node PU 2.

Alternatively, as can be seen with continued reference to FIG. 5, the pull-down control subcircuit 021 may include: a fifth transistor M5, a sixth transistor M6, and a third capacitor C3.

A gate of the fifth transistor M5 may be coupled to the first reset terminal R1, a first pole of the fifth transistor M5 may be coupled to the pull-down terminal VGL, and a second pole of the fifth transistor M5 may be coupled to the pull-down control node pd_c.

The gate of the sixth transistor M6 may be coupled to the second reset terminal R2, the first pole of the sixth transistor M6 may be coupled to the pull-down terminal VGL, and the second pole of the sixth transistor M6 may be coupled to the pull-down control node pd_c.

A first terminal of the third capacitor C3 may be coupled to the third clock terminal ECK, and a second terminal of the third capacitor C3 may be coupled to the pull-down control node pd_c.

Alternatively, as can be seen with continued reference to fig. 5, the pull-down subcircuit 022 may include: a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.

The gate of the seventh transistor M7 may be coupled to the pull-down control node pd_c, the first pole of the seventh transistor M7 may be coupled to the third clock terminal ECK, and the second pole of the seventh transistor M7 may be coupled to the pull-down node PD.

A gate of the eighth transistor M8 may be coupled to the first pull-up node PU1, a first pole of the eighth transistor M8 may be coupled to the pull-down terminal VGL, and a second pole of the eighth transistor M8 may be coupled to the pull-down node PD.

A gate of the ninth transistor M9 may be coupled to the second pull-up node PU2, a first pole of the ninth transistor M9 may be coupled to the pull-down terminal VGL, and a second pole of the ninth transistor M9 may be coupled to the pull-down node PD.

Alternatively, as can be seen with continued reference to fig. 5, the first output subcircuit 031 may include: a tenth transistor M10 and a fourth capacitor C4. The second output sub-circuit 032 may include: an eleventh transistor M11 and a fifth capacitance C5. The third output sub-circuit 033 may include: a twelfth transistor M12 and a sixth capacitance C6.

The gate of the tenth transistor M10 may be coupled to the first pull-up node PU1, the first pole of the tenth transistor M10 may be coupled to the pull-up terminal VGH, and the second pole of the tenth transistor M10 may be coupled to the output terminal Eout.

A first terminal of the fourth capacitor C4 may be coupled to the first pull-up node PU1, and a second terminal of the fourth capacitor C4 may be coupled to the output terminal Eout.

The gate of the eleventh transistor M11 may be coupled to the second pull-up node PU2, the first pole of the eleventh transistor M11 may be coupled to the pull-up terminal VGH, and the second pole of the eleventh transistor M11 may be coupled to the output terminal Eout.

A first terminal of the fifth capacitor C5 may be coupled to the second pull-up node PU2, and a second terminal of the fifth capacitor C5 may be coupled to the output terminal Eout.

A gate of the twelfth transistor M12 may be coupled to the pull-down node PD, a first pole of the twelfth transistor M12 may be coupled to the pull-down terminal VGL, and a second pole of the twelfth transistor M12 may be coupled to the output terminal Eout.

A first terminal of the sixth capacitor C6 may be coupled to the pull-down node PD, and a second terminal of the sixth capacitor C6 may be coupled to the pull-down terminal VGL.

Optionally, as can be seen with continued reference to fig. 5, the twelfth transistor M12 includes: two transistors M12a and M12b connected in series between the output terminal Eout and the pull-down terminal VGL belong to double gate transistors. In this way, the leakage current of the third output sub-circuit 033 can be reduced, ensuring reliable signal transmission to the output terminal Eout.

On the basis that the twelfth transistor M12 includes two transistors M12a and M12b connected in series, as shown in fig. 5, the shift register unit may further include: an anti-leakage circuit 04.

The anti-leakage circuit 04 may be coupled to a series node N1 of two transistors in series among the first pull-up node PU1, the second pull-up node PU2, the pull-up terminal VGH, and the twelfth transistor M12, respectively. The anti-leakage circuit 04 may be configured to control the on-off of the pull-up terminal VGH and the series node N1 in response to the potential of the first pull-up node PU1, and to control the on-off of the pull-up terminal VGH and the series node N1 in response to the potential of the second pull-up node PU 2.

For example, the anti-leakage circuit 04 may control the pull-up terminal VGH to be conducted with the series node N1 when the potential of the first pull-up node PU1 is the first potential, so that the pull-up signal is transmitted to the series node N1. And, the anti-leakage circuit 04 may control the pull-up terminal VGH to be decoupled from the series node N1 when the potential of the first pull-up node PU1 is the second potential. Similarly, when the potential of the second pull-up node PU2 is the first potential, the anti-leakage circuit 04 may control the pull-up terminal VGH to be connected to the series node N1, so that the pull-up signal is transmitted to the series node N1. And, the anti-leakage circuit 04 may control the pull-up terminal VGH to be decoupled from the series node N1 when the potential of the second pull-up node PU2 is the second potential. In this way, leakage at the series node N1 can be avoided, further ensuring reliable transmission of signals to the output Eout.

As can be seen from fig. 5, with further reference to the schematic circuit diagram of another shift register unit shown in fig. 6, the anti-leakage circuit 04 may include: a thirteenth transistor M13 and a fourteenth transistor M14.

A gate of the thirteenth transistor M13 may be coupled to the first pull-up node PU1, a first pole of the thirteenth transistor M13 may be coupled to the pull-up terminal VGH, and a second pole of the thirteenth transistor M13 may be coupled to the series node N1.

The gate of the fourteenth transistor M14 may be coupled to the second pull-up node PU2, the first pole of the fourteenth transistor M14 may be coupled to the pull-up terminal VGH, and the second pole of the fourteenth transistor M14 may be coupled to the series node N1.

Optionally, each transistor in the shift register unit provided in the embodiments of the present disclosure may include: an N-type oxide transistor. I.e., an N-type transistor made of an oxide material. Here, the material refers to a material of an active layer in a transistor. Accordingly, as described above, the first potential may be a high potential and the second potential may be a low potential. Of course, in some other embodiments, each transistor may further include: and a P-type transistor. The material of the P-type transistor may include low temperature polysilicon (low temperature poly-silicon, LTPS). Of course, the materials herein are only schematically illustrated.

It will be appreciated that the shift register cell shown in fig. 6 is a shift register cell of 14T6C (i.e., including 14 transistors and 6 capacitors) structure. Of course, in some other embodiments, too, is not limited to this 14T6C structure.

Alternatively, the output end Eout of the shift register unit according to the embodiments of the present disclosure may be used to be coupled to the light emission control end of the pixel circuit. Accordingly, the signal output through the output terminal Eout may be a light emission control signal provided to the light emission control terminal.

By way of example, fig. 7 shows a schematic diagram of a pixel circuit. As shown in fig. 7, the pixel circuit may be a 7T1C (i.e., including 7 transistors T1 to T7 and 1 capacitor Cst) structure pixel circuit. The 7 transistors T1 to T7 in the pixel circuit may be coupled to the following signal terminals: a reset signal terminal Rst (n), a light emission control terminal EM (n), an initial power terminal Vinit, a Data signal terminal Data (n), a driving power terminal VDD, and Gate signal terminals Gate (n) and Gate (n-1). The pixel circuit may be further coupled to the first pole of the light emitting element L1, and the second pole of the light emitting element L1 may be further coupled to the pull-down power source terminal VSS. The pixel circuit can transmit a light-emitting driving signal to the first electrode of the light-emitting element L1 based on signals provided by the coupled signal terminals, so that the light-emitting element L1 emits light under the action of the voltage difference between the light-emitting driving signal and a pull-down power signal provided by the pull-down power terminal VSS. Of course, the pixel circuit is not limited to the 7T1C structure shown in fig. 7.

Alternatively, the light emitting element L1 may be an organic light emitting diode (organic light emitting diode, OLED). The first electrode of the light emitting element L1 may be an anode, and the second electrode may be a cathode. Alternatively, in some other embodiments, the first pole of the light emitting element L1 may be a cathode and the second pole may be an anode. Each transistor in the pixel circuit may be an N-type transistor. Alternatively, in some other embodiments, P-type transistors may be included.

It is understood that a structure including a pixel circuit and a light emitting element may be referred to as a pixel. The display panel generally comprises a plurality of rows and columns of pixels, and a plurality of cascaded shift register units can be coupled with the plurality of rows of pixels in a one-to-one correspondence manner. In the embodiment of the present disclosure, the shift register unit may be coupled to the light emission control terminal EM (n) coupled to the pixel circuit and configured to provide the light emission control signal to the light emission control terminal EM (n).

For example, based on the structure shown in fig. 7, fig. 8 shows a timing diagram of signal terminals to which a pixel circuit is coupled. As can be seen with reference to fig. 8, driving the light emitting element L1 to emit light may include a reset phase t01, a data writing phase t02, and a light emitting phase t03, which are sequentially performed.

In the reset phase T01, the potential of the reset signal provided by the reset signal terminal Rst (n) and the potential of the Gate driving signal provided by the Gate signal terminal Gate (n-1) are both high, so that the transistors T6 and T7 are turned on, further, the driving power signal provided by the driving power terminal VDD is transmitted to the Gate of the transistor T3, and the initial power signal provided by the initial power terminal Vinit is transmitted to the anode of the light emitting element L1. In the Data writing stage T02, the potential of the Gate driving signal provided by the Gate signal terminal Gate (n) is high, so that the transistors T2 and T4 are turned on, and the Data signal provided by the Data signal terminal Data (n) is transmitted to the Gate of the transistor T3. Also, in the data writing stage t02, the potential of the reset signal supplied from the reset signal terminal Rst (n) is kept at a high potential so that the initial power supply signal is continuously transmitted to the anode of the light emitting element L1. In the light emitting stage T03, the potential of the light emission control signal provided by the light emission control terminal EM (n) is high, so that the transistors T1 and T5 are turned on, and a path is formed between the driving power terminal VDD and the pull-down power terminal VSS, so that the light emission driving signal is transmitted to the light emitting element L1 to drive the light emitting element L1 to emit light.

Fig. 9 is a flowchart of a driving method of a shift register unit according to an embodiment of the present disclosure, which can be used to drive the shift register unit shown in any of fig. 1 to 6. As shown in fig. 9, the driving method includes:

Step 901, in the first stage, the potential of the first power signal provided by the first power supply terminal and the potential of the first clock signal provided by the first clock terminal are both the first potential, and the potential of the second power signal provided by the second power supply terminal and the potential of the second clock signal provided by the second clock terminal are both the second potential; the input circuit controls the starting end to be conducted with the first pull-up node in response to a first clock signal, and controls the pull-down end to be conducted with the second pull-up node in response to a first power signal, wherein the potential of a starting signal provided by the starting end is a first potential; the pull-down circuit responds to the potential of the first pull-up node to control the pull-down end to be conducted with the pull-down node; the output circuit responds to the potential of the first pull-up node to control the pull-up end to be conducted with the output end.

Step 902, in the second stage, the potential of the second power signal and the potential of the second clock signal are the first potential, and the potential of the first power signal and the potential of the first clock signal are the second potential; the input circuit controls the starting end to be conducted with the second pull-up node in response to the second clock signal, and controls the pull-down end to be conducted with the first pull-up node in response to the second power signal, wherein the potential of the starting signal is a second potential; the pull-down circuit responds to a third clock signal provided by a third clock end to control the third clock end to be conducted with the pull-down node, and the potential of the third clock signal is the first potential; the output circuit controls the pull-down terminal to be conducted with the output terminal in response to the potential of the pull-down node.

Alternatively, taking the shift register unit shown in fig. 6, each transistor is an N-type transistor, and accordingly, the first potential (i.e., the active potential) is a high potential, the second potential (i.e., the inactive potential) is a low potential, and the potential of the pull-up signal provided by the pull-up terminal VGH is a high potential, and the potential of the pull-down signal provided by the pull-down terminal VGL is a low potential as an example, the driving principle of the shift register unit described in the embodiments of the disclosure will be described in detail. Fig. 10 is a timing diagram of signal terminals in a shift register unit according to an embodiment of the disclosure. As shown in fig. 10, the driving process may be divided into at least 12 phases: (1) to (12).

In the first stage (1), the potential of the first power signal provided by the first power terminal VDD1, the potential of the start signal provided by the start terminal escv, the potential of the first clock signal provided by the first clock terminal p_eck1, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the second power signal provided by the second power terminal VDD2 and the potential of the second clock signal provided by the second clock terminal p_eck2 are both low. At this time, the potential of the first pull-up node PU1 (n-1) of the cascaded shift register unit of the previous stage is at a high potential, that is, the potential of the first reset signal provided by the first reset terminal R1 is at a high potential. The potential of the second pull-up node PU2 (n-1) of the cascaded upper stage shift register unit is low, i.e. the potential of the second reset signal provided by the second reset terminal R2 is low. Accordingly, the first transistor M1, the fourth transistor M4, and the fifth transistor M5 may be turned on, and the second transistor M2, the third transistor M3, and the sixth transistor M6 may be turned off. Furthermore, a high start signal can be transmitted to the first pull-up node PU1 through the turned-on first transistor M1 to charge the first pull-up node PU 1. A low pull-down signal may be transmitted to the second pull-up node PU2 through the turned-on fourth transistor M4 to discharge the second pull-up node PU2, and transmitted to the pull-down control node pd_c through the turned-on fifth transistor M5 to discharge the pull-down control node pd_c. Accordingly, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 may be further turned on, and the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 may be turned off. Further, a pull-down signal of a low potential may be also transmitted to the pull-down node PD through the turned-on eighth transistor M8 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 may be further turned off. Further, a pull-up signal of high potential may be transmitted to the series node N1 through the turned-on thirteenth transistor M13, and the turned-on tenth transistor M10 is transmitted to the output terminal Eout.

I.e. in the first stage (1), a signal of high potential can be output through the output terminal Eout. For example, the high-potential light emission control signal will not be described in detail below. By way of example, fig. 11 shows an equivalent circuit diagram of the shift register unit in the first stage (1).

In the second stage (2), the potential of the start signal provided by the start-end ESTV is high. The potential of the first power signal provided by the first power terminal VDD1, the potential of the second power signal provided by the second power terminal VDD2, the potential of the first clock signal provided by the first clock terminal p_eck1, the potential of the second clock signal provided by the second clock terminal p_eck2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) of the shift register unit of the previous stage is high, that is, the potential of the first reset signal is high. The potential of the second pull-up node PU2 (n-1) of the cascaded upper stage shift register unit is low, i.e. the potential of the second reset signal is low. Accordingly, the fifth transistor M5 may be turned on, and the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 may be turned off. Further, a pull-down signal of a low potential may be transmitted to the pull-down control node pd_c through the turned-on fifth transistor M5 to discharge the pull-down control node pd_c. In addition, the potential of the first pull-up node PU1 may be maintained at the high potential of the first stage (1) by the first capacitor C1; the potential of the second pull-up node PU2 may be maintained at the low potential of the first stage (1) by the second capacitor C2. Accordingly, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 may be further turned on, and the seventh transistor M7, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 may be turned off. Further, a pull-down signal of a low potential may be also transmitted to the pull-down node PD through the turned-on eighth transistor M8 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 may be further turned off. Further, a pull-up signal of high potential may be transmitted to the series node N1 through the turned-on thirteenth transistor M13, and the turned-on tenth transistor M10 is transmitted to the output terminal Eout.

I.e. in the second phase (2) the signal of high potential can continue to be output through the output terminal Eout. By way of example, fig. 12 shows an equivalent circuit diagram of the shift register unit in the second stage (2).

In the third stage (3), the potential of the start signal provided by the start terminal ESTV, the potential of the second clock signal provided by the second clock terminal P_ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the first power signal provided by the first power terminal VDD1, the potential of the second power signal provided by the second power terminal VDD2, and the potential of the first clock signal provided by the first clock terminal p_eck1 are all low potentials. At this time, the potential of the second pull-up node PU2 (n-1) of the shift register unit of the previous stage is high, that is, the potential of the second reset signal is high. The potential of the first pull-up node PU1 (n-1) of the cascaded upper stage shift register unit is low, i.e. the potential of the first reset signal is low. Accordingly, the third transistor M3 and the sixth transistor M6 may be turned on, and the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 may be turned off. Further, a pull-down signal of a low potential may be transmitted to the pull-down control node pd_c through the turned-on sixth transistor M6 to discharge the pull-down control node pd_c. The high start signal is transmitted to the second pull-up node PU2 via the turned-on third transistor M3 to charge the second pull-up node PU 2. However, since the high level of the start signal is smaller than the high level of the pull-up signal, the second pull-up node PU2 is not fully charged to the desired high level. In addition, the potential of the first pull-up node PU1 may be maintained at the high potential of the second stage (2) by the first capacitor C1. Accordingly, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the thirteenth transistor M13 may be further turned on, and the seventh transistor M7, the eleventh transistor M11, and the fourteenth transistor M14 may be turned off. Further, a pull-down signal of a low potential may be also transmitted to the pull-down node PD via the turned-on eighth transistor M8 and the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 may be further turned off. Further, a pull-up signal of high potential may be transmitted to the series node N1 through the turned-on thirteenth transistor M13, and the turned-on tenth transistor M10 is transmitted to the output terminal Eout.

I.e. in the third stage (3) the signal of high potential can continue to be output through the output terminal Eout. By way of example, fig. 13 shows an equivalent circuit diagram of the shift register unit in the third stage (3).

In the fourth stage (4), the potential of the second power signal provided by the second power terminal VDD2 is high. The potential of the start signal provided by the start end ESTV, the potential of the first power signal provided by the first power end VDD1, the potential of the first clock signal provided by the first clock end P_ECK1, the potential of the second clock signal provided by the second clock end P_ECK2, and the potential of the third clock signal provided by the third clock end ECK are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded shift register units are both low, that is, the potential of the first reset signal and the potential of the second reset signal are both low. Accordingly, the second transistor M2 may be turned on, and the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may be turned off. Further, a pull-down signal of low potential can be transmitted to the first pull-up node PU1 through the turned-on second transistor M2 to discharge the first pull-up node PU 1. Further, the potential of the pull-down control node pd_c may be maintained at the low potential of the third stage (3) by the third capacitor C3. And, under the action of the second capacitor C2, the potential of the second pull-up node PU2 is further charged and pulled up to a higher potential. Accordingly, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 may be further turned on, and the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 may be turned off. Further, a pull-down signal of a low potential may be also transmitted to the pull-down node PD via the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 may be further turned off. Further, a pull-up signal of high potential may be transmitted to the series node N1 through the turned-on fourteenth transistor M14, and the turned-on eleventh transistor M11 is transmitted to the output terminal Eout.

I.e. in the fourth stage (4) the signal of high potential can continue to be output through the output terminal Eout. By way of example, fig. 14 shows an equivalent circuit diagram of the shift register unit in the fourth stage (4). Through setting up first electric capacity C1 and second electric capacity C2, can be after the electric potential switching of the first power signal that first power end VDD1 provided and the second power signal that second power end VDD2 provided, avoid the output end Eout to appear unsettled (floating) state before exporting to output end Eout, ensure output stability.

In the fifth stage (5), the potential of the second power signal provided by the second power terminal VDD2, the potential of the second clock signal provided by the second clock terminal p_eck2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the start signal provided by the start terminal ESTV, the potential of the first power signal provided by the first power terminal VDD1, and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded shift register units are both low, that is, the potential of the first reset signal and the potential of the second reset signal are both low. Accordingly, the second transistor M2 and the third transistor M3 may be turned on, and the first transistor M1, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may be turned off. Further, a pull-down signal of low potential can be transmitted to the first pull-up node PU1 through the turned-on second transistor M2 to discharge the first pull-up node PU 1. The low start signal is transmitted to the second pull-up node PU2 via the turned-on third transistor M3 to discharge the second pull-up node PU 2. Further, the potential of the pull-down control node pd_c may transition to a high potential based on the third clock signal of the high potential under the action of the third capacitor C3. Accordingly, the seventh transistor M7 may be further turned on, and the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, and the fourteenth transistor M14 may be turned off. Further, the third clock signal of the high potential may be transmitted to the pull-down node PD through the turned-on seventh transistor M7 to charge the pull-down node PD. Accordingly, the twelfth transistor M12 may be further turned on. Further, the pull-down signal of low voltage can be transmitted to the output terminal Eout through the turned-on twelfth transistor M12.

I.e. in the fifth stage (5), a signal of low potential can be output through the output terminal Eout. For example, the low-potential light emission control signal will not be described in detail below. By way of example, fig. 15 shows an equivalent circuit diagram of the shift register unit in the fifth stage (5).

In the sixth stage (6), the potential of the second power signal provided by the second power terminal VDD2 is high. The potential of the start signal provided by the start end ESTV, the potential of the first power signal provided by the first power end VDD1, the potential of the first clock signal provided by the first clock end P_ECK1, the potential of the second clock signal provided by the second clock end P_ECK2, and the potential of the third clock signal provided by the third clock end ECK are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded shift register units are both low, that is, the potential of the first reset signal and the potential of the second reset signal are both low. Accordingly, the second transistor M2 may be turned on, and the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may be turned off. Further, a pull-down signal of low potential can be transmitted to the first pull-up node PU1 through the turned-on second transistor M2 to discharge the first pull-up node PU 1. In addition, the potential of the second pull-up node PU2 may be maintained at the low potential of the fifth stage (5) by the second capacitor C2. The potential of the pull-down control node pd_c may transition to a low potential based on the third clock signal of the low potential under the action of the third capacitor C3. And, the potential of the pull-down node PD may be maintained at the high potential of the fifth stage (5) by the sixth capacitance C6. Accordingly, the twelfth transistor M12 may be further turned on, and the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the thirteenth transistor M13, and the fourteenth transistor M14 may be turned off. Further, the pull-down signal of low voltage can be transmitted to the output terminal Eout through the turned-on twelfth transistor M12.

I.e. in the sixth stage (6), a signal of low potential can be output through the output terminal Eout. By way of example, fig. 16 shows an equivalent circuit diagram of the shift register unit in the sixth stage (6).

In the seventh stage (7), the potential of the second power signal provided by the second power terminal VDD2, the potential of the second clock signal provided by the second clock terminal p_eck2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the start signal provided by the start terminal ESTV, the potential of the first power signal provided by the first power terminal VDD1, and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded shift register units are both low, that is, the potential of the first reset signal and the potential of the second reset signal are both low. Due to the same signal timing as in the fifth stage (5). Therefore, the driving principle of the shift register unit in the seventh stage (7) is also the same as that of the fifth stage (5), and will not be described again. Correspondingly, the equivalent circuit diagram of the seventh stage (7) may also refer to the equivalent circuit diagram 15 of the fifth stage (5) in the same way, and is not shown.

In the eighth stage (8), the potential of the second power signal provided by the second power terminal VDD2 is high. The potential of the start signal provided by the start end ESTV, the potential of the first power signal provided by the first power end VDD1, the potential of the first clock signal provided by the first clock end P_ECK1, the potential of the second clock signal provided by the second clock end P_ECK2, and the potential of the third clock signal provided by the third clock end ECK are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded shift register units are both low, that is, the potential of the first reset signal and the potential of the second reset signal are both low. Due to the same signal timing as in the sixth stage (6). Therefore, the driving principle of the shift register unit in the eighth stage (8) is the same as that of the sixth stage (6), and will not be described again. Correspondingly, the equivalent circuit diagram of the eighth stage (8) may also refer to the equivalent circuit diagram 16 of the sixth stage (6) in the same way, and is not shown.

In the ninth stage (9), the potential of the second power signal provided by the second power terminal VDD2, the potential of the second clock signal provided by the second clock terminal p_eck2, and the potential of the third clock signal provided by the third clock terminal ECK are all high potentials. The potential of the start signal provided by the start terminal ESTV, the potential of the first power signal provided by the first power terminal VDD1, and the potential of the first clock signal provided by the first clock terminal P_ECK1 are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded shift register units are both low, that is, the potential of the first reset signal and the potential of the second reset signal are both low. Due to the same signal timing as in the fifth stage (5). Therefore, the driving principle of the shift register unit in the ninth stage (9) is also the same as that of the fifth stage (5), and will not be described again. Correspondingly, the equivalent circuit diagram of the ninth stage (9) may also refer to the equivalent circuit diagram 15 of the fifth stage (5) in the same way, and is not shown.

In the tenth stage (10), the potential of the second power signal supplied from the second power terminal VDD2 is high. The potential of the start signal provided by the start end ESTV, the potential of the first power signal provided by the first power end VDD1, the potential of the first clock signal provided by the first clock end P_ECK1, the potential of the second clock signal provided by the second clock end P_ECK2, and the potential of the third clock signal provided by the third clock end ECK are all low potentials. At this time, the potential of the first pull-up node PU1 (n-1) and the potential of the second pull-up node PU2 (n-1) of the cascaded shift register units are both low, that is, the potential of the first reset signal and the potential of the second reset signal are both low. Due to the same signal timing as in the sixth stage (6). Therefore, the driving principle of the shift register unit in the tenth stage (10) is the same as that of the sixth stage (6), and will not be described again. Correspondingly, the equivalent circuit diagram of the tenth stage (10) may also refer to the equivalent circuit diagram 16 of the sixth stage (6) in the same way, and is not shown.

In the eleventh stage (11), the potential of the second power signal provided by the second power terminal VDD2, the potential of the start signal provided by the start terminal STV, the potential of the second clock signal provided by the second clock terminal ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all high. The potential of the first power signal provided by the first power terminal VDD1 and the potential of the first clock signal provided by the first clock terminal p_eck1 are both low. At this time, the potential of the second pull-up node PU2 (n-1) of the shift register unit of the previous stage is high, that is, the potential of the second reset signal is high. The potential of the first pull-up node PU1 (n-1) of the cascaded upper stage shift register unit is low, i.e. the potential of the first reset signal is low. Accordingly, the second transistor M2, the third transistor M3, and the sixth transistor M6 may be turned on, and the first transistor M1, the fourth transistor M4, and the fifth transistor M5 may be turned off. Further, a pull-down signal of a low potential may be transmitted to the first pull-up node PU1 through the turned-on second transistor M2 to discharge the first pull-up node PU1, and the turned-on sixth transistor M6 is transmitted to the pull-down control node pd_c to discharge the pull-down control node pd_c. The high start signal is transmitted to the second pull-up node PU2 via the turned-on third transistor M3 to charge the second pull-up node PU 2. Accordingly, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 may be further turned on, and the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 may be turned off. Further, a pull-down signal of a low potential may be transmitted to the pull-down node PD through the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 may be further turned off. Further, a pull-up signal of high potential may be transmitted to the series node N1 through the turned-on fourteenth transistor M14, and the turned-on eleventh transistor M11 is transmitted to the output terminal Eout.

I.e. in the eleventh stage (11), a signal of high potential can be output through the output terminal Eout. By way of example, fig. 17 shows an equivalent circuit diagram of the shift register unit at the eleventh stage (11). When the eleventh transistor M11 turns on the pull-up signal transmitting the high potential to the output terminal Eout, the potential of the second pull-up node PU2 may be raised to a higher potential. Wherein the potential change amount DeltaV of the first pull-up node PU1 _PU1 And the potential variation Δv of the second pull-up node PU2 _PU2 Can satisfy the following conditions:

ΔV _PU1 ＝C40/(CgsM10+C40+C _PU1 )*ΔEout；

ΔV _PU2 ＝C50/(CgsM11+C50+C _PU2 )*ΔEout；

wherein C40 is the capacitance of the fourth capacitor C4; c50 is the capacitance of the fifth capacitor C5; cgsM10 refers to the parasitic capacitance value of the tenth transistor M10; cgsM11 refers to the parasitic capacitance value of the eleventh transistor M11; c (C) _PU1 Refers to the parasitic capacitance value of the first pull-up node PU1, except for C40 and CgsM 10; c (C) _PU2 Refers to the parasitic capacitance value of the second pull-up node PU2 in addition to C50 and CgsM 11; Δ Eout refers to the variation of the output signal from the output terminal Eout.

In the twelfth stage (12), the potential of the second power signal provided by the second power terminal VDD2 and the potential of the start signal provided by the start terminal STV are both high. The potential of the first power signal provided by the first power terminal VDD1, the potential of the first clock signal provided by the first clock terminal p_eck1, the potential of the second clock signal provided by the second clock terminal ECK2, and the potential of the third clock signal provided by the third clock terminal ECK are all low potentials. At this time, the potential of the second pull-up node PU2 (n-1) of the shift register unit of the previous stage is high, that is, the potential of the second reset signal is high. The potential of the first pull-up node PU1 (n-1) of the cascaded upper stage shift register unit is low, i.e. the potential of the first reset signal is low. Accordingly, the second transistor M2 and the sixth transistor M6 may be turned on, and the first transistor M1, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 may be turned off. Further, a pull-down signal of a low potential may be transmitted to the first pull-up node PU1 through the turned-on second transistor M2 to discharge the first pull-up node PU1, and the turned-on sixth transistor M6 is transmitted to the pull-down control node pd_c to discharge the pull-down control node pd_c. Further, the potential of the second pull-up node PU2 may be maintained at the high potential of the eleventh stage (11) by the second capacitor C2. Accordingly, the ninth transistor M9, the eleventh transistor M11, and the fourteenth transistor M14 may be further turned on, and the seventh transistor M7, the eighth transistor M8, the tenth transistor M10, and the thirteenth transistor M13 may be turned off. Further, a pull-down signal of a low potential may be transmitted to the pull-down node PD through the turned-on ninth transistor M9 to discharge the pull-down node PD. Accordingly, the twelfth transistor M12 may be further turned off. Further, a pull-up signal of high potential may be transmitted to the series node N1 through the turned-on fourteenth transistor M14, and the turned-on eleventh transistor M11 is transmitted to the output terminal Eout.

I.e. in the twelfth stage (12), the signal of high potential can be continuously output through the output terminal Eout. By way of example, fig. 18 shows an equivalent circuit diagram of the shift register unit in the twelfth stage (12).

In fig. 11 to 18, "x indicated by a broken line" is used to indicate that the transistor is turned off. In addition, the signal flow direction of the high potential and the signal flow direction of the low potential are also identified in fig. 11 to 18, respectively. Fig. 19 shows, in combination with fig. 11 to 18 on the basis of fig. 10, a signal simulation diagram, with the abscissa representing time in microseconds (mus) and the ordinate representing voltage in volts (V). The first stage of step 901 may be referred to as a first stage 1 described in the above-described embodiment, and the second stage of step 902 may be referred to as a fifth stage 5 described in the above-described embodiment.

It should be noted that, since the driving method has substantially the same technical effects as those of the shift register unit described in the foregoing embodiments, the technical effects of the driving method are not repeated here for the sake of brevity.

Fig. 20 is a schematic diagram of a structure of a light-emitting driving circuit according to an embodiment of the present disclosure. As shown in fig. 20, the light emission driving circuit includes: at least two cascaded shift register cells EOA as shown in any of fig. 1 to 6. By way of example, fig. 20 schematically shows 4 cascaded EOAs (1) to (4).

As shown in fig. 20, the start end ESTV of the first stage shift register unit EOA may be externally connected to a terminal for providing a start signal. In other stages of shift register units EOA except the first stage of shift register unit EOA, the start end ESTV of each stage of shift register unit EOA may be coupled with the output end Eout of the last stage of shift register unit EOA of the cascade. In addition, referring to fig. 20, it can be further seen that the light-emitting driving circuit provided in the embodiment of the present disclosure may be driven by a two-phase clock. That is, at least two shift register units 00 of the cascade connection may be coupled with two first clock terminals p_eck1 and p_ecb1, two second clock terminals p_eck2 and p_ecb2, and two third clock terminals ECK and ECB. Every adjacent two cascaded shift register cells 00 are coupled to a different first clock terminal, to a different second clock terminal, and to a different third clock terminal. Of course, this is only a schematic illustration. For example, in some other embodiments, four-phase clock driving may also be employed. In addition, fig. 20 also schematically illustrates a first power supply terminal VDD1, a second power supply terminal VDD2, a pull-up terminal VGH and a pull-down terminal VGL, which are coupled to each stage of shift register unit.

Fig. 21 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 21, the display device includes: a display panel 100, and a light emission driving circuit 000 as shown in fig. 20. The display panel 100 includes a plurality of pixels. At least one pixel includes the pixel circuit and the light emitting element shown in fig. 7.

Wherein the light emitting driving circuit 000 is coupled to the pixel circuit and is used for transmitting a light emitting driving signal to the pixel circuit. The pixel circuit is also coupled to the light emitting element and is configured to drive the light emitting element to emit light in response to the light emission control signal. For example, the light emission driving signal supplied from the light emission driving circuit 000 may refer to fig. 8.

Alternatively, the display device may be: any product or component with display function such as electronic paper, mobile phone, tablet computer, television, display, notebook computer or navigator.

It is to be understood that the terminology used in the description of the embodiments of the disclosure is for the purpose of describing the embodiments of the disclosure only and is not intended to be limiting of the disclosure. Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs.

As used in the specification and claims of this application, the terms "first," "second," or "third," and the like, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another.

Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

The word "comprising" or "comprises", and the like, is intended to mean that elements or items that are present in front of "comprising" or "comprising" are included in the word "comprising" or "comprising", and equivalents thereof, without excluding other elements or items.

"upper", "lower", "left" or "right" etc. are only used to indicate relative positional relationships, which may also be changed accordingly when the absolute position of the object to be described is changed. "connected" or "coupled" refers to electrical connections.

"and/or" means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working processes of the light emitting driving circuit, the shift register unit, each circuit and each sub-circuit described above may refer to corresponding processes in the method embodiments, and are not described herein again.

The foregoing description of the preferred embodiments of the present disclosure is provided for the purpose of illustration only, and is not intended to limit the disclosure to the particular embodiments disclosed, but on the contrary, the intention is to cover all modifications, equivalents, alternatives, and alternatives falling within the spirit and principles of the disclosure.

Claims

1. A shift register unit, characterized in that the shift register unit comprises:

2. The shift register unit according to claim 1, wherein the input circuit comprises:

3. The shift register cell of claim 2, wherein the first input sub-circuit comprises: a first transistor, a second transistor, and a first capacitor;

4. The shift register cell of claim 2, wherein the second input sub-circuit comprises: a third transistor, a fourth transistor, and a second capacitor;

5. The shift register cell as claimed in any one of claims 1 to 4, wherein the pull-down circuit comprises:

6. The shift register cell of claim 5, wherein the pull-down control sub-circuit comprises: a fifth transistor, a sixth transistor, and a third capacitor;

7. The shift register cell of claim 5, wherein the pull-down subcircuit comprises: a seventh transistor, an eighth transistor, and a ninth transistor;

8. The shift register unit according to any one of claims 1 to 4, wherein the output circuit includes:

9. The shift register cell of claim 8, wherein the first output sub-circuit comprises: a tenth transistor and a fourth capacitor; the second output sub-circuit includes: an eleventh transistor and a fifth capacitor; the third output sub-circuit includes: a twelfth transistor and a sixth capacitor;

10. The shift register cell of claim 9, wherein the twelfth transistor comprises: two transistors connected in series between the output terminal and the pull-down terminal; the shift register unit further includes:

11. The shift register cell of claim 10, wherein the anti-leakage circuit comprises: a thirteenth transistor and a fourteenth transistor;

12. The shift register cell as claimed in any one of claims 1-4, wherein the output terminal is adapted to be coupled to a light emission control terminal of a pixel circuit;

13. A method of driving a shift register unit, characterized in that the method is for driving a shift register unit as claimed in any one of claims 1 to 12, the method comprising:

14. A light-emitting drive circuit, characterized by comprising: at least two cascaded shift register cells according to any of claims 1 to 12.

15. A display device, characterized in that the display device comprises: a display panel, a light-emitting drive circuit as claimed in claim 14; the display panel includes a plurality of pixels; the pixel includes a pixel circuit and a light emitting element;