CN116863874B - Scan driving circuit, scan driving method and display device - Google Patents
Scan driving circuit, scan driving method and display device Download PDFInfo
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- CN116863874B CN116863874B CN202311134669.5A CN202311134669A CN116863874B CN 116863874 B CN116863874 B CN 116863874B CN 202311134669 A CN202311134669 A CN 202311134669A CN 116863874 B CN116863874 B CN 116863874B
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- 230000008878 coupling Effects 0.000 abstract description 6
- 238000010168 coupling process Methods 0.000 abstract description 6
- 238000005859 coupling reaction Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 description 10
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- 238000010586 diagram Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
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- 230000005525 hole transport Effects 0.000 description 2
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
Abstract
The application discloses a scanning driving circuit, a scanning driving method and a display device, wherein a pull-up unit is provided with a first switch unit and a second switch unit, the control end of the first switch unit is connected with the second output end of a logic control unit, the first end is connected with a voltage signal source, the second end is connected with a first node, and the first switch unit is conducted when the second output end of the logic control unit is at a high level; the control end of the second switch unit is connected with the third node, the first end of the second switch unit is connected with the second node, the second end of the second switch unit is connected with the second output end of the logic control unit, and the second switch unit is conducted when the clock signal is in a high level. The first end of the first switch unit is provided with a preset level signal smaller than the high level of the clock signal and larger than the low level of the clock signal through the voltage signal source, the level of the first node is pulled up in advance by utilizing the preset level signal, the problem of insufficient effective charging time of the scanning transistor caused by level switching delay can be solved, and meanwhile, the potential coupling influence of parasitic capacitance is reduced.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a scan driving circuit, a scan driving method, and a display device.
Background
The scanning signal is used as an input signal of the pixel units and used for controlling the on-off state of the scanning transistors corresponding to the pixel units, and when the scanning transistors on a certain row are conducted, the data voltage can be applied to the pixel units on the row, so that the display of a specific picture is realized. However, when the scan signal is switched from the low level VSS to the high level VDD, the effective charging time of the scan transistor is insufficient due to the switching delay, which affects the screen display effect.
Disclosure of Invention
In order to improve the influence of switching delay on picture display, the application provides a scanning driving circuit, a scanning driving method and a display device.
According to an aspect of an embodiment of the present application, a scan driving circuit is disclosed, which includes a plurality of scan driving modules including a logic control unit, a pull-up unit, and a pull-down unit. Wherein the pull-down unit is connected to the first output terminal of the logic control unit and the first node.
The pull-up unit comprises a pull-up switch unit, a bootstrap capacitor, a first switch unit and a second switch unit, wherein the control end of the pull-up switch unit is connected with a second node, the first end of the pull-up switch unit is connected with a third node, the third node is configured to receive a clock signal, and the second end of the pull-up switch unit is connected with the first node; one end of the bootstrap capacitor is connected with the first node, and the other end of the bootstrap capacitor is connected with the second node; the control end of the first switch unit is connected with the second output end of the logic control unit, the first end of the first switch unit is connected with a voltage signal source, the voltage signal source is used for providing a preset level signal, the high level of the preset level signal is smaller than that of the clock signal and is larger than that of the clock signal, and the second end of the first switch unit is connected with the first node; the control end of the second switch unit is connected with the third node, the first end of the second switch unit is connected with the second node, and the second end of the second switch unit is connected with the second output end of the logic control unit.
The first switch unit is configured to be turned on when the second output end of the logic control unit is at a high level so as to pull up the potential of the first node to the preset level signal, and the second switch unit is configured to be turned on when the clock signal is at a high level so as to pull up the potential of the first node to the high level of the clock signal.
In an exemplary embodiment, the preset level signal is smaller than a turn-on voltage of a scan transistor in the pixel unit, and a control terminal of the scan transistor is connected to the first node.
In an exemplary embodiment, the preset level signal includes a first level signal and a second level signal greater than the first level signal, a period in which the second output terminal of the logic control unit is high and the clock signal is low includes a first period and a second period later than the first period, and the voltage signal source is configured to supply the first level signal during the first period and the second level signal during the second period.
In one exemplary embodiment, the voltage signal source is a timing controller.
In an exemplary embodiment, the first and second switching units are thin film transistors.
In an exemplary embodiment, the pull-down unit includes a pull-down switch unit, a control terminal of the pull-down switch unit is connected to a first output terminal of the logic control unit, a first terminal of the pull-down switch unit is connected to the first node, and a second terminal of the pull-down switch unit is connected to a common ground terminal.
In an exemplary embodiment, the plurality of scan driving modules are cascaded, and the logic control unit of at least some of the scan driving modules is configured to output a corresponding low level signal or high level signal to the second output terminal based on the scan signal of the previous stage scan driving module, and output a corresponding low level signal or high level signal to the first output terminal based on the scan signal of the next stage scan driving module.
According to an aspect of an embodiment of the present application, a display device is disclosed, the display device including a display panel and a driving circuit, wherein the display panel includes a pixel cell array; the driving circuit is used for driving the pixel unit and comprises the scanning driving circuit.
In one exemplary embodiment, the pixel unit is a self-luminous pixel unit.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
the application discloses a scanning driving circuit, wherein a pull-up unit is provided with a first switch unit and a second switch unit, the control end of the first switch unit is connected with the second output end of a logic control unit, the first end is connected with a voltage signal source, the second end is connected with a first node, and the first switch unit is conducted when the second output end of the logic control unit is at a high level; the control end of the second switch unit is connected with the third node, the first end of the second switch unit is connected with the second node, the second end of the second switch unit is connected with the second output end of the logic control unit, and the second switch unit is conducted when the clock signal is in a high level. The first end of the first switch unit is provided with a preset level signal smaller than the high level of the clock signal and larger than the low level of the clock signal through the voltage signal source, the level of the first node is pulled up in advance by utilizing the preset level signal, the voltage difference between the level of the first node and the high level of the clock signal can be reduced, when the scanning signal of the first node is required to be switched to the high level of the clock signal, the problem of insufficient effective charging time of the scanning transistor caused by level switching delay can be solved, meanwhile, the potential coupling influence of parasitic capacitance on other nodes is reduced, and the picture display effect is improved.
According to an aspect of an embodiment of the present application, there is disclosed a scan driving method for the foregoing scan driving circuit, the scan driving method including: when the second output end of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output a preset level signal to the first end of the first switch unit.
The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:
according to the scanning driving method disclosed by the application, when the second output end of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output the preset level signal to the first end of the first switch unit, and the voltage difference between the level of the first node and the high level of the clock signal can be reduced in advance before the high level of the clock signal comes, so that the problem of insufficient effective charging time of the scanning transistor caused by level switching delay is solved, meanwhile, the potential coupling influence of parasitic capacitance on other nodes is reduced, and the picture display effect is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 schematically shows a schematic composition of an OLED display.
Fig. 2 shows a circuit diagram of a conventional scan driving circuit.
Fig. 3 shows a driving waveform diagram of a conventional scan driving circuit.
Fig. 4 schematically shows a circuit diagram of a pixel cell.
Fig. 5 schematically shows a circuit diagram of a scan driving circuit according to an embodiment of the present application.
Fig. 6 schematically shows a driving waveform diagram of a scan driving circuit according to an embodiment of the present application.
Fig. 7 schematically shows the voltage fluctuation alignment at the level switching with the prior art using the present application.
Fig. 8 schematically illustrates a schematic composition of a display device according to an embodiment of the present application.
The reference numerals are explained as follows:
10. a scan driving module; 101. a logic control unit; q, the first output end; p, the second output end; 102. a pull-up unit; m1, a pull-up switch unit; C. a bootstrap capacitor; t1, a first switch unit; t2, a second switch unit; n1, a first node; n2, a second node; n3, a third node; 103. a pull-down unit; m2, pull-down switch unit; 100. a driving circuit; 20. a timing controller; 30. a data driving circuit; 40. a power supply circuit; 200. a display panel; S-TFT, scanning transistor; D-TFT, drive transistor; cst, a first capacitor; an OLED, sub-pixel; c', parasitic capacitance.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
In the description of the present application, unless otherwise indicated, the meaning of "a plurality" means two or more.
Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or more features, either explicitly or implicitly.
An OLED (Organic Light-Emitting Diode) display has a fast response speed and a wide viewing angle, and can generate luminance with high luminous efficiency. The OLED includes an anode electrode, a cathode electrode, and an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer includes a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an emission layer (EML), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). Upon application of a driving voltage to the anode electrode and the cathode electrode, holes passing through the Hole Transport Layer (HTL) and electrons passing through the Electron Transport Layer (ETL) move to the light emitting layer (EML), thereby forming excitons, and the light emitting layer (EML) generates visible light.
The OLED display generally includes a display panel and a driving circuit, wherein the display panel is provided with pixel units (R, G, B) and necessary wirings, and the driving circuit includes a timing controller 20 (i.e., TCON), a scan driving circuit, a data driving circuit 30, and a power supply circuit 40, wherein the scan driving circuit is used for outputting a scan signal as an input signal of the pixel units and controlling on/off states of scan transistors corresponding to the pixel units, and when the scan transistors on a certain row are turned on, a data voltage can be applied to the pixel units on the row, thereby realizing a picture display.
The conventional scan driving circuit has a structure as shown in fig. 2, which includes a logic control section and an output section. Wherein the logic control section is configured to receive the trigger signal IN (i.e., the scan signal) and output a corresponding high level signal or low level signal to the output section based on the received trigger signal. The output section includes a pull-up circuit and a pull-down circuit, wherein the pull-up circuit is composed of a pull-up transistor M1 and a bootstrap capacitor C. The output terminal of the pull-up transistor M1 serves as a scan signal output node, and the output state thereof can be switched between the low level VSS of the clock signal CK and the high level VDD of the clock signal CK. The pull-down circuit consists of one pull-down transistor M2.
However, when the scan signal is switched from the low level VSS to the high level VDD, the effective charging time of the scan transistor S-TFT (as shown in fig. 4) is insufficient due to the switching delay, which results in insufficient turn-on of the scan transistor S-TFT and possibly the data voltage V Data The display brightness is affected due to incomplete writing, and the potential of other nodes is also affected by coupling of the parasitic capacitance C', for example, the gate-drain potential of the scan transistor S-TFT is affected, and the drain-source potential of the drive transistor D-TFT is affected. This adversely affects the picture display effect of the display.
In order to solve the above-described problems, an embodiment of the present application provides a scan driving circuit including a plurality of scan driving modules 10, each scan driving module 10 for driving a row of pixel units. As shown in fig. 5, the scan driving module 10 includes a logic control unit 101 and an output unit.
The logic control unit 101 is configured to receive a scan signal and output a corresponding high level signal or low level signal based on the received scan signal. The logic control unit 101 has a first output terminal Q and a second output terminal P, the output levels of the first output terminal Q and the second output terminal P are opposite, and when the output of the first output terminal Q is low, the output of the second output terminal P is high, so that the scan signal output node of the output unit is high, thereby turning on the scan transistors on the corresponding rows; when the first output terminal Q outputs a high level, the second output terminal P outputs a low level to make the scan signal output node of the output unit low level, thereby turning off the scan transistors on the corresponding row.
The plurality of scan driving modules 10 are cascaded, and the logic control unit 101 of at least some of the scan driving modules 10 is configured to output a corresponding low level signal or high level signal to the second output terminal P based on the scan signal of the previous stage scan driving module 10, and to output a corresponding low level signal or high level signal to the first output terminal Q based on the scan signal of the next stage scan driving module 10. Illustratively, before the scan signal (here, a high-level scan signal) of the previous stage scan driving module 10 comes, the second output terminal P of the logic control unit 101 is output at a low level, and the first output terminal Q is output at a high level, at this time, the scan transistor on the corresponding row of the current scan driving module 10 is turned off; when the scanning signal (particularly, the scanning signal with high level) of the previous stage scanning driving module 10 comes, the potentials of the second output end P and the first output end Q of the logic control unit 101 are inverted, the second output end P of the logic control unit 101 outputs high level, and the first output end Q outputs low level, at this time, the scanning transistor on the row corresponding to the current scanning driving module 10 is turned on; when the scanning signal (particularly, the high-level scanning signal) of the next stage of the scanning driving module 10 comes, the potentials of the second output terminal P and the first output terminal Q of the logic control unit 101 are inverted again, the second output terminal P of the logic control unit 101 outputs a low level, and the first output terminal Q outputs a high level, at this time, the scanning transistor on the row corresponding to the current scanning driving module 10 is turned off.
It should be noted that the logic control unit 101 may have a first input terminal (not shown in the figure) and a second input terminal (not shown in the figure), where the first input terminal may be a scan signal output node connected to the next stage scan driving module 10, and the second input terminal may be a scan signal output node connected to the previous stage scan driving module 10. When the second input terminal receives the high level scan signal of the previous stage scan driving module 10, the second output terminal P of the logic control unit 101 outputs a high level, and the first output terminal Q outputs a low level. When the first input terminal receives the high level scan signal of the next stage scan driving module 10, the first output terminal Q of the logic control unit 101 outputs a high level, and the second output terminal P outputs a low level.
For the scan driving module 10 located at the first stage, the second input terminal thereof may be connected to the timing controller, and the second input terminal receives the trigger signal output by the timing controller, so as to output a high-level scan signal, and turn on the scan transistors on the corresponding row. For the scan driving module 10 located at the last stage, a redundant scan driving module may be connected to turn off the scan transistors on the last row.
The logic control unit 101 may adopt any existing logic control unit structure, so long as the present application can be implemented, and the specific constituent structure of the logic control unit 101 will not be further described in detail herein.
In the foregoing embodiment, the plurality of scan driving modules 10 are cascaded, and the logic control unit 101 outputs the corresponding low level signal or high level signal based on the scan signals of the previous stage scan driving module 10 and the next stage scan driving module 10, which is only an exemplary embodiment of the present application, and is not limited in practical implementation.
Referring to fig. 5, the output unit includes a pull-up unit 102 and a pull-down unit 103.
The pull-up unit 102 includes a pull-up switch unit M1, a bootstrap capacitor C, a first switch unit T1, a second switch unit T2, and a first node N1, a second node N2, and a third node N3. The first node N1 is used as a Scan signal output node of the Scan driving module 10, and outputs a Scan signal Scan. The third node N3 serves as a clock signal input node configured to receive the clock signal CK.
The pull-up switch unit M1 has a control end, a first end and a second end, wherein the control end of the pull-up switch unit M1 is connected to the second node N2, the first end of the pull-up switch unit M1 is connected to the third node N3, and the second end of the pull-up switch unit M1 is connected to the first node N1. When the pull-up switch unit M1 is fully turned on, the potential of the first node N1 is equal to the potential of the third node N3, that is, the potential of the first node N1 is equal to the high potential of the clock signal, and the scan driving module 10 outputs the scan signal VDD with the high potential.
In this embodiment, the pull-up switching unit M1 is a pull-up transistor, the control terminal corresponds to a gate of the pull-up transistor, and the first terminal and the second terminal correspond to a source and a drain of the pull-up transistor, respectively. The pull-up transistor is preferably a MOS transistor, and has the advantages of strong anti-interference capability, low power consumption and simple control mode.
In an embodiment, the pull-up switch unit M1 is a thin film transistor, which has fast response time and low power consumption, and is beneficial to achieving a good image display effect.
Alternatively, the pull-up unit M1 may be another type of switching unit.
The first switch unit T1 has a control end, a first end and a second end, wherein the control end of the first switch unit T1 is connected to the second output end P of the logic control unit 101, the first end of the first switch unit T1 is connected to the voltage signal source, and the second end of the first switch unit T1 is connected to the first node N1. The voltage signal source is configured to provide a preset level signal VM, where the preset level signal VM is smaller than a high level VDD of the clock signal CK and is greater than a low level VSS of the clock signal CK, when the second output terminal P of the logic control unit 101 is at a high level, the first switch unit T1 is turned on, the potential of the first node N1 is pulled up to the preset level signal VM, and when the second output terminal P of the logic control unit 101 is at a low level, the first switch unit T1 is turned off, and the preset level signal VM cannot be output to the first node N1 through the first switch unit T1.
In this embodiment, the first switching unit T1 is a transistor, the control terminal is corresponding to the gate of the transistor, and the first terminal and the second terminal are corresponding to the source and the drain of the transistor, respectively. The transistor is preferably an MOS transistor, has strong anti-interference capability, low power consumption and simple control mode.
In an embodiment, the first switch unit T1 is a thin film transistor, which has fast response time and low power consumption, and is beneficial to achieving a good image display effect.
Alternatively, the first switching unit T1 may be another type of switching unit.
In this embodiment, the preset level signal VM is smaller than the turn-on voltage of the scan transistor in the pixel unit, wherein the control terminal of the scan transistor is connected to the first node N1. The preset level signal VM is set to be smaller than the on voltage of the scan transistor in the pixel unit, so that abnormal display of the picture caused by that the preset level signal VM turns on the scan transistor in the pixel unit in advance can be avoided.
In some embodiments, other mechanisms may be provided to avoid the scan transistor in the pixel unit from being turned on in advance, and the preset level signal VM may be equal to or greater than the turn-on voltage of the scan transistor in the pixel unit.
Alternatively, the preset level signal VM may be a fixed level signal, and when the first switching unit T1 is turned on, the potential of the first node N1 is pulled up to the fixed level.
Alternatively, the preset level signal VM may be a level signal including a plurality of different magnitudes. For example, the preset level signal VM includes a first level signal and a second level signal greater than the first level signal, and accordingly, a period in which the second output terminal P of the logic control unit 101 is high and the clock signal CK is low includes a first period and a second period later than the first period, and the voltage signal source is configured to supply the first level signal in the first period and the second level signal in the second period. For another example, the preset level signal VM includes a first level signal, a second level signal, and a third level signal, the magnitudes of the first level signal, the second level signal, and the third level signal are sequentially increased, and accordingly, the period in which the second output terminal P of the logic control unit 101 is at a high level and the clock signal CK is at a low level includes a first period, a second period, and a third period, and the time corresponding to the first period, the second period, and the third period is sequentially pushed, and the voltage signal source is configured to provide the first level signal in the first period, the second level signal in the second period, and the third level signal in the third period. By this arrangement, the potential of the first node N1 can be pulled up in stages.
In an embodiment, the voltage signal source is a timing controller, and the preset level signal VM is output through an idle output channel of the timing controller, without adding additional electronic devices. Of course, the voltage signal source may be an additionally provided voltage source.
The second switch unit T2 has a control end, a first end and a second end, where the control end of the second switch unit T2 is connected to the third node N3, the first end of the second switch unit T2 is connected to the second node N2, and the second end of the second switch unit T2 is connected to the second output end P of the logic control unit 101. When the clock signal CK is at a high level, the second switching unit T2 is turned on to turn on the pull-up switching unit M1, thereby pulling the potential of the first node N1 up to the high level VDD of the clock signal CK, when the clock signal CK is at a low level, the second switching unit T2 is turned off, the pull-up switching unit M1 is turned off, and the high level VDD of the clock signal CK cannot be output to the first node N1 through the pull-up switching unit M1.
In this embodiment, the second switching unit T2 is a transistor, the control terminal is corresponding to the gate of the transistor, and the first terminal and the second terminal are corresponding to the source and the drain of the transistor, respectively. The transistor is preferably an MOS transistor, has strong anti-interference capability, low power consumption and simple control mode.
In an embodiment, the second switching unit T2 is a thin film transistor, which has a fast response time and low power consumption, and is beneficial to achieving a good image display effect.
Alternatively, the second switching unit T2 may be another type of switching unit.
One end of the bootstrap capacitor C is connected with the first node N1, and the other end of the bootstrap capacitor C is connected with the second node N2.
With continued reference to fig. 5, the pull-down unit 103 is connected to the first output terminal Q of the logic control unit 101 and the first node N1 for pulling the potential of the first node N1 low.
In this embodiment, the pull-down unit 103 includes a pull-down switch unit M2, where the pull-down switch unit M2 has a control terminal, a first terminal and a second terminal, where the control terminal of the pull-down switch unit M2 is connected to the first output terminal Q of the logic control unit 101, the first terminal of the pull-down switch unit M2 is connected to the first node N1, and the second terminal of the pull-down switch unit M2 is connected to the common ground terminal, i.e., VSS. When the first output terminal Q of the logic control unit 101 outputs a high level, the pull-down switch unit M2 is turned on to pull down the level of the first node N1 to the level of the common ground, i.e., pull down the level of the first node N1 to the low level VSS of the clock signal.
In this embodiment, the pull-down switching unit M2 is a pull-down transistor, the control terminal is corresponding to the gate of the pull-down transistor, and the first terminal and the second terminal are corresponding to the source and the drain of the pull-down transistor, respectively. The pull-down transistor is preferably a MOS transistor, so that the anti-interference capability is high, the power consumption is low, and the control mode is simple.
In an embodiment, the pull-down switch unit M2 is a thin film transistor, which has fast response time and low power consumption, and is beneficial to realizing good image display effect.
Alternatively, the pull-down unit M2 may be another type of switching unit.
The operation principle of the pull-up unit 102 will be described with reference to fig. 5 and 6:
at time T0, the second output terminal P is at the low level VSS, the first switch unit T1 is turned off, the preset level signal VM cannot be output to the first node N1 through the first switch unit T1, and the first node N1 is at the low level, so the Scan signal Scan is at the low level VSS. At time T1, the second output terminal P is at a high level V1, the clock signal CK is at a low level VSS, the first switching unit T1 is turned on, the second switching unit T2 is turned off, and the preset level signal VM is output to the first node N1 through the first switching unit T1, so the Scan signal Scan is the preset level signal VM. At time T2, the second output terminal P is still at a high level, the clock signal CK is also at a high level, the first switch unit T1, the second switch unit T2, and the pull-up switch unit M1 are all turned on, and under the action of the bootstrap capacitor C, the second output terminal P is further pulled up to a higher level V2, at this time, the pull-up switch unit M1 can be fully opened, and the first end and the second end of the pull-up switch unit M1 can reach the same potential, so the first node N1 is the high level VDD of the clock signal CK, and the Scan signal Scan is the high level VDD of the clock signal CK. At time t3, the second output terminal P is at the low level VSS, the clock signal CK is at the low level VSS, and the potential of the first node N1 is pulled down to the low level VSS by the pull-down unit 103.
It should be noted that, in practical implementation, when the potential of the first node N1 needs to be pulled up to the preset level signal VM, the clock signal CK is preferably configured to be at the low level VSS to ensure that the second switch unit T2 is not turned on in advance. That is, when the clock signal CK is at the low level VSS and the second output terminal P is at the high level, the first switching unit T1 is turned on, and the preset level signal VM is output to the first node N1 through the first switching unit T1. When the clock signal CK is at the high level VSS and the second output terminal P is at the high level, the first switch unit T1 and the second switch unit T2 are configured to be turned on, so that the pull-up switch unit M1 is turned on, the high level VDD of the clock signal CK is output to the first node N1, and the Scan signal Scan is the high level VDD of the clock signal CK.
In summary, in the scan driving circuit disclosed by the application, a first switch unit T1 and a second switch unit T2 are arranged in the pull-up unit 102, a control end of the first switch unit T1 is connected to a second output end P of the logic control unit 101, a first end is connected to a voltage signal source, a second end is connected to a first node N1, and the first switch unit T1 is turned on when the second output end P of the logic control unit 101 is at a high level; the control end of the second switching unit T2 is connected to the third node N3, the first end is connected to the second node N2, the second end is connected to the second output end P of the logic control unit 101, and the second switching unit T2 is turned on when the clock signal CK is at the high level VDD. Before the rising edge of the clock signal CK comes, a preset level signal VM smaller than the high level VDD of the clock signal CK and larger than the low level VSS of the clock signal CK is provided to the first end of the first switch unit T1 through a voltage signal source, the level of the first node N1 is pulled up in advance by using the preset level signal VM, and the voltage difference between the level of the first node N1 and the high level VDD of the clock signal CK is reduced, as shown in fig. 7, the voltage difference Δv between the level of the first node N1 and the high level VDD of the clock signal CK is smaller than the voltage difference Δv' corresponding to the scan driving circuit shown in fig. 2. When the rising edge of the clock signal CK comes, the level of the first node N1 only needs to be pulled up to the high level VDD of the clock signal CK by the preset level signal VM, and because the level variation amplitude of the first node N1 is small, the potential coupling influence of parasitic capacitance on other nodes can be reduced, meanwhile, the problem of insufficient effective charging time of the scanning transistor caused by level switching delay can be solved, and the picture display effect is improved.
The present application also provides a scan driving method which can be applied to the scan driving circuit in any of the foregoing embodiments, the scan driving method including: when the second output end of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output a preset level signal to the first end of the first switch unit.
In one embodiment, the preset level signal is a fixed level signal, and when the second output terminal of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output the preset level signal to the first terminal of the first switch unit.
In one embodiment, the preset level signal includes two level signals with different magnitudes, and correspondingly, the period in which the second output terminal of the logic control unit is at a high level and the clock signal is at a low level includes a first period and a second period later than the first period. When the second output end of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output a first level signal to the first end of the first switch unit in a first period, and is enabled to output a second level signal to the first end of the first switch unit in a second period.
In one embodiment, the preset level signal includes three level signals with different magnitudes, and correspondingly, the period in which the second output terminal of the logic control unit is at a high level and the clock signal is at a low level includes a first period, a second period later than the first period, and a third period later than the second period. When the second output end of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output a first level signal to the first end of the first switch unit in a first period, the voltage signal source is enabled to output a second level signal to the first end of the first switch unit in a second period, and the voltage signal source is enabled to output a third level signal to the first end of the first switch unit in a third period.
The level of the first node is pulled up in advance by using the preset level signal, the voltage difference between the level of the first node and the high level of the clock signal is reduced, when the rising edge of the clock signal arrives, the level of the first node only needs to be pulled up to the high level of the clock signal by the preset level signal, the level change amplitude of the first node is small, the potential coupling influence of parasitic capacitance on other nodes can be reduced, meanwhile, the problem that the effective charging time of a scanning transistor is insufficient due to level switching delay is solved, and the picture display effect is improved.
Referring next to fig. 8, the present application also provides a display device including a driving circuit 100 and a display panel 200. The driving circuit 100 is connected to the display panel 200, and is used for driving the display panel 200 to display images.
The display panel 200 includes a plurality of pixel units, which are arranged in an array to form a pixel unit array. The pixel unit comprises a scanning transistor S-TFT, a driving transistor D-TFT, a first capacitor Cst and a sub-pixel OLED.
The control terminal of the scan transistor S-TFT is connected to the row line, i.e. to the aforementioned first node N1, and the first terminal of the scan transistor S-TFT is connected to the column line for receiving the data voltage V Data The second end of the scanning transistor S-TFT is connected with the control end of the driving transistor D-TFT. The first end of the driving transistor D-TFT is connected with the power supply ELVDD, the second end of the driving transistor D-TFT is connected with the power supply ELVSS, and when the scanning transistor S-TFT is conducted, the control end of the driving transistor D-TFT is at a high level, and the driving transistor D-TFT is conducted. One end of the first capacitor Cst is connected to a control end of the driving transistor D-TFT, that is, a second end of the scanning transistor S-TFT.
It is understood that the control terminal of the scan transistor S-TFT corresponds to the gate of the scan transistor S-TFT, and the first terminal and the second terminal correspond to the source and the drain of the scan transistor S-TFT, respectively. Similarly, the control end of the driving transistor D-TFT corresponds to the grid electrode of the driving transistor D-TFT, and the first end and the second end respectively correspond to the source electrode and the drain electrode of the driving transistor D-TFT.
The sub-pixel is an OLED, the anode of the OLED is connected with the second end of the driving transistor D-TFT, and the cathode of the OLED is connected with the power supply ELVSS. When the driving transistor D-TFT is turned on, the OLED is turned on to emit light, so that picture display is realized.
The driving circuit 100 includes the scanning driving circuit described in any of the above-described aspects. The scan driving circuit may be formed In an edge region of the display Panel 200 In a Gate In Panel (GIP or GOA) method, for example, the display Panel 200 includes a display region and a non-display region at an edge, and the scan driving circuit is formed In the non-display region of the display Panel 200.
The driving circuit 100 further includes a timing controller 20, a data driving circuit 30, and a power circuit 40, and can be specifically referred to fig. 1. Wherein the data driving circuit 30 is connected to the timing controller 20 for outputting corresponding data voltage V based on the control signal of the timing controller 20 Data And driving the pixel units on the current pilot line to each column of data line, so as to realize picture display. The power supply circuit 40 is for supplying power supplies ELVDD and ELVSS.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (10)
1. The scanning driving circuit is characterized by comprising a plurality of scanning driving modules, wherein each scanning driving module comprises a logic control unit, a pull-up unit and a pull-down unit, and the pull-down unit is connected to a first output end and a first node of the logic control unit; wherein, the pull-up unit includes:
a pull-up switch unit, a control end of the pull-up switch unit is connected with a second node, a first end of the pull-up switch unit is connected with a third node, the third node is configured to receive a clock signal, and a second end of the pull-up switch unit is connected with the first node;
one end of the bootstrap capacitor is connected with the first node, and the other end of the bootstrap capacitor is connected with the second node;
the control end of the first switch unit is connected with the second output end of the logic control unit, the first end of the first switch unit is connected with a voltage signal source, the voltage signal source is used for providing a preset level signal, the high level of the preset level signal is smaller than that of the clock signal and is larger than that of the clock signal, and the second end of the first switch unit is connected with the first node;
the control end of the second switch unit is connected with the third node, the first end of the second switch unit is connected with the second node, and the second end of the second switch unit is connected with the second output end of the logic control unit;
the first switch unit is configured to be turned on when the second output end of the logic control unit is at a high level so as to pull up the potential of the first node to the preset level signal, and the second switch unit is configured to be turned on when the clock signal is at a high level so as to pull up the potential of the first node to the high level of the clock signal.
2. The scan driving circuit according to claim 1, wherein the preset level signal is smaller than a turn-on voltage of a scan transistor in the pixel unit, and a control terminal of the scan transistor is connected to the first node.
3. The scan driving circuit according to claim 1 or 2, wherein the preset level signal includes a first level signal and a second level signal greater than the first level signal, a period in which the second output terminal of the logic control unit is high and the clock signal is low includes a first period and a second period later than the first period, and the voltage signal source is configured to supply the first level signal in the first period and the second level signal in the second period.
4. A scan driving circuit according to claim 3, wherein the voltage signal source is a timing controller.
5. The scan driving circuit according to claim 1, wherein the first switching unit and the second switching unit are thin film transistors.
6. The scan driving circuit according to claim 1, wherein the pull-down unit comprises a pull-down switch unit, a control terminal of the pull-down switch unit is connected to a first output terminal of the logic control unit, a first terminal of the pull-down switch unit is connected to the first node, and a second terminal of the pull-down switch unit is connected to a common ground terminal.
7. The scan driving circuit according to claim 1, wherein the plurality of scan driving modules are cascaded, and the logic control unit of at least some of the scan driving modules is configured to output a corresponding low level signal or high level signal to the second output terminal based on the scan signal of the previous stage scan driving module, and output a corresponding low level signal or high level signal to the first output terminal based on the scan signal of the next stage scan driving module.
8. A scan driving method for the scan driving circuit according to any one of claims 1 to 7, comprising:
when the second output end of the logic control unit is at a high level and the clock signal is at a low level, the voltage signal source is enabled to output a preset level signal to the first end of the first switch unit.
9. A display device, comprising:
a display panel including a pixel cell array;
a driving circuit for driving the pixel unit, comprising the scanning driving circuit of any one of claims 1 to 7.
10. The display device according to claim 9, wherein the pixel unit is a self-luminous pixel unit.
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