KR102658432B1 - Emitting control Signal Generator and Light Emitting Display Device including the same - Google Patents

Abstract

The present invention relates to a light emission control signal generator capable of reliably maintaining a high voltage of a light emission control signal and a light emitting display device including the same, wherein the light emission control signal generator is dependently connected to sequentially output the light emission control signal. An output unit comprising a plurality of stages, each stage outputting a first voltage as a light emission control signal according to the potential of the QB-node and outputting a second voltage as a light emission control signal according to the potential of the Q-node; A node control unit that operates based on a start signal or a light emission control signal output from a previous stage, a first clock signal, and a second clock signal to control the potentials of the QB-node and the Q-node; and a node prevention transistor that compensates so that the high voltage of the light emission control signal can be stably output even if voltage coupling occurs due to the first clock signal and the Q-node changes to the turn-on voltage.

Description

Light emitting control signal generator and light emitting display device including the same {Emitting control Signal Generator and Light Emitting Display Device including the same}

The present invention relates to a light emitting display device, and particularly to a light emitting control signal generator and a light emitting display device including the same.

As the information society develops and various portable electronic devices such as mobile communication terminals and laptop computers develop, the demand for flat panel display devices applicable to them is gradually increasing.

As such flat display devices, liquid crystal displays (LCDs) using liquid crystals and OLED displays using organic light emitting diodes (OLEDs) are used.

These flat panel display devices consist of a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

Among the above display devices, the display panel of the liquid crystal display device includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed on a glass substrate, and the thin film transistor A liquid crystal layer is provided between the array substrate and the color filter array substrate.

The thin film transistor array substrate includes a plurality of gate lines (GL) extending in a first direction and a plurality of data lines (DL) extending in a second direction perpendicular to the first direction, and each gate line One sub-pixel area (Pixel; P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub-pixel area (P).

The display panel of such a liquid crystal display device generates an electric field in the liquid crystal layer by applying a voltage to the electric field generating electrodes (pixel electrode and common electrode), and adjusts the arrangement of liquid crystal molecules in the liquid crystal layer by the electric field to control the amount of incident light. Images are displayed by controlling polarization.

In addition, in the display panel of the OLED display device among the above display devices, sub-pixels are defined by crossing the plurality of gate lines and the plurality of data lines, and each sub-pixel includes an anode and a cathode and an anode and a cathode. It is provided with an OLED composed of an organic light-emitting layer therebetween, and a pixel circuit that independently drives the OLED.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to the scan pulse. The driving TFT adjusts the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

Recently, it is further equipped with a light emission control transistor to determine the light emission time of the pixels.

The display panel for such a display device is defined by a display area (active area, AA) that provides an image to the user and a non-display area (NA) that is a surrounding area of the display area (AA).

Additionally, the driving circuit for driving the display panel includes a gate driving circuit that sequentially supplies gate pulses (or scan pulses) to the plurality of gate lines of the display panel, and the plurality of data lines of the display panel. It consists of a data driving circuit that supplies data voltage to the gate driving circuit and a timing controller that supplies image data and various control signals to the data driving circuit.

The gate driving circuit may be composed of at least one gate drive IC, but may cause non-display of the display panel in the process of forming the plurality of signal lines (gate lines and data lines) and sub-pixels of the display panel. They can be formed simultaneously in an area.

That is, the Gate-In-Panel (hereinafter referred to as “GIP”) method, which directly integrates the gate driving circuit into the display panel, is being applied.

The gate driving circuit as described above outputs scan signals and emission control signals that can turn on or off the switching transistor and emission control transistor formed in the display panel.

The gate driving circuit includes a scan signal generator and an emission control signal generator including a plurality of stages equal to or greater than the number of gate lines in order to sequentially supply scan signals and emission control signals.

However, there was a problem in that a node voltage drop occurred in the emission control signal generator for sequentially supplying emission control signals, causing the emission control signal to be abnormally generated.

The present invention is intended to solve the above problems. The purpose of the present invention is to provide a light emission control signal generator that can reliably maintain a high voltage of the light emission control signal and a light emitting display device including the same.

The light emission control signal generator according to the present invention for achieving the above object includes a plurality of stages that are dependently connected to sequentially output the light emission control signal, and each stage has a first stage according to the potential of the QB-node. An output unit that outputs a voltage as a light emission control signal and outputs a second voltage as a light emission control signal according to the potential of the Q-node, a light emission control signal output from a start signal or previous stage, a first clock signal, and a second A node control unit that operates based on a clock signal to control the potentials of the QB-node and the Q-node, and even if voltage coupling is generated by the first clock signal and the Q-node changes to the turn-on voltage, It is characterized by having a node prevention transistor that compensates so that the high voltage of the light emission control signal can be output stably.

The node control unit has a gate electrode connected to a second clock signal supply line supplying the second clock signal, a first electrode connected to an output terminal of a start signal line supplying the start signal or a previous stage thereof, and the Q- A first transistor with a second electrode connected to a node, a second transistor with a gate electrode connected to a first clock signal line that supplies the first clock signal and a first electrode connected to the Q-node, and the second transistor a third transistor having a first electrode connected to a second electrode and a second electrode connected to a first voltage supply line supplying a first voltage, and a gate electrode connected to the second clock signal supply line and the second transistor a fourth transistor whose first electrode is connected to a second voltage supply line that supplies voltage and whose second electrode is connected to the gate electrode of the third transistor, and whose gate electrode is connected to the Q-node and to the QB-node; A fifth transistor having a first electrode connected to the first voltage supply line and a second electrode connected to the first voltage supply line, a gate electrode connected to the second electrode of the fourth transistor and a first electrode connected to the first clock signal supply line An eighth transistor is connected, a gate electrode is connected to the first clock signal supply line, a first electrode is connected to the second electrode of the eighth transistor T8, and a second electrode is connected to the QB-node. It is characterized in that it includes 9 transistors and a 10th transistor whose gate electrode is connected to the Q-node and whose first electrode is connected to the second clock signal supply line.

The node compensation transistor has a gate electrode connected to the start signal line or the output terminal of the previous stage, a first electrode connected to the second electrode of the tenth transistor, and a second electrode connected to the gate electrode of the eighth transistor. It is characterized by being

The node control unit includes a first capacitor connected between the Q-node and the first clock signal supply line, a second capacitor connected between the QB-node and the first voltage supply line, and the eighth transistor. It is characterized in that it further includes a third capacitor connected between the gate electrode of and the second electrode of the eighth transistor.

The output unit includes a sixth transistor having a gate electrode connected to the Q-node, a first electrode connected to a second voltage supply line that supplies the second voltage, and a second electrode connected to an output terminal, and the QB- It is characterized by comprising a seventh transistor in which a gate electrode is connected to a node, a first electrode is connected to the output terminal, and a second electrode is connected to a first voltage supply line that supplies the first voltage.

The light emission control signal generator is controlled according to a reset signal and further includes a reset transistor that resets the output terminal of the output unit to the first voltage.

In addition, a light emitting display device according to the present invention for achieving the above object includes a display panel that displays an image, a scan signal generator that supplies a scan signal to the display panel, and a light emitting control signal that is supplied to the display panel. and a light emission control signal generator that supplies a light emission control signal, wherein the light emission control signal generator includes a plurality of stages that are dependently connected to sequentially output light emission control signals, and each stage generates a first voltage according to the potential of the QB-node. An output unit that outputs a light emission control signal and outputs a second voltage as a light emission control signal according to the potential of the Q-node, a start signal or a light emission control signal output from the previous stage, a first clock signal, and a second clock A node control unit that operates based on a signal to control the potential of the QB-node and the Q-node, and voltage coupling is generated by the first clock signal to emit light even if the Q-node changes to the turn-on voltage It is characterized by having a node prevention transistor that compensates so that the high voltage of the control signal can be output stably.

The light emission control signal generator according to the present invention having the above features and the light emitting display device including the same have the following effects.

Since the node compensation transistor exists, when the duty driving of the emission control signal (EM) is performed, the output of the emission control signal (EM) can stably maintain a high voltage state.

In addition, since the node compensation transistor as described above exists, the output margin of the light emission control signal is improved, thereby improving the reliability of the light emission control signal generator.

1 is a block diagram schematically showing an OLED display device according to an embodiment of the present invention.
Figure 2 is an equivalent circuit diagram schematically showing the subpixel shown in Figure 1
Figure 3 is a first configuration example diagram of a device related to the scan driver shown in Figure 1
Figure 4 is a second configuration example of a device related to the scan driver shown in Figure 1
Figure 5 is a first configuration example diagram of the shift register shown in Figure 3
Figure 6 is a block diagram showing light emission control signal generators according to the first embodiment of the present invention.
Figure 7 is a circuit diagram showing in detail the light emission control signal generator of the (k)th stage according to the first embodiment of the present invention.
Figure 8 is an example waveform for explaining the operation of the light emission control signal generator according to the present invention.
Figure 9 is a stress summary table of elements of the light emission control signal generator according to the present invention.
Figure 10 is an example waveform when there is no node compensation unit in the light emission control signal generator according to the present invention.
Figure 11 is an example waveform by the node compensation unit in the light emission control signal generator according to the present invention.

Hereinafter, the light emission control signal generator according to the present invention having the above features and the light emitting display device including the same will be described in more detail with reference to the attached drawings.

The device described below includes a p-type thin film transistor as an example, but it may also be implemented as an n-type thin film transistor or a combination of n-type and p-type. A thin film transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within a thin film transistor, carriers begin to flow from a source. The drain is the electrode through which carriers go out in a thin film transistor. That is, in a thin film transistor, carriers flow from the source to the drain.

In the case of an n-type thin film transistor, because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type thin film transistor, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. On the other hand, in the case of a p-type thin film transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, current flows from the source to the drain because holes flow from the source to the drain. However, the source and drain of a thin film transistor can change depending on the applied voltage. Reflecting this, in the following description, one of the source and drain will be described as the first electrode, and the other one of the source and drain will be described as the second electrode.

FIG. 1 is a block diagram schematically showing an OLED display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram schematically showing the subpixel shown in FIG. 1.

As shown in Figures 1 and 2, the organic electroluminescent display device according to an embodiment of the present invention includes an image supply unit 110, a timing control unit 120, a scan driver 130, a data driver 140, and a display panel. 150 and a power supply unit 180 are included.

The image supply unit 110 (or host system) outputs various driving signals in addition to image data signals supplied from the outside or image data signals stored in internal memory. The image supply unit 110 may supply data signals and various driving signals to the timing control unit 120.

The timing control unit 120 generates a gate timing control signal (GDC) for controlling the operation timing of the scan driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals. (Vsync, a vertical synchronization signal, Hsync, a horizontal synchronization signal) are output.

The timing control unit 120 supplies the data signal DATA supplied from the image supply unit 110 along with the data timing control signal DDC to the data driver 140. The timing control unit 120 may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited to this.

The scan driver 130 includes a scan signal generator and a light emission control signal generator that output a scan signal (or scan voltage) and a light emission control signal in response to a gate timing control signal (GDC) supplied from the timing control unit 120. do.

The scan driver 130 supplies scan signals to subpixels included in the display panel 150 through gate lines GL1 to GLm. Additionally, the scan driver 130 outputs an emission control signal to emission control lines to control emission control transistors configured in each sub-pixel. During the period when the data voltage (Vdata) is addressed, the scan signal is generated at the turn-on level, and the light emission control signal is generated at the turn-off level. Then, during the period when the pixels emit light, the scan signal is generated at the turn-off level, and the light emission The control signal is generated at the turn-on level.

The scan driver 130 may be formed in the form of an IC or directly on the display panel 150 using a gate in panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal (DATA) in response to the data timing control signal (DDC) supplied from the timing control unit 120 and converts the data signal in digital form into analog form based on the gamma reference voltage. Converts it to data voltage and outputs it.

The data driver 140 supplies data voltage to subpixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates and outputs a high-potential first panel power source (EVDD) and a low-potential second panel power source (EVSS) based on an external input voltage. The power supply unit 180 supplies not only the first panel power and the second panel power (EVDD, EVSS) but also the voltage (e.g., scan high voltage, scan low voltage) required to drive the scan driver 130 or the data driver 140. The voltage (drain voltage, half-drain voltage) required for driving can be generated and output.

The display panel 150 receives a driving signal including a scan signal and a data voltage output from a driving unit including a scan driving unit 130 and a data driving unit 140, and a first panel power output from the power supply unit 180 and a second power supply. 2 Displays images according to panel power (EVDD, EVSS). Subpixels of the display panel 150 directly emit light.

The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. And the subpixels that emit light may be composed of pixels containing red, green, and blue, or pixels containing red, green, blue, and white.

For example, in one subpixel (SP), as shown in FIG. 2, an OLED element (OLED) that emits light by a driving current flowing between a high potential voltage (VDD) and a low potential voltage (VSS), and the OLED Using the driving TFT (DT), which controls the amount of driving current applied to the device (OLED), the data voltage (Vdata) applied from the data line (DL), and the scan signal (SCAN) applied from the gate line (GL), etc. A switch circuit (SWC) that adjusts the gate voltage of the driving TFT (DT), and an emission control TFT (ET) that turns on/off the current flow between the driving TFT (DT) and the OLED in response to the emission control signal (EM). It consists of: Here, the TFTs formed in the pixel may be selected as P-type, but are not limited to this and may be selected as N-type.

Although not shown in FIG. 2, a sensing transistor for sensing the threshold voltage or mobility of the driving TFT (DT) to compensate for the deterioration (threshold voltage or mobility) of the driving TFT (DT), and the driving transistor ( DT) may further include an internal compensation circuit to compensate for the threshold voltage or mobility.

Meanwhile, in the above description, the timing control unit 120, scan driver 130, data driver 140, etc. were described as if they were individual components. However, depending on the implementation method of the light emitting display device, one or more of the timing control unit 120, scan driver 130, and data driver 140 may be integrated into one IC.

FIG. 3 is an example diagram of a first configuration of a device related to the scan driver shown in FIG. 1, FIG. 4 is an example diagram of a second configuration of a device related to the scan driver shown in FIG. 1, and FIG. 5 is an example diagram of the device related to the scan driver shown in FIG. This is an example of the configuration of a shift register.

As shown in FIG. 3, the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 generates and outputs a plurality of clock signals (GCLK, ECLK) and start signals (GVST, EVST) based on signals output from the timing control unit 120. Multiple clock signals (GCLK, ECLK) may be generated and output in the form of K (K is an integer greater than 2) with different phases, such as 2-phase, 4-phase, and 8-phase.

The shift register 131 operates based on signals (GCLK, ECLK, GVST, EVST) output from the level shifter 135 and scan signals that can turn on or off the transistor formed in the display panel. (Scan[1] ~ Scan[m]) and emission control signals (EM[1] ~ EM[m]) are output. The shift register 131 is formed in the form of a thin film on the display panel by a gate-in-panel method. Accordingly, the portion of the scan driver 130 formed on the display panel may be the shift register 131.

Unlike the shift register 131, the level shifter 135 is formed in the form of an IC. The level shifter unit 135 may be configured as a separate IC as shown in FIG. 3, and may be included inside the power supply unit 180 or another device as shown in FIG. 4.

As shown in FIG. 5, the shift register 131 is composed of multiple stages (STG1 to STGm). A plurality of stages (STG1 to STGm) have a dependently connected structure and receive at least one output signal from the front or back stage as an input signal.

The stages (STG1 to STGm) of the shift register 131 include scan signal generators (SCAN[1] to SCAN[m]) and emission control signal generators (EM[1] to EM[m]), respectively. can do.

For example, the first stage (STG1) includes a first scan signal generator (SCAN[1]) that outputs a first scan signal (Scan[1]) and a light emission control device that outputs a light emission control signal (Em[1]). It has a signal generator (EM[1]).

The scan signal generators (SCAN[1] ~ SCAN[m]) output scan signals (Scan[1] ~ Scan[m]) through scan lines of the display panel. The emission control signal generators (EM[1] to EM[m]) output emission control signals (Em[1] to Em[m]) through the emission control signal lines of the display panel.

The emission control signals (Em[1] to Em[m]) may be used as signals to drive emission control transistors included in subpixels. For example, when the emission control transistors of subpixels are controlled using emission control signals (Em[1] to Em[m]), the emission time of the organic light emitting diode is varied.

However, the example in FIG. 5 is an example to help understand the shift register 131, and the present invention is not limited to this, and may be implemented in a form that outputs more diverse and more signals.

Although not shown in the drawing, the scan signal generators (SCAN[1] ~ SCAN[m]) that output the scan signals (Scan[1] ~ Scan[m]) generate a scan start signal (GVST), They may be driven by a high voltage (GVGH), a reset signal for scanning (GRST), a low voltage for scanning (GVGL), and clock signals for scanning (GCLKs).

The light emission control signal generators (EM[1] ~ EM[m]) that output the light emission control signals (Em[1] ~ Em[m]) include a start signal (EVST), a reset signal (ERST), and a high voltage. (EVGH), low voltage (EVGL), and clock signals (ECLKs).

Figure 6 is a block diagram showing the emission control signal generators according to the first embodiment of the present invention, and Figure 7 is a circuit configuration showing in detail the emission control signal generator of the (k)th stage according to the first embodiment of the present invention. It is also a degree.

As shown in FIG. 6, the emission control signal generators (EM[1] to EM[m]) according to the first embodiment of the present invention have dependently connected stages (STG1 to STGm-1). And the light emission control signal generators (EM[1] ~ EM[m-1]) receive the signal output through the output terminal at the front end as a start signal at the back end.

The emission control signal output from the output terminal (EMO[1]) of the emission control signal generator (EM[1]) of the first stage (STG1) is applied to the first pixel group (Pixel[1]), and is also applied to the first pixel group (Pixel[1]). It is also applied to the input terminal of the start signal of the emission control signal generator (EM[1]) of the second stage (STG2). Therefore, the light emission control signal generator (EM[1]) of the first stage (STG1) is connected to the light emission start signal line (EVST), but the light emission control signal generator (EM[2]) of the second stage (STG2) is connected to the light emission start signal line (EVST). The light emission control signal output from the light emission control signal generator of the previous stage is used as a start signal.

In FIG. 6, the light emission signal output from the output terminal (EMO[1]) of the light emission control signal generator (EM[1]) of the first stage (STG1) is expressed as "Start[1]". This is to show that the output signal of ) is used as the start signal of the next stage. In addition, this connection relationship and signal transmission system are applied equally to all stages (STG1 to STGm-1).

As shown in FIG. 7, the light emission control signal generator (EM[k]) of the (k)th stage according to the first embodiment of the present invention includes the first transistor (T1) to the tenth transistor (T10) and the node. It may include a compensation transistor (Tbk), first to third capacitors (CQ, CQB, CQ'), and a reset transistor (TR).

The sixth and seventh transistors T6 and T7 among the first transistors T1 to tenth transistors T10 and the node compensation transistor Tbk may be included in an output unit that outputs a light emission control signal.

The first to fifth transistors T1 to T5 and the eighth to tenth transistors T8 to T10 may be included in the node control unit.

For example, the first transistor (T1) to the tenth transistor (T10), the node compensation transistor (Tbk), and the reset transistor (TR) are implemented as p-type thin film transistors. The first transistor (T1) to the tenth transistor (T10), the node compensation transistor (Tbk), and the reset transistor (TR) implemented with p-type thin film transistors are turned on under the condition of applying a low voltage (EVGL) and are turned on at a high voltage. It is turned off under the condition that (EVGH) is applied.

The first transistor (T1) has its gate electrode connected to the second clock signal line (ECLK2), its first electrode connected to the start signal line (EVST) or the output terminal (EMO (k-1)) of this previous stage, and Q -A second electrode is connected to the node (QN). The first transistor T1 is turned on or off according to the second clock signal applied through the second clock signal line ECLK2.

The second transistor T2 has a gate electrode connected to the first clock signal line ECLK1, a first electrode connected to the Q-node (QN), and a second electrode connected to the first electrode of the third transistor T3. connected. The second transistor T2 is turned on or off according to the first clock signal applied through the first clock signal line ECLK1.

The third transistor T3 has a gate electrode connected to the second electrode of the fourth transistor T4, a first electrode connected to the second electrode of the second transistor T2, and a first electrode connected to the first voltage line EVGH. 2 electrodes are connected. When the fourth transistor T4 is turned on, the third transistor T3 is turned on according to the second voltage applied through the second voltage line EVGL.

The fourth transistor T4 has a gate electrode connected to the second clock signal line ECLK2, a first electrode connected to the second voltage line EVGL, and a second electrode connected to the gate electrode of the third transistor T3. Electrodes are connected. The fourth transistor T4 is turned on or off according to the second clock signal applied through the second clock signal line ECLK2. Accordingly, the fourth transistor T4 is turned on or off simultaneously with the first transistor T1.

The fifth transistor T5 has a gate electrode connected to the Q-node (QN), a first electrode connected to the QB-node (QBN), and a second electrode connected to the first voltage line (EVGH). The fifth transistor T5 is turned on or turned off depending on the potential of the Q-node (QN).

The sixth transistor (T6) has a gate electrode connected to the Q-node (QN) and one end of the first capacitor (CQ), a first electrode connected to the second voltage line (EVGL), and light emission of the (k)th stage. The second electrode is connected to the output terminal (EMO[k]) of the control signal generator (EM[k]). The sixth transistor T6 is turned on or turned off depending on the potential of the Q-node (QN).

The seventh transistor (T7) has a gate electrode connected to the QB-node (QBN) and a first electrode connected to the output terminal (EMO[k]) of the light emission control signal generator (EM[k]) of the (k)th stage. is connected, and a second electrode is connected to the first voltage line (EVGH). The seventh transistor T7 is turned on or turned off depending on the potential of the QB-node (QBN).

The eighth transistor T8 has a gate electrode connected to the Q'-node Q'N, a first electrode connected to the first clock signal line ECLK1, and a first electrode connected to the ninth transistor T9. 2 electrodes are connected. The eighth transistor T8 is turned on or turned off depending on the potential of the Q'-node (Q'N).

The ninth transistor T9 has a gate electrode connected to the first clock signal line ECLK1, a first electrode connected to the second electrode of the eighth transistor T8, and a second electrode connected to the QB-node (QBN). Electrodes are connected. The ninth transistor T9 is turned on or off depending on the potential of the eighth transistor T8.

The tenth transistor T10 has a gate electrode connected to the Q-node (QN), a first electrode connected to the second clock signal line (ECLK2), and a second electrode connected to the first electrode of the node compensation transistor (Tbk). This is connected. The tenth transistor T10 is turned on or turned off depending on the potential of the Q-node (QN).

The node compensation transistor (Tbk) has a gate electrode connected to the start signal line (EVST) or the output terminal (EMO(k-1)) of the previous stage, and has a first electrode connected to the second electrode of the tenth transistor (T10). is connected, and a second electrode is connected to the Q'-node (Q'N). The node compensation transistor (Tbk) is turned on or turned off according to the potential of the start signal supplied to the start signal line (EVST) or the emission control signal (EMO (k-1)) output from this previous stage. .

The node compensation transistor (Tbk) generates voltage coupling to the first capacitor (CQ) by the first clock signal (ECLK1) applied to the first clock signal line (ECLK1), thereby generating the Q-node (QN). ) ensures that the high voltage of the light emission control signal can be output stably even if it changes to the turn-on voltage.

The first capacitor CQ has one end connected to the Q-node (QN) and the other end connected to the first clock signal line (ECLK1). The second capacitor (CQB) is connected between the QB-node (QBN) and the first voltage line (EVGH). The third capacitor CQ' is connected between the Q'-node Q'N and the second electrode of the eighth transistor T8 and the gate electrode of the ninth transistor T9.

The reset transistor (TR) has a gate electrode connected to the reset signal line (ERST) and a first electrode connected to the output terminal (EMO[k]) of the light emission control signal generator (EM[1]) of the first stage. The second electrode is connected to the first voltage line EVGH. The reset transistor TR is turned on or turned off according to a reset signal applied through the reset signal line ERST. When the reset transistor (TR) is turned on, the output terminal (EMO[1]) of the light emission control signal generator (EM[1]) of the first stage is connected to the first voltage line (EVGH). Outputs a high-voltage light emitting signal based on the voltage.

Figure 8 is a waveform diagram for explaining the operation of the light emission control signal generator according to the present invention, and is an example waveform of the light emission control signal generator of the first stage.

As shown in FIG. 8, the start signal EVST applied through the start signal line EVST may generate a high voltage for 3 horizontal times (3H). The second clock signal (ECLK2) applied through the second clock signal line (ECLK2) generates low voltage and high voltage alternately in a period of 1 horizontal time (1H) in synchronization with the high voltage point (rising edge) of the start signal. It can have the form: The first clock signal (ECLK1) applied through the first clock signal line (ECLK1) generates high and low voltages alternately in a period of 1 horizontal time (1H) in synchronization with the high voltage point (rising edge) of the start signal. It can have the form: That is, the second clock signal ECLK2 and the first clock signal ECLK1 may generate high and low voltages in opposite phases.

The elements included in the light emission control signal generator (EM[1]) of the first stage include a start signal (EVST), a first clock signal (ECLK1), a second clock signal (ECLK2), a first voltage (VGH), and a first clock signal (ECLK1). 2 Operates according to voltage (VGL).

By the operation of the elements included in the light emission control signal generator (EM[1]) of the first stage, the Q-node (QN) has a period of charging to a high voltage, and the Q'-node (Q'N) and the QB-node (QBN) has a period of discharging to low voltage. At this time, the QB-node (QBN) can maintain a low voltage in the form of an anti-phase delayed by 1 horizontal time (1H) compared to the start signal (EVST) for 3 horizontal hours (3H).

That is, the first transistor T1 and the fourth transistor T4 are turned on in the low voltage section of the second clock signal ECLK2, and the start signal EVST generates a high voltage for the three horizontal times (3H). ) is applied to the Q-node (QN), and the second voltage (EVGL) is applied to the gate electrode of the third transistor (T3) and the Q'-node (Q'N). At this time, the tenth transistor T10 and the fifth transistor T5 are turned off, and the eighth transistor T8 is turned on.

And, when the second clock signal (ECLK2) transitions to the high voltage section and the first clock signal (ECLK1) transitions to the low voltage section, the first transistor (T1) and the fourth transistor (T4) turn- is turned off, and the second transistor T2 and the ninth transistor T9 are turned on, and the low voltage of the first clock signal ECLK1 is supplied to the QB-node QBN. Accordingly, the seventh transistor T7 is turned on and the first voltage EVGH is output to the output terminal EMO of the emission control signal generator EM[1] of the first stage.

After the start signal (EVST) transitions to a low voltage, the second clock signal (ECLK2) transitions to a low voltage again, and the first clock signal (ECLK1) transitions to a high voltage section again, the The Q-node (QN) is discharged to a low voltage and the QB-node (QBN) is charged to a first voltage, and the output terminal (EMO) of the light emission control signal generator (EM[1]) of the first stage is also discharged to a low voltage. It is output as a second voltage.

The sixth transistor (T6) constituting the emission control signal output unit of the emission control signal generator (EM[1]) of the first stage is turned on or off depending on the potential of the Q-node (QN), The seventh transistor T7 is turned on or turned off depending on the potential of the QB-node (QBN). When the potential of the Q-node (QN) maintains a high voltage, the potential of the QB-node (QBN) may maintain a low voltage.

Since the seventh transistor T7 is turned on according to the low voltage of the QB-node (QBN), the first voltage (VGH) applied through the first voltage line (EVGH) is the light emission control signal of the first stage. It is output through the output terminal (EMO[1]) of the generator (EM[1]). As a result, the output terminal (EMO[1]) of the light emission control signal generator (EM[1]) operates for at least 3 horizontal hours (3H) based on the first voltage (VGH) applied through the first voltage line (EVGH). ), the high voltage light emission control signal (Em[1]) is output and then converted to the low voltage light emission control signal (Em[1]).

As the elements included in the light emission control signal generator (EM[1]) of the first stage operate as above, they may experience bias stress. Bias stress is related to the lifespan as well as the threshold voltage of the devices.

The elements included in the light emission control signal generator (EM[1]) of the first stage are elements that receive HJTS (High Junction Temperature Stress) due to the transfer operation of high voltage through the source-drain electrode, and elements that receive high junction temperature stress through the gate electrode. It can be divided into devices that receive PBTS (Positive Bias Temperature Stress) due to the application of voltage, and devices that receive NBTS (Negative Bias Temperature Stress) due to the application of low voltage through the gate electrode.

However, the elements included in the light emission control signal generator (EM[1]) of the first stage except the third transistor (T3) during the duty variable operation to lower the duty of the light emission control signal (Em[1]). The pattern of stress experienced by other transistors changes as follows.

Figure 9 is a stress summary table of elements of the light emission control signal generator according to the present invention.

As shown in FIG. 9, the first transistor T1 corresponds to a transistor that receives PBTS (PB) at high duty but NBTS (NB) at low duty. The second transistor (T2) corresponds to a transistor that receives HJTS (HJ) at high duty but receives NBTS (NB) at low duty. The fourth transistor (T4) corresponds to a transistor that receives HJTS (HJ) at high duty but receives PBTS (PB) at low duty. The fifth transistor (T5) corresponds to a transistor that receives NBTS (NB) at high duty but receives HJTS (HJ) at low duty. The sixth transistor (T6) corresponds to a transistor that receives NBTS (NB) at high duty but receives HJTS (HJ) at low duty. The seventh transistor (T7) corresponds to a transistor that receives HJTS (HJ) at high duty but NBTS (NB) at low duty. The eighth transistor (T8) corresponds to a transistor that receives HJTS (HJ) at high duty but NBTS (NB) at low duty. The ninth transistor (T9) corresponds to a transistor that receives NBTS (NB) at high duty but receives HJTS (HJ) at low duty. The tenth transistor (T10) corresponds to a transistor that receives NBTS (NB) at high duty, but receives PBTS (PB) or HJTS (HJ) at low duty.

In the table of Figure 9, HNV (High Negative Voltage), HPV (High Positive Voltage), HJV (High Junction Voltage), and LV (Low Voltage) are indicated.

It is very important to maintain a high voltage of the light emission control signal for dual driving of the light emission control signal generator.

However, in the light emission control signal generator of FIG. 7, if the node compensation transistor (Tbk) is not present, the following phenomenon may occur.

Figure 10 is a waveform diagram when there is no node compensation transistor in the light emission control signal generator according to the present invention, and is an example waveform of the light emission control signal generator of the first stage.

As explained in FIG. 9, when the duty drive is varied (100% → 1%), the tenth transistor T10 receives NBTS at a high duty, but receives PBTS or HJTS at a low duty.

As shown in FIG. 10, while the Q-node (QN) maintains the high voltage, the second clock signal (ECLK2) transitions to the high voltage section, and the first clock signal (ECLK1) At the time of transition to the low voltage section, voltage coupling may be generated in the first capacitor CQ by the first clock signal ECLK1. Because of this, the Q-node (QN) may be dropped to the turn-on voltage due to voltage coupling of the first capacitor (CQ). Accordingly, the tenth transistor T10 is turned on, the Q'-node (Q'N) rises to the turn-off voltage, and the eighth transistor T8 is turned off.

In this way, since the eighth transistor T8 is turned off, even if the ninth transistor T9 is turned on by the first clock signal ECLK1, a low voltage is not applied to the QB-node (QBN). Since the high voltage is maintained without turning off the seventh transistor T7, the first voltage EVGH cannot be supplied to the output terminal EMO of the light emission control signal generator.

However, the presence of the node compensation transistor Tbk can prevent the above defect.

Figure 11 is a waveform diagram of the node compensation transistor in the light emission control signal generator according to the present invention, and is an example waveform of the light emission control signal generator of the first stage.

At a time when the second clock signal (ECLK2) transitions to a high voltage section and the first clock signal (ECLK1) transitions to a low voltage section while the Q-node (QN) maintains a high voltage, the Voltage coupling may occur in the first capacitor CQ due to the first clock signal ECLK1. As a result, the Q-node (QN) is dropped to the turn-on voltage due to voltage coupling of the first capacitor (CQ), so that the tenth transistor (T10) can be turned on.

However, while the Q-node (QN) maintains the high voltage, at the time when the second clock signal (ECLK2) transitions to the high voltage section and the first clock signal (ECLK1) transitions to the low voltage section, , Since the start signal (EVST) or the light emission control signal (EMO(k-1)) of the previous stage maintains a high voltage state, the node compensation transistor (Tbk) is turned off. Accordingly, the node compensation transistor Tbk blocks the turn-off voltage (high voltage) applied to the Q'-node (Q'N) through the tenth transistor (T10).

Therefore, since the eighth transistor T8 is turned on and the ninth transistor T9 is turned on by the first clock signal ECLK1, the first clock signal (T9) is transmitted to the QB-node (QBN). The low voltage of ECLK1) is applied to the gate electrode of the seventh transistor (T7), and the seventh transistor (T7) is turned on to transmit the first voltage (EVGH) to the output terminal (EMO) of the light emission control signal generator. will be supplied.

As described above, since the node compensation transistor Tbk exists, when the duty driving of the emission control signal EM is performed, the output of the emission control signal EM can stably maintain a high voltage state.

In addition, since the node compensation transistor Tbk as described above exists, the output margin of the light emission control signal is improved, thereby improving the reliability of the light emission control signal generator.

That is, when the node compensation unit as described above does not exist, the threshold voltage margin (Vth) of the transistors of the light emission control signal generator is about 3V, but due to the presence of the node compensation unit, the threshold voltage margin of the transistors of the light emission control signal generator is reduced. (Vth) increased to about 7V.

The above description is merely an illustrative description of the present invention, and various modifications may be made by those skilled in the art without departing from the technical spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be interpreted in accordance with the scope of the patent claims below, and all technologies within the equivalent scope thereof should be interpreted as being included in the scope of the present invention.

AA: Display area NA: Non-display area
AR: Area of application

Claims (7)

Equipped with a plurality of stages that are dependently connected to sequentially output light emission control signals,
Each stage,
An output unit that outputs a first voltage as a light emission control signal according to the potential of the QB-node and outputs a second voltage as a light emission control signal according to the potential of the Q-node;
A gate electrode is connected to a second clock signal supply line that supplies a second clock signal, a first electrode is connected to the output terminal of a start signal line or a previous stage thereof that supplies a start signal, and a second electrode is connected to the Q-node. A first transistor, a second transistor whose gate electrode is connected to the first clock signal line that supplies the first clock signal and whose first electrode is connected to the Q-node, and a first electrode connected to the second electrode of the second transistor a third transistor having a second electrode connected to a first voltage supply line that is connected and supplies a first voltage; and a second voltage supply line that has a gate electrode connected to the second clock signal supply line and supplies a second voltage. a fourth transistor having a first electrode connected to the first electrode and a second electrode connected to the gate electrode of the third transistor, a gate electrode connected to the Q-node and a first electrode connected to the QB-node, and a fourth transistor having a gate electrode connected to the Q-node and a first electrode connected to the QB-node a fifth transistor having a second electrode connected to a voltage supply line; an eighth transistor having a gate electrode connected to the second electrode of the fourth transistor and a first electrode connected to the first clock signal supply line; 1 A ninth transistor whose gate electrode is connected to the clock signal supply line, whose first electrode is connected to the second electrode of the eighth transistor and whose second electrode is connected to the QB-node, and whose gate electrode is connected to the Q-node Including a tenth transistor connected and having a first electrode connected to the second clock signal supply line, and a first capacitor connected between the Q-node and the first clock signal supply line, the start signal or the front end a node control unit that operates based on a light emission control signal output from a stage, the first clock signal, and the second clock signal to control potentials of the QB-node and the Q-node;
Node compensation that compensates so that the high voltage of the light emission control signal can be stably output even when voltage coupling is generated in the first capacitor of the node control unit by the first clock signal and the Q-node changes to the turn-on voltage. transistor; and
A light emission control signal generator including a reset transistor that is controlled according to a reset signal to reset the output terminal of the output unit to the first voltage. delete According to claim 1,
The node compensation transistor is,
A light emission control signal generator having a gate electrode connected to the start signal line or an output terminal of the preceding stage, a first electrode connected to the second electrode of the tenth transistor, and a second electrode connected to the gate electrode of the eighth transistor. . According to claim 1,
The node control unit,
a second capacitor connected between the QB-node and the first voltage supply line;
A light emission control signal generator further comprising a third capacitor connected between the gate electrode of the eighth transistor and the second electrode of the eighth transistor. According to claim 1,
The output unit,
a sixth transistor having a gate electrode connected to the Q-node, a first electrode connected to a second voltage supply line that supplies the second voltage, and a second electrode connected to an output terminal;
A light emission control signal generator including a seventh transistor having a gate electrode connected to the QB-node, a first electrode connected to the output terminal, and a second electrode connected to a first voltage supply line that supplies the first voltage. . delete A display panel that displays images;
a scan signal generator supplying a scan signal to the display panel; and
It includes a light emission control signal generator that supplies a light emission control signal to the display panel,
The emission control signal generator includes a plurality of stages that are dependently connected to sequentially output emission control signals,
Each stage,
An output unit that outputs a first voltage as a light emission control signal according to the potential of the QB-node and outputs a second voltage as a light emission control signal according to the potential of the Q-node;
A gate electrode is connected to a second clock signal supply line that supplies a second clock signal, a first electrode is connected to the output terminal of a start signal line or a previous stage thereof that supplies a start signal, and a second electrode is connected to the Q-node. A first transistor, a second transistor whose gate electrode is connected to the first clock signal line that supplies the first clock signal and whose first electrode is connected to the Q-node, and a first electrode connected to the second electrode of the second transistor a third transistor having a second electrode connected to a first voltage supply line that is connected and supplies a first voltage; and a second voltage supply line that has a gate electrode connected to the second clock signal supply line and supplies a second voltage. a fourth transistor having a first electrode connected to the first electrode and a second electrode connected to the gate electrode of the third transistor, a gate electrode connected to the Q-node and a first electrode connected to the QB-node, and a fourth transistor having a gate electrode connected to the Q-node and a first electrode connected to the QB-node a fifth transistor having a second electrode connected to a voltage supply line; an eighth transistor having a gate electrode connected to the second electrode of the fourth transistor and a first electrode connected to the first clock signal supply line; 1 A ninth transistor whose gate electrode is connected to the clock signal supply line, whose first electrode is connected to the second electrode of the eighth transistor and whose second electrode is connected to the QB-node, and whose gate electrode is connected to the Q-node Including a tenth transistor connected and having a first electrode connected to the second clock signal supply line, and a first capacitor connected between the Q-node and the first clock signal supply line, the start signal or the front end a node control unit that operates based on a light emission control signal output from a stage, the first clock signal, and the second clock signal to control potentials of the QB-node and the Q-node;
Voltage coupling is generated in the first capacitor of the node control unit by the first clock signal, preventing node compensation so that the high voltage of the light emission control signal can be stably output even if the Q-node changes to the turn-on voltage. transistor; and
A light emitting display device comprising a reset transistor controlled according to a reset signal to reset the output terminal of the output unit to the first voltage.