KR20210061086A - Emitting control Signal Generator and Light Emitting Display Device including the same - Google Patents

Abstract

The present invention relates to a light emission control signal generation part capable of reliably maintaining a high voltage of a light emission control signal, and a light emitting display device including the same. The light emission control signal generation part includes a plurality of stages subordinately connected to sequentially output a light emission control signal. Each of the stages includes: an output part outputting a first voltage as a light emission control signal in accordance with a potential of a QB-node, and outputting a second voltage as a light emission control signal in accordance with a potential of a Q-node; a node control part operated based on a start signal or a light emission control signal outputted from a stage at a front end, a first clock signal and a second clock signal to control the potentials of the QB-node and the Q-node; and a node prevention part preventing the first voltage from being disabled to be outputted to the output part due to a voltage coupling of the first clock signal.

Description

Light emission control signal generator and light emitting display device including the same {Emitting control Signal Generator and Light Emitting Display Device including the same}

The present invention relates to a light-emitting display device, and more particularly, to a light emission control signal generator and a light-emitting display device including the same.

As the information society develops and various portable electronic devices such as mobile communication terminals and notebook computers are developed, demand for a flat panel display device that can be applied thereto is gradually increasing.

As such a flat panel display, an OLED display using a liquid crystal display (LCD) and an organic light emitting diode (OLED) using a liquid crystal is used.

These flat panel displays include a display panel including a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

Among the above display devices, a display panel of a liquid crystal display includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed on a glass substrate, and the thin film transistor And a liquid crystal layer filled between the array substrate and the color filter array substrate.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, and each gate line And each data line defines one sub-pixel area (Pixel) P. One thin film transistor and a pixel electrode are formed in one sub-pixel region P.

The display panel of such a liquid crystal display device generates an electric field in the liquid crystal layer by applying a voltage to an electric field generating electrode (pixel electrode and a common electrode), and adjusts the arrangement of liquid crystal molecules in the liquid crystal layer by the electric field. The image is displayed by controlling the polarization.

In addition, among the above display devices, in the display panel of the OLED display device, a sub-pixel is defined by crossing the plurality of gate lines and a plurality of data lines, and each of the sub-pixels includes an anode and a cathode, and the anode and cathode. An OLED composed of an organic light emitting layer therebetween, and a pixel circuit for independently driving the OLED.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges a data voltage into the capacitor in response to a scan pulse. The driving TFT controls the amount of current supplied to the OLED according to the data voltage charged in the capacitor to control the amount of light emitted by the OLED.

Recently, it is configured to further include a light emission control transistor for determining the light emission time of the pixels.

The display panel for a display device is defined as an active area (AA) that provides an image to a user and a non-active area (NA) that is a peripheral area of the display area (AA).

In addition, the driving circuit for driving the display panel includes a gate driving circuit for sequentially supplying a gate pulse (or scan pulse) to the plurality of gate lines of the display panel, and the plurality of data lines of the display panel. A data driving circuit for supplying a data voltage to each field, and a timing controller for supplying image data and various control signals to the gate driving circuit and the data driving circuit.

The gate driving circuit may be configured with at least one gate drive IC, but in the process of forming the plurality of signal lines (gate lines and data lines) and sub-pixels of the display panel, the display panel is not displayed. It can be formed simultaneously on the area.

That is, a gate-in-panel (hereinafter referred to as “GIP”) method in which the gate driving circuit is directly applied to the display panel is applied.

The gate driving circuit as described above outputs scan signals and emission control signals for turning on or off the switching transistor and the emission control transistor formed on the display panel.

In order to sequentially supply scan signals and emission control signals, the gate driving circuit includes a scan signal generation unit and a light emission control signal generation unit including a plurality of stages equal to or greater than the number of gate lines.

However, there is a problem in that a node voltage drop phenomenon of the emission control signal generator for sequentially supplying the emission control signals occurs and the emission control signal is abnormally generated.

An object of the present invention is to solve the above problem, and an object of the present invention is to provide a light emission control signal generator and a light emitting display device including the same so that a high voltage of the light emission control signal can be reliably maintained.

The light emission control signal generator according to the present invention for achieving the above object includes a plurality of stages that are dependently connected to sequentially output the light emission control signal, and each stage includes a first stage according to the potential of the QB-node. An output unit that outputs a voltage as a light emission control signal and outputs a second voltage as a light emission control signal according to the potential of the Q-node, a start signal or a light emission control signal output from a stage in the previous stage, a first clock signal, and a second A node control unit that operates based on a clock signal to control the potentials of the QB-node and the Q-node, and prevents the first voltage from being output to the output unit by voltage coupling of the first clock signal. It is characterized by having a node prevention unit.

Here, it characterized in that it comprises a capacitor for canceling the coupling voltage.

The node control unit includes a gate electrode connected to a second clock signal supply line supplying the second clock signal, a first electrode connected to a start signal line supplying the start signal or an output terminal of a previous stage thereof, and the Q- A first transistor having a second electrode connected to a node, a second transistor having a gate electrode connected to a first clock signal line supplying the first clock signal and a first electrode connected to the Q-node, A third transistor having a first electrode connected to a second electrode of the second transistor, a second electrode connected to a first voltage supply line supplying a first voltage, and a gate electrode connected to the second clock signal supply line A fourth transistor having a first electrode connected to a second voltage supply line supplying the second voltage and a second electrode connected to the gate electrode of the third transistor, and a gate electrode connected to the Q-node, and the A fifth transistor having a first electrode connected to the QB-node and a second electrode connected to the first voltage supply line, and a gate electrode connected to the second electrode of the fourth transistor and connected to the first clock signal supply line. An eighth transistor to which a first electrode is connected, a gate electrode to the first clock signal supply line, a first electrode to a second electrode of the eighth transistor T8, and a second electrode to the QB-node And a tenth A transistor having a gate electrode connected to the Q-node and a first electrode connected to the second clock signal supply line.

The node compensation unit includes a tenth B transistor having a gate electrode connected to the Q-node, a first electrode connected to a second electrode of the tenth A transistor, and a second electrode connected to the gate electrode of the eighth transistor. And a first capacitor connected between the second electrode of the tenth A transistor and the first clock signal supply line.

The node controller includes a second capacitor connected between the Q-node and the first clock signal supply line, A third capacitor connected between the QB-node and the first voltage supply line, and a fourth capacitor connected between the gate electrode of the eighth transistor and the second electrode of the eighth transistor. do.

The output unit includes a sixth transistor having a gate electrode connected to the Q-node, a first electrode connected to a second voltage supply line supplying the second voltage, and a second electrode connected to an output terminal, and the QB- And a seventh transistor having a gate electrode connected to a node, a first electrode connected to the output terminal, and a second electrode connected to a first voltage supply line supplying the first voltage.

The emission control signal generator may further include a reset transistor controlled according to a reset signal to reset an output terminal of the output unit to the first voltage.

In addition, a light emitting display device according to the present invention for achieving the above object includes a display panel displaying an image, a scan signal generator supplying a scan signal to the display panel, and a light emission control signal to the display panel. And a light emission control signal generator to supply, and the light emission control signal generator includes a plurality of stages that are dependently connected to sequentially output light emission control signals, each stage having a first voltage according to a potential of the QB-node Output as a light emission control signal and outputs a second voltage as a light emission control signal according to the potential of the Q-node, a start signal or a light emission control signal output from a stage in the previous stage, a first clock signal, and a second clock A node control unit that operates based on a signal to control the potentials of the QB-node and the Q-node, and a node that prevents the first voltage from being output to the output unit by voltage coupling of the first clock signal It is characterized by having a prevention part.

In the light emission control signal generator and the light emitting display device including the same according to the present invention having the above characteristics, there are the following effects.

Since the node compensation unit including the tenth B transistor and the fourth capacitor is present, the output of the light emission control signal EM can stably maintain a high voltage state when the duty of the light emission control signal EM is driven.

In addition, since the node compensation unit as described above is present, the output margin of the emission control signal is improved, and the reliability of the emission control signal generator is improved.

1 is a block diagram schematically showing an OLED display device according to an embodiment of the present invention
2 is an equivalent circuit diagram schematically showing the sub-pixel shown in FIG. 1
3 is a diagram illustrating a first configuration of a device related to a scan driver illustrated in FIG. 1,
4 is a diagram illustrating a second configuration of a device related to the scan driver illustrated in FIG. 1;
5 is a diagram illustrating a first configuration of the shift register shown in FIG. 3
6 is a block diagram showing emission control signal generators according to a first embodiment of the present invention;
7 is a circuit diagram showing in detail a light emission control signal generator of a first stage according to a first embodiment of the present invention
8 is an exemplary waveform diagram for explaining the operation of the emission control signal generator of the first stage according to the present invention
9 is a table of stresses of elements of a light emission control signal generator according to the present invention
10 is an exemplary view of waveforms when there is no node compensation unit in the emission control signal generation unit of the first stage according to the present invention
11 is an exemplary view of waveforms by a node compensating unit in the emission control signal generation unit of the first stage according to the present invention.

Hereinafter, a light emission control signal generator and a light emitting display device including the same according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

The device described below will be described as an example of including a p-type thin film transistor, but this may be implemented in a form in which an n-type thin film transistor or an n-type and p-type exist together. The thin film transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the thin film transistor, carriers start flowing from the source. The drain is an electrode through which carriers exit from the thin film transistor. That is, in the thin film transistor, the carrier flows from the source to the drain.

In the case of an n-type thin film transistor, since carriers are electrons, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In the n-type thin film transistor, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. In contrast, in the case of a p-type thin film transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-type thin film transistor, since holes flow from the source to the drain, current flows from the source to the drain. However, the source and drain of the thin film transistor can be changed according to the applied voltage. Reflecting this, in the following description, one of the source and the drain will be described as a first electrode, and the other of the source and the drain will be described as a second electrode.

1 is a block diagram schematically illustrating an OLED display device according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram schematically illustrating a sub-pixel illustrated in FIG. 1.

1 and 2, the organic electroluminescent display device according to an embodiment of the present invention includes an image supply unit 110, a timing control unit 120, a scan driving unit 130, a data driving unit 140, and a display panel. 150 and a power supply unit 180 are included.

The image supply unit 110 (or host system) outputs various driving signals in addition to an image data signal supplied from the outside or an image data signal stored in an internal memory. The image supply unit 110 may supply data signals and various driving signals to the timing controller 120.

The timing control unit 120 includes a gate timing control signal (GDC) for controlling the operation timing of the scan driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals. (Vsync, which is a vertical synchronization signal, and Hsync, which is a horizontal synchronization signal), etc. are output.

The timing control unit 120 supplies the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140. The timing control unit 120 may be formed in an integrated circuit (IC) shape and mounted on a printed circuit board, but is not limited thereto.

The scan driver 130 includes a scan signal generator and a light emission control signal generator for outputting a scan signal (or a scan voltage) and a light emission control signal in response to a gate timing control signal GDC supplied from the timing controller 120. do. The scan driver 130 supplies scan signals to subpixels included in the display panel 150 through gate lines GL1 to GLm. In addition, the scan driver 130 outputs emission control signals to emission control lines to control emission control transistors included in each sub-pixel. During the period in which the data voltage Vdata is addressed, the scan signal is generated at a turn-on level, and the emission control signal is generated at a turn-off level. Thereafter, during the period when the pixels emit light, the scan signal is generated at a turn-off level, and The control signal is generated at the turn-on level.

The scan driver 130 may be formed in an IC form or directly on the display panel 150 in a gate in panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, and converts the digital data signal into an analog form based on a gamma reference voltage. Converts to data voltage and outputs it.

The data driver 140 supplies a data voltage to subpixels included in the display panel 150 through data lines DL1 to DLn. The data driver 140 may be formed in an IC shape and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates and outputs a high-potential first panel power EVDD and a low-potential second panel power EVSS based on an external input voltage supplied from the outside. The power supply unit 180 includes not only a first panel power supply and a second panel power supply (EVDD, EVSS), but also a voltage (for example, a scan high voltage, a scan low voltage) or a data driver 140 required to drive the scan driver 130. It is possible to generate and output voltages (drain voltage, half-drain voltage), etc. required for driving of.

The display panel 150 includes a scan signal output from a driver including a scan driver 130 and a data driver 140 and a driving signal including a data voltage, and a first panel power and a first panel power output from the power supply unit 180. 2 Displays images according to the panel power (EVDD, EVSS). Sub-pixels of the display panel 150 directly emit light.

The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. In addition, the subpixels emitting light may include pixels including red, green, and blue, or pixels including red, green, blue, and white.

For example, in one sub-pixel SP, as shown in FIG. 2, an OLED element (OLED) that emits light by a driving current flowing between a high potential voltage (VDD) and a low potential voltage (VSS), and the OLED Using the driving TFT (DT) that controls the amount of driving current applied to the device (OLED), the data voltage (Vdata) applied from the data line (DL) and the scan signal (SCAN) applied from the gate line (GL), etc. A switch circuit (SWC) that adjusts the gate voltage of the driving TFT (DT) and a light emission control TFT (ET) that turns on/off the current flow between the driving TFT (DT) and the OLED in response to the emission control signal (EM). It consists of including. Here, the TFTs formed in the pixel may be selected as P-type, but are not limited thereto and may be selected as N-type.

Although not shown in FIG. 2, a sensing transistor for sensing a threshold voltage or mobility of the driving TFT DT to compensate for deterioration (threshold voltage or mobility) of the driving TFT DT, and the driving transistor ( DT) may further include an internal compensation circuit for compensating for the threshold voltage or mobility.

Meanwhile, in the above description, the timing control unit 120, the scan driving unit 130, the data driving unit 140, and the like have been described as having individual configurations. However, one or more of the timing controller 120, the scan driver 130, and the data driver 140 may be integrated into one IC according to an implementation method of the light emitting display device.

3 is a first configuration example of the device related to the scan driver illustrated in FIG. 1, FIG. 4 is a second configuration example of the device related to the scan driver illustrated in FIG. 1, and FIG. 5 is It is an exemplary configuration diagram of a shift register.

3, the gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 generates and outputs a plurality of clock signals GCLK and ECLK and start signals GVST and EVST based on signals output from the timing control unit 120. A plurality of clock signals GCLK and ECLK may be generated and output in the form of a phase of K (K is an integer greater than or equal to 2) having different phases such as 2-phase, 4-phase, and 8-phase.

The shift register 131 operates based on signals (GCLK, ECLK, GVST, EVST) output from the level shifter 135, and scan signals capable of turning on or off a transistor formed on a display panel. (Scan[1] ~ Scan[m]) and emission control signals (EM[1] ~ EM[m]) are output. The shift register 131 is formed in the form of a thin film on the display panel by a gate-in-panel method. Accordingly, a portion of the scan driver 130 formed on the display panel may be the shift register 131.

Unlike the shift register 131, the level shifter 135 is formed in an IC shape. The level shifter 135 may be configured in a separate IC type as shown in FIG. 3, and may be included inside the power supply unit 180 or inside other devices as shown in FIG. 4.

As shown in FIG. 5, the shift register 131 includes a plurality of stages STG1 to STGm. The plurality of stages STG1 to STGm have a structure connected in a dependent manner, and receive at least one output signal of a front end or a rear end as an input signal.

The stages STG1 to STGm of the shift register 131 include scan signal generators SCAN[1] to SCAN[m] and emission control signal generators EM[1] to EM[m], respectively. can do.

For example, the first stage STG1 includes a first scan signal generator SCAN[1] that outputs a first scan signal Scan[1] and a light emission control that outputs a light emission control signal Em[1]. It has a signal generator (EM[1]).

The scan signal generators SCAN[1] to SCAN[m] output scan signals Scan[1] to Scan[m] through scan lines of the display panel. The emission control signal generators EM[1] to EM[m] output emission control signals Em[1] to Em[m] through emission control signal lines of the display panel.

The emission control signals Em[1] to Em[m] may be used as signals for driving emission control transistors included in sub-pixels. For example, when the emission control transistor of the sub-pixels is controlled using the emission control signals Em[1] to Em[m], the emission time of the organic light emitting diode is varied.

However, the example of FIG. 5 is an example to aid understanding of the shift register 131, and the present invention is not limited thereto, and may be implemented in a form in which more various and more signals are output.

Although not shown in the drawing, the scan signal generators (SCAN[1] to SCAN[m]) that output the scan signals (Scan[1] to Scan[m]) are They may be driven by the high voltage GVGH, the scan reset signal GRST, the scan low voltage GVGL, and the scan clock signals GCLKs, respectively.

The emission control signal generators EM[1] to EM[m] that output the emission control signals Em[1] to Em[m] are a start signal EVST, a reset signal EST, and a high voltage. It may be driven by (EVGH), the low voltage (EVGL), and the clock signals ECLKs.

6 is a block diagram showing emission control signal generation units according to the first embodiment of the present invention, and FIG. 7 is a circuit configuration diagram showing in detail the emission control signal generation unit of the first stage according to the first embodiment of the present invention. .

As shown in FIG. 6, the emission control signal generation units EM[1] to EM[m] according to the first embodiment of the present invention have stages STG1 to STGm-1 that are connected in a dependent manner. In addition, the emission control signal generators EM[1] to EM[m-1] receive a signal output through an output terminal at the front end as a start signal at the rear end.

The emission control signal output from the output terminal EMO[1] of the emission control signal generator EM[1] of the first stage STG1 is applied to the first pixel group Pixel[1], and It is also applied to the input terminal of the start signal of the emission control signal generator EM[1] of the second stage STG2. Therefore, the emission control signal generation unit EM[1] of the first stage STG1 is connected to the emission start signal line EVST, but from the emission control signal generation unit EM[2] of the second stage STG2 The light emission control signal output from the light emission control signal generator of the previous stage is used as a start signal.

In FIG. 6, the emission signal output from the output terminal EMO[1] of the emission control signal generator EM[1] of the first stage STG1 is expressed as “Start[1]”. It is to show that the output signal of) is used as the start signal of the next stage. In addition, such a connection relationship and a signal transmission system are equally applied to all stages STG1 to STGm-1.

As shown in FIG. 7, the emission control signal generator EM[1] of the first stage according to the first embodiment of the present invention includes a first transistor T1 to a tenth A transistor T10a and a tenth transistor T10a. B transistors T10a and T10b, first to fourth capacitors CQ, CQB, CQ', Cclk, and reset transistor TR.

Sixth and seventh transistors T6 and T7 among the first to tenth A transistors T10a and 10th B transistors T10b may be included in an output unit that outputs a light emission control signal.

The first to fifth transistors T1 to T5 and the eighth transistors T8 to 10 A transistors T10a may be included in the node controller. In addition, the tenth B transistor T10b and the fourth capacitor Cclk may be included in the node compensation unit.

The first to tenth A transistor T10a, the tenth B transistor T10b, and the reset transistor TR are implemented as p-type thin film transistors as an example. The first to tenth A and B transistors T10a and T10b implemented as p-type thin film transistors, and the reset transistor TR are turned on under the condition that the low voltage EVGL is applied, and the high voltage EVGH ) Is turned off when applied.

The first transistor T1 has a gate electrode connected to the second clock signal line ECLK2, a first electrode connected to the start signal line EVST, and a second electrode connected to the Q-node QN. The first transistor T1 is turned on or off according to a second clock signal applied through the second clock signal line ECLK2.

The second transistor T2 has a gate electrode connected to the first clock signal line ECLK1, a first electrode connected to the Q-node QN, and a second electrode connected to the first electrode of the third transistor T3. Connected. The second transistor T2 is turned on or off according to the first clock signal applied through the first clock signal line ECLK1.

The third transistor T3 has a gate electrode connected to a second electrode of the fourth transistor T4, a first electrode connected to the second electrode of the second transistor T2, and a first voltage line EVGH. 2 electrodes are connected. When the fourth transistor T4 is turned on, the third transistor T3 is turned on according to the second voltage applied through the second voltage line EVGL.

The fourth transistor T4 has a gate electrode connected to the second clock signal line ECLK2, a first electrode connected to the second voltage line EVGL, and a second electrode connected to the gate electrode of the third transistor T3. The electrodes are connected. The fourth transistor T4 is turned on or off according to a second clock signal applied through the second clock signal line ECLK2. Accordingly, the fourth transistor T4 is turned on or off simultaneously with the first transistor T1.

The fifth transistor T5 has a gate electrode connected to the Q-node QN, a first electrode connected to the QB-node QBN, and a second electrode connected to the first voltage line EVGH. The fifth transistor T5 is turned on or off according to the potential of the Q-node QN.

The sixth transistor T6 has a gate electrode connected to one end of the Q-node QN and the first capacitor CQ, the first electrode connected to the second voltage line EVGL, and the emission control signal of the first stage. The second electrode is connected to the output terminal EMO[1] of the generator EM[1]. The sixth transistor T6 is turned on or off according to the potential of the Q-node QN.

The seventh transistor T7 has a gate electrode connected to the QB-node QBN, and a first electrode connected to the output terminal EMO[1] of the emission control signal generator EM[1] of the first stage. And a second electrode is connected to the first voltage line EVGH. The seventh transistor T7 is turned on or off according to the potential of the QB-node QBN.

The eighth transistor T8 has a gate electrode connected to the Q'-node Q'N, a first electrode connected to the first clock signal line ECLK1, and a first electrode of the ninth transistor T9. 2 electrodes are connected. The eighth transistor T8 is turned on or off according to the potential of the Q'-node Q'N.

In the ninth transistor T9, a gate electrode is connected to the first clock signal line ECLK1, a first electrode is connected to a second electrode of the eighth transistor T8, and a second electrode is connected to the QB-node QBN. The electrodes are connected. The ninth transistor T9 is turned on or off according to the potential of the eighth transistor T8.

The tenth A transistor T10a has a gate electrode connected to the Q-node QN, a first electrode connected to the second clock signal line ECLK2, and a first electrode of the tenth B transistor T10b. 2 electrodes are connected. The tenth B transistor T10b has a gate electrode connected to the Q-node QN, a first electrode connected to the second electrode of the tenth A transistor T10a, and the Q'-node Q'N. The second electrode is connected to. The tenth A transistor T10a and the tenth B transistor T10b are turned on or off at the same time according to the potential of the Q-node QN.

One end of the first capacitor CQ is connected to the Q-node QN and the other end is connected to the first clock signal line ECLK1. The second capacitor CQB is connected between the QB-node QBN and the first voltage line EVGH. The third capacitor CQ' is connected between the Q'-node Q'N and the second electrode of the eighth transistor T8 and the gate electrode of the ninth transistor T9. The fourth capacitor Cclk has one end connected to the second electrode of the tenth A transistor T10a and the first electrode of the tenth B transistor T10b, and the other end connected to the first clock signal line ECLK1. .

Voltage coupling between the tenth B transistor T10b and the fourth capacitor Cclk to the first capacitor CQ by the first clock signal ECLK1 applied to the first clock signal line ECLK1 Even if is generated and the Q-node QN is changed to a turn-on voltage, it may be defined as a node compensating unit that compensates for it.

The reset transistor TR has a gate electrode connected to the reset signal line EST, and a first electrode connected to the output terminal EMO[1] of the emission control signal generator EM[1] of the first stage. The second electrode is connected to the first voltage line EVGH. The reset transistor TR is turned on or off according to a reset signal applied through a reset signal line EST. When the reset transistor TR is turned on, the output terminal EMO[1] of the emission control signal generator EM[1] of the first stage is applied through the first voltage line EVGH. Outputs a high-voltage light-emitting signal based on the voltage.

8 is a waveform diagram illustrating an operation of a light emission control signal generator of a first stage according to the present invention.

As shown in FIG. 8, the start signal EVST applied through the start signal line EVST may have a form of generating a high voltage for 3 horizontal periods (3H). The second clock signal ECLK2 applied through the second clock signal line ECLK2 is synchronized with the high voltage timing (rising edge) of the start signal, and the low voltage and the high voltage alternately occur in a period of one horizontal time (1H). It can have a form to do. The first clock signal ECLK1 applied through the first clock signal line ECLK1 alternately generates a high voltage and a low voltage in a period of one horizontal time (1H) in synchronization with the high voltage timing (rising edge) of the start signal. It can have a form to do. That is, the high voltage and the low voltage of the second clock signal ECLK2 and the first clock signal ECLK1 may be generated in reverse phase.

The devices included in the emission control signal generator EM[1] of the first stage include a start signal EVST, a first clock signal ECLK1, a second clock signal ECLK2, a first voltage VGH, and a second voltage. 2 Operates according to the voltage (VGL).

By the operation of the elements included in the emission control signal generator EM[1] of the first stage, the Q-node QN has a period in which it is charged to a high voltage, and the Q'-node Q'N And a period in which the QB-node QBN is discharged to a low voltage. In this case, the QB-node QBN may maintain a low voltage in a reversed phase form delayed by 1 horizontal time (1H) compared to the start signal EVST for 3 horizontal hours (3H).

That is, the first transistor T1 and the fourth transistor T4 are turned on in the low voltage period of the second clock signal ECLK2 to generate the high voltage during the third horizontal time period (3H). ) Is applied to the Q-node QN, and the second voltage EVGL is applied to the gate electrode of the third transistor TR and the Q'-node Q'N. At this time, the tenth A and B transistors T10a and T10b and the fifth transistor T5 are turned off, and the eighth transistor T8 is turned on.

And, when the second clock signal ECLK2 transitions to the high voltage period and the first clock signal ECLK1 transitions to the low voltage period, the first transistor T1 and the fourth transistor T4 are turned- When the second transistor T2 and the ninth transistor T9 are turned off, the low voltage of the first clock signal ECLK1 is supplied to the QB-node QBN. Accordingly, the seventh transistor T7 is turned on and the first voltage EVGH is output to the output terminal EMO of the emission control signal generator EM[1] of the first stage.

After the start signal EVST transitions to a low voltage, when the second clock signal ECLK2 transitions to a low voltage again, and the first clock signal ECLK1 transitions to a high voltage section again, the The Q-node QN is discharged to a low voltage, the QB-node QBN is charged to a first voltage, and the output terminal EMO of the emission control signal generator EM[1] of the first stage is also It is output as the second voltage.

The sixth transistor T6 constituting the emission control signal output unit of the emission control signal generation unit EM[1] of the first stage is turned on or off according to the potential of the Q-node QN, The seventh transistor T7 is turned on or off according to the potential of the QB-node QBN. When the potential of the Q-node QN maintains a high voltage, the potential of the QB-node QBN may maintain a low voltage.

Since the seventh transistor T7 is turned on according to the low voltage of the QB-node QBN, the first voltage VGH applied through the first voltage line EVGH is a light emission control signal of the first stage. It is output through the output terminal EMO[1] of the generator EM[1]. As a result, the output terminal EMO[1] of the emission control signal generator EM[1] of the first stage is at least 3 based on the first voltage VGH applied through the first voltage line EVGH. After the high voltage emission control signal Em[1] is output during the horizontal time period (3H), it is converted to the low voltage emission control signal Em[1].

The devices included in the emission control signal generator EM[1] of the first stage may receive a bias stress as they operate as described above. The bias stress is related to the lifetime of the devices together with the threshold voltage.

The devices included in the emission control signal generator EM[1] of the first stage are those that are subjected to High Junction Temperature Stress (HJTS) due to the transmission of a high voltage through the source-drain electrode, and are high through the gate electrode. It can be classified into a device that receives PBTS (Positive Bias Temperature Stress) due to application of a voltage, and a device that receives NBTS (Negative Bias Temperature Stress) due to application of a low voltage through a gate electrode.

However, the devices included in the emission control signal generator EM[1] of the first stage exclude the third transistor T3 during a duty variable operation to lower the duty of the emission control signal Em[1]. The pattern of stress on other transistors changes as follows.

9 is a table of stresses of elements of the emission control signal generator according to the present invention.

As shown in FIG. 9, the first transistor T1 corresponds to a transistor that receives PBTS(PB) at a high duty but receives NBTS(NB) at a low duty. The second transistor T2 corresponds to a transistor that receives HJTS(HJ) at a high duty, but receives NBTS(NB) at a low duty. The fourth transistor T4 corresponds to a transistor that receives HJTS(HJ) at a high duty, but receives PBTS(PB) at a low duty. The fifth transistor T5 corresponds to a transistor that receives NBTS(NB) at a high duty, but receives HJTS(HJ) at a low duty. The sixth transistor T6 corresponds to a transistor that receives NBTS(NB) at a high duty, but receives HJTS(HJ) at a low duty. The seventh transistor T7 corresponds to a transistor that receives HJTS(HJ) at a high duty, but receives NBTS(NB) at a low duty. The eighth transistor T8 corresponds to a transistor that receives HJTS(HJ) at a high duty, but receives NBTS(NB) at a low duty. The ninth transistor T9 corresponds to a transistor that receives NBTS(NB) at a high duty but receives HJTS(HJ) at a low duty. The tenth A and B transistors T10a and T10b correspond to transistors that receive NBTS(NB) at high duty, but receive PBTS(PB) or HJTS(HJ) at low duty.

In the table of FIG. 9, HNV (High Negative Voltage), HPV (High Positive Voltage), HJV (High Junction Voltage), and LV (Low Voltage) are indicated.

It is very important to maintain a high voltage of the light emission control signal for driving the light emission control signal generator.

However, in the light emission control signal generator of FIG. 7, when there is no node compensator including the tenth B transistor T10b and the fourth capacitor Cclk, the following phenomenon may occur.

10 is an exemplary view of waveforms when there is no node compensation unit in the emission control signal generation unit of the first stage according to the present invention.

As described in FIG. 9, when the duty driving is varied (100% → 1%), the tenth A transistor T10a receives NBTS at high duty, but receives PBTS or HJTS at low duty.

In addition, as shown in FIG. 10, while the Q-node QN maintains a high voltage, the second clock signal ECLK2 transitions to a high voltage period, and the first clock signal ECLK1 is When transitioning to the low voltage period, voltage coupling may occur in the first capacitor CQ by the first clock signal ECLK1. Accordingly, the Q-node QN may be dropped to a turn-on voltage due to voltage coupling of the first capacitor CQ. Accordingly, the tenth A transistor T10a is turned on, the Q'-node QN rises to a turn-off voltage, and the eighth transistor T8 is turned off.

In this way, since the eighth transistor T8 is turned off, the low voltage is not applied to the QB-node QBN even if the ninth transistor T9 is turned on by the first clock signal ECLK1. Since the high voltage is maintained, the seventh transistor T7 is turned off, so that the first voltage EVGH cannot be supplied to the output terminal EMO of the emission control signal generator. However, since the node compensation unit including the tenth B transistor T10b and the fourth capacitor Cclk is present, the above defect can be prevented.

11 is an exemplary view of waveforms by a node compensator in the emission control signal generator of the first stage according to the present invention.

When the second clock signal ECLK2 transitions to a high voltage period while the Q-node QN maintains a high voltage, and the first clock signal ECLK1 transitions to a low voltage period, the Voltage coupling may occur in the first capacitor CQ by the first clock signal ECLK1. Accordingly, the Q-node QN is dropped to a turn-on voltage due to voltage coupling of the first capacitor CQ, so that the tenth A transistor T10a may be turned on.

However, due to the fourth capacitor Cclk, the coupling voltage is canceled and the gate-source voltage Vgs of the tenth B transistor T10b is maintained, so that the tenth B transistor T10b is It does not turn on.

Accordingly, since the eighth transistor T8 is turned on and the ninth transistor T9 is turned on by the first clock signal ECLK1, the first clock signal ( A low voltage of ECLK1 is applied to the gate electrode of the seventh transistor T7, and the seventh transistor T7 is turned on to apply the first voltage EVGH to the output terminal EMO of the emission control signal generator. Will be supplied.

As described above, since there is a node compensation unit composed of the tenth B transistor T10b and the fourth capacitor Cclk, when the duty of the light emission control signal EM is driven, the output of the light emission control signal EM is The high voltage state can be stably maintained.

In addition, since the node compensation unit as described above is present, the output margin of the emission control signal is improved, and the reliability of the emission control signal generator is improved.

That is, when the node compensation unit as described above does not exist, the threshold voltage margin (Vth) of the transistors of the emission control signal generation unit is about 3V, but since the node compensation unit is present, the threshold voltage margin of the transistors of the emission control signal generation unit is (Vth) increased to about 7V.

The above description is merely illustrative of the present invention, and various modifications may be made without departing from the technical spirit of the present invention by those of ordinary skill in the technical field to which the present invention pertains. Therefore, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be construed by the following claims, and all technologies within the scope equivalent thereto should be construed as being included in the scope of the present invention.

130: scan driving unit 150: display panel
131: shift register 135: level shifter unit

Claims (8)

And a plurality of stages that are subordinately connected to sequentially output light emission control signals,
Each stage,
An output unit that outputs a first voltage as a light emission control signal according to the potential of the QB-node and outputs a second voltage as a light emission control signal according to the potential of the Q-node;
A node controller configured to control potentials of the QB-node and the Q-node by operating based on a start signal or a light emission control signal output from a previous stage, a first clock signal, and a second clock signal; And
A light emission control signal generation unit including a node prevention unit for preventing the first voltage from being output to the output unit due to voltage coupling of the first clock signal. The method of claim 1,
The node compensation unit,
Light emission control signal generator comprising a capacitor for canceling the coupling voltage. The method of claim 1,
The node control unit,
A gate electrode is connected to a second clock signal supply line supplying the second clock signal, a first electrode is connected to a start signal line supplying the start signal or an output terminal of the previous stage, and a second electrode is connected to the Q-node The connected first transistor,
A second transistor having a gate electrode connected to a first clock signal line supplying the first clock signal and a first electrode connected to the Q-node,
A third transistor having a first electrode connected to a second electrode of the second transistor and a second electrode connected to a first voltage supply line supplying a first voltage,
A fourth transistor having a gate electrode connected to the second clock signal supply line, a first electrode connected to a second voltage supply line supplying the second voltage, and a second electrode connected to the gate electrode of the third transistor; ,
A fifth transistor having a gate electrode connected to the Q-node, a first electrode connected to the QB-node, and a second electrode connected to the first voltage supply line,
An eighth transistor having a gate electrode connected to the second electrode of the fourth transistor and a first electrode connected to the first clock signal supply line,
A ninth transistor having a gate electrode connected to the first clock signal supply line, a first electrode connected to a second electrode of the eighth transistor T8, and a second electrode connected to the QB-node,
A light emission control signal generator including a tenth A transistor having a gate electrode connected to the Q-node and a first electrode connected to the second clock signal supply line. The method of claim 3,
The node compensation unit,
A tenth B transistor having a gate electrode connected to the Q-node, a first electrode connected to a second electrode of the tenth transistor A, and a second electrode connected to the gate electrode of the eighth transistor,
A light emission control signal generator including a first capacitor connected between the second electrode of the tenth A transistor and the first clock signal supply line. The method of claim 3,
The node control unit,
A second capacitor connected between the Q-node and the first clock signal supply line,
A third capacitor connected between the QB-node and the first voltage supply line,
A light emission control signal generator further comprising a fourth capacitor connected between the gate electrode of the eighth transistor and the second electrode of the eighth transistor. The method of claim 1,
The output unit,
A sixth transistor having a gate electrode connected to the Q-node, a first electrode connected to a second voltage supply line supplying the second voltage, and a second electrode connected to an output terminal,
A light emission control signal generator comprising a seventh transistor having a gate electrode connected to the QB-node, a first electrode connected to the output terminal, and a second electrode connected to a first voltage supply line supplying the first voltage . The method of claim 1,
The emission control signal generator further comprises a reset transistor controlled according to a reset signal to reset the output terminal of the output unit to the first voltage. A display panel that displays an image;
A scan signal generator supplying a scan signal to the display panel; And
A light emission control signal generator supplying a light emission control signal to the display panel,
The light emission control signal generator includes a plurality of stages that are subordinately connected to sequentially output light emission control signals,
Each stage,
An output unit that outputs a first voltage as a light emission control signal according to the potential of the QB-node and outputs a second voltage as a light emission control signal according to the potential of the Q-node;
A node controller configured to control potentials of the QB-node and the Q-node by operating based on a start signal or a light emission control signal output from a previous stage, a first clock signal, and a second clock signal; And
And a node preventing unit for preventing the first voltage from being output to the output unit due to voltage coupling of the first clock signal.

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