KR20210080960A - Gate driving circuit and light emitting display apparatus comprising the same - Google Patents

Abstract

An object of the present specification is to provide a gate driving circuit which can be reduced in size (or width), and a light emitting display device including the same. The gate driving circuit according to some of the present specification includes first to m^th scan drivers cascaded to each other, wherein each of the first to m^th scan drivers may include a first output terminal outputting a signal having a positive polarity pulse, and a second output terminal outputting a signal having a negative polarity pulse synchronized with the positive polarity pulse.

Description

GATE DRIVING CIRCUIT AND LIGHT EMITTING DISPLAY APPARATUS COMPRISING THE SAME

The present specification relates to a gate driving circuit and a light emitting display device including the same.

Since the light emitting display device displays an image using a self-luminous element, it has a high response speed, low power consumption, and has no problem in a viewing angle, so it is attracting attention as a next-generation display device.

The light emitting display device may include pixels having a light emitting element and a pixel circuit driving the light emitting element. For example, the pixel circuit includes a driving thin film transistor for controlling a driving current flowing through the light emitting device, and a switching thin film transistor for controlling (or programming) a gate-source voltage of the driving thin film transistor according to a scan signal. Furthermore, the pixel circuit may further include an emission thin film transistor for controlling the emission period according to the emission control signal of the light emitting device.

The light emitting display device may include a gate driving circuit that generates a scan signal to be supplied to the pixels. The gate driving circuit may be directly formed or mounted (or embedded) on a non-display area (or bezel area) defined on the base substrate of the display panel.

In the light emitting display device, it is difficult to reduce the bezel width due to the size (or width) of the gate driving circuit disposed in the non-display area of the display panel.

An object of the present specification is to provide a gate driving circuit having a reduced size (or width) and a light emitting display device including the same.

Another object of the present specification is to provide a gate driving circuit capable of ensuring operation stability while reducing size (or width) and a light emitting display device including the same.

The problems to be solved according to the example of the present specification are not limited to the above-mentioned problems, and other problems not mentioned are from the description below to those of ordinary skill in the art to which the technical idea of the present specification belongs. can be clearly understood.

The gate driving circuit according to some of the present specification includes first to m-th scan drivers cascaded to each other, and each of the first to m-th scan drivers includes a first output terminal for outputting a signal having a positive polarity pulse, and and a second output terminal for outputting a signal having a negative pulse synchronized with the positive pulse.

A light emitting display device according to some of the present specification provides a light emitting display panel including pixels disposed in a pixel area defined by a plurality of data lines and first to m-th gate line groups, and a data voltage is supplied to each of the plurality of data lines. a data driving circuit unit comprising: a data driving circuit unit; and a gate driving circuit unit having first to m-th stage blocks disposed on the light emitting display panel and connected to each of the first to m-th gate line groups, wherein each of the first to m-th stage blocks includes a first a first stage circuit connected to a first gate line of each of the to mth gate line groups, wherein the first stage circuit of each of the first to mth stage blocks is a first gate line of each of the first to mth gate line groups a first output terminal electrically connected to and outputting a first scan signal having a positive polarity pulse, and a second output terminal outputting a carry signal having a negative polarity pulse synchronized with the positive polarity pulse to the next stage block; can do.

Specific details according to various examples of the present specification other than the means for solving the above-mentioned problems are included in the description and drawings below.

According to the present specification, the size (or width) of the gate driving circuit and the light emitting display device including the same may be reduced.

According to the present specification, operation stability may be secured while the size (or width) of the gate driving circuit and the light emitting display device including the same is reduced.

Since the content of the problems to be solved, the means for solving the problems, and the effects mentioned above do not specify essential features of the claims, the scope of the claims is not limited by the matters described in the content of the invention.

1 is a diagram illustrating a gate driving circuit according to an example of the present specification.
2 is a diagram illustrating a gate driving circuit according to a first example of the present specification.
3 is a circuit diagram illustrating a scan driver according to a first example of the present specification.
FIG. 4 is a waveform diagram illustrating a method of driving the scan driver shown in FIG. 3 .
5 is a diagram illustrating a gate driving circuit according to a second example of the present specification.
6 is a circuit diagram illustrating a scan driver according to a second example of the present specification.
7 is a waveform diagram illustrating a method of driving the scan driver shown in FIG. 6 .
8 is a diagram illustrating a gate driving circuit according to a third example of the present specification.
9 is a circuit diagram illustrating a scan driver according to a third example of the present specification.
10 is a diagram illustrating a light emitting display device according to an example of the present specification.
11 is an equivalent circuit diagram according to an example of the pixel illustrated in FIG. 10 .
12 is a waveform diagram illustrating a signal supplied to the pixel illustrated in FIG. 11 .
13 is a diagram illustrating a gate driving circuit unit according to the first example shown in FIG. 10 .
14 is a diagram illustrating a gate driving circuit unit according to the second example shown in FIG. 10 .
15 is a waveform diagram illustrating an output waveform of a carry signal according to a size (or channel width) of a seventh thin film transistor in the scan driver illustrated in FIG. 3 .

Advantages and features of the present specification, and methods of achieving them, will become apparent with reference to the various examples described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the examples disclosed below, but will be implemented in various different forms, and only examples of the present specification allow the disclosure of the present specification to be complete, and in the technical field to which the technical spirit of the present specification belongs It is provided to completely inform those of ordinary skill in the scope of the technical idea, and the technical idea of the present specification is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining an example of the present specification are exemplary and the present specification is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing an example of the present specification, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present specification, the detailed description thereof will be omitted.

When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

Although the first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present specification.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It may mean a combination of all items that can be presented from more than one.

The technical features of each of the various examples of the present specification may be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each example may be independently implemented with respect to each other or may be implemented together in a related relationship. have.

Hereinafter, a preferred example of a gate driving circuit according to the present specification and a light emitting display device including the same will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings.

1 is a diagram illustrating a gate driving circuit according to an example of the present specification.

Referring to FIG. 1 , a gate driving circuit according to an example of the present specification is configured to switch an N-type oxide thin film transistor (hereinafter, referred to as “TFT”) included in a pixel of a light emitting display panel. , can be implemented to output the scan signal SS having a positive polarity pulse For example, a pixel is formed by using an NMOS-type oxide TFT with excellent off current characteristics to prevent image quality deterioration due to leakage current. may include

The gate driving circuits are dependently connected to each other, and include a gate start signal GVst, first and second gate shift clocks GCLK1 and GCLK2, a first driving voltage VGH of a gate high voltage, and a second driving voltage of a gate low voltage. Based on the driving voltage VGL, internal output signals OS1 to OSm having negative polarity pulses are generated and then inverted to sequentially output scan signals SS1 to SSm having positive polarity pulses. It may include stage blocks 701 to 70m.

The gate start signal GVst is supplied to the first stage block 701 among the first to m-th stage blocks 701 to 70m. The internal output signals OS2 to OSm of each of the second to mth stage blocks 702 to 70m are supplied as the gate start signal GVst of the next (or subsequent) stage.

Each of the first to mth stage blocks 701 to 70m may include a scan driver SD and an inverter driver IVT.

The scan driver SD may output the signals OS1 to OSm having negative pulses based on the gate start signal GVst and the first and second gate shift clocks GCLK1 and GCLK2 .

The scan driver SD according to an example may be implemented with low-temperature poly-Si (LTPS) TFTs having excellent on-current characteristics and driving reliability characteristics. For example, the scan driver SD may be implemented with PMOS type LTPS TFTs. The scan driver SD sets the respective voltages of the first and second nodes according to the gate start signal GVst and the first and second gate shift clocks GCLK1 and GCLK2, and the first and second nodes according to the voltage of the first node. Signals OS1 to OSm having negative pulses corresponding to the low voltage level of any one of the first and second gate shift clocks GCLK1 and GCLK2 may be output.

The inverter driver IVT converts the output signals OS1 to OSm having negative pulses supplied from the scan driver SD into positive pulses based on the first driving voltage VGH and the second driving voltage VGL. The scan signals SS1 to SSm may be inverted and supplied to the pixel.

As described above, in the gate driving circuit according to an example of the present specification, an output signal OS1 having a negative polarity output from the scan driver SD including the P-type LTPS TFTs in order to switch the N-type LTPS TFTs disposed in the pixel. to OSm) are required to invert the scan signals SS1 to SSm having positive polarity pulses, and an inverter driver IVT is required, and the size increases due to the addition of the inverter driver IVT.

2 is a diagram illustrating a gate driving circuit according to a first example of the present specification.

Referring to FIG. 2 , the gate driving circuit according to the first example of the present specification includes a first output terminal outputting scan signals SS1 to SSm having a positive pulse and a carry having a negative pulse synchronized with the positive pulse. and first to mth scan drivers SD1 to SDm implemented to include a second output terminal for outputting the signals CS1 to CSm.

Each of the first to mth scan drivers SD1 to SDm is connected to each other dependently, and a first driving voltage VGH supplied through a first power supply line and a second driving voltage supplied through a second power supply line, respectively. (VGL), three gate shift clocks among the first to sixth gate shift clocks GCLK1 to GCLK6 supplied through the first to sixth clock supply lines, and the gate start signal GVst, a positive pulse It is possible to sequentially output the scan signals SS1 to SSm and the carry signals CS1 to CSm having the negative polarity pulse synchronized with the positive polarity pulse. For example, the first to sixth gate shift clocks GCLK1 to GCLK6 and the gate start signal GVst may be expressed as a gate control signal GCS.

Each of the first and second driving voltages VGH and VGL may be commonly supplied to each of the first to mth scan drivers SD1 to SDm through the first and second power supply lines, respectively.

The first driving voltage VGH may have a high potential voltage level (or a high voltage level). For example, the first driving voltage VGH is a high potential voltage level for turning off the PMOS-type LTPS TFT implementing the scan drivers SD1 to SDm or turning on the NMOS-type oxide TFT included in the pixel. (or high voltage level).

The second driving voltage VGL may have a low potential voltage level (or a low voltage level) lower than a high potential voltage level (or a high voltage level). For example, the second driving voltage VGL is a low potential voltage level for turning on the PMOS-type LTPS TFT implementing the scan drivers SD1 to SDm or turning off the NMOS-type oxide TFT included in the pixel. (or a low voltage level).

The first and second gate shift clocks GCLK1 and GCLK2 may be commonly supplied to each of the first to mth scan drivers SD1 to SDm through the first and second clock supply lines, respectively.

Each of the first and second gate shift clocks GCLK1 and GCLK2 may include a high voltage level (or a positive pulse) and a low voltage level (or a negative pulse) that are cyclically repeated in units of one horizontal period. For example, the high voltage level may have the same voltage level as the first driving voltage VGH. In addition, the low voltage level may have the same voltage level as the second driving voltage VGL.

The first and second gate shift clocks GCLK1 and GCLK2 may have inverted voltage levels. The second gate shift clock GCLK2 may have a shape inverted from that of the first gate shift clock GCLK1 or may have a shape shifted from the first gate shift clock GCLK1 by one horizontal period. For example, the rising time (or the first voltage transition time) of the second gate shift clock GCLK2 may be synchronized with the falling time (or the second voltage transition time) of the first gate shift clock GCLK1 .

The third to sixth gate shift clocks GCLK3 to GCLK6 may be selectively supplied to the first to mth scan drivers SD1 to SDm through the third to sixth clock supply lines, respectively.

Each of the third to sixth gate shift clocks GCLK3 to GCLK6 may have a shape different from that of the first and second gate shift clocks GCLK1 and GCLK2 .

Each of the third to sixth gate shift clocks GCLK3 to GCLK6 according to an example may include a high voltage level and a low voltage level that are cyclically repeated in units of two horizontal periods.

Each of the third to sixth gate shift clocks GCLK3 to GCLK6 may include a high voltage level and a low voltage level that are cyclically repeated in units of two horizontal periods.

Each of the third to sixth gate shift clocks GCLK3 to GCLK6 may be shifted by one horizontal period.

The third gate shift clock GCLK3 may include a high voltage level and a low voltage level that are cyclically repeated in units of two horizontal periods. Each of the rising time and the falling time of the third gate shift clock GCLK3 may be synchronized with the rising time of the first gate shift clock GCLK1 .

The fourth gate shift clock GCLK4 may be shifted from the third gate shift clock GCLK3 by one horizontal period. For example, each of the rising time and the falling time of the fourth gate shift clock GCLK4 may be synchronized with the rising time of the second gate shift clock GCLK2 .

The fifth gate shift clock GCLK5 may have a shape inverted to the third gate shift clock GCLK3 or shifted from the fourth gate shift clock GCLK4 by one horizontal period.

The sixth gate shift clock GCLK6 may have a shape inverted to the fourth gate shift clock GCLK4 or shifted from the fifth gate shift clock GCLK5 by one horizontal period.

The gate start signal GVst is a signal indicating the first horizontal period among one frame for displaying one image on the panel, and may include a negative pulse (or low voltage level) generated immediately before the first horizontal period of each frame. have. For example, the gate start signal GVst may be synchronized with the second gate shift clock GCLK2 .

The first to mth scan drivers SD1 to SDm may be connected in a cascade manner through carry signal lines that transmit carry signals CS1 to CSm.

The first scan driver SD1 among the first to mth scan drivers SD1 to SDm may receive the gate start signal GVst supplied from the outside. Among the first to mth scan drivers SD1 to SDm, the second to mth scan drivers SD2 to SDm carry a carry having a negative pulse output from the previous (or previous) scan drivers SD1 to SDm-1. The signals CS1 to CSm may be received as the gate start signal GVst.

The 4i-3 (i is 1 to m/4) scan drivers SD4i-3 among the first to mth scan drivers SD1 to SDm are supplied through the first, second, and third clock supply lines, respectively. The first, second, and third gate shift clocks GCLK1 , GCLK2 , and GCLK3 may be received.

Among the first to mth scan drivers SD1 to SDm, the 4i-2th scan driver SD4i-2 is the first, second, and fourth clock supply lines supplied through the first, second, and fourth clock supply lines, respectively. It can receive 4 gate shift clocks GCLK1, GCLK2, and GCLK4.

Among the first to mth scan drivers SD1 to SDm, the 4i-1th scan driver SD4i-1 includes first, second, and second clock supply lines supplied through the first, second, and fifth clock supply lines, respectively. 5 gate shift clocks GCLK1, GCLK2, and GCLK5 can be received.

The 4i scan driver SD4i among the first to mth scan drivers SD1 to SDm is the first, second, and sixth gate shift clocks supplied through the first, second, and sixth clock supply lines, respectively. (GCLK1, GCLK2, GCLK6) can be received.

The 4i-3th scan driver SD4i-3 includes a first driving voltage VGH, a second driving voltage VGL, first, second, and third gate shift clocks GCLK1, GCLK2, GCLK3, and a gate Based on the start signal GVst, the scan signal SS4i-3 having the positive pulse and the carry signal CS4i-3 having the negative pulse may be simultaneously output. For example, the 4i-3th scan driver SD4i-3 includes the first driving voltage VGH, the second driving voltage VGL, and the first, second, and third gate shift clocks GCLK1, GCLK2, and GCLK3. ), and each voltage of the first node and the second node is set according to the gate start signal GVst, and the high voltage level of the second gate shift clock GCLK2 supplied to the second node is applied to the scan signal SS4i-3 ) and simultaneously outputting the low voltage level of the first gate shift clock GCLK1 as a negative pulse of the carry signal CS4i-3 according to the voltage of the first node, the second node The second driving voltage VGL may be supplied to the second node according to the third gate shift clock GCLK3 during the electrical floating period of .

The 4i-2th scan driver SD4i-2 includes a first driving voltage VGH, a second driving voltage VGL, first, second, and fourth gate shift clocks GCLK1, GCLK2, GCLK4, and a gate Based on the start signal GVst, the scan signal SS4i-2 having the positive pulse and the carry signal CS4i-2 having the negative pulse may be simultaneously output. For example, the 4i-2th scan driver SD4i-2 includes the first driving voltage VGH, the second driving voltage VGL, and the first, second, and fourth gate shift clocks GCLK1, GCLK2, and GCLK4. ), and each voltage of the first node and the second node is set according to the gate start signal GVst, and the high voltage level of the first gate shift clock GCLK1 supplied to the second node is applied to the scan signal SS4i-2 ) and simultaneously outputting the low voltage level of the second gate shift clock GCLK2 as a negative pulse of the carry signal CS4i-2 according to the voltage of the first node, the second node The second driving voltage VGL may be supplied to the second node according to the fourth gate shift clock GCLK4 during the electrical floating period of .

The 4i-1th scan driver SD4i-1 includes a first driving voltage VGH, a second driving voltage VGL, first, second, and fifth gate shift clocks GCLK1, GCLK2, GCLK5, and a gate Based on the start signal GVst, the scan signal SS4i-1 having the positive pulse and the carry signal CS4i-1 having the negative pulse may be simultaneously output. For example, the 4i-1th scan driver SD4i-1 includes the first driving voltage VGH, the second driving voltage VGL, and the first, second, and fifth gate shift clocks GCLK1, GCLK2, and GCLK5. ), and each voltage of the first node and the second node is set according to the gate start signal GVst, and the high voltage level of the second gate shift clock GCLK2 supplied to the second node is applied to the scan signal SS4i-1 ) and simultaneously outputting the low voltage level of the first gate shift clock GCLK1 as a negative pulse of the carry signal CS4i-1 according to the voltage of the first node, the second node The second driving voltage VGL may be supplied to the second node according to the fifth gate shift clock GCLK5 during the electrical floating period of .

The 4i scan driver SD4i includes the first driving voltage VGH, the second driving voltage VGL, the first, second, and sixth gate shift clocks GCLK1 , GCLK2 , GCLK6 , and the gate start signal GVst. ), the scan signal SS4i having the positive polarity pulse and the carry signal CS4i having the negative polarity pulse may be simultaneously output. For example, the 4i scan driver SD4i includes the first driving voltage VGH, the second driving voltage VGL, the first, second, and sixth gate shift clocks GCLK1 , GCLK2 , and GCLK6 , and the gate The voltage of each of the first node and the second node is set according to the start signal GVst, and the high voltage level of the first gate shift clock GCLK1 supplied to the second node is converted to a positive pulse of the scan signal SS4i. Simultaneously with the output, the low voltage level of the second gate shift clock GCLK2 may be output as a negative polarity pulse of the carry signal CS4i according to the voltage of the first node, and in the electrical floating period of the second node, the sixth The second driving voltage VGL may be supplied to the second node according to the gate shift clock GCLK6 .

3 is a circuit diagram illustrating a scan driver according to a first example of the present specification. For convenience of explanation, the first scan driver illustrated in FIG. 2 is shown.

2 and 3 , the scan driver SD according to the first example of the present specification includes a first node control circuit NCC1 , a second node control circuit NCC2 , an output buffer circuit OBC, and a capacitor. (Cq).

The first node control circuit NCC1 controls the voltage of the first node Q in response to voltages (or signals) of the first to third input terminals IT1 , IT2 , and IT3 and the first power terminal PT1 , respectively. It can be implemented to control.

The first input terminal IT1 (or the first input line) may receive the gate start signal GVst. The second input terminal IT2 (or the second input line) may receive the first gate shift clock GCLK1 supplied through the first clock supply line. The third input terminal IT3 (or the third input line) may receive the second gate shift clock GCLK2 supplied through the second clock supply line. The first power terminal PT1 (or the first power line) may receive the first driving voltage VGH supplied through the first power supply line.

The first node control circuit NCC1 according to an example may include first to third TFTs T1 , T2 , and T3 .

Each of the first to third TFTs T1 , T2 , and T3 may be implemented as a PMOS type LTPS TFT.

The first TFT T1 may selectively connect the first input terminal IT1 and the first node Q in response to the second gate shift clock GCLK2 supplied through the third input terminal IT3 . The first TFT T1 according to an example has a gate electrode electrically connected to the third input terminal IT3 , a first source/drain electrode electrically connected to the first input terminal IT1 , and a first node Q and a second source/drain electrode electrically connected to the .

The second TFT T2 may selectively connect the first node Q and the third TFT T3 in response to the first gate shift clock GCLK1 supplied through the second input terminal IT2 . The first TFT T1 according to an example has a gate electrode electrically connected to the second input terminal IT2 , a first source/drain electrode electrically connected to the first node Q, and a third TFT T3 . It may include a second electrically connected source/drain electrode.

The third TFT T3 may be connected in series with the second TFT T2 , and may selectively connect the second TFT T2 and the first power terminal PT1 in response to the voltage of the second node QB. The third TFT T3 according to an example includes a gate electrode electrically connected to the second node QB, a first source/drain electrode electrically connected to the second source/drain electrode of the second TFT T2, and a first A second source/drain electrode electrically connected to the first power terminal PT1 may be included.

The second node control circuit NCC2 is a second node in response to voltages (or signals) of the first node Q, the third and fourth input terminals IT3 and IT4, and the second power supply terminal PT2, respectively. It can be implemented to control the voltage of (QB).

The second node QB is implemented to be electrically connected to the first output terminal OT1. Accordingly, the second node control circuit NCC2 controls the voltage supplied to the second node QB in response to the voltage supplied through each of the third and fourth input terminals IT3 and IT4 to control the second node ( QB) and the voltage level of the scan signal SS output to the outside through the first output terminal OT1 may be controlled.

The fourth input terminal IT4 (or the fourth input line) may receive the third gate shift clock GCLK3 supplied through the third clock supply line. The second power terminal PT2 (or the second power line) may receive the second driving voltage VGL supplied through the second power supply line.

The second node control circuit NCC2 according to an example may include fourth to sixth TFTs T4 , T5 , and T6 .

Each of the fourth to sixth TFTs T4, T5, and T6 may be implemented as a PMOS type LTPS TFT.

The fourth TFT T4 may selectively connect the second power terminal PT2 and the second node QB in response to the second gate shift clock GCLK2 supplied through the third input terminal IT3 . According to an example, the fourth TFT T4 includes a gate electrode electrically connected to the third input terminal IT3 , a first source/drain electrode electrically connected to the second power terminal PT2 , and a second node QB. and a second source/drain electrode electrically connected to the .

The fifth TFT T5 may selectively connect the third input terminal IT3 and the second node QB in response to the voltage of the first node Q. The first TFT T1 according to an example has a gate electrode electrically connected to the first node Q, a first source/drain electrode electrically connected to the third input terminal IT3, and a second node QB. It may include a second electrically connected source/drain electrode.

The sixth TFT T6 may selectively connect the second power terminal PT2 and the second node QB in response to the third gate shift clock GCLK3 supplied through the fourth input terminal IT4 . According to an example, the sixth TFT T6 includes a gate electrode electrically connected to the fourth input terminal IT4 , a first source/drain electrode electrically connected to the second power terminal PT2 , and a second node QB. and a second source/drain electrode electrically connected to the .

The output buffer circuit OBC responds to the voltage of the first node Q and the voltage of the second node QB to the voltage (or signal) of the second input terminal IT2 or the voltage of the first power terminal PT1 . (or a signal) may be implemented to be supplied to the second output terminal OT2. That is, the output buffer circuit OBC receives the first gate shift clock GCLK1 or the first gate shift clock GCLK1 supplied through the second input terminal IT2 in response to the voltage of the first node Q and the voltage of the second node QB. By supplying the first driving voltage VGH supplied through the first power terminal PT1 to the second output terminal OT2, the voltage level of the carry signal CS output to the outside through the second output terminal OT2 is increased. can be controlled

The output buffer circuit OBC according to an example may include a seventh TFT ( T7 ) and an eighth TFT ( T8 ).

The seventh TFT T7 may selectively connect the second input terminal IT2 and the second output terminal OT2 in response to the voltage of the first node Q. According to an example, the seventh TFT T7 includes a gate electrode electrically connected to the first node Q, a first source/drain electrode electrically connected to the second input terminal IT2, and a second output terminal OT2. and a second source/drain electrode electrically connected to the .

The eighth TFT T8 may selectively connect the first power terminal PT1 and the second output terminal OT2 in response to the voltage of the second node QB. According to an example, the eighth TFT T8 includes a gate electrode electrically connected to the second node QB, a first source/drain electrode electrically connected to the second output terminal OT2 , and a first power terminal PT1 . and a second source/drain electrode electrically connected to the .

As such, in the output buffer circuit OBC, each of the seventh TFT ( T7 ) and the eighth TFT ( T8 ) has a relatively low withstand voltage because a load of a gate line disposed on the light emitting display panel is not applied. , and as the size of each of the seventh TFT T7 and the eighth TFT T8 is reduced, the size of the scan driver SD may be reduced.

The capacitor Cq may be included in the output buffer circuit OBC. The capacitor Cq may be connected (or formed) between the first node Q and the second output terminal OT2 .

The capacitor Cq according to an example includes a first capacitor electrode electrically connected to the first node Q, and a second capacitor electrode electrically connected to the second output terminal OT2 while overlapping the first capacitor electrode with a dielectric layer interposed therebetween. It may include a capacitor electrode. The capacitor Cq may control the voltage between the first node Q and the second output terminal OT2 or the gate-source voltage of the seventh TFT T7. For example, the capacitor Cq may be charged with a voltage corresponding to turn-on or turn-off of the seventh TFT T7 .

FIG. 4 is a waveform diagram illustrating a method of driving the scan driver shown in FIG. 3 .

A driving method (or operation) of the scan driver SD according to the first example of the present specification will be described with reference to FIGS. 3 and 4 .

First, during the first period P1 , the first gate shift clock GCLK1 having the high voltage level VH is supplied to the second input terminal IT2 and the second gate shift clock having the low voltage level VL is supplied to the second gate shift clock GCLK1 . The clock GCLK2 is supplied to the third input terminal IT3, the third gate shift clock GCLK3 having the high voltage level VH is supplied to the fourth input terminal IT4, and the second gate shift clock A gate start signal GVst having a low voltage level VL synchronized with GCLK2 is supplied to the first input terminal IT1, whereby each of the first TFT T1 and the fourth TFT T4 turns- is turned on, and each of the second TFT ( T2 ) and the sixth TFT ( T6 ) may be turned off.

In the first period P1 , when the first TFT T1 is turned on by the second gate shift clock GCLK2 having the low voltage level VL, the low voltage supplied to the first input terminal IT1 The first node Q is set to the low voltage level VL by the gate start signal GVst having the level VL, and the fifth TFT T5 by the voltage VQ of the first node Q and each of the seventh TFTs T7 is turned on. When the seventh TFT T7 is turned on, the first gate shift clock GCLK1 of the high voltage level VH supplied to the second input terminal IT2 moves to the high voltage level VH of the carry signal CS. may be output through the second output terminal OT2. Accordingly, the carry signal CS may stably maintain the high voltage level VH following the previous period. When the fifth TFT (T5) is turned on at the same time as the seventh TFT (T7), the second gate shift clock (GCLK2) having the low voltage level (VL) supplied to the third input terminal (IT3) The node QB is set to the low voltage level VL, so that the low voltage level VL of the second node QB is the low voltage level VL of the scan signal SS and the first output terminal OT1 ) can be output.

In the first period P1 , when the fourth TFT T4 is turned on by the second gate shift clock GCLK2 having the low voltage level VL, the second voltage supplied to the second power terminal PT2 is turned on. The second node QB is set to the second driving voltage VGL by the driving voltage VGL, so that the second driving voltage VGL of the second node QB is the low voltage of the scan signal SS. The level VL may be output through the first output terminal OT1 . At this time, the first output terminal OT1 is connected to the low voltage level VL of the second gate shift clock GCLK2 supplied to the second node QB through the fifth TFT T5 and/or the fourth TFT T4 ) may output the scan signal SS having a low voltage level VL corresponding to the second driving voltage VGL supplied to the second node QB. Accordingly, the scan signal SS may stably maintain the low voltage level VL following the previous period.

In the first period P1 , when the second node QB is set to the second driving voltage VGL, each of the third TFT T3 and the eighth TFT T8 is turned on. When the eighth TFT T8 is turned on, the first driving voltage VGH supplied to the first power terminal PT1 is the high voltage level VH of the carry signal CS and the second output terminal OT2 . can be output through At this time, the second output terminal OT2 is the high voltage level VH of the first gate shift clock GCLK1 supplied through the seventh TFT T7 and/or the first output terminal supplied through the eighth TFT T8 . A carry signal CS having a high voltage level VH corresponding to the driving voltage VGH may be output.

Subsequently, during the second period P2 , the first gate shift clock GCLK1 having the low voltage level VL is supplied to the second input terminal IT2 and the second gate shift clock having the high voltage level VH is supplied. The clock GCLK2 is supplied to the third input terminal IT3 and the third gate shift clock GCLK3 having the high voltage level VH is supplied to the fourth input terminal IT4 and the high voltage level VH. is supplied to the first input terminal IT1, whereby the second TFT T2 is turned on, and each of the first TFT T1 and the fourth TFT T4 is turned on. - may be turned off, and the sixth TFT T6 may maintain a turned-off state.

In the second period P2, when each of the first TFT T1 and the fourth TFT T4 is turned off by the second gate shift clock GCLK2 having the high voltage level VH, the first node ( Q) is electrically floating. In a state in which the first node Q is electrically floated, the first gate shift clock GCLK1 having the low voltage level VL is transmitted through the second input terminal IT2 to the first source of the seventh TFT T7. When supplied to the /drain electrode, the voltage VQ of the first node Q is a couple of the first gate shift clock GCLK1 supplied to the second source/drain electrode of the seventh TFT T7 and the capacitor Cq. By bootstrapping according to the ring effect, the voltage is lowered to a lower voltage by the low voltage level VL of the first gate shift clock GCLK1, so that the seventh TFT T7 is completely turned on. do. Accordingly, the low voltage level VL of the first gate shift clock GCLK1 supplied to the second input terminal IT2 may be output through the second output terminal OT2 as a negative pulse of the carry signal CS. can At this time, the low voltage level VL (or negative pulse) of the first gate shift clock GCLK1 is to be output through the second output terminal OT2 without voltage loss through the fully turned-on seventh TFT T7. can For example, the negative pulse of the carry signal CS may be supplied to the first input terminal IT1 of the next stage scan driver SD2 as the gate start signal GVst.

In the second period P2, when the fifth TFT T5 is completely turned on by the voltage VQ of the first node Q, the high voltage level ( The second node QB is set to the high voltage level VH by the second gate shift clock GCLK2 having SS) and may be output through the first output terminal OT1 as a positive pulse. In this case, the high voltage level VH of the second gate shift clock GCLK2 may be supplied to the second node QB through the fully turned-on fifth TFT T5 without voltage loss. For example, the positive pulse of the scan signal SS may be used as a signal for turning on the NMOS-type oxide TFT included in the pixel.

Subsequently, during the third period P3 , the first gate shift clock GCLK1 having the high voltage level VH is supplied to the second input terminal IT2 and the second gate shift clock having the low voltage level VL is applied. The clock GCLK2 is supplied to the third input terminal IT3 and the third gate shift clock GCLK3 having the low voltage level VL is supplied to the fourth input terminal IT4 and the high voltage level VH. is supplied to the first input terminal IT1, whereby each of the first TFT (T1), the fourth TFT (T4), and the sixth TFT (T6) is turned on; The second TFT T2 may be turned off.

In the third period P3 , when the first TFT T1 is turned on by the second gate shift clock GCLK2 having the low voltage level VL, the high voltage supplied to the first input terminal IT1 The first node Q is set to the high voltage level VH by the gate start signal GVst having the level VH, and the fifth TFT T5 is set by the voltage VQ of the first node Q. and each of the seventh TFTs T7 is turned off.

In the third period P3 , when the fourth TFT T4 is turned on by the second gate shift clock GCLK2 having the low voltage level VL, the second voltage supplied to the second power terminal PT2 is turned on. The second node QB is set to the second driving voltage VL by the driving voltage VGL, so that the second driving voltage VGL of the second node QB is the low voltage of the scan signal SS. The level VL may be output through the first output terminal OT1 .

In the third period P3, when the sixth TFT T6 is turned on by the third gate shift clock GCLK3 having the low voltage level VL, the second power supply terminal PT2 is supplied to the second power supply terminal PT2. The second node QB is set to the second driving voltage VL by the driving voltage VGL, so that the second driving voltage VGL of the second node QB is the low voltage of the scan signal SS. The level VL may be output through the first output terminal OT1 . At this time, the first output terminal OT1 is a scan signal having a low voltage level VL corresponding to the second driving voltage VGL supplied through the fourth TFT T4 and/or the sixth TFT T6. SS) can be printed.

Subsequently, during the fourth period P4 , the first gate shift clock GCLK1 having the low voltage level VL is supplied to the second input terminal IT2 and the second gate shift clock GCLK1 having the high voltage level VH is applied. The clock GCLK2 is supplied to the third input terminal IT3 and the third gate shift clock GCLK3 having the low voltage level VL is supplied to the fourth input terminal IT4 and the high voltage level VH. is supplied to the first input terminal IT1, whereby the second TFT T2 is turned on, and each of the first TFT T1 and the fourth TFT T4 is turned on. - may be turned off, and the sixth TFT T6 may maintain a turned-on state.

In the fourth period P4, as the sixth TFT T6 is maintained in the turned-on state by the third gate shift clock GCLK3 having the low voltage level VL, the voltage ( VQB) is maintained at the second driving voltage VGL supplied to the second power supply terminal PT2, and the third TFT T3 and the eighth TFT T8 are maintained by the voltage VQB of the second node QB. Each may remain turned-on. Accordingly, the second driving voltage VGL of the second node QB is output as the low voltage level VL of the scan signal SS through the first output terminal OT1, and thus the scan signal SS may stably maintain the low voltage level VL following the third period P3 . At the same time, as the eighth TFT T8 is maintained in the turned-on state, the first driving voltage VGH supplied to the first power terminal PT1 is set as the high voltage level VH of the carry signal CS. It is continuously output through the second output terminal OT2 , so that the carry signal CS may stably maintain the high voltage level VH after the third period P3 .

In the fourth period P4, while the third TFT T3 is turned on, the second TFT T2 is turned on by the first gate shift clock GCLK1 having the low voltage level VL, and , when each of the first TFT ( T1 ) and the fourth TFT ( T4 ) are turned off by the second gate shift clock ( GCLK2 ) having the high voltage level ( VH ), the first voltage supplied to the first power supply terminal ( PT1 ) The first node Q is set to the first driving voltage VGH by the first driving voltage VGH, and the fifth TFT T5 and the seventh TFT ( T5 ) and the seventh TFT ( T5 ) are set by the voltage VQ of the first node Q ( VGH ). T7) each may be turned off.

Then, the scan driver SD operates the third and fourth periods P3 and P4 as described above until the gate start signal GVst having the low voltage level VL is supplied to the first input terminal IT1. ) to continuously output the scan signal SS of the low voltage level VL through the first output terminal OT1 and the carry signal of the high voltage level VH through the second output terminal OT2 at the same time. (CS) can be output continuously.

As such, the gate driving circuit according to the first example of the present specification outputs the scan signal SS through the first output terminal OT1 directly connected to the second node QB, so that the scan driver SD is performed without an inverter driver. A scan signal SS having a positive polarity pulse may be output through , and thus the size (or width) may be reduced due to deletion (or removal) of the inverter driver. For example, the gate driving circuit shown in FIGS. 2 and 3 may have a size smaller than the gate driving circuit shown in FIG. 1 by the size (or width) of the inverter driver.

5 is a diagram illustrating a gate driving circuit according to a second example of the present specification.

Referring to FIG. 5 , the gate driving circuit according to the second example of the present specification sequentially simultaneously and sequentially generates scan signals SS1 to SSm having positive pulses and carry signals CS1 to CSm having negative pulses without an inverter driver. It may include first to mth scan drivers SD1 to SDm implemented to output.

Each of the first to mth scan drivers SD1 to SDm is connected to each other dependently, and a first driving voltage VGH supplied through a first power supply line and a second driving voltage supplied through a second power supply line, respectively. (VGL), three gate shift clocks among the first to fourth gate shift clocks GCLK1 to GCLK4 supplied through the first to fourth clock supply lines, and the gate start signal GVst, a positive pulse The scan signals SS1 to SSm having , and the carry signals CS1 to CSm having negative pulses may be sequentially output simultaneously. For example, the first to fourth gate shift clocks GCLK1 to GCLK4 and the gate start signal GVst may be expressed as a gate control signal GCS.

The first driving voltage VGH may have a high potential voltage level (or a high voltage level) as described above. As described above, the second driving voltage VGL may have a low potential voltage level (or a low voltage level) lower than the high potential voltage level (or high voltage level).

The first and second gate shift clocks GCLK1 and GCLK2 may be commonly supplied to each of the first to mth scan drivers SD1 to SDm through the first and second clock supply lines, respectively.

Each of the first and second gate shift clocks GCLK1 and GCLK2 may include a high voltage level (or a positive pulse) and a low voltage level (or a negative pulse) that are cyclically repeated in units of one horizontal period as described above. have. The first and second gate shift clocks GCLK1 and GCLK2 may have inverted voltage levels.

Each of the third and fourth gate shift clocks GCLK3 and GCLK4 may include a high voltage level (or a positive pulse) and a low voltage level (or a negative pulse) that are cyclically repeated in units of one horizontal period. The third and fourth gate shift clocks GCLK3 and GCLK4 may have inverted voltage levels. For example, the third gate shift clock GCLK3 may be identical to the second gate shift clock GCLK2 , and the fourth gate shift clock GCLK4 may be identical to the first gate shift clock GCLK1 .

Among the first to mth scan drivers SD1 to SDm, the 2j-1 (j is 1 to m/2) scan drivers SD2j-1 are supplied through the first, second, and third clock supply lines, respectively. The first, second, and third gate shift clocks GCLK1 , GCLK2 , and GCLK3 may be received.

The 2i scan driver SD2i among the first to mth scan drivers SD1 to SDm is the first, second, and fourth gate shift clocks supplied through the first, second, and fourth clock supply lines, respectively. (GCLK1, GCLK2, GCLK4) can be received.

6 is a circuit diagram illustrating a scan driver according to a second example of the present specification. For convenience of explanation, the first scan driver illustrated in FIG. 5 is shown.

5 and 6 , the scan driver SD according to the second example of the present specification includes a first node control circuit NCC1 , a second node control circuit NCC2 , an output buffer circuit OBC, and a capacitor ( Cq), and an auxiliary capacitor Cqb. The scan driver SD according to the second example having such a configuration includes an auxiliary capacitor Cqb in addition to the scan driver SD shown in FIG. 3 . Accordingly, in the following description, descriptions of components other than the auxiliary capacitor Cqb and related components will be omitted or simplified.

The auxiliary capacitor Cqb may be included in the output buffer circuit OBC. The auxiliary capacitor Cqb may be connected (or formed) between the second node QB and the first power terminal PT1 .

The auxiliary capacitor Cqb according to an example has a first capacitor electrode electrically connected to the second node QB, and a first capacitor electrode electrically connected to the first power terminal PT1 while overlapping the first capacitor electrode with a dielectric layer interposed therebetween. It may include two capacitor electrodes. The auxiliary capacitor Cqb may store (or charge) a differential voltage between the second node QB and the first power terminal PT1 . For example, the auxiliary capacitor Cqb may be implemented to stably maintain a voltage applied to the second node QB.

7 is a waveform diagram illustrating a method of driving the scan driver shown in FIG. 6 .

The driving method (or operation) of the scan driver SD according to the second example of the present specification will be described with reference to FIGS. 6 and 7 .

First, during the first period P1 , the first gate shift clock GCLK1 having the high voltage level VH is supplied to the second input terminal IT2 and the second gate shift clock having the low voltage level VL is supplied to the second gate shift clock GCLK1 . The clock GCLK2 is supplied to the third input terminal IT3, the third gate shift clock GCLK3 having the low voltage level VL is supplied to the fourth input terminal IT4, and the first gate shift clock A gate start signal GVst having a low voltage level VL synchronized with GCLK1 is supplied to the first input terminal IT1, whereby the first TFT T1, the fourth TFT T4, and the sixth Each of the TFTs T6 may be turned on, and the second TFT T2 may be turned off.

In the first period P1 , when the first TFT T1 is turned on by the second gate shift clock GCLK2 having the low voltage level VL, the low voltage supplied to the first input terminal IT1 The first node Q is set to the low voltage level VL by the gate start signal GVst having the level VL, and the fifth TFT T5 by the voltage VQ of the first node Q and each of the seventh TFTs T7 is turned on. When the seventh TFT T7 is turned on, the first gate shift clock GCLK1 of the high voltage level VH supplied to the second input terminal IT2 moves to the high voltage level VH of the carry signal CS. may be output through the second output terminal OT2.

In the first period P1 , when the fifth TFT T5 is turned on simultaneously with the seventh TFT T7 , the second gate shift having the low voltage level VL supplied to the third input terminal IT3 is The second node QB may be set to the low voltage level VL by the clock GCLK2 . Also, when the fourth TFT T4 is turned on by the second gate shift clock GCLK2 having the low voltage level VL, the second driving voltage VGL supplied to the second power terminal PT2 is It may be supplied to the second node QB. At the same time, when the sixth TFT T6 is turned on by the third gate shift clock GCLK3 having the low voltage level VL, the second driving voltage VGL is supplied to the second power terminal PT2. This may be supplied to the second node QB. Accordingly, the auxiliary capacitor Cqb may charge a voltage corresponding to the voltage VQB of the second node QB and stably maintain the voltage VQB of the second node QB with the charged voltage. .

In the first period P1, the voltage VQB of the second node QB is stably maintained by the voltage charged in the auxiliary capacitor Cqb, whereby the first output terminal OT1 is connected to the fifth TFT ( The second node through at least one of the low voltage level VL of the second gate shift clock GCLK2 supplied to the second node QB through T5 and the fourth TFT T4 and the sixth TFT T6 The scan signal SS having a low voltage level VL corresponding to the second driving voltage VGL supplied to QB may be stably output. Accordingly, the scan signal SS may stably maintain the low voltage level VL following the previous period.

In the first period P1 , when the second node QB is set to the second driving voltage VGL, each of the third TFT T3 and the eighth TFT T8 is turned on. When the eighth TFT T8 is turned on, the first driving voltage VGH supplied to the first power terminal PT1 is the high voltage level VH of the carry signal CS and the second output terminal OT2 . can be output through At this time, each of the third TFT T3 and the eighth TFT T8 is applied to the voltage VQB or the auxiliary capacitor Cqb of the second node QB stably maintained by the voltage charged in the auxiliary capacitor Cqb. The turn-on state may be stably maintained in response to the charged voltage, and due to phosphorus, the second output terminal OT2 is supplied from the first power terminal PT1 through the eighth TFT T8. The carry signal CS having the high voltage level VH corresponding to the voltage VGH may be stably output.

Subsequently, during the second period P2 , the first gate shift clock GCLK1 having the low voltage level VL is supplied to the second input terminal IT2 and the second gate shift clock having the high voltage level VH is supplied. The clock GCLK2 is supplied to the third input terminal IT3 and the third gate shift clock GCLK3 having the high voltage level VH is supplied to the fourth input terminal IT4 and the high voltage level VH. is supplied to the first input terminal IT1, whereby the second TFT T2 is turned on, and each of the first TFT T1 and the fourth TFT T4 is turned on. - may be turned off, and the sixth TFT T6 may maintain a turned-off state. In this second period P2 , a positive pulse of the scan signal SS is output through the first output terminal OT1 and a negative pulse of the carry signal CS is outputted through the second output terminal OT2 at the same time. output, which is substantially the same as the second period P2 shown in FIG. 4 except that the voltage VQB of the second node QB is stably maintained by the voltage charged in the auxiliary capacitor Cqb. Since they are the same, a redundant description thereof will be omitted.

Subsequently, during the third period P3 , the first gate shift clock GCLK1 having the high voltage level VH is supplied to the second input terminal IT2 and the second gate shift clock having the low voltage level VL is applied. The clock GCLK2 is supplied to the third input terminal IT3 and the third gate shift clock GCLK3 having the low voltage level VL is supplied to the fourth input terminal IT4 and the high voltage level VH. is supplied to the first input terminal IT1, whereby each of the first TFT (T1), the fourth TFT (T4), and the sixth TFT (T6) is turned on; The second TFT T2 may be turned off. The third period P3 outputs the scan signal SS of the low voltage level VL through the first output terminal OT1 and simultaneously outputs the high voltage level VH through the second output terminal OT2. Outputting the carry signal CS, which is the third period shown in FIG. 4 except that the voltage VQB of the second node QB is stably maintained by the voltage charged in the auxiliary capacitor Cqb. Since it is substantially the same as (P3), a redundant description thereof will be omitted.

Subsequently, during the fourth period P4 , the first gate shift clock GCLK1 having the low voltage level VL is supplied to the second input terminal IT2 and the second gate shift clock GCLK1 having the high voltage level VH is applied. The clock GCLK2 is supplied to the third input terminal IT3 and the third gate shift clock GCLK3 having the high voltage level VH is supplied to the fourth input terminal IT4 and the high voltage level VH. is supplied to the first input terminal IT1, whereby the second TFT T2 is turned on, and each of the first TFT T1 and the fourth TFT T4 is turned on. - may be turned off, and the sixth TFT (T6) may be turned off. The fourth period P4 outputs the scan signal SS of the low voltage level VL through the first output terminal OT1 and simultaneously outputs the high voltage level VH through the second output terminal OT2. By outputting the carry signal CS, the sixth TFT T6 is turned off, and the voltage VQB of the second node QB is stably maintained by the voltage charged in the auxiliary capacitor Cqb. Since it is similar to the fourth period P4 illustrated in FIG. 4 , a redundant description thereof will be omitted.

Then, the scan driver SD operates the third and fourth periods P3 and P4 as described above until the gate start signal GVst having the low voltage level VL is supplied to the first input terminal IT1. ) to continuously output the scan signal SS of the low voltage level VL through the first output terminal OT1 and the carry signal of the high voltage level VH through the second output terminal OT2 at the same time. (CS) can be output continuously.

As described above, the gate driving circuit according to the second example of the present specification may have the same effect as the gate driving circuit according to the first example, and furthermore, due to two fewer clock supply lines than the gate driving circuit according to the first example, size can be reduced.

Alternatively, in the gate driving circuit according to the second example of the present specification, as shown in FIG. 7 , the third gate shift clock GCLK3 is the same as the second gate shift clock GCLK2 and the fourth gate shift clock Since GCLK4 is the same as the first gate shift clock GCLK1, the third gate shift clock GCLK3 and the fourth gate shift clock GCLK4 may be omitted, and in this case, the size of the gate driving circuit is further increased. can be reduced. For example, among the first to mth scan drivers SD1 to SDm, the fourth input terminal IT4 disposed in the 2j-1 scan driver SD2j-1 among the first to mth scan drivers SD1 to SDm is electrically connected to the third input terminal IT3 Alternatively, the second clock supply line providing the second gate shift clock GCLK2 connected to the third input terminal IT3 may be commonly connected to the third input terminal IT3 and the fourth input terminal IT4, respectively. In addition, the fourth input terminal IT4 disposed in the 2j scan driver SD2j among the first to mth scan drivers SD1 to SDm is electrically connected to the third input terminal IT3 or the third input terminal ( The first clock supply line providing the first gate shift clock GCLK1 connected to IT3 may be commonly connected to each of the third input terminal IT3 and the fourth input terminal IT4 .

Optionally, in the gate driving circuit according to the second example of the present specification, the auxiliary capacitor Cqb may be equally applied to the scan driver of the gate driving circuit according to the first example shown in FIG. 3 , and even in this case, the above-described An effect according to the auxiliary capacitor Cqb may be realized.

8 is a diagram illustrating a gate driving circuit according to a third example of the present specification.

Referring to FIG. 8 , the gate driving circuit according to the third example of the present specification sequentially simultaneously and sequentially performs scan signals PSS1 to PSSm having positive pulses and scan signals NSS1 to NSSm having negative pulses without an inverter driver. It may include first to mth scan drivers SD1 to SDm implemented to output.

Each of the first to mth scan drivers SD1 to SDm is connected to each other dependently, and a first driving voltage VGH supplied through a first power supply line and a second driving voltage supplied through a second power supply line, respectively. (VGL), three gate shift clocks among the first to fourth gate shift clocks GCLK1 to GCLK4 supplied through the first to fourth clock supply lines, and the gate start signal GVst, a positive pulse The scan signals PSS1 to PSSm and the scan signals NSS1 to NSSm having negative pulses may be sequentially output at the same time. In this case, each of the scan signals NSS1 to NSSm-1 having a negative pulse output from each of the first to m-1th scan drivers SD1 to SDm-1 corresponds to the second to mth scan drivers SD2 to SDm. Each gate start signal GVst may be used. For example, the first to fourth gate shift clocks GCLK1 to GCLK4 and the gate start signal GVst may be expressed as a gate control signal GCS.

Since each of the first driving voltage VGH, the second driving voltage VGL, the first to fourth gate shift clocks GCLK1 to GCLK4, and the gate start signal GVst is substantially the same as that of FIG. A description is omitted.

9 is a circuit diagram illustrating a scan driver according to a third example of the present specification. For convenience of explanation, the first scan driver illustrated in FIG. 8 is shown.

8 and 9 , the scan driver SD according to the third example of the present specification includes a first node control circuit NCC1 , a second node control circuit NCC2 , an output buffer circuit OBC, and a capacitor ( Cq), and an auxiliary capacitor Cqb. The scan driver SD according to the second example having such a configuration is substantially the same as the scan driver SD shown in FIG. 6 except that a ninth TFT T9 is additionally configured in the first node control circuit NCC1. equal to Accordingly, in the following description, descriptions of the components other than the ninth TFT T9 and related components will be omitted or simplified.

The first node control circuit NCC1 according to the present example further includes a ninth TFT T9 implemented to always maintain a turned-on state between the first node Q and the gate electrode of the seventh TFT T7. can do. The ninth TFT T9 may be implemented as a PMOS type LTPS TFT.

The ninth TFT (T9) is connected between the first node (Q) and the gate electrode (G) of the seventh TFT (T7), and is connected to the second driving voltage VGL supplied through the second power terminal PT2. It can always maintain the turn-on state. According to an example, the ninth TFT T9 includes a gate electrode electrically connected to the second power terminal PT2 , a first source/drain electrode electrically connected to the first node Q, and the seventh TFT T7 . A second source/drain electrode electrically connected to the gate electrode G may be included.

The ninth TFT T9 shortens the voltage polling time of the second output terminal OT2 by isolating the load between the first node Q and the gate electrode G of the seventh TFT T7. Through this, output characteristics and driving reliability for the scan signals NSS1 to NSSm-1 having negative pulses may be improved. For example, even if the gate voltage VG of the seventh TFT T7 is lowered to a voltage lower than the second driving voltage VGL by the above-described bootstrapping, the voltage of the first node Q is Regardless of the gate voltage VG of the TFT T7 , it may not be lower than a voltage obtained by subtracting the threshold voltage of the ninth TFT T9 from the second driving voltage VGL. Accordingly, the first, second, and fifth TFTs ( T1 , T2 , T5 ) connected to the first node ( Q ) by limiting the falling voltage of the first node ( Q ) by the ninth TFT ( T9 ), respectively may be implemented with a size having a relatively low withstand voltage, and as the size of each of the first, second, and fifth TFTs T1, T2, and T5 is reduced, the size of the scan driver SD may be reduced. .

On the other hand, each of the seventh TFT ( T7 ) and the eighth TFT ( T8 ) implemented in the output buffer circuit OBC of the scan driver SD according to the third example according to this example is a gate line of the light emitting display panel. Since a load is applied, the size of the seventh TFT ( T7 ) and the eighth TFT ( T8 ) shown in FIGS. 3 and 6 is relatively larger than that of each, and thus the size of the scan driver SD is increased. can do. However, since the gate driving circuit according to the present example outputs two scan signals from one scan driver SD, the number of scan drivers SD is reduced, and thus the gate driving circuit shown in FIG. 2 or FIG. 5 . It may have a smaller size.

As described above, in the scan driver SD according to the third example according to this example, the ninth TFT T9 always maintains a turn-on state based on the driving waveform shown in FIG. 7 , and the first output terminal OT1 ) may output the scan signals PSS1 to PSSm having a positive polarity pulse and simultaneously output the scan signals NSS1 to NSSm having a negative polarity pulse through the first output terminal OT1 . In the method of driving the scan driver SD according to the third example, the carry signal CS having a positive polarity pulse is generated in the driving method of the scan driver SD according to the second example described with reference to FIGS. 6 and 7 . Since they are substantially the same except that the scan signals PSS1 to PSSm having positive polarity pulses are output, a redundant description thereof will be omitted.

Additionally, in the scan driver SD according to the third example according to this example, the ninth TFT T9 is configured in addition to the first node control circuit NCC1 of the scan driver SD shown in FIG. 3 . can be

10 is a diagram illustrating a light emitting display device according to an example of the present specification.

Referring to FIG. 10 , the light emitting display device according to an example of the present specification may include a light emitting display panel 100 , a timing controller 300 , a data driving circuit unit 500 , and a gate driving circuit unit 700 .

The light emitting display panel 100 may include a display area AA (or an active area) defined on a substrate, and a non-display area IA (or a non-active area) surrounding the display area AA.

The display area AA may include a plurality of pixels P disposed in a pixel area defined by intersections of the first to mth gate line groups GLG1 to GLGm and the plurality of data lines DL1 to DLn. have.

Each of the first to mth gate line groups GLG1 to GLGm may include a plurality of gate lines arranged to be spaced apart from each other on the substrate. For example, each of the first to mth gate line groups GLG1 to GLGm may include a first gate line (or a first scan line), a second gate line (or a second scan line), and a third gate line (or a third gate line). 3 scan lines), and a fourth gate line (or emission line).

Each of the plurality of data lines DL1 to DLn may be disposed on the substrate to cross the first to mth gate line groups GLG1 to GLGm while being spaced apart from each other.

Each of the plurality of pixels P according to an example may be a red pixel, a green pixel, or a blue pixel. In this case, the adjacent red pixel, green pixel, and blue pixel may implement one unit pixel.

Each of the plurality of pixels P according to an example may be a red pixel, a green pixel, a blue pixel, or a white pixel. In this case, the adjacent red pixel, green pixel, blue pixel, and white pixel may implement one unit pixel for displaying one color image.

The plurality of pixels P may be implemented in a stripe structure or a pentile structure on the display area AA.

One unit pixel implemented in a pentile structure may include at least one red pixel, at least one green pixel, and at least one blue pixel arranged in a planar polygonal shape. For example, a unit pixel having a pentile structure may be arranged such that one red pixel, two green pixels, and one blue pixel have an octagonal shape in a plane, and in this case, the blue pixel has the largest size. and the green pixel may have the smallest size.

Each of the plurality of pixels P emits light based on the light emitting device, a plurality of gate signals supplied from the adjacent gate line groups GLG1 to GLGm, and data voltages supplied from the adjacent data lines DL1 to DLn. It may include a pixel circuit.

The pixel circuit may include a gate driving thin film transistor, a plurality of switching thin film transistors, and a storage capacitor. Some of the plurality of switching transistors may be turned on in response to a positive pulse of a scan signal supplied from the gate line groups GLG1 to GLGm, and the rest of the plurality of switching transistors may be scanned from the gate line groups GLG1 to GLGm. It can be turned on on a negative pulse of the signal.

The non-display area IA may be provided along an edge of the substrate to surround the display area AA. One non-display area of the non-display area IA may include a pad portion provided on the substrate and connected to the plurality of data lines DL1 to DLn.

The timing controller 300 aligns the input image data Idata to be suitable for driving the light emitting display panel 100 to generate digital data Pdata for each pixel, and generates data based on the input timing synchronization signal TSS. A control signal DCS may be generated and provided to the data driving circuit unit 500 .

The timing controller 300 may generate a gate control signal GCS including a gate start signal and a plurality of gate shift clocks based on the timing synchronization signal TSS and provide the generated gate control signal GCS to the gate driving circuit unit 700 .

The data driving circuit unit 500 may be connected to a plurality of data lines DL1 to DLn provided in the light emitting display panel 100 . The data driving circuit unit 500 according to an exemplary embodiment uses digital data Pdata for each pixel provided from the timing controller 300 and a data control signal DCS and a plurality of reference gamma voltages provided from the power supply unit to provide digital data for each pixel. The data Pdata may be converted into an analog data voltage for each pixel, and the converted data voltage for each pixel may be supplied to the corresponding data lines DL1 to DLn.

The gate driving circuit unit 700 may be disposed in the non-display area IA of the light emitting display panel 100 and may be electrically connected to the first to mth gate line groups GLG1 to GLGm. For example, the gate driving circuit unit 700 may be integrated on one edge or both edges of the substrate according to a manufacturing process of the thin film transistor and may be connected to the first to mth gate line groups GLG1 to GLGm one-to-one.

The gate driving circuit unit 700 may drive the first to mth gate line groups GLG1 to GLGm in a predetermined order based on the gate control signal GCS supplied from the timing controller 300 .

As an example, the gate driving circuit unit 700 is implemented in the left non-display area IA of the substrate and supplies the first to mth gate line groups GLG1 to GLGm in a predetermined order according to a single feeding method. can drive

As another example, the gate driving circuit unit 700 is implemented in the left and right non-display areas IA of the substrate, respectively, and the first to mth gate line groups GLG1 to GLG1 to m th gate line groups according to a double feeding method or a single feeding method. GLGm) can be driven in a predetermined order. For example, in the single feeding method, the gate driving circuit unit 700 implemented in the left non-display area IA of the substrate sequentially applies odd-numbered gate line groups among the first to m-th gate line groups GLG1 to GLGm. and the gate driving circuit unit 700 implemented in the right non-display area IA of the substrate may sequentially drive even-numbered gate line groups among the first to m-th gate line groups GLG1 to GLGm. have. In the double feeding method, the gate driving circuit unit 700 implemented in the left non-display area IA of the substrate and the gate driving circuit unit 700 implemented in the right non-display area IA of the substrate are first to m-th, respectively. Each of the gate line groups GLG1 to GLGm may be simultaneously and sequentially driven.

Additionally, the light emitting display device according to the present specification may further include a power circuit unit 900 .

Based on the input power Vin, the power circuit unit 900 includes a pixel driving voltage EVdd, a pixel common voltage EVss, an initialization voltage EVini, a first driving voltage VGH, and a second driving voltage VGL. ) may be generated and provided to the light emitting display panel 100 . For example, the power circuit unit 900 may supply the pixel driving voltage EVdd, the pixel common voltage EVss, and the initialization voltage EVini to the pixels P, respectively. In addition, the power circuit unit 900 may supply each of the first driving voltage VGH and the second driving voltage VGL to the gate driving circuit unit 700 .

11 is an equivalent circuit diagram according to an example of the pixel illustrated in FIG. 10 , and illustrates one pixel disposed on a k-th horizontal line of the light emitting display panel.

10 and 11 , a pixel P according to the present specification may include a light emitting device ELD and a pixel circuit PC.

The light emitting device ELD may emit white light or color light having a predetermined luminance by emitting light in proportion to the size of the data current idata supplied from the pixel circuit PC.

The light emitting device ELD according to an example includes a first electrode (or anode electrode) connected to the pixel circuit PC and a second electrode (or cathode electrode) connected to the pixel common power line Lvss (or a low potential power line). It may include a light emitting layer interposed therebetween. The light emitting layer may include an organic light emitting layer, a quantum dot light emitting layer, an inorganic light emitting layer, or a micro light emitting diode.

The pixel circuit PC emits a data current idata based on the data voltage Vdata supplied to the data line DL in response to a gate group driving signal applied to the gate line group GLGk from the gate driving circuit. By supplying to the element LED, light emission of the light emitting element LED can be controlled.

The gate line group GLGk may include first to fourth gate lines GL1 , GL2 , GL3 , and GL4 . The gate group driving signal includes the first scan signal SSk[1] (or the initialization control signal) supplied to the first gate line GL1 (or the first scan line), the second gate line GL2 (or the second scan line). The second scan signal SSk[2] (or scan control signal) supplied to the second scan signal SSk[2] (or scan control line) supplied to the scan line), the third gate line GL3 ( or the third scan signal SSk[3] (or anode reset control signal) supplied to the third scan line), and the fourth scan signal SSk supplied to the fourth gate line GL4 (or the emission line) [4]) (or an emission control signal).

The pixel circuit PC according to an example may include a driving TFT Tdr, first to sixth switching TFTs Tsw1 to Tsw6, and a storage capacitor Cst.

At least one of the driving TFT Tdr and the first to sixth switching TFTs Tsw1 to Tsw6 according to an example is an NMOS type that is turned on by a positive pulse of a scan signal supplied to a part of the gate line group GLGk It may be implemented as an oxide TFT, and the remaining TFTs may be implemented as a PMOS type LTPS TFT which is turned on by a negative pulse of a scan signal supplied to the rest of the gate line group GLGk. For example, each of the driving TFT (Tdr) and the third, fourth, and sixth switching TFTs (Tsw3, Tsw4, Tsw6) is implemented as a PMOS type LTPS TFT, and the first, second, and fifth switching TFTs ( Each of Tsw1, Tsw2, and Tsw5) may be implemented as an NMOS type oxide TFT.

The driving TFT Tdr may control the data current idata flowing through the light emitting device ELD. The driving TFT Tdr according to an example has a gate electrode connected to the first pixel node N1 , a first source/drain electrode connected to the second pixel node N2 , and a second connected to the third pixel node N3 . It may include source/drain electrodes. The driving TFT Tdr is turned on according to the voltage between the first pixel node N1 and the second pixel node N2 during the light emission period of the pixel P, and thus the data current idata flowing through the light emitting device ELD. ) can be controlled.

The first switching TFT Tsw1 may selectively connect the data line DL and the second pixel node N2 in response to the second scan signal SSk[2] supplied to the second gate line GL2. have. According to an example, the first switching TFT Tsw1 includes a gate electrode connected to the second gate line GL2 , a first source/drain electrode connected to the data line DL, and a second connected to the second pixel node N2 . It may include source/drain electrodes. The first switching TFT Tsw1 is turned by the positive pulse (or high voltage period) of the second scan signal SSk[2] supplied to the second gate line GL2 during the sampling period of the pixel P. By being turned on, the data voltage Vdata supplied to the data line DL may be supplied to the second pixel node N2 .

The second switching TFT Tsw2 selectively connects the first pixel node N1 and the third pixel node N3 in response to the second scan signal SSk[2] supplied to the second gate line GL2. can do it The second switching TFT Tsw2 according to an example has a gate electrode connected to the second gate line GL2 , a first source/drain electrode connected to the first pixel node N1 , and a third pixel node N3 connected to the second switching TFT Tsw2 . A second source/drain electrode may be included. This second switching TFT Tsw2 is turned by the positive pulse (or high voltage period) of the second scan signal SSk[2] supplied to the second gate line GL2 during the sampling period of the pixel P. By being turned on, the first pixel node N1 and the third pixel node N3 are electrically connected, and through this, the driving TFT Tdr is connected in the form of a diode.

The third switching TFT Tsw3 is connected to the pixel driving power line Lvdd (or high potential power line) and the second pixel node in response to the fourth scan signal SSk[4] supplied to the fourth gate line GL4. (N2) can be selectively connected. The third switching TFT Tsw3 according to an example has a gate electrode connected to the fourth gate line GL4 , a first source/drain electrode connected to the second pixel node N2 , and a pixel driving power line Lvdd connected to the third switching TFT Tsw3 . A second source/drain electrode may be included. This third switching TFT Tsw3 is turned by the negative pulse (or low voltage period) of the fourth scan signal SSk[4] supplied to the fourth gate line GL4 during the light emission period of the pixel P By being turned on, the pixel driving voltage EVdd supplied from the pixel driving power line Lvdd may be supplied to the first source/drain electrode of the driving TFT Tdr through the second pixel node N2.

The fourth switching TFT Tsw4 selectively connects the third pixel node N3 and the fourth pixel node N4 in response to the fourth scan signal SSk[4] supplied to the fourth gate line GL4. can do it The fourth switching TFT Tsw4 according to an example has a gate electrode connected to the fourth gate line GL4 , a first source/drain electrode connected to the third pixel node N3 , and a fourth pixel node N4 connected to the fourth switching TFT Tsw4 . A second source/drain electrode may be included. This fourth switching TFT Tsw4 is turned by the negative pulse (or low voltage period) of the fourth scan signal SSk[4] supplied to the fourth gate line GL4 during the light emission period of the pixel P. By being turned on, the data current Idata supplied from the driving TFT Tdr through the third pixel node N3 may be supplied to the first electrode of the light emitting device ELD through the fourth pixel node N4 .

The fifth switching TFT Tsw5 selectively connects the initialization power line Lvini and the first pixel node N1 in response to the first scan signal SSk[1] supplied to the first gate line GL1. can According to an example, the fifth switching TFT Tsw5 includes a gate electrode connected to the first gate line GL1 , a first source/drain electrode connected to the first pixel node N1 , and a first gate electrode connected to the initialization power line Lvini. Two source/drain electrodes may be included. The fifth switching TFT Tsw5 is turned by the positive pulse (or high voltage period) of the first scan signal SSk[1] supplied to the first gate line GL1 during the initialization period of the pixel P. By being turned on, the initialization power Vini supplied from the initialization power line Lvini may be supplied to the first pixel node N1 .

The sixth switching TFT Tsw6 selectively connects the initialization power line Lvini and the fourth pixel node N4 in response to the third scan signal SSk[3] supplied to the third gate line GL3. can According to an exemplary embodiment, the sixth switching TFT Tsw6 includes a gate electrode connected to the third gate line GL3 , a first source/drain electrode connected to the fourth pixel node N4 , and a first source/drain electrode connected to the initialization power line Lvini. Two source/drain electrodes may be included. This sixth switching TFT Tsw6 is turned by the negative pulse (or low voltage period) of the third scan signal SSk[3] supplied to the third gate line GL3 during the sampling period of the pixel P. By being turned on, the initialization power Vini supplied from the initialization power line Lvini is supplied to the fourth pixel node N4, and the voltage of the fourth pixel node N4 is discharged to the initialization power line Lvini through this. The voltage of the first electrode of the light emitting device ELD may be reset.

The storage capacitor Cst may be connected between the pixel driving power line Lvdd and the first pixel node N1 .

Alternatively, each of the second and fifth switching TFTs Tsw2 and Tsw5 connected to the first pixel node N1 may include a dual channel structure. That is, since each of the second and fifth switching TFTs Tsw2 and Tsw5 is electrically connected to the gate electrode of the driving TFT Tdr, it may be implemented in a dual-channel structure to keep the gate voltage of the driving TFT Tdr constant. can According to the dual-channel structure, since the channel length becomes longer than that of the single-gate structure, the off-resistance increases and the off-current decreases, thereby ensuring operation stability. For example, each of the second and fifth switching TFTs Tsw2 and Tsw5 is made of at least two thin film transistors connected in series to each other so as to be simultaneously turned on according to the corresponding scan signals SSk[1] and SSk[2]. can be implemented.

12 is a waveform diagram illustrating a signal supplied to the pixel illustrated in FIG. 11 .

11 and 12 , the pixel P according to an example of the present specification may be implemented to be driven in first to third operation periods t1, t2, and t3.

The first operation period t1 may be an initialization period for initializing the first pixel node N1 . For example, the first period t1 may be set to a time corresponding to one horizontal period.

The first scan signal SSk[1] supplied to the first gate line GL1 during the first operation period t1 has a high voltage level VH (or positive pulse), and the second gate line GL2 The second scan signal SSk[2] supplied to ) has a low voltage level VL, and the third scan signal SSk[3] supplied to the third gate line GL3 has a high voltage level VH. ), and the fourth scan signal SSk[4] supplied to the fourth gate line GL4 may have a high voltage level VH.

During the first operation period t1, only the fifth switching TFT Tsw5 among the first to sixth switching TFTs Tsw1 to Tsw6 is turned on by the first scan signal SSk[1] of the high voltage level VH. By being turned on, the voltage of the first pixel node N1 may be initialized to the initialization voltage EVini supplied from the initialization power line Lvini through the turned-on fifth switching TFT Tsw5. In addition, the storage capacitor Cst includes the pixel driving voltage EVdd supplied from the pixel driving power line Lvdd and the initialization voltage EVini supplied from the initialization power line Lvini through the turned-on fifth switching TFT Tsw5. ) may be initialized as the voltage difference between EVdd-Vini.

The second operation period t2 may be a sampling period following the first operation period t1 and storing the data voltage Vdata and the threshold voltage of the driving thin film transistor Tdr in the storage capacitor Cst. For example, the second operation period t2 may be set to a time corresponding to one horizontal period.

During the second operation period t2 , the first scan signal SSk[1] supplied to the first gate line GL1 has a low voltage level VL, and the first scan signal SSk[1] supplied to the second gate line GL2 The second scan signal SSk[2] has a high voltage level VH (or positive pulse), and the third scan signal SSk[3] supplied to the third gate line GL3 has a low voltage level ( VL) (or negative pulse), and the fourth scan signal SSk[4] supplied to the fourth gate line GL4 may maintain the high voltage level VH. That is, the fourth scan signal SSk[4] may maintain the high voltage level VH for two horizontal periods corresponding to the first operation period t1 and the second operation period t2.

During the second operation period t2 , the first and second switching TFTs Tsw1 and Tsw2 among the first to sixth switching TFTs Tsw1 to Tsw6 transmit the second scan signal SSk[2] of the high voltage level VH. ]), and at the same time, the sixth switching TFT Tsw6 is turned on by the third scan signal SSk[3] of the low voltage level VL. Accordingly, the voltage of the second pixel node N2 is changed to the data voltage Vdata supplied from the data line DL through the turned-on first switching TFT Tsw1, and the driving TFT Tdr is turned- As the gate electrode N1 and the second source/drain electrode N3 are electrically shorted by the on second switching TFT Tsw2, they are connected in a diode form, and thereby the gate electrode of the driving TFT Tdr and the first A voltage difference equal to the threshold voltage of the driving TFT Tdr may occur between the source/drain electrodes. In other words, the voltage level Vdata-Vth lower than the voltage level of the data voltage Vdata applied to the first source/drain electrode N2 of the driving TFT Tdr by the threshold voltage of the driving TFT Tdr (eg, Vdata-Vth) For example, the data voltage for which the threshold voltage is compensated) may be applied to the gate electrode N1 of the driving TFT Tdr, and the storage capacitor Cst may be the voltage Vdata applied to the gate electrode of the driving TFT Tdr. -Vth) may be maintained for a preset time.

And, during the second operation period t2, the voltage of the fourth pixel node N4 is initialized to the initialization voltage EVini supplied from the initialization power line Lvini through the turned-on sixth switching TFT Tsw6. can In other words, in the second period t2, the voltage of the fourth pixel node N4 or the voltage of the first electrode of the light emitting element ELD is applied to the initialization power line (Tsw6) through the turned-on sixth switching TFT Tsw6. Lvini) may be reset to the initialization voltage EVini.

The third operation period t3 may be a light emitting period following the second operation period t2 and causing the light emitting device ELD to emit light.

In the third operation period t3 , the first scan signal SSk[1] supplied to the first gate line GL1 maintains the low voltage level VL as it is and is supplied to the second gate line GL2. The second scan signal SSk[2] to be used has a low voltage level VL, and the third scan signal SSk[3] supplied to the third gate line GL3 has a high voltage level VH. , the fourth scan signal SSk[4] supplied to the fourth gate line GL4 may maintain the low voltage level VL.

During the third operation period t3, only the third and fourth switching TFTs Tsw3 and Tsw4 among the first to sixth switching TFTs Tsw1 to Tsw6 have the fourth scan signal SSk[4] at the low voltage level VL. ]) is turned on. Accordingly, the voltage of the second pixel node N2 is changed to the pixel driving voltage EVdd supplied from the pixel driving power line Lvdd through the turned-on third switching TFT Tsw3, and the first pixel node ( The voltage of N1) maintains the data voltage Vdata-Vth for which the threshold voltage of the driving TFT Tdr is compensated by the storage capacitor Cst, and the second source/drain electrode of the driving TFT Tdr is turned on. It may be connected to the first electrode of the light emitting device ELD through the fourth switching TFT Tsw4 .

Accordingly, during the third period t3, the driving TFT Tdr is a voltage EVdd-(Vdata-|Vth|) obtained by subtracting the threshold voltage Vth from the gate-source voltage EVdd-(Vdata-|Vth|). )-|Vth|) squared ((EVdd-(Vdata-|Vth|)-|Vth|)2) outputs a data current idata, and a data current idata output from the driving TFT Tdr ) may be supplied to the light emitting device ELD through the turned-on fourth switching TFT Tsw4 . As a result, during the third period t3 , the data current idata flowing through the light emitting device ELD is not affected by the threshold voltage of the driving TFT Tdr, so that the driving provided in each of the plurality of pixels P is A threshold voltage deviation between the TFTs Tdr may be minimized.

As described above, in the method of driving the pixel P according to an example of the present specification, the threshold voltage of the driving TFT Tdr may be compensated, and through this, a threshold between the driving TFTs Tdr provided in each of the plurality of pixels P may be compensated. It is possible to minimize the image quality degradation due to voltage deviation.

13 is a diagram illustrating a gate driving circuit unit according to the first example shown in FIG. 10 .

10, 11, and 13, the gate driving circuit unit 700 according to the first example of the present specification is dependently connected to each other and individually (GLG1 to GLGm) to each of the first to mth gate line groups (GLG1 to GLGm). Alternatively, it may include first to m-th stage blocks 7101 to 710m connected in a one-to-one manner. For example, each of the first to mth stage blocks 7101 to 710m may be expressed as a scan driver block or a scan driver group.

The first stage block 7101 may receive the gate start signal GVst provided from the timing controller 300 . Each of the second to m-th stage blocks 7102 to 710m may receive the gate start signal GVst for the carry signal CS output from each of the first to m-1 th stage blocks 7101 to 710m-1, respectively. have.

Each of the first to mth stage blocks 7101 to 710m may receive a corresponding gate shift clock from among the plurality of gate shift clocks GCLK provided from the timing controller 300 . Each of the first to mth stage blocks 7101 to 710m may commonly receive the first driving voltage VGH and the second driving voltage VGL provided from the power circuit unit 900 .

Each of the first to m-th stage blocks 7101 to 710m according to an example includes a first stage circuit SD1[1] to SDm[1], a second stage circuit SD1[2] to SDm[2], third stage circuits SD1[3] to SDm[3], and fourth stage circuits SD1[4] to SDm[4].

The first stage circuits SD1[1] to SDm[1] may be electrically connected to the first gate line GL1 of each of the first to mth gate line groups GLG1 to GLGm. The first stage circuits SD1[1] to SDm[1] have a first scan with positive pulses based on one gate start signal GVst and three gate shift clocks provided from the timing controller 300 . Signals SS1[1] to SSm[1] may be output.

The first stage circuits SD1[1] to SDm[1] of each of the first to m-th stage blocks 7101 to 710m according to an example are the first to m-th gate line groups GLG1 to GLGm, respectively. A first output terminal electrically connected to the first gate line GL1 and outputting the first scan signals SS1[1] to SSm[1] having a positive pulse, and a negative pulse synchronized with the positive pulse It may include a second output terminal for outputting a carry signal having a carry signal to the next stage block. The first stage circuits SD1[1] to SDm[1] of each of the first to mth stage blocks 7101 to 710m have substantially the same configuration as the scan driver SD shown in FIG. 3 or FIG. 6 . Therefore, a redundant description thereof will be omitted.

In the gate driving circuit unit 700 according to the present example, the first stage circuits SD1[1] to SDm[1] of each of the first to m-th stage blocks 7101 to 710m cascadingly connected to each other are shown in FIGS. The gate driving circuit according to the first example of the present specification shown in 4 or the gate driving circuit according to the second example of the present specification shown in FIGS. 5 to 7 may have substantially the same configuration. For example, the first stage circuits SD1[1] to SDm[1] of each of the first to mth stage blocks 7101 to 710m according to the first example of the present specification shown in FIGS. When configured the same as the gate driving circuit or the gate driving circuit according to the second example of the present specification shown in FIGS. 5 to 7 , the first output terminal OT1 shown in FIGS. 3 or 6 is the first to mth Each of the gate line groups GLG1 to GLGm may be electrically connected to the first gate line GL1 .

The second stage circuits SD1[2] to SDm[2] may be electrically connected to the second gate line GL2 of each of the first to mth gate line groups GLG1 to GLGm. The second stage circuits SD1[2] to SDm[2] have a second scan having a positive polarity pulse based on one gate start signal GVst and three gate shift clocks provided from the timing controller 300 . Signals SS1[2] to SSm[2] may be output.

The second stage circuits SD1[2] to SDm[2] of each of the first to mth stage blocks 7101 to 710m according to an example may include the first to mth gate line groups GLG1 to GLGm, respectively. 2 A first output terminal electrically connected to the gate line GL2 and outputting second scan signals SS1[2] to SSm[2] having a positive pulse, and a negative pulse synchronized with the positive pulse It may include a second output terminal for outputting a carry signal having a carry signal to the next stage block. The second stage circuits SD1[2] to SDm[2] of each of the first to mth stage blocks 7101 to 710m have substantially the same configuration as the scan driver SD shown in FIG. 3 or FIG. 6 . Therefore, a redundant description thereof will be omitted.

In the gate driving circuit unit 700 according to the present example, the second stage circuits SD1[2] to SDm[2] of each of the first to mth stage blocks 7101 to 710m cascadingly connected to each other are shown in FIGS. The gate driving circuit according to the first example of the present specification shown in 4 or the gate driving circuit according to the second example of the present specification shown in FIGS. 5 to 7 may have substantially the same configuration. For example, the second stage circuits SD1[2] to SDm[2] of each of the first to mth stage blocks 7101 to 710m according to the first example of the present specification shown in FIGS. When configured the same as the gate driving circuit or the gate driving circuit according to the second example of the present specification shown in FIGS. 5 to 7 , the first output terminal OT1 shown in FIGS. 3 or 6 is the first to mth Each of the gate line groups GLG1 to GLGm may be electrically connected to the second gate line GL2 .

The third stage circuits SD1[3] to SDm[3] may be electrically connected to the third gate line GL3 of each of the first to mth gate line groups GLG1 to GLGm. The third stage circuits SD1[3] to SDm[3] have a third scan having a negative polarity pulse based on one gate start signal GVst and two gate shift clocks provided from the timing controller 300 . Signals SS1[3] to SSm[3] may be output. Accordingly, the third stage circuits SD1[3] to SDm[3] of each of the first to mth stage blocks 7101 to 710m according to an example may include the first to mth gate line groups GLG1 to GLGm. The third scan signals SS1[3] to SSm[3] having a negative polarity pulse may be supplied to each of the third gate lines GL3 .

The third stage circuits SD1[3] to SDm[3] of each of the first to mth stage blocks 7101 to 710m according to an example are substantially identical to the scan driver SD of the gate driving circuit shown in FIG. can have the same configuration. That is, the third stage circuits SD1[3] to SDm[3] perform a third scan with negative pulses based on the gate start signal GVst and the first and second gate shift clocks GCLK1 and GCLK2. The signals SS1[3] to SSm[3] may be supplied to the third gate line GL3 of each of the first to mth gate line groups GLG1 to GLGm.

In the third stage circuits SD1[3] to SDm[3] according to an example, in the scan driver SD shown in FIG. 3, 6, or 9, the sixth TFT T6 is removed and the second It may be implemented to output the third scan signals SS1[3] to SSm[3] through the output terminal OT2. At this time, the third scan output through the second output terminal OT2 from the third stage circuits SD1[3] to SDm[3] of the first to m-1th stage blocks 7101 to 710m-1, respectively. Signals SS1[3] to SSm-1[3] are to be supplied as gate start signals to the third stage circuits SD1[3] to SDm[3] of the second to mth stage blocks 7102 to 710m. can

The third stage circuits SD1[3] to SDm[3] according to another example output the third scan signals SS1[3] to SSm-1[3] shown in FIG. 12, which is a light emitting display Since the device has substantially the same configuration as a scan driver already known in the art, a description thereof will be omitted.

The fourth stage circuits SD1[4] to SDm[4] may be electrically connected to the fourth gate line GL4 of each of the first to mth gate line groups GLG1 to GLGm. The fourth stage circuits SD1[4] to SDm[4] according to an example include one gate start signal GVst and two gate shift clocks (or emission shift clocks) provided from the timing controller 300 . Based on the positive polarity pulse, the fourth scan signals SS1[4] to SSm[4] may be output. Accordingly, the fourth stage circuits SD1[4] to SDm[4] of each of the first to m-th stage blocks 7101 to 710m are connected to the fourth stage circuits SD1[4] to SDm[4] of the first to m-th gate line groups GLG1 to GLGm, respectively. The fourth scan signals SS1[4] to SSm[4] having a positive polarity pulse may be supplied to the gate line GL4 .

The fourth stage circuits SD1[4] to SDm[4] of each of the first to mth stage blocks 7101 to 710m according to an example are shown in FIG. 1 except for output with positive pulses. It may have substantially the same configuration as the scan driver SD of the gate driving circuit. That is, the fourth stage circuits SD1[4] to SDm[4] generate the fourth scan signal SS1[ having a positive polarity pulse based on the gate start signal GVst and the first and second emission shift clocks. 4] to SSm[4]) may be supplied to the fourth gate line GL4 of each of the first to mth gate line groups GLG1 to GLGm.

In the fourth stage circuits SD1[4] to SDm[4] according to an example, in the scan driver SD shown in FIG. 3, 6, or 9, the sixth TFT T6 is removed and the second It may be implemented to output the fourth scan signals SS1[4] to SSm[4] through the output terminal OT2. At this time, the fourth scan output through the second output terminal OT2 in the fourth stage circuits SD1[4] to SDm[4] of the first to m-1th stage blocks 7101 to 710m-1, respectively. Signals SS1[4] to SSm-1[4] are to be supplied to the fourth stage circuits SD1[4] to SDm[4] of the second to m-th stage blocks 7102 to 710m as gate start signals. can

The fourth stage circuits SD1[4] to SDm[4] according to another example output the fourth scan signals SS1[4] to SSm[4] or the emission control signal shown in FIG. 12, Since it has substantially the same configuration as a light emission control driver (or an emission driver) already known in the art of a light emitting display device, a description thereof will be omitted.

As such, the gate driving circuit unit 700 according to the first example of the present specification includes the first stage circuits SD1[1] to SDm[1] and the second stage circuits SD1[1] to SDm[1] of the first to m-th stage blocks 7101 to 710m, respectively. Each of the stage circuits SD1[2] to SDm[2] outputs a scan signal having a positive polarity pulse without the inverter driver shown in Fig. 1, so that the size (or width) is increased due to deletion (or removal) of the inverter driver. is reduced, for example, the size may be reduced by the size occupied by the inverter driver.

14 is a diagram illustrating a gate driving circuit unit according to the second example shown in FIG. 10 .

10, 11, and 14, the gate driving circuit unit 700 according to the second example of the present specification is connected to each other dependently and is individually (GLG1 to GLGm) to each of the first to mth gate line groups (GLG1 to GLGm). Alternatively, it may include first to m-th stage blocks 7101 to 710m connected in a one-to-one manner. For example, each of the first to mth stage blocks 7101 to 710m may be expressed as a scan driver block or a scan driver group.

The first stage block 7101 may receive the gate start signal GVst provided from the timing controller 300 . Each of the second to m-th stage blocks 7102 to 710m may receive the gate start signal GVst for the carry signal CS output from each of the first to m-1 th stage blocks 7101 to 710m-1, respectively. have.

Each of the first to mth stage blocks 7101 to 710m may receive a corresponding gate shift clock from among the plurality of gate shift clocks GCLK provided from the timing controller 300 . Each of the first to mth stage blocks 7101 to 710m may commonly receive the first driving voltage VGH and the second driving voltage VGL provided from the power circuit unit 900 .

Each of the first to m-th stage blocks 7101 to 710m according to an example includes a first stage circuit SD1[1] to SDm[1], a second stage circuit SD1[2] to SDm[2], and third stage circuits SD1[3] to SDm[3].

The first stage circuits SD1[1] to SDm[1] may be electrically connected to the first gate line GL1 of each of the first to mth gate line groups GLG1 to GLGm. The first stage circuits SD1[1] to SDm[1] have a first scan with positive pulses based on one gate start signal GVst and three gate shift clocks provided from the timing controller 300 . Signals SS1[1] to SSm[1] may be output.

The first stage circuits SD1[1] to SDm[1] of each of the first to m-th stage blocks 7101 to 710m according to an example are the first to m-th gate line groups GLG1 to GLGm, respectively. A first output terminal electrically connected to the first gate line GL1 and outputting the first scan signals SS1[1] to SSm[1] having a positive pulse, and a negative pulse synchronized with the positive pulse It may include a second output terminal for outputting a carry signal having a carry signal to the next stage block. The first stage circuits SD1[1] to SDm[1] of each of the first to mth stage blocks 7101 to 710m have substantially the same configuration as the scan driver SD shown in FIG. 3 or FIG. 6 . Therefore, a redundant description thereof will be omitted.

In the gate driving circuit unit 700 according to the present example, the first stage circuits SD1[1] to SDm[1] of each of the first to m-th stage blocks 7101 to 710m cascadingly connected to each other are shown in FIGS. The gate driving circuit according to the first example of the present specification shown in 4 or the gate driving circuit according to the second example of the present specification shown in FIGS. 5 to 7 may have substantially the same configuration. For example, the first stage circuits SD1[1] to SDm[1] of each of the first to mth stage blocks 7101 to 710m according to the first example of the present specification shown in FIGS. When configured the same as the gate driving circuit or the gate driving circuit according to the second example of the present specification shown in FIGS. 5 to 7 , the first output terminal OT1 shown in FIGS. 3 or 6 is the first to mth Each of the gate line groups GLG1 to GLGm may be electrically connected to the first gate line GL1 .

The second stage circuits SD1[2] to SDm[2] are electrically connected to the second gate line GL2 and the third gate line GL3 of each of the first to mth gate line groups GLG1 to GLGm, respectively. can be connected The second stage circuits SD1[2] to SDm[2] according to an example generate positive pulses based on one gate start signal GVst and three gate shift clocks provided from the timing controller 300 . The second scan signals SS1[2] to SSm[2] and the third scan signals SS1[3] to SSm[3] having negative pulses may be simultaneously output.

The second stage circuits SD1[2] to SDm[2] of each of the first to mth stage blocks 7101 to 710m according to an example may include the first to mth gate line groups GLG1 to GLGm, respectively. A first output terminal electrically connected to the second gate line GL2 and outputting the second scan signals SS1[2] to SSm[2] having positive pulses, and the first to mth gate line groups GLG1 to GLGm) a second output terminal electrically connected to each of the third gate lines GL3 and outputting third scan signals SS1[3] to SSm[3] having negative pulses synchronized with the positive pulses In this case, the third scan signals SS1[3] to SSm[3] may be supplied to the next stage block as a carry signal. The second stage circuits SD1[2] to SDm[2] of each of the first to mth stage blocks 7101 to 710m have substantially the same configuration as the scan driver SD shown in FIGS. 8 and 9 . Therefore, a redundant description thereof will be omitted.

In the gate driving circuit unit 700 according to the present example, the second stage circuits SD1[2] to SDm[2] of each of the first to m-th stage blocks 7101 to 710m cascadingly connected to each other are shown in FIGS. 8 and FIG. 9 may have substantially the same configuration as the gate driving circuit according to the third example of the present specification. For example, the second stage circuits SD1[2] to SDm[2] of each of the first to mth stage blocks 7101 to 710m are shown in FIGS. 8 and 9 according to the third example of the present specification. When configured the same as the gate driving circuit, the first output terminal OT1 shown in FIG. 9 may be electrically connected to the second gate line GL2 of each of the first to m-th gate line groups GLG1 to GLGm, and , the second output terminal OT2 illustrated in FIG. 9 may be electrically connected to the third gate line GL3 of each of the first to mth gate line groups GLG1 to GLGm.

The third stage circuits SD1[3] to SDm[3] may be electrically connected to the fourth gate line GL4 of each of the first to mth gate line groups GLG1 to GLGm. The third stage circuits SD1[3] to SDm[3] according to an example include one gate start signal GVst and two gate shift clocks (or emission shift clocks) provided from the timing controller 300 . Based on the positive polarity pulse, the fourth scan signals SS1[4] to SSm[4] may be output. Accordingly, each of the first to m-th stage blocks 7101 to 710m is the third stage circuit SD1[3] to SDm[3], and the fourth to fourth stage circuits SD1[3] to SDm[3] of the first to mth gate line groups GLG1 to GLGm, respectively. The fourth scan signals SS1[4] to SSm[4] having positive pulses may be sequentially supplied to the gate line GL4.

The third stage circuits SD1[3] to SDm[3] of each of the first to mth stage blocks 7101 to 710m according to an example are shown in FIG. 1 except for output with positive pulses. It may have substantially the same configuration as the scan driver SD of the gate driving circuit. That is, the third stage circuits SD1[3] to SDm[3] generate the fourth scan signal SS1[ having a positive polarity pulse based on the gate start signal GVst and the first and second emission shift clocks. 4] to SSm[4]) may be supplied to the fourth gate line GL4 of each of the first to mth gate line groups GLG1 to GLGm.

In the third stage circuits SD1[3] to SDm[3] according to an example, in the scan driver SD shown in FIG. 3, 6, or 9, the sixth TFT T6 is removed and the second It may be implemented to output the fourth scan signals SS1[4] to SSm[4] through the output terminal OT2. At this time, the fourth scan output through the second output terminal OT2 in the third stage circuits SD1[3] to SDm[3] of the first to m-1th stage blocks 7101 to 710m-1, respectively. The signals SS1[4] to SSm-1[4] are to be supplied to the third stage circuits SD2[3] to SDm[3] of the second to mth stage blocks 7102 to 710m as gate start signals. can

The third stage circuits SD1[3] to SDm[3] according to an example output the fourth scan signals SS1[4] to SSm-1[4] or the emission control signal shown in FIG. 12 . As such, it has substantially the same configuration as a light emission control driver (or an emission driver) known in the art of a light emitting display device, and thus a description thereof will be omitted.

As described above, the gate driving circuit unit 700 according to the second example of the present specification has the same effect as the gate driving circuit unit shown in FIG. 13 , and the second stage of each of the first to mth stage blocks 7101 to 710m In the circuits SD1[2] to SDm[2], the second scan signals SS1[2] to SSm[2] having positive pulses and the third scan signals SS1[3] to SSm having negative pulses By simultaneously outputting [3]), the size (or width) can be further reduced as one stage circuit is deleted compared to the gate driving circuit shown in FIG. 13 .

15 is a waveform diagram illustrating an output waveform of a carry signal according to the size (or channel width) of the seventh TFT in the scan driver shown in FIG. 3 . In the scan driver shown in FIG. 3 , the fifth TFT (T5) FIG. Simulation waveform diagram to check whether the carry signal is normally output when the size of the 7th TFT (T7) is 160um and 20um, based on the size of 80um and the size of the 6th TFT (T6) is 40um to be. In FIG. 15, the waveform of the dotted line represents the scan signal SS output through the first output terminal of the scan driver shown in FIG. 3, and the waveform of the dashed line is the seventh TFT (T7) of the scan driver shown in FIG. ) represents the carry signal CS outputted through the second output terminal when the size of ) is 160um, and the waveform of the solid line is the second output when the size of the 7th TFT (T7) of the scan driver shown in FIG. 3 is 20um. Indicates the carry signal CS output through the terminal.

As can be seen from FIGS. 3 and 15 , in the scan driver according to the present specification, the load for the gate line disposed on the panel is not applied to the seventh TFT (T7), so the size of the fifth TFT (T5) is 80um, It can be checked whether the carry signal is normally output even when the size of the seventh TFT T7 is decreased from 160 um to 20 um based on when the size of the TFT T6 is 40 um.

Accordingly, the scan driver according to the present specification outputs the scan signal SS through the first output terminal OT1 directly connected to the second node QB, thereby generating the seventh TFT ( The size of T7) can be reduced to 20 μm, which can reduce the overall size.

The gate driving circuit according to the present specification may be described as follows.

The gate driving circuit according to some of the present specification includes first to m-th scan drivers cascaded to each other, and each of the first to m-th scan drivers includes a first output terminal for outputting a signal having a positive polarity pulse, and and a second output terminal for outputting a signal having a negative pulse synchronized with the positive pulse.

According to some of the present specification, each of the first to mth scan drivers outputs a signal having a positive pulse through a first output terminal to the outside as a scan signal, and carries a signal having a positive pulse through a second output terminal As a signal, it can be output to the next stage scan driver.

According to some of the present specification, any one of the first to mth scan drivers may include: a first node; a second node directly coupled to the first output terminal; a first node control circuit implemented to control a voltage of the first node in response to a voltage of each of the first input terminal, the second input terminal, the third input terminal, and the first power supply terminal; a second node control circuit implemented to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and an output buffer circuit configured to supply the voltage of the second input terminal or the voltage of the first power terminal to the second output terminal in response to the voltage of the first node and the voltage of the second node.

According to some of the present specification, the first input terminal receives the gate start signal or the carry signal, the second input terminal receives the first gate shift clock, and the third input terminal receives the first gate shift clock and inverted form. , and the fourth input terminal may receive a third gate shift clock having a shape different from that of the first and second gate shift clocks.

According to some of the present specification, each of the first and second gate shift clocks includes a high voltage level and a low voltage level that are cyclically repeated in units of one horizontal period, and the third gate shift clock is cyclically repeated in units of two horizontal periods. It includes a high voltage level and a low voltage level, and the high voltage level of the first gate shift clock and the high voltage level of the second gate shift clock may overlap the high voltage level of the third gate shift clock.

According to some of the present specification, each of the first to mth scan drivers outputs a signal having a positive pulse through a first output terminal to the outside as a first scan signal, and having a negative pulse through a second output terminal The signal is output as a second scan signal to the outside, and the second scan signal may be supplied to the next stage scan driver as a carry signal.

According to some of the present specification, any one of the first to mth scan drivers may include: a first node; a second node directly coupled to the first output terminal; a first node control circuit implemented to control a voltage of the first node in response to a voltage of each of the first input terminal, the second input terminal, the third input terminal, and the first power supply terminal; a second node control circuit implemented to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and an output buffer circuit configured to supply the voltage of the second input terminal or the voltage of the first power terminal to the second output terminal in response to the voltage of the first node and the voltage of the second node.

According to some of the present specification, the first input terminal receives the gate start signal or the carry signal, the second input terminal receives the first gate shift clock, and the third input terminal receives the first gate shift clock and inverted form. , and the fourth input terminal may receive a third gate shift clock having the same shape as the second gate shift clock.

According to some of the present specification, each of the first and second gate shift clocks may include a high voltage level and a low voltage level that are cyclically repeated in units of one horizontal period.

According to some of the present specification, the first node control circuit includes first to third thin film transistors, wherein the first thin film transistor selectively selects the first input terminal and the first node in response to a voltage supplied to the third input terminal. and the second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal, and the third thin film transistor is connected in series with the second thin film transistor, and the second The second thin film transistor and the first power terminal may be selectively connected in response to the voltage of the node.

According to some of the present specification, the second node control circuit is a fourth thin film transistor selectively connecting the second power supply terminal and the second node in response to the voltage supplied to the third input terminal, and in response to the voltage of the first node. a fifth thin film transistor selectively connecting the third input terminal and the second node, and a sixth thin film transistor selectively connecting the second power terminal and the second node in response to a voltage supplied to the fourth input terminal can

According to some of the present specification, the output buffer circuit includes a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node, the first power terminal in response to the voltage of the second node and an eighth thin film transistor selectively connecting the to the second output terminal, and a capacitor connected between the first node and the second output terminal.

According to some of the present specification, the output buffer circuit may further include an auxiliary capacitor connected between the second node and the first power terminal.

According to some of the present specification, the output buffer circuit includes a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node, the first power terminal in response to the voltage of the second node and an eighth thin film transistor selectively connecting the to the second output terminal, a capacitor connected between the first node and the second output terminal, and an auxiliary capacitor connected between the second node and the first power terminal.

According to some of the present specification, the first node control circuit includes first to third thin film transistors, and a ninth thin film transistor, wherein the first thin film transistor is responsive to a voltage supplied to the third input terminal at the first input terminal. to selectively connect the first node, the second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal, and the third thin film transistor comprises the second thin film transistor and the second thin film transistor connected in series, selectively connecting the second thin film transistor and the first power terminal in response to the voltage of the second node, the ninth thin film transistor being connected between the first node and the gate electrode of the seventh thin film transistor, The turn-on state can be always maintained by the voltage supplied to the power terminal.

A light emitting display device according to some of the present specification provides a light emitting display panel including pixels disposed in a pixel area defined by a plurality of data lines and first to m-th gate line groups, and a data voltage is supplied to each of the plurality of data lines. a data driving circuit unit comprising: a data driving circuit unit; and a gate driving circuit unit having first to m-th stage blocks disposed on the light emitting display panel and connected to each of the first to m-th gate line groups, wherein each of the first to m-th stage blocks includes a first a first stage circuit connected to a first gate line of each of the to mth gate line groups, wherein the first stage circuit of each of the first to mth stage blocks is a first gate line of each of the first to mth gate line groups a first output terminal electrically connected to and outputting a first scan signal having a positive polarity pulse, and a second output terminal outputting a carry signal having a negative polarity pulse synchronized with the positive polarity pulse to the next stage block; can do.

According to some of the present specification, any one of the first stage circuits of each of the first to mth stage blocks includes a first node; a second node directly coupled to the first output terminal; a first node control circuit implemented to control a voltage of the first node in response to voltages of each of the first input terminal, the second input terminal, the third input terminal, and the first power supply terminal; a second node control circuit implemented to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and an output buffer circuit configured to supply the voltage of the second input terminal or the voltage of the first power terminal to the second output terminal in response to the voltage of the first node and the voltage of the second node.

According to some of the present specification, the first input terminal receives the gate start signal or the carry signal, the second input terminal receives the first gate shift clock, and the third input terminal receives the first gate shift clock and inverted form. , and the fourth input terminal may receive a third gate shift clock having a shape different from that of the first and second gate shift clocks.

According to some of the present specification, each of the first to mth stage blocks further includes a second stage circuit connected to each of the second gate line and the third gate line of each of the first to mth gate line groups, The second stage circuit of each of the m-th stage blocks includes a first output terminal electrically connected to a second gate line of each of the first to m-th gate line groups and outputting a second scan signal having a positive polarity pulse, and a first to a second output terminal electrically connected to the third gate line of each of the mth gate line groups and outputting a third scan signal having a negative polarity pulse, the third scan signal being a carry signal to the next stage block can be supplied.

According to some of the present specification, each of the pixels includes a light emitting element and a pixel circuit for controlling light emission of the light emitting element, wherein the pixel circuit turns on a positive pulse of a first scan signal and a positive pulse of a second scan signal It may include a plurality of N-type oxide thin film transistors that are turned on, and a plurality of P-type LTPS thin film transistors that are turned on by a negative pulse of the third scan signal.

According to some of the present specification, any one of the second stage circuits of each of the first to mth stage blocks includes: a first node; a second node directly coupled to the first output terminal; a first node control circuit implemented to control a voltage of the first node in response to a voltage of each of the first input terminal, the second input terminal, the third input terminal, and the first power supply terminal; a second node control circuit implemented to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and an output buffer circuit configured to supply the voltage of the second input terminal or the voltage of the first power terminal to the second output terminal in response to the voltage of the first node and the voltage of the second node.

According to some of the present specification, the first input terminal receives the gate start signal or the carry signal, the second input terminal receives the first gate shift clock, and the third input terminal receives the first gate shift clock and inverted form. , and the fourth input terminal may receive a third gate shift clock having the same shape as the second gate shift clock.

According to some of the present specification, the first node control circuit includes first to third thin film transistors, wherein the first thin film transistor selectively selects the first input terminal and the first node in response to a voltage supplied to the third input terminal. and the second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal, and the third thin film transistor is connected in series with the second thin film transistor, and the second The second thin film transistor and the first power terminal may be selectively connected in response to the voltage of the node.

According to some of the present specification, the second node control circuit is a fourth thin film transistor selectively connecting the second power supply terminal and the second node in response to the voltage supplied to the third input terminal, and in response to the voltage of the first node. a fifth thin film transistor selectively connecting the third input terminal and the second node, and a sixth thin film transistor selectively connecting the second power terminal and the second node in response to a voltage supplied to the fourth input terminal can

According to some of the present specification, the output buffer circuit includes a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node, the first power terminal in response to the voltage of the second node and an eighth thin film transistor selectively connecting the to the second output terminal, and a capacitor connected between the first node and the second output terminal.

According to some of the present specification, the output buffer circuit includes a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node, the first power terminal in response to the voltage of the second node and an eighth thin film transistor selectively connecting the to the second output terminal, a capacitor connected between the first node and the second output terminal, and an auxiliary capacitor connected between the second node and the first power terminal.

According to some of the present specification, the first node control circuit includes first to third thin film transistors, and a ninth thin film transistor, wherein the first thin film transistor is responsive to a voltage supplied to the third input terminal at the first input terminal. to selectively connect the first node, the second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal, and the third thin film transistor comprises the second thin film transistor and the second thin film transistor connected in series, selectively connecting the second thin film transistor and the first power terminal in response to the voltage of the second node, the ninth thin film transistor being connected between the first node and the gate electrode of the seventh thin film transistor, The turn-on state can be always maintained by the voltage supplied to the power terminal.

The gate driving circuit and the light emitting display device including the same according to the present specification may be applied to all electronic devices including the light emitting display panel and the gate driving circuit unit built in the light emitting display panel. For example, the gate driving circuit and the light emitting display device including the same according to the present specification may include a mobile device, a video phone, a smart watch, a watch phone, a wearable device, and a foldable device ( foldable device, rollable device, bendable device, flexible device, curved device, electronic notebook, e-book, PMP (portable multimedia player), PDA ( personal digital assistant, MP3 player, mobile medical device, desktop PC, laptop PC, netbook computer, workstation, navigation, car navigation system, car display device, television, It may be applied to a wall paper display device, a signage device, a game device, a notebook computer, a monitor, a camera, a camcorder, and a home appliance.

Features, structures, effects, etc. described in various examples of the present specification are included in at least one example of the present specification, and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. illustrated in at least one example of the present specification can be combined or modified with respect to other examples by those of ordinary skill in the art to which the technical idea of the present specification pertains. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the technical scope or scope of the present specification.

The present specification described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which this specification belongs that various substitutions, modifications, and changes are possible without departing from the technical spirit of the present specification. It will be clear to those who have the knowledge of Therefore, the scope of the present specification is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present specification.

100: light emitting display panel 300: timing control unit
500: data driving circuit unit 700: gate driving circuit unit
900: power circuit unit 7101 to 710m: stage block
NCC1: first node control circuit NCC2: second node control circuit
OBC: output buffer circuit P: pixel
PC: Pixel circuit SD1 to SDm: Scan driver
SD1[1] to SDm[1]: first stage circuit SD1[2] to SDm[2]: second stage circuit
SD1[3] to SDm[3]: Third stage circuit SD1[4] to SDm[4]: Second stage circuit

Claims (27)

It includes first to mth scan drivers dependently connected to each other,
Each of the first to mth scan drivers,
a first output terminal for outputting a signal having a positive polarity pulse; and
and a second output terminal for outputting a signal having a negative polarity pulse synchronized with the positive polarity pulse. The method of claim 1,
Each of the first to mth scan drivers,
outputting the signal having the positive polarity pulse to the outside as a scan signal through the first output terminal,
and outputting the signal having the positive pulse to the next stage scan driver as a carry signal through the second output terminal. 3. The method of claim 2,
Any one of the first to mth scan drivers,
first node;
a second node directly coupled to the first output terminal;
a first node control circuit implemented to control a voltage of the first node in response to a voltage of each of a first input terminal, a second input terminal, a third input terminal, and a first power supply terminal;
a second node control circuit configured to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and
and an output buffer circuit configured to supply a voltage of the second input terminal or a voltage of the first power supply terminal to the second output terminal corresponding to the voltage of the first node and the voltage of the second node. drive circuit. 4. The method of claim 3,
The first input terminal receives the gate start signal or the carry signal,
The second input terminal receives a first gate shift clock,
The third input terminal receives a second gate shift clock having an inverted form of the first gate shift clock,
and the fourth input terminal receives a third gate shift clock having a shape different from that of the first and second gate shift clocks. 5. The method of claim 4,
Each of the first and second gate shift clocks includes a high voltage level and a low voltage level that are cyclically repeated in units of one horizontal period,
The third gate shift clock includes a high voltage level and a low voltage level that are cyclically repeated in units of two horizontal periods,
The high voltage level of the first gate shift clock and the high voltage level of the second gate shift clock overlap the high voltage level of the third gate shift clock. The method of claim 1,
Each of the first to mth scan drivers,
outputting the signal having the positive polarity pulse to the outside as a first scan signal through the first output terminal,
outputting the signal having the negative polarity pulse to the outside as a second scan signal through the second output terminal,
and the second scan signal is supplied to a next stage scan driver as a carry signal. 7. The method of claim 6,
Any one of the first to mth scan drivers,
first node;
a second node directly coupled to the first output terminal;
a first node control circuit implemented to control a voltage of the first node in response to a voltage of each of a first input terminal, a second input terminal, a third input terminal, and a first power supply terminal;
a second node control circuit configured to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and
and an output buffer circuit configured to supply a voltage of the second input terminal or a voltage of the first power supply terminal to the second output terminal corresponding to the voltage of the first node and the voltage of the second node. drive circuit. 8. The method of claim 7,
The first input terminal receives the gate start signal or the carry signal,
The second input terminal receives a first gate shift clock,
The third input terminal receives a second gate shift clock having an inverted form of the first gate shift clock,
and the fourth input terminal receives a third gate shift clock having the same shape as the second gate shift clock. 9. The method of claim 8,
and each of the first and second gate shift clocks includes a high voltage level and a low voltage level that are cyclically repeated in units of one horizontal period. 10. The method according to any one of claims 3 to 5 and 7 to 9,
The first node control circuit includes first to third thin film transistors,
The first thin film transistor selectively connects the first input terminal and the first node in response to a voltage supplied to the third input terminal,
The second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal,
The third thin film transistor is connected in series with the second thin film transistor and selectively connects the second thin film transistor and the first power terminal in response to a voltage of the second node. 10. The method according to any one of claims 3 to 5 and 7 to 9,
The second node control circuit,
a fourth thin film transistor selectively connecting the second power terminal and the second node in response to a voltage supplied to the third input terminal;
a fifth thin film transistor selectively connecting the third input terminal and the second node in response to the voltage of the first node; and
and a sixth thin film transistor selectively connecting the second power terminal and the second node in response to a voltage supplied to the fourth input terminal. 6. The method according to any one of claims 3 to 5,
The output buffer circuit is
a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node;
an eighth thin film transistor selectively connecting the first power terminal and the second output terminal in response to the voltage of the second node; and
and a capacitor coupled between the first node and the second output terminal. 13. The method of claim 12,
and the output buffer circuit further comprises an auxiliary capacitor connected between the second node and the first power supply terminal. 10. The method according to any one of claims 7 to 9,
The output buffer circuit,
a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node;
an eighth thin film transistor selectively connecting the first power terminal and the second output terminal in response to the voltage of the second node;
a capacitor connected between the first node and the second output terminal; and
and an auxiliary capacitor connected between the second node and the first power supply terminal. 15. The method of claim 14,
The first node control circuit includes first to third thin film transistors and a ninth thin film transistor,
The first thin film transistor selectively connects the first input terminal and the first node in response to a voltage supplied to the third input terminal,
the second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal;
the third thin film transistor is connected in series with the second thin film transistor, and selectively connects the second thin film transistor and the first power terminal in response to a voltage of the second node;
and the ninth thin film transistor is connected between the first node and the gate electrode of the seventh thin film transistor, and is always in a turned-on state by a voltage supplied to the second power supply terminal. a light emitting display panel including pixels disposed in a pixel area defined by a plurality of data lines and first to mth gate line groups;
a data driving circuit unit supplying a data voltage to each of the plurality of data lines; and
a gate driving circuit part disposed on the light emitting display panel and having first to mth stage blocks connected to each of the first to mth gate line groups;
Each of the first to mth stage blocks includes a first stage circuit connected to a first gate line of each of the first to mth gate line groups,
The first stage circuit of each of the first to m-th stage blocks,
a first output terminal electrically connected to the first gate line of each of the first to mth gate line groups and outputting a first scan signal having a positive polarity pulse; and
and a second output terminal for outputting a carry signal having a negative pulse synchronized with the positive pulse to a next stage block. 17. The method of claim 16,
Any one of the first stage circuits of each of the first to m-th stage blocks,
first node;
a second node directly coupled to the first output terminal;
a first node control circuit implemented to control a voltage of the first node in response to a voltage of each of a first input terminal, a second input terminal, a third input terminal, and a first power supply terminal;
a second node control circuit configured to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and
and an output buffer circuit implemented to supply the voltage of the second input terminal or the voltage of the first power supply terminal to the second output terminal in response to the voltage of the first node and the voltage of the second node. display device. 18. The method of claim 17,
The first input terminal receives the gate start signal or the carry signal,
the second input terminal receives a first gate shift clock;
The third input terminal receives a second gate shift clock having an inverted form of the first gate shift clock,
and the fourth input terminal receives a third gate shift clock having a shape different from that of the first and second gate shift clocks. 17. The method of claim 16,
Each of the first to mth stage blocks further includes a second stage circuit connected to each of the second gate line and the third gate line of each of the first to mth gate line groups,
The second stage circuit of each of the first to mth stage blocks,
a first output terminal electrically connected to the second gate line of each of the first to mth gate line groups and outputting a second scan signal having the positive polarity pulse; and
a second output terminal electrically connected to the third gate line of each of the first to mth gate line groups and outputting a third scan signal having the negative pulse;
and the third scan signal is supplied to a next stage block as a carry signal. 20. The method of claim 19,
Each of the pixels,
light emitting element; and
and a pixel circuit for controlling the light emission of the light emitting device,
The pixel circuit is
a plurality of N-type oxide thin film transistors turned on to the positive pulse of the first scan signal and the positive pulse of the second scan signal; and
and a plurality of P-type LTPS thin film transistors turned on by a negative pulse of the third scan signal. 20. The method of claim 19,
Any one of the second stage circuits of each of the first to mth stage blocks,
first node;
a second node directly coupled to the first output terminal;
a first node control circuit implemented to control a voltage of the first node in response to a voltage of each of a first input terminal, a second input terminal, a third input terminal, and a first power supply terminal;
a second node control circuit configured to control a voltage of the second node in response to voltages of each of the first node, the third input terminal, the fourth input terminal, and the second power supply terminal; and
and an output buffer circuit implemented to supply the voltage of the second input terminal or the voltage of the first power supply terminal to the second output terminal in response to the voltage of the first node and the voltage of the second node. display device. 22. The method of claim 21,
The first input terminal receives the gate start signal or the carry signal,
The second input terminal receives a first gate shift clock,
The third input terminal receives a second gate shift clock having an inverted form of the first gate shift clock,
and the fourth input terminal receives a third gate shift clock having the same shape as the second gate shift clock. 23. The method of any one of claims 17, 18, 21, and 22,
The first node control circuit includes first to third thin film transistors,
The first thin film transistor selectively connects the first input terminal and the first node in response to a voltage supplied to the third input terminal,
The second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal,
and the third thin film transistor is connected in series with the second thin film transistor and selectively connects the second thin film transistor and the first power terminal in response to a voltage of the second node. 23. The method of any one of claims 17, 18, 21, and 22,
The second node control circuit,
a fourth thin film transistor selectively connecting the second power terminal and the second node in response to a voltage supplied to the third input terminal;
a fifth thin film transistor selectively connecting the third input terminal and the second node in response to the voltage of the first node; and
and a sixth thin film transistor selectively connecting the second power terminal and the second node in response to a voltage supplied to the fourth input terminal. 19. The method of claim 17 or 18,
The output buffer circuit,
a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node;
an eighth thin film transistor selectively connecting the first power terminal and the second output terminal in response to the voltage of the second node; and
and a capacitor connected between the first node and the second output terminal. 23. The method of claim 21 or 22,
The output buffer circuit,
a seventh thin film transistor selectively connecting the first input terminal and the second output terminal in response to the voltage of the first node;
an eighth thin film transistor selectively connecting the first power terminal and the second output terminal in response to the voltage of the second node;
a capacitor connected between the first node and the second output terminal; and
and an auxiliary capacitor connected between the second node and the first power terminal. 27. The method of claim 26,
The first node control circuit includes first to third thin film transistors and a ninth thin film transistor,
The first thin film transistor selectively connects the first input terminal and the first node in response to a voltage supplied to the third input terminal,
the second thin film transistor selectively connects the first node and the third thin film transistor in response to a voltage supplied to the second input terminal;
the third thin film transistor is connected in series with the second thin film transistor, and selectively connects the second thin film transistor and the first power terminal in response to a voltage of the second node;
The ninth thin film transistor is connected between the first node and the gate electrode of the seventh thin film transistor, and is always turned on by a voltage supplied to the second power supply terminal.

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