KR20240083577A - Scan Signal Generation Circuit and Display Device including the same - Google Patents

Abstract

The present invention includes a shift register including a first scan signal generator that outputs a first scan signal and a second scan signal generator that outputs a second scan signal; and a modulation transistor included in the shift register, wherein the modulation transistor is a scan signal generation circuit that modulates the level of the first scan signal output from the first scan signal generator in response to a signal supplied from the outside. can be provided.

Description

Scan signal generation circuit and display device including the same {Scan Signal Generation Circuit and Display Device including the same}

The present invention relates to a scan signal generation circuit and a display device including the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as Light Emitting Display Device (LED), Quantum Dot Display Device (QDD), and Liquid Crystal Display Device (LCD) is increasing.

The display devices described above include a display panel including subpixels, a driver that outputs a driving signal to drive the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

The above display devices can display images by transmitting light or directly emitting light through the selected subpixels when driving signals, such as scan signals and data signals, are supplied to the subpixels formed on the display panel.

The present invention provides a scan signal generation circuit that can improve the kickback phenomenon. In addition, the present invention reduces the kickback difference resulting from the device characteristics of the oxide transistor, improves the driving uniformity of the entire display panel, and can improve stains that may appear in low gray. The purpose is to provide a display device.

The present invention includes a shift register including a first scan signal generator that outputs a first scan signal and a second scan signal generator that outputs a second scan signal; and a modulation transistor included in the shift register, wherein the modulation transistor is a scan signal generation circuit that modulates the level of the first scan signal output from the first scan signal generator in response to a signal supplied from the outside. can be provided.

The modulation transistor has a gate electrode connected to a signal line through which the externally supplied signal is transmitted, a first electrode connected to a gate modulation voltage line through which a modulation voltage is transmitted, and a second electrode connected to the output terminal of the first scan signal generator. Electrodes can be connected.

The modulation transistor is included in the first scan signal generator of the first stage included in the shift register, and has a gate electrode at the output terminal of the second scan signal generator of the second stage located at the next stage of the first stage. can be connected

The first scan signal may be modulated before being converted from a high voltage to a low voltage by the operation of the modulation transistor.

The modulation transistor may be selected as a p-type transistor.

In another aspect, the present invention provides a display panel including subpixels connected to a first scan line and a second scan line; a shift register including a first scan signal generator that outputs a first scan signal to the first scan line and a second scan signal generator that outputs a second scan signal to the second scan line; and a modulation transistor included in the shift register, wherein the modulation transistor modulates the level of the first scan signal output from the first scan signal generator in response to a signal supplied from the outside. You can.

The modulation transistor has a gate electrode connected to a signal line through which the externally supplied signal is transmitted, a first electrode connected to a gate modulation voltage line through which a modulation voltage is transmitted, and a second electrode connected to the output terminal of the first scan signal generator. Electrodes can be connected.

The modulation transistor is included in the first scan signal generator of the first stage included in the shift register, and has a gate electrode at the output terminal of the second scan signal generator of the second stage located at the next stage of the first stage. can be connected

The first scan signal may be modulated before being converted from a high voltage to a low voltage by the operation of the modulation transistor.

The modulation voltage may be fixed or variable.

The present invention has the effect of improving the kickback phenomenon by implementing a device that modulates the level of the gate signal at the shift register stage. Additionally, the present invention has the effect of reducing the kickback difference resulting from the device characteristics of the oxide transistor included in the subpixel. Additionally, the present invention has the effect of improving the driving uniformity of the entire display panel, thereby improving spotting that may appear in low gray levels.

FIG. 1 is a block diagram schematically showing a light emitting display device, and FIG. 2 is a block diagram schematically showing the subpixel shown in FIG. 1.
Figures 3 and 4 are diagrams for explaining the configuration of a gate-in-panel type gate driver, and Figure 5 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver.
FIG. 6 is a block diagram schematically showing a subpixel according to the first embodiment of the present invention, FIG. 7 is a block diagram schematically showing a shift register according to the first embodiment of the present invention, and FIG. 8 is a block diagram schematically showing a subpixel according to the first embodiment of the present invention. It is a block diagram showing a part of the shift register shown in FIG. 7 according to the first embodiment, and FIG. 9 is a circuit diagram showing the first scan signal generator shown in FIG. 8 according to the first embodiment of the present invention. FIG. 10 is a waveform diagram for explaining the output of the first scan signal generator shown in FIG. 9.
FIG. 11 is a block diagram showing a portion of the shift register shown in FIG. 7 according to the second embodiment of the present invention, and FIG. 12 is a first scan signal generator shown in FIG. 11 according to the second embodiment of the present invention. This is a circuit diagram, and FIG. 13 is a waveform diagram for explaining the output of the first scan signal generator shown in FIG. 12.
Figures 14 and 15 are diagrams showing simulation results of shift registers according to experimental examples and embodiments.

The display device according to the present invention can be implemented in a television, video player, personal computer (PC), home theater, automobile electric device, smartphone, etc., but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

In addition, the thin film transistor described below may be implemented as an n-type thin film transistor, a p-type thin film transistor, or a combination of n-type and p-type. A thin film transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within a thin film transistor, carriers begin to flow from a source. The drain is the electrode through which carriers go out in a thin film transistor. That is, in a thin film transistor, carriers flow from the source to the drain.

In the case of a p-type thin film transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, current flows from the source to the drain because holes flow from the source to the drain. On the other hand, in the case of an n-type thin film transistor, since the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type thin film transistor, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. However, the source and drain of a thin film transistor can change depending on the applied voltage. Reflecting this, in the following description, one of the source and drain will be described as the first electrode, and the other one of the source and drain will be described as the second electrode.

FIG. 1 is a block diagram schematically showing a light emitting display device, and FIG. 2 is a block diagram schematically showing the subpixel shown in FIG. 1.

As shown in Figures 1 and 2, the light emitting display device includes an image supply unit 110, a timing control unit 120, a gate driver 130, a data driver 140, a display panel 150, and a power supply unit 180. It may include etc.

The image supply unit (set or host system) 110 can output various driving signals in addition to image data signals supplied from outside or image data signals (image data signals) stored in internal memory. The image supply unit 110 may supply data signals and various driving signals to the timing control unit 120.

The timing control unit 120 includes a gate timing control signal (GDC) for controlling the operation timing of the gate driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals ( The vertical synchronization signal (VSYNC) and the horizontal synchronization signal (HSYNC) can be output. The timing control unit 120 may supply the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140. The timing control unit 120 may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited to this.

The gate driver 130 may output a gate signal (or gate voltage) in response to a gate timing control signal (GDC) supplied from the timing control unit 120. The gate driver 130 may supply a gate signal to subpixels included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 may be formed in the form of an IC or directly on the display panel 150 using a gate in panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal (DATA) in response to the data timing control signal (DDC) supplied from the timing control unit 120 and converts the digital data signal into analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply a data voltage to subpixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The power supply unit 180 may generate a high potential voltage and a low potential voltage based on an external input voltage supplied from the outside, and output them through the first power line (EVDD) and the second power line (EVSS). The power supply unit 180 provides not only the high potential voltage and the low potential voltage, but also the voltage required to drive the gate driver 130 (e.g., a gate voltage including the gate high voltage and gate low voltage) or the data driver 140. The necessary voltage (drain voltage including drain voltage and half-drain voltage) can be generated and output.

The display panel 150 can display an image in response to a driving signal including a gate signal and a data voltage, and a driving voltage including a high potential voltage and a low potential voltage. Subpixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. And the subpixels that emit light may be composed of pixels containing red, green, and blue, or pixels containing red, green, blue, and white.

For example, one subpixel (SP) may be connected to the first data line (DL1), the first gate line (GL1), the first power line (EVDD), and the second power line (EVSS), and a switching transistor, driving It may include a pixel circuit made of transistors, capacitors, organic light emitting diodes, etc. Subpixels (SP) used in light-emitting displays directly emit light, so the circuit configuration is complex. In addition, there are various compensation circuits that compensate for the deterioration of not only the organic light-emitting diode that emits light, but also the driving transistor that supplies the driving current required to drive the organic light-emitting diode. Therefore, please refer to the fact that the subpixel SP is simply shown in the form of a block.

Meanwhile, in the above description, the timing control unit 120, gate driver 130, data driver 140, etc. were described as if they were individual components. However, depending on the implementation method of the light emitting display device, one or more of the timing control unit 120, gate driver 130, and data driver 140 may be integrated into one IC.

Figures 3 and 4 are diagrams for explaining the configuration of a gate-in-panel type gate driver, and Figure 5 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver.

As shown in FIG. 3, the gate-in-panel type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate clock signals Clks and a start signal Vst based on signals and voltages output from the timing control unit 120 and the power supply unit 180. The shift register 131 operates based on the clock signals (Clks) and the start signal (Vst) output from the level shifter 135 and can output gate signals (Gout[1] to Gout[m]). there is.

As shown in FIGS. 3 and 4 , unlike the shift register 131, the level shifter 135 may be formed independently in the form of an IC or may be included inside the power supply unit 180. However, this is only an example and is not limited to this.

As shown in FIG. 5, the first and second shift registers 131a and 131b that output gate signals from the gate-in-panel type gate driver may be disposed in the non-display area (NA) of the display panel 150. . The first and second shift registers 131a and 131b may be formed in a thin film form on the display panel 150 using a gate-in-panel method. The first and second shift registers 131a and 131b are shown as an example of being disposed in the left and right non-display areas (NA) of the display panel 150, but the present invention is not limited thereto.

FIG. 6 is a block diagram schematically showing a subpixel according to the first embodiment of the present invention, FIG. 7 is a block diagram schematically showing a shift register according to the first embodiment of the present invention, and FIG. 8 is a block diagram schematically showing a subpixel according to the first embodiment of the present invention. It is a block diagram showing a part of the shift register shown in FIG. 7 according to the first embodiment, and FIG. 9 is a circuit diagram showing the first scan signal generator shown in FIG. 8 according to the first embodiment of the present invention. FIG. 10 is a waveform diagram for explaining the output of the first scan signal generator shown in FIG. 9.

As shown in FIG. 6, the subpixel SP according to the first embodiment includes a first gate line GL1, a first data line DL1, a first power line EVDD, and a second power line EVSS. ) can be connected to. The first gate line GL1 may include a first scan line GL1a and a second scan line GL1b. The first scan line GL1a and the second scan line GL1b may be arranged on the same horizontal line. The subpixel according to the first embodiment may operate based on the first scan signal and the second scan signal.

As shown in FIG. 7, the shift register 131a according to the first embodiment includes first clock signal lines (CLKS1), second clock signal lines (CLKS2), gate modulation voltage line (VGPM), and gate high It can be connected to the voltage line (VGH), gate low voltage line (VGL), and start signal line (VST).

The shift register 131a stores the first clock signals applied through the first clock signal lines CLKS1, the second clock signals applied through the second clock signal lines CLKS2, and the gate modulation voltage line VGPM. ), gate modulation voltage applied through the gate high voltage line (VGH), gate low voltage applied through the gate low voltage line (VGL), and start applied through the start signal line (VST). It can operate based on signals, etc.

In order to drive the subpixel shown in FIG. 6, the shift register 131a includes first scan signal generators (SCN1[1] to SCN1[m]) that output the first scan signal and output the second scan signal. It may include second scan signal generators (SCN2[1] to SCN2[m]). The shift register 131a is composed of stages (STG1 to STGm) that are dependently connected to sequentially output gate signals (Gout[1] to Gout[m]) through gate lines (GL1 to GLm). These are the same as the first stage (STG1) below.

The first scan signal generator (SCN1[1]) and the second scan signal generator (SCN2[1]) located in the first stage (STG1) generate the first gate signal (Gout) through the first gate line (GL1). [1]) can be output. The first gate signal (Gout[1]) may include a first scan signal and a second scan signal. The first scan signal and the second scan signal may be applied to the subpixel through the first scan line and the second scan line included in the first gate line GL1.

As shown in FIGS. 8 to 10, the first scan signal generator SCN1[1] of the first stage STG1 may modulate the output level of the first scan signal Gout1a. And this is not only the first scan signal generator (SCN1[1]) of the first stage (STG1) but also the first scan signal generators (SCN1[2] to SCN1) of the second stage (STG2) to the M stage (STGm). [m]) is also possible. Hereinafter, this will be described in detail based on the first scan signal generator (SCN1[1]) of the first stage (STG1) as follows.

The first scan signal generator (SCN1[1]) of the first stage (STG1) includes a node control unit (NDC), a first output transistor (T6), a second output transistor (T7), and a modulation transistor (MT). can do.

The node control unit NDC may be connected to the first clock signal line CLK1, the gate high voltage line VGH, the gate low voltage line VGL, and the start signal line VST. The node control unit (NDC) receives the first clock signal applied through the first clock signal line (CLK1), the gate high voltage applied through the gate high voltage line (VGH), and the gate applied through the gate low voltage line (VGL). It can operate based on a low voltage and a start signal applied through the start signal line (VST). The nose control unit (NDC) operates based on the start signal and the first clock signal, and can control the Q node (Q) and QB node (QB) based on the gate high voltage and gate low voltage.

The first output transistor (T6) has a gate electrode connected to the Q node (Q), a first electrode connected to the gate low voltage line (VGL), and an output terminal ( A second electrode may be connected to Out). The first output transistor T6 may be turned on or off in response to the potential of the Q node (Q). When the first output transistor (T6) is turned on, the gate low voltage applied through the gate low voltage line (VGL) is converted to a low voltage (Out) through the output terminal (Out) of the first scan signal generator (SCN1[1]). L) can be output.

The second output transistor T7 has a gate electrode connected to the QB node (QB), a first electrode connected to the gate high voltage line (VGH), and an output terminal ( A second electrode may be connected to Out). The second output transistor T7 may be turned on or turned off in response to the potential of the QB node QB. When the second output transistor (T7) is turned on, the gate high voltage applied through the gate high voltage line (VGH) is a high voltage (Out) through the output terminal (Out) of the first scan signal generator (SCN1[1]). H) can be output.

The modulation transistor (MT) has its gate electrode connected to the signal line (SCN2O) connected to the output terminal of the second scan signal generator (SCN2[2]) of the second stage (STG2) and applied to the gate modulation voltage line (VGPM). One electrode may be connected and the second electrode may be connected to the output terminal (Out) of the first scan signal generator (SCN1[1]). The modulation transistor MT may be turned on or off in response to the second scan signal Gout2b output through the output terminal of the second scan signal generator SCN2[2] of the second stage STG2. When the modulation transistor MT is turned on, the level of the low voltage L output through the output terminal Out of the first scan signal generator SCN1[1] may be modulated.

Referring to FIG. 10, it can be seen that the first scan signal (Gout1a) does not convert from the high voltage (H) to the low voltage (L), but occurs at a voltage level between the high voltage (H) and the low voltage (L). there is. This is because the modulation transistor (MT) is turned on in response to the second scan signal (Gout2b), and a modulation voltage between the high voltage (H) and the low voltage (L) is applied through the turned-on modulation transistor (MT). Figure 10 shows an example in which the modulation voltage between the gate high voltage and the gate low voltage is fixedly applied through the gate modulation voltage line (VGPM). However, this is only an example, and the modulation voltage may vary depending on the characteristics of the device.

The level of the first scan signal (Gout1a) may vary depending on the level of the modulation voltage applied through the gate modulation voltage line (VGPM) during the gate modulation period (GPM). And the gate modulation period (GPM) may correspond to the generation period of the second scan signal (Gout2b).

Meanwhile, in the first embodiment, the first output transistor (T6), the second output transistor (T7), and the modulation transistor (MT) are selected as p-type as an example, but the present invention is not limited thereto. That is, the first output transistor (T6), the second output transistor (T7), and the modulation transistor (MT) may be selected as n-type.

In addition, in the first embodiment, it is only shown as an example that modulation is performed in response to the time when the first scan signal (Gout1a) is converted from the high voltage (H) to the low voltage (L), and the present invention is not limited to this. No. That is, the circuit may be configured so that modulation is performed in response to the time when the first scan signal (Gout1a) is converted from the low voltage (L) to the high voltage (H), and a voltage may be applied in response.

FIG. 11 is a block diagram showing a portion of the shift register shown in FIG. 7 according to the second embodiment of the present invention, and FIG. 12 is a first scan signal generator shown in FIG. 11 according to the second embodiment of the present invention. This is a circuit diagram, and FIG. 13 is a waveform diagram for explaining the output of the first scan signal generator shown in FIG. 12.

As shown in FIG. 11, the shift register 131a according to the second embodiment includes first clock signal lines (CLKS1), second clock signal lines (CLKS2), gate modulation voltage line (VGPM), and gate high It can be connected to the voltage line (VGH), gate low voltage line (VGL), and start signal line (VST). The first clock signal lines CLKS1 may include a 1-1 clock signal line CLK1 and a 1-2 clock signal line CLK2, and the second clock signal lines CLKS2 may include a 1-1 clock signal line CLK1 and a 1-2 clock signal line CLK2. It may include a first clock signal line (CLK1') and a second-second clock signal line (CLK2'). The 1-1 clock signal and the 1-2 clock signal applied through the 1-1 clock signal line (CLK1) and the 1-2 clock signal line (CLK2) are connected to the 2-1 clock signal line (CLK1') and may have different phases from the 2-1 clock signal and the 2-2 clock signal applied through the 2-2 clock signal line CLK2'.

The shift register 131a stores the first clock signals applied through the first clock signal lines CLKS1, the second clock signals applied through the second clock signal lines CLKS2, and the gate modulation voltage line VGPM. ), gate modulation voltage applied through the gate high voltage line (VGH), gate low voltage applied through the gate low voltage line (VGL), and start applied through the start signal line (VST). It can operate based on signals, etc.

The shift register 131a includes first scan signal generators (SCN1[1] ~ SCN1[2]) that output the first scan signal and second scan signal generators (SCN2[1] ~) that output the second scan signal. SCN2[2]) may be included.

As shown in FIGS. 11 to 13, the first scan signal generator (SCN1[1]) of the first stage (STG1) may modulate the output level of the first scan signal (Gout1a). And this generates all the first scan signals, such as the first scan signal generator (SCN1[1]) of the first stage (STG1) as well as the first scan signal generator (SCN1[2]) of the second stage (STG2). It is possible in the department. Hereinafter, this will be described in detail based on the first scan signal generator (SCN1[1]) of the first stage (STG1) as follows.

The first scan signal generator (SCN1[1]) of the first stage (STG1) includes the first transistor (T1) to the fifth transistor (T5), the first capacitor (CO) to the third capacitor (CB), and the first transistor (T1) to the fifth transistor (T5). It may include an output transistor (T6), a second output transistor (T7), and a modulation transistor (MT). The first transistor (T1) to the fifth transistor (T5), the first output transistor (T6), the second output transistor (T7), and the modulation transistor (MT) may be selected as p-type.

The first to fifth transistors T1 to T5 and the first to third capacitors CO may be included in the node control unit NDC. The nose control unit (NDC) operates based on the start signal and the first clock signal, and can control the Q node (Q) and QB node (QB) based on the gate high voltage and gate low voltage.

The first scan signal generator (SCN1[1]) of the first stage (STG1) receives the first clock signal applied through the first clock signal line (CLK1) and the gate high voltage line (VGH). It can operate based on voltage, the gate low voltage applied through the gate low voltage line (VGL), and the start signal applied through the start signal line (VST), which is explained as follows.

The first transistor T1 may have a gate electrode connected to the first clock signal line CLK1, a first electrode connected to the start signal line VST, and a second electrode connected to the Q2 node Q2. The first transistor T1 may operate based on the first clock signal applied through the first clock signal line CLK1. When the first transistor (T1) is turned on, the start signal applied through the start signal line (VST) may be transmitted to the Q2 node (Q2).

The second transistor (T2) has a gate electrode connected to the first clock signal line (CLK1), a first electrode connected to the gate high voltage line (VGH), and a second electrode connected to the gate electrode of the third transistor (T3). You can. The second transistor T2 may operate based on the first clock signal applied through the first clock signal line CLK1. When the second transistor (T2) is turned on, the gate high voltage applied through the gate high voltage line (VGH) can be transmitted to the first electrode of the first capacitor (CO) and the gate electrode of the third transistor (T3). there is.

The third transistor (T3) has a gate electrode connected to the first electrode of the first capacitor (CO) and the second electrode of the second transistor (T2), a first electrode connected to the first clock signal line (CLK1), and QB. A second electrode may be connected to the node QB. The third transistor T3 may operate in response to the potential charged in the first capacitor CO. When the third transistor T3 is turned on, the first clock signal applied through the first clock signal line CLK1 may be transmitted to the QB node QB. The third transistor T3 may have a dual gate electrode, but is not limited thereto.

The fourth transistor T4 may have a gate electrode connected to the Q2 node (Q2), a first electrode connected to the gate high voltage line (VGH), and a second electrode connected to the QB node (QB). The fourth transistor T4 may operate in response to the potential of the Q2 node Q2. When the fourth transistor T4 is turned on, the gate high voltage applied through the gate high voltage line VGH may be transmitted to the QB node (QB).

The fifth transistor T5 may have a gate electrode connected to the gate low voltage line VGL, a first electrode connected to the Q2 node (Q2), and a second electrode connected to the Q1 node (Q1). The fifth transistor T5 may operate in response to the gate low voltage applied through the gate low voltage line VGL. The fifth transistor T5 remains turned on and can stabilize the potential between the Q2 node (Q2) and the Q1 node (Q1).

The first capacitor CO may have a first electrode connected to the second electrode of the second transistor T2 and the gate electrode of the third transistor T3, and a second electrode connected to the first clock signal line CLK1. . The first capacitor CO may be charged or discharged in response to the first clock signal applied through the first clock signal line CLK1. The first capacitor (CO) may serve to help the potential of the node change quickly in response to the first clock signal.

The second capacitor CQ may have a first electrode connected to the Q1 node (Q1) and a second electrode connected to the output terminal (Out) of the first scan signal generator (SCN1[1]). The second capacitor (CQ) suppresses the ripple of the Q1 node (Q1) and can play a role in maintaining an electrically stable state.

The third capacitor CB may have a first electrode connected to the QB node QB and a second electrode connected to the gate high voltage line VGH. The third capacitor (CB) suppresses the ripple of the QB node (QB) and can play a role in maintaining an electrically stable state.

The first output transistor (T6) has a gate electrode connected to the Q node (Q), a first electrode connected to the gate low voltage line (VGL), and an output terminal ( A second electrode may be connected to Out). The first output transistor T6 may be turned on or off in response to the potential of the Q node (Q). When the first output transistor (T6) is turned on, the gate low voltage applied through the gate low voltage line (VGL) is converted to a low voltage (Out) through the output terminal (Out) of the first scan signal generator (SCN1[1]). L) can be output.

The second output transistor T7 has a gate electrode connected to the QB node (QB), a first electrode connected to the gate high voltage line (VGH), and an output terminal ( A second electrode may be connected to Out). The second output transistor T7 may be turned on or turned off in response to the potential of the QB node QB. When the second output transistor (T7) is turned on, the gate high voltage applied through the gate high voltage line (VGH) is a high voltage (Out) through the output terminal (Out) of the first scan signal generator (SCN1[1]). H) can be output.

The modulation transistor (MT) has its gate electrode connected to the signal line (SCN2O) connected to the output terminal of the second scan signal generator (SCN2[2]) of the second stage (STG2) and applied to the gate modulation voltage line (VGPM). One electrode may be connected and the second electrode may be connected to the output terminal (Out) of the first scan signal generator (SCN1[1]). The modulation transistor MT may be turned on or off in response to the second scan signal Gout2b output through the output terminal of the second scan signal generator SCN2[2] of the second stage STG2. When the modulation transistor MT is turned on, the level of the low voltage L output through the output terminal Out of the first scan signal generator SCN1[1] may be modulated.

Referring to FIG. 13, it can be seen that the first scan signal (Gout1a) does not convert from the high voltage (H) to the low voltage (L), but occurs at a voltage level between the high voltage (H) and the low voltage (L). there is. This is because the modulation transistor (MT) is turned on in response to the second scan signal (Gout2b), and a modulation voltage between the high voltage (H) and the low voltage (L) is applied through the turned-on modulation transistor (MT). Figure 13 only shows an example in which a modulation voltage between the gate high voltage and the gate low voltage is applied through the gate modulation voltage line (VGPM), but the present invention is not limited to this and can be varied depending on the characteristics of the device.

The level of the first scan signal (Gout1a) may vary depending on the level of the modulation voltage applied through the gate modulation voltage line (VGPM) during the gate modulation period (GPM). The gate modulation period (GPM) may correspond to the generation period of the second scan signal (Gout2b). Accordingly, the gate modulation period (GPM) may vary depending on the low voltage (L) generation period of the second scan signal (Gout2b).

Figures 14 and 15 are diagrams showing simulation results of shift registers according to experimental examples and embodiments. Figures 14 and 15 are simulation results of a shift register including a first scan signal generator implemented based on the second embodiment of the present invention.

As shown in Figures 14 and 15, the first scan signal (Gout1a) output from the first scan signal generator according to the experimental example is not modulated until the transition period (TP) when the level of the signal is changed and maintains a high voltage. It can be maintained and then generated as low voltage.

In contrast, the first scan signal (Gout1a) output from the first scan signal generator according to the embodiment is modulated in the form of falling from a high voltage to a low voltage before the transition period (TP) in which the level of the signal is changed. It can be caused by low voltage. When outputting the first scan signal (Gout1a), modulating the voltage can reduce the peak-to-peak voltage (Vpp) of the first scan signal generator, thereby improving the kickback phenomenon. Additionally, the kickback difference resulting from the device characteristics of the oxide transistor included in the subpixel can be reduced. Additionally, by improving the driving uniformity of the entire display panel, spots that may appear in low gray can be improved.

As can be seen by comparing the first scan signal (Gout1a) generated according to the experimental example with the first scan signal (Gout1a) generated according to the embodiment, the subpixel is based on the first scan signal (Gout1a) according to the embodiment. By driving, the kickback phenomenon that may occur at the gate electrode of the driving transistor (DTG) can be improved. This can be seen more clearly by referring to Table 1 below along with Figures 14 and 15. In addition, the embodiment may set the gate modulation voltage to one level or vary it to multiple levels in consideration of the kickback phenomenon.

Before kickback effect After the kickback impact DTG fluctuation amount Decrease rate of change Experiment example 0.63V -0.32V △ 0.95V - Example 0.63V -0.18V △ 0.82V 13.9%

As above, the present invention has the effect of improving the kickback phenomenon by implementing a device to modulate the level of the gate signal at the shift register stage. Additionally, the present invention has the effect of reducing the kickback difference resulting from the device characteristics of the oxide transistor included in the subpixel. Additionally, the present invention has the effect of improving the driving uniformity of the entire display panel, thereby improving spotting that may appear in low gray levels.

130: gate driver 150: display panel
SCN1[1]: First scan signal generator NDC: Node control unit
T6: First output transistor T7: Second output transistor
MT: Modulation transistor VGPM: Gate modulation voltage line

Claims (10)

A shift register including a first scan signal generator that outputs a first scan signal and a second scan signal generator that outputs a second scan signal; and
Including a modulation transistor included in the shift register,
A scan signal generation circuit wherein the modulation transistor modulates the level of the first scan signal output from the first scan signal generator in response to a signal supplied from the outside. According to paragraph 1,
The modulation transistor is
A gate electrode is connected to a signal line through which a signal supplied from the outside is transmitted, a first electrode is connected to a gate modulation voltage line through which a modulation voltage is transmitted, and a second electrode is connected to the output terminal of the first scan signal generator. Signal generation circuit. According to paragraph 2,
The modulation transistor is
Included in a first scan signal generator of the first stage included in the shift register,
A scan signal generation circuit where the gate electrode is connected to the output terminal of the second scan signal generator of the second stage located at the next stage of the first stage. According to paragraph 1,
The first scan signal is
A scan signal generation circuit in which modulation is performed before switching from a high voltage to a low voltage by the operation of the modulation transistor. According to paragraph 1,
The modulation transistor is
A scan signal generation circuit selected with a p-type transistor. A display panel including subpixels connected to a first scan line and a second scan line;
a shift register including a first scan signal generator that outputs a first scan signal to the first scan line and a second scan signal generator that outputs a second scan signal to the second scan line; and
Including a modulation transistor included in the shift register,
The display device wherein the modulation transistor modulates the level of the first scan signal output from the first scan signal generator in response to a signal supplied from the outside. According to clause 6,
The modulation transistor is
A gate electrode is connected to a signal line through which a signal supplied from the outside is transmitted, a first electrode is connected to a gate modulation voltage line through which a modulation voltage is transmitted, and a second electrode is connected to the output terminal of the first scan signal generator. Device. In clause 7,
The modulation transistor is
Included in a first scan signal generator of the first stage included in the shift register,
A display device whose gate electrode is connected to the output terminal of the second scan signal generator of the second stage located next to the first stage. According to clause 6,
The first scan signal is
A display device in which modulation is performed before switching from a high voltage to a low voltage by the operation of the modulation transistor. In clause 7,
The modulation voltage is
A fixed or variable scan signal display device.