KR20240063360A - Display device and gate driving circuit - Google Patents

Abstract

Embodiments of the present disclosure relate to a display device and a gate driving circuit, and more specifically, a gate line including at least one scan line and a light emitting signal line extending in a first direction and arranged in the first direction. A display panel including a subpixel line made up of a plurality of subpixels, a first light emitting driver that shares one light emitting signal line connected to one subpixel line and is disposed on one side of the display panel, and the display panel. A display device can be provided that includes a gate driving circuit including a second light-emitting driver disposed on the other side, and a timing controller that controls the first light-emitting driver and the second light-emitting driver to be driven alternately.

Description

Display device and gate driving circuit {DISPLAY DEVICE AND GATE DRIVING CIRCUIT}

Embodiments of the present disclosure relate to a display device and a gate driving circuit capable of stable operation by reducing stress.

As the information society develops, various demands for display devices that display images are increasing, and various types of display devices such as liquid crystal displays and organic light emitting displays are being utilized.

Among these display devices, organic light emitting display devices use organic light emitting diodes that emit light on their own, so they have advantages in terms of fast response speed, contrast ratio, luminous efficiency, brightness, and viewing angle.

The display device includes a light-emitting element disposed in each of a plurality of subpixels arranged on a display panel, and controls the luminance displayed by each subpixel by controlling the voltage flowing through the light-emitting element to emit light, thereby creating an image. It can be displayed.

At this time, a light emitting element and a plurality of switching transistors for controlling it are disposed in each subpixel defined in the display panel. The gate driving circuit that drives the switching transistor to display image data on the display panel during the display driving period is the display panel. The turn-on state is maintained during the driving period.

As a result, stress may accumulate in the scan driver or light emitting driver constituting the gate driving circuit due to the continuous turn-on state, resulting in an operation error.

Accordingly, the inventors of the present specification are able to provide a display device and a gate driving circuit that can reduce stress occurring during the display driving process.

Embodiments of the present disclosure provide a display device and a gate driving circuit that can reduce the stress of the gate driving circuit by alternately driving the gate driving circuit in a structure of a dual gate driving circuit in which gate driving circuits are disposed on both sides of the display panel. can be provided.

In addition, embodiments of the present disclosure can provide a display device and a gate driving circuit that can reduce the stress of the light emitting driver by alternately driving a plurality of light emitting drivers included in the gate driving circuit in the structure of the dual gate driving circuit. there is.

Additionally, embodiments of the present disclosure can provide a display device and a gate driving circuit having a light emitting driver capable of alternating driving according to an alternating control signal in a dual gate driving circuit structure.

Embodiments of the present disclosure include a display panel including a gate line including at least one scan line and a light emitting signal line extending in a first direction and a subpixel line composed of a plurality of subpixels arranged in the first direction; , a gate driving circuit that shares one light-emitting signal line connected to one subpixel line and includes a first light-emitting driver disposed on one side of the display panel and a second light-emitting driver disposed on the other side of the display panel; , a display device including a timing controller that controls the first light emitting driver and the second light emitting driver to drive alternately.

Embodiments of the present disclosure include a display panel including a gate line including at least one scan line and a light emitting signal line extending in a first direction and a subpixel line composed of a plurality of subpixels arranged in the first direction; , shares two light-emitting signal lines connected to two adjacent subpixel lines, and includes two first light-emitting drivers disposed on one side of the display panel and two second light-emitting drivers disposed on the other side of the display panel. A display device including a gate driving circuit and a timing controller that controls odd-numbered first light-emitting drivers and second light-emitting drivers to be driven alternately with even-numbered first light-emitting drivers and second light-emitting drivers. can do.

Embodiments of the present disclosure include a display panel including a gate line including at least one scan line and a light emitting signal line extending in a first direction and a subpixel line composed of a plurality of subpixels arranged in the first direction. In the gate driving circuit, at least one first light-emitting driver disposed on one side of the display panel and supplying a light-emitting signal through a first light-emitting signal line connected to a first subpixel line, and At least one second light-emitting driver disposed on the other side and supplying a light-emitting signal through a first light-emitting signal line connected to the first subpixel line, wherein the at least one first light-emitting driver and the at least one In the second light emitting driver, the first group of light emitting diodes and the second group of light emitting diodes may provide a gate driving circuit in which turn-on periods and turn-off periods alternately operate.

According to embodiments of the present disclosure, there is an effect of reducing stress occurring during the display driving process.

In addition, according to embodiments of the present disclosure, in the structure of a dual gate driving circuit in which gate driving circuits are disposed on both sides of the display panel, the stress of the gate driving circuit can be reduced by alternately driving the gate driving circuit. there is.

Additionally, according to embodiments of the present disclosure, in the structure of the dual gate driving circuit, the stress of the light emitting drivers can be reduced by alternately driving the plurality of light emitting drivers included in the gate driving circuit.

Additionally, according to embodiments of the present disclosure, there is an effect of providing a light emitting driver capable of alternating driving according to an alternating control signal in the structure of a dual gate driving circuit.

1 is a diagram schematically showing a display device according to embodiments of the present disclosure.
Figure 2 is a system diagram of a display device according to embodiments of the present disclosure.
FIG. 3 is a diagram showing an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure.
Figure 4 is a diagram showing an example of a subpixel circuit of a display device according to embodiments of the present disclosure.
FIG. 5 is a diagram illustrating the configuration of a gate driving integrated circuit for driving a subpixel circuit in a display device according to embodiments of the present disclosure.
FIG. 6 is a diagram illustrating the circuit configuration of a light emitting driver in a display device according to embodiments of the present disclosure.
FIG. 7 is a diagram illustrating a structure in which light emitting drivers sharing the same gate line are alternately operated in a display device according to embodiments of the present disclosure.
FIG. 8 is a diagram illustrating an example of a signal flow when light emitting drivers sharing the same gate line are alternately operated in a display device according to embodiments of the present disclosure.
FIG. 9 is a diagram illustrating an example of a structure in which light emitting drivers share adjacent light emitting signal lines in a display device according to embodiments of the present disclosure.
FIG. 10 is a diagram illustrating a structure for alternately driving light emitting drivers sharing adjacent subpixel lines in a display device according to embodiments of the present disclosure.
FIG. 11 is a diagram illustrating a signal flow diagram when alternately driving light emitting drivers sharing adjacent subpixel lines in a display device according to embodiments of the present disclosure.
FIG. 12 is a diagram illustrating an example of a structure in which two light-emitting drivers share two adjacent light-emitting signal lines in a display device according to embodiments of the present disclosure.
FIG. 13 is a diagram illustrating a structure in which two light emitting drivers sharing adjacent subpixel lines are alternately driven in a display device according to embodiments of the present disclosure.
FIG. 14 is a diagram showing an example of a signal flow diagram when two light emitting drivers sharing adjacent subpixel lines are alternately driven in a display device according to embodiments of the present disclosure.
FIG. 15 is a diagram showing an example of a signal waveform when a light emitting driver alternates turn-on and turn-off operations in a display device according to embodiments of the present disclosure.
FIG. 16 is a diagram showing an example of the amount of change in threshold voltage of a pull-up transistor according to a method of driving a light emitting driver in a display device according to embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to illustrative drawings. In adding reference numerals to components in each drawing, identical components may have the same reference numerals as much as possible even if they are shown in different drawings. Additionally, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When “comprises,” “has,” “consists of,” etc. mentioned in the specification are used, other parts may be added unless “only” is used. When a component is expressed in the singular, it can also include the plural, unless specifically stated otherwise.

Additionally, in describing the components of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term.

In the description of the positional relationship of components, when two or more components are described as being “connected,” “coupled,” or “connected,” the two or more components are directly “connected,” “coupled,” or “connected.” ", but it should be understood that two or more components and other components may be further "interposed" and "connected," "combined," or "connected." Here, other components may be included in one or more of two or more components that are “connected,” “coupled,” or “connected” to each other.

In the explanation of temporal flow relationships related to components, operation methods, production methods, etc., for example, temporal precedence relationships such as “after”, “after”, “after”, “before”, etc. Or, when a sequential relationship is described, non-continuous cases may be included unless “immediately” or “directly” is used.

On the other hand, when a numerical value or corresponding information (e.g. level, etc.) for a component is mentioned, even if there is no separate explicit description, the numerical value or corresponding information is related to various factors (e.g. process factors, internal or external shocks, It can be interpreted as including the error range that may occur due to noise, etc.).

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a diagram illustrating a schematic configuration of a display device according to embodiments of the present disclosure.

Referring to FIG. 1, the display device 100 according to embodiments of the present disclosure has a plurality of gate lines (GL) and data lines (DL) connected and a plurality of subpixels (SP) arranged in a matrix form. Display panel 110, a first gate driving circuit 120a that drives a plurality of gate lines GL on the left side of the display panel 110, and a first gate driving circuit 120a that drives a plurality of gate lines GL on the right side of the display panel 110 a second gate driving circuit 120b that supplies data voltages through a plurality of data lines DL, a data driving circuit 130 that supplies data voltages, and timing that controls the gate driving circuits 120a and 120b and the data driving circuit 130. It may include a controller 140 and a power management circuit 150.

The display panel 110 receives gate signals transmitted from the gate driving circuits 120a and 120b through a plurality of gate lines GL and a data voltage transmitted from the data driving circuit 130 through a plurality of data lines DL. Displays video based on

In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates, and operates in Twisted Nematic (TN) mode, Vertical Alignment (VA) mode, In Plane Switching (IPS) mode, and Fringe Field Switching (FFS) mode. ) mode, etc. may be operated in any known mode. On the other hand, in the case of an organic light emitting display, the display panel 110 may be implemented in a top emission method, a bottom emission method, or a dual emission method.

The display panel 110 may have a plurality of pixels arranged in a matrix form, and each pixel has subpixels (SP) of different colors, for example, white subpixel, red subpixel, green subpixel, and blue subpixel. It consists of, and each subpixel (SP) may be defined by a plurality of data lines (DL) and a plurality of gate lines (GL).

One subpixel (SP) is formed in the area where the data line (DL) intersects the gate line (GL), and includes a plurality of thin film transistors (TFT) and a data voltage to drive the subpixel (SP). It may include a light-emitting device such as an organic light-emitting diode that charges, a storage capacitor that is electrically connected to the light-emitting device to maintain a voltage, and the like.

For example, if the display device 100 with a resolution of 2,160 By 3,840 data lines (DL) connected to the gate line (GL) and four subpixels (WRGB), a total of 3,840 A subpixel (SP) will be placed at each point where ) and the data line (DL) intersect.

The gate driving circuits 120a and 120b are controlled by the timing controller 140, which sequentially outputs gate signals to a plurality of gate lines GL arranged on the display panel 110 to a plurality of subpixels SP. Controls the driving timing for

The gate signal may include a scan signal that controls the operation of the switching transistor constituting the subpixel (SP) and a light emission signal that controls the light emission section of the subpixel (SP).

In the display device 100 with a resolution of 2,160 can do. Alternatively, as in the case of sequentially outputting gate signals from the first gate line to the fourth gate line and then sequentially outputting the gate signals from the fifth gate line to the eighth gate line, four gate lines (GL) The case of sequentially outputting gate signals in units is called 4-phase driving. In other words, the case where the gate signal is sequentially output for each of the N gate lines (GL) can be referred to as N-phase driving.

At this time, the gate driving circuits 120a and 120b may include one or more gate driving integrated circuits (GDIC), and may be located on only one side of the display panel 110 or on both sides depending on the driving method. It may be located on the side. Alternatively, the gate driving circuit 120 may be built into the bezel area of the display panel 110 and implemented in a GIP (Gate In Panel) form.

Here, the case where the first gate driving circuit 120a is located on the left side of the display panel 110 and the second gate driving circuit 120b is located on the right side of the display panel 110 is shown as an example, and the first gate The driving circuit 120a and the second gate driving circuit 120b may be disposed at the same location.

The gate driving circuits 120a and 120b may include a scan driver that outputs a scan signal to the subpixel (SP) through a scan signal line and a light emitting driver that outputs a light emission signal to the subpixel (SP) through a light emission signal line. .

At this time, the scan signal line through which the scan signal is transmitted and the light emission signal line through which the light emission signal is transmitted may be collectively referred to as the gate line GL.

The gate driving circuits 120a and 120b can sequentially supply the scan signal and the light emission signal to the scan signal line and the light emission signal line by shifting the scan signal and the light emission signal using a shift register. At this time, the light emission driver can drive the display panel 110 at a constant duty ratio by repeatedly toggling the light emission signal during the display driving period under the control of the timing controller 140.

A plurality of gate driving integrated circuits (GDICs) constituting the gate driving circuits 120a and 120b may each include a scan driver and a light emission driver.

One frame period can be divided into a recording period in which data voltage is applied to each subpixel (SP) and recorded, and a light emission period in which the subpixel (SP) emits light at a preset duty ratio according to the light emission signal after the recording period. Generally, the light emitting signal causes the subpixel (SP) to emit light at a duty ratio of 50% or less during the light emission period. Since the recording section is approximately only one horizontal period (1H), most of one frame period corresponds to the light emission section.

The subpixel (SP) charges the data voltage to the storage capacitor during the recording period, and the subpixel (SP) repeatedly turns on and off according to the light emission signal. That is, the subpixel SP repeats turning on and off within one frame period, emitting light at a duty ratio of 50% or less and repeating On/Off.

In this way, the subpixel (SP) turns off and then emits light due to the voltage charged in the storage capacitor, thereby maintaining the same luminance during one frame period with a duty ratio of 50% or less without receiving additional data voltage during the light emission period after the recording period. You can display data as .

The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, the data voltage is output to each data line (DL) according to the timing when the scan signal is applied through the gate line (GL), and each subpixel connected to the data line (DL) according to the timing when the light emission signal is applied. (SP) displays a light emitting signal with brightness corresponding to the data voltage.

Likewise, the data driving circuit 130 may include one or more source driving integrated circuits (SDICs), which may use a Tape Automated Bonding (TAB) method or a Chip On Glass (COG) method. ) may be connected to a bonding pad of the display panel 110 or may be placed directly on the display panel 110.

In some cases, each source driving integrated circuit (SDIC) may be integrated and disposed on the display panel 110. In addition, each source driving integrated circuit (SDIC) may be implemented in a COF (Chip On Film) method. In this case, each source driving integrated circuit (SDIC) is mounted on a circuit film and displays the display panel through the circuit film. It may be electrically connected to the data line (DL) of (110).

The timing controller 140 supplies various control signals to the gate driving circuits 120a and 120b and the data driving circuit 130, and controls the operations of the gate driving circuits 120a and 120b and the data driving circuit 130. . That is, the timing controller 140 controls the output of the scan signal and the light emission signal of the gate driving circuits 120a and 120b according to the timing implemented in each frame, and on the other hand, controls the output of image data (DATA) received from the outside. It is transmitted to the data driving circuit 130.

At this time, the timing controller 140 includes video data (DATA), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable; DE), a main clock (MCLK), etc. Various timing signals are received from the external host system 200.

The host system 200 may be any one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, and a wearable device.

Accordingly, the timing controller 140 generates a control signal using various timing signals received from the host system 200 and transmits the control signal to the gate driving circuits 120a and 120b and the data driving circuit 130.

For example, the timing controller 140 uses various gate controls including a gate start signal (GVST), a gate clock (GCLK), a gate reset signal (GRST), etc. to control the gate driving circuits 120a and 120b. Output a signal. Here, the gate start signal GVST controls the timing at which one or more gate driving integrated circuits (GDIC) constituting the gate driving circuit 120 start operating. Additionally, the gate clock (GCLK) is a clock signal commonly input to one or more gate driving integrated circuits (GDIC), and controls the shift timing of the scan signal and the light emission signal. Additionally, the gate reset signal (GRST) specifies the reset timing of the scan driver and light emitting driver that constitute one or more gate driving integrated circuits (GDIC).

Additionally, the timing controller 140 outputs various data control signals including a data start signal (DVST), a data clock (DCLK), and a data reset signal (DRST) to control the data driving circuit 130. Here, the data start signal DVST controls the timing at which one or more source driving integrated circuits (SDICs) constituting the data driving circuit 130 start sampling data. Data clock (DCLK) is a clock signal that controls the timing of sampling data in a source driving integrated circuit (SDIC). The data reset signal DRST specifies the reset timing of the data driving circuit 130.

This display device 100 supplies various voltages or currents to the display panel 110, the gate driving circuits 120a and 120b, and the data driving circuit 130, or includes a power management circuit ( 150) may be included.

The power management circuit 150 adjusts the direct current input voltage (Vin) supplied from the host system 200 to provide the power required to drive the display panel 100, the gate driving circuits 120a and 120b, and the data driving circuit 130. occurs.

Meanwhile, the subpixel SP is located at a point where the gate line GL and the data line DL intersect, and a light emitting device may be disposed in each subpixel SP. For example, an organic light emitting display device includes a light emitting device such as an organic light emitting diode in each subpixel (SP), and can display an image by controlling the current flowing through the light emitting device according to the data voltage.

This display device 100 may be of various types such as a liquid crystal display, organic light emitting display, and plasma display panel.

Figure 2 is a system diagram of a display device according to embodiments of the present disclosure.

Referring to FIG. 2, the display device 100 according to embodiments of the present disclosure has a source driving integrated circuit (SDIC) included in the data driving circuit 130 that uses COF among various methods (TAB, COG, COF, etc.). It is implemented in a (Chip On Film) method, and the gate driving circuit 120 is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

When the gate driving circuit 120 is implemented in the GIP form, a plurality of gate driving integrated circuits (GDICa, GDICb) included in the gate driving circuit 120 may be formed directly in the bezel area of the display panel 110. At this time, the gate driving integrated circuit (GDICa, GDICb) generates various signals (clock signal, gate high signal, gate low signal, etc.) required for generating scan signals and light emitting signals through gate driving-related signal wiring arranged in the bezel area. can be supplied.

Likewise, one or more source driving integrated circuits (SDICs) included in the data driving circuit 130 may each be mounted on the source film (SF), and one side of the source film (SF) is electrically connected to the display panel 110. can be connected Additionally, wires for electrically connecting the source driving integrated circuit (SDIC) and the display panel 110 may be disposed on the source film SF.

This display device 100 includes at least one source printed circuit board (SPCB), control components, and various electrical components for circuit connection between a plurality of source driving integrated circuits (SDICs) and other devices. It may include a control printed circuit board (CPCB) for mounting devices.

At this time, the other side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted may be connected to at least one source printed circuit board (SPCB). That is, one side of the source film SF on which the source driving integrated circuit (SDIC) is mounted may be electrically connected to the display panel 110, and the other side may be electrically connected to the source printed circuit board (SPCB).

A timing controller 140 and a power management circuit 150 may be mounted on a control printed circuit board (CPCB). The timing controller 140 may control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 150 may supply driving voltage or current to the display panel 110, the data driving circuit 130, and the gate driving circuit 120, and may control the supplied voltage or current.

At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be connected circuitously through at least one connecting member, for example, a flexible printed circuit (FPC). , Flexible Flat Cable (FFC), etc. Additionally, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated and implemented as one printed circuit board.

The display device 100 may further include a set board (Set Board) 170 electrically connected to a control printed circuit board (CPCB). At this time, the set board 170 may also be referred to as a power board. A main power management circuit 160 that manages the entire power of the display device 100 may be present in this set board 170. The main power management circuit 160 may be interconnected with the power management circuit 150.

In the case of the display device 100 configured as above, the driving voltage is generated in the set board 170 and transmitted to the power management circuit 150 in the control printed circuit board (CPCB). The power management circuit 150 transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) through a flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage delivered to the source printed circuit board (SPCB) is supplied to emit or sense a specific subpixel (SP) in the display panel 110 through the source driving integrated circuit (SDIC).

At this time, each subpixel SP arranged on the display panel 110 in the display device 100 may be composed of a light emitting element and a circuit element such as a driving transistor for driving the same.

The type and number of circuit elements constituting each subpixel (SP) can be determined in various ways depending on the provided function and design method.

FIG. 3 is a diagram showing an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure.

Referring to FIG. 3, the display device 100 according to embodiments of the present disclosure may have n gate lines (GL) arranged in the active area (A/A) for displaying an image.

Here, the active area (A/A) is a plurality of subpixels (SP) for emitting light of the corresponding color, for example, a white subpixel, a red subpixel, a green subpixel, and a blue subpixel are arranged to produce an image. This is the area that displays . Additionally, a plurality of dummy pixels that do not emit light because the gate signal or data voltage (Vdata) is not applied but have a load similar to that of the subpixel (SP) may be located in some locations of the active area (A/A).

In embodiments of the present disclosure, an area in which a plurality of subpixel areas that emit light of a corresponding color and dummy pixels that do not emit light are disposed is referred to as an active area (A/A). Alternatively, it may be referred to as a pixel array, including a plurality of subpixel areas that emit light of a corresponding color and an area in which dummy pixels that do not emit light are disposed.

The gate driving circuit 120 is embedded and disposed in the bezel area (Bezel) where no pixels are formed on the left and right sides of the active area (A/A), and integrates n gate drives corresponding to n gate lines (GL). It may include a circuit (GDIC).

For example, the first gate driving integrated circuit (GDICa1, GDICb1) that supplies the gate signal through the first gate line (GL1) is located on the left side of the active area (A/A) where the first gate line (GL1) extends. It may include a left first gate driving integrated circuit (GDICa1) and a right first gate driving integrated circuit (GDICb1) disposed to the right of the active area (A/A).

In addition, the second gate driving integrated circuits (GDICa2, GDICb2) that supply gate signals through the second gate line (GL2) are disposed on the left side of the active area (A/A) where the second gate line (GL2) extends. It may include a second gate driving integrated circuit (GDICa2) on the left and a second gate driving integrated circuit (GDICb2) on the right disposed to the right of the active area (A/A).

In addition, the third gate driving integrated circuit (GDICa3, GDICb3) that supplies the gate signal through the third gate line (GL3) is disposed on the left side of the active area (A/A) where the third gate line (GL3) extends. It may include a third gate driving integrated circuit (GDICa3) on the left and a third gate driving integrated circuit (GDICb3) on the right disposed to the right of the active area (A/A).

In addition, the fourth gate driving integrated circuit (GDICa4, GDICb4) that supplies the gate signal through the fourth gate line (GL4) is disposed on the left side of the active area (A/A) where the fourth gate line (GL4) extends. It may include a fourth gate driving integrated circuit (GDICa4) on the left and a fourth gate driving integrated circuit (GDICb4) on the right arranged to the right of the active area (A/A).

At this time, the first gate driving integrated circuit (GDICa1) on the left to the fourth gate driving integrated circuit (GDICa4) on the left arranged to the left of the active area (A/A) are referred to as the left gate driving integrated circuit (GDICa). , the right first gate driving integrated circuit (GDICb1) to the right fourth gate driving integrated circuit (GDICb4) disposed on the right side of the active area (A/A) may be referred to as the right gate driving integrated circuit (GDICb). will be.

At this time, each gate driving integrated circuit (GDIC) includes a scan driver (SCD) that supplies a scan signal through the gate line (GL) and an emission driver (EMD) that supplies a light emission signal through the gate line (GL). It can be included.

For example, the first gate driving integrated circuit (GDICa1, GDICb1) includes first scan drivers (SCDa1, SCDb1) that supply the first scan signal through the first gate line (GL1), and a first gate line (GL1) may each include first light emission drivers (EMDa1 and EMDb1) that supply the first light emission signal through . Additionally, the second gate driving integrated circuit (GDICa2, GDICb2) includes second scan drivers (SCDa2, SCDb2) that supply a second scan signal through the second gate line (GL2), and a second scan signal through the second gate line (GL1). Each may include second light emission drivers (EMDa2 and EMDb2) that supply a second light emission signal.

The n gate driving integrated circuit (GDIC) can output scan signals and light emission signals through n gate lines (GL). Here, the gate line GL is shown to include a scan line to which a scan signal is supplied and a light emission signal line to which a light emission signal is supplied.

In this way, when the gate driving circuit 120 is implemented as a GIP type, there is no need to manufacture a separate integrated circuit with a gate driving function or a light emission driving function and bond it to the display panel 110, so the integrated circuit The number can be reduced and the process of connecting the integrated circuit to the display panel 110 can be omitted. Additionally, the size of the bezel area (Bezel) that bonds the integrated circuit in the display panel 110 can be reduced.

At this time, n gate driving integrated circuits (GDIC) may be arranged on both sides of the active area (A/A), but may also be arranged on one side of the display panel 110.

On one side of the active area (A/A), the gate clock (GCLK) required for generation and output of the gate signal (scan signal and light emission signal) is transmitted to the gate driving circuit 120 in the bezel area (Bezel) where pixels are not formed. A plurality of clock lines may be arranged to do this.

Figure 4 is a diagram showing an example of a subpixel circuit of a display device according to embodiments of the present disclosure.

Referring to FIG. 4, the subpixel (SP) of the display device 100 according to embodiments of the present disclosure includes first to sixth switching transistors (T1 - T6), a driving transistor (DRT), and a storage capacitor (Cst). , and may include a light emitting element (ED).

Here, the light emitting device (ED) may be a self-light emitting device that can emit light on its own, such as an organic light emitting diode (OLED).

In the subpixel SP according to embodiments of the present disclosure, the second to fourth switching transistors T2-T4, the sixth switching transistor T6, and the driving transistor DRT may be P-type transistors. Additionally, the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

P-type transistors are relatively more reliable than N-type transistors. In the case of a P-type transistor, there is an advantage that the current flowing through the light emitting device (ED) is not shaken by the capacitor (Cst) because the drain electrode is fixed to the high potential driving voltage (VDD). Therefore, it is easy to supply current stably.

For example, the P-type transistor may be connected to the anode electrode of the light emitting device (ED). At this time, when the transistors (T4, T6) connected to the light emitting device (ED) operate in the saturation region, a constant current can flow regardless of changes in the current and threshold voltage of the light emitting device (ED), so reliability is high. Relatively high.

In this subpixel (SP) structure, the N-type transistors T1 and T5 are oxide transistors formed using a semiconducting oxide (e.g., a channel formed from a semiconducting oxide such as indium, gallium, zinc oxide, or IGZO). transistors), and other P-type transistors (DRT, T2-T4, T6) are silicon transistors formed from semiconductors such as silicon (e.g., formed using a low-temperature process referred to as LTPS or low-temperature polysilicon). transistor with a polysilicon channel).

Oxide transistors have a relatively lower leakage current than silicon transistors, so when implementing a transistor using an oxide transistor, current leakage from the gate electrode of the driving transistor (DRT) is prevented, thereby improving image quality such as flicker. It has the effect of reducing defects.

Meanwhile, the remaining P-type transistors (DRT, T2-T4, T6), excluding the first switching transistor (T1) and the fifth switching transistor (T5) corresponding to the N-type transistors, may be made of low-temperature polysilicon.

The gate electrode of the first switching transistor T1 receives the first scan signal SCAN1. The drain electrode of the first switching transistor (T1) is connected to the gate electrode of the driving transistor (DRT).

The source electrode of the first switching transistor (T1) is connected to the source electrode of the driving transistor (DRT).

The first switching transistor T1 is turned on by the first scan signal SCAN1 and controls the operation of the driving transistor DRT through the high potential driving voltage VDD stored in the storage capacitor Cst.

The first switching transistor T1 may be made of an N-type MOS transistor to form an oxide transistor. Because the N-type MOS transistor uses electrons rather than holes as carriers, the mobility is faster than the P-type MOS transistor, so the switching speed can be fast.

The gate electrode of the second switching transistor T2 receives the second scan signal SCAN2. The drain electrode of the second switching transistor T2 may be supplied with a data voltage (Vdata) or a bias voltage (VOBS). The source electrode of the second switching transistor (T2) is connected to the drain electrode of the driving transistor (DRT).

The second switching transistor T2 is turned on by the second scan signal SCAN2 and supplies the data voltage Vdata to the drain electrode of the driving transistor DRT.

The gate electrode of the third switching transistor T3 receives the light emission signal EM. The drain electrode of the third switching transistor (T3) is supplied with a high potential driving voltage (VDD). The source electrode of the third switching transistor (T3) is connected to the drain electrode of the driving transistor (DRT).

The third switching transistor T3 is turned on by the light emission signal EM and supplies the high potential driving voltage VDD to the drain electrode of the driving transistor DRT.

The gate electrode of the fourth switching transistor T4 receives the light emission signal EM. The drain electrode of the fourth switching transistor (T4) is connected to the source electrode of the driving transistor (DRT). The source electrode of the fourth switching transistor (T4) is connected to the anode electrode of the light emitting element (ED).

The fourth switching transistor T4 is turned on by the light emission signal EM to supply a driving current to the anode electrode of the light emitting element ED.

The gate electrode of the fifth switching transistor T5 receives the third scan signal SCAN3.

Here, the third scan signal SCAN3 may be the first scan signal SCAN1 supplied to the subpixel SP at a different location. For example, when the first scan signal (SCAN1) is applied to the n-th gate line, the third scan signal (SCAN3) is the first scan signal (SCAN1[n-9]) applied to the n-9th gate line. It can be. That is, the third scan signal SCAN3 may use the first scan signal SCAN1 that varies the gate line GL depending on the phase in which the display panel 110 is driven.

The drain electrode of the fifth switching transistor (T5) is supplied with the initialization voltage (Vini). The source electrode of the fifth switching transistor (T5) is connected to the gate electrode of the driving transistor (DRT) and the storage capacitor (Cst).

The fifth switching transistor T5 is turned on by the third scan signal SCAN3 and supplies the initialization voltage Vini to the gate electrode of the driving transistor DRT.

The gate electrode of the sixth switching transistor T6 receives the second scan signal SCAN2 together with the second switching transistor T2.

The drain electrode of the sixth switching transistor (T6) is supplied with a reset voltage (VAR). The source electrode of the sixth switching transistor (T6) is connected to the anode electrode of the light emitting element (ED).

The sixth switching transistor T6 is turned on by the second scan signal SCAN2 and supplies the reset voltage VAR to the anode electrode of the light emitting device ED.

The gate electrode of the driving transistor (DRT) is connected to the drain electrode of the first switching transistor (T1). The drain electrode of the driving transistor (DRT) is connected to the source electrode of the second switching transistor (T2). The source electrode of the driving transistor (DRT) is connected to the source electrode of the first switching transistor (T1).

The driving transistor DRT is turned on by the voltage difference between the source electrode and the drain electrode of the first switching transistor T1, and a driving current is applied to the light emitting element ED.

A high-potential driving voltage (VDD) is applied to one side of the storage capacitor (Cst), and the other side is connected to the gate electrode of the driving transistor (DRT). The storage capacitor (Cst) stores the voltage of the gate electrode of the driving transistor (DRT).

The anode electrode of the light emitting element (ED) is connected to the source electrode of the fourth switching transistor (T4) and the source electrode of the sixth switching transistor (T6). A low potential driving voltage (VSS) is applied to the cathode electrode of the light emitting device (ED).

The light emitting element (ED) emits light with a predetermined brightness by a driving current flowing through the driving transistor (DRT).

At this time, the initialization voltage (Vini) is supplied to stabilize the change in capacitance formed on the gate electrode of the driving transistor (DRT), and the reset voltage (VAR) is supplied to reset the anode electrode of the light emitting element (ED). supplied.

The fourth switching transistor (T4), located between the anode electrode of the light emitting device (ED) and the driving transistor (DRT) and controlled by the light emitting signal (EM), is turned off and applied to the anode electrode of the light emitting device (ED). When supplying the reset voltage VAR, the anode electrode of the light emitting element ED may be reset.

The sixth switching transistor (T6) that supplies the reset voltage (VAR) is connected to the anode electrode of the light emitting device (ED).

A third scan signal ( SCAN3) and the second scan signal (SCAN2) for controlling the supply of the reset voltage (VAR) to the anode electrode of the light emitting device (ED) are separated from each other.

At this time, when turning on the switching transistors (T5, T6) that supply the initialization voltage (Vini) and reset voltage (VAR), the source electrode of the driving transistor (DRT) and the anode electrode of the light emitting element (ED) are connected. The fourth switching transistor (T4) is turned off to block the driving current of the driving transistor (DRT) from flowing to the anode electrode of the light emitting element (ED), and the anode electrode is blocked by a voltage other than the reset voltage (VAR). Subpixels (SP) can be configured so that there is no effect.

In this way, the subpixel (SP) consisting of seven transistors (DRT, T1, T2, T3, T4, T5, T6) and one capacitor (Cst) can be referred to as a 7T1C structure.

Here, the 7T1C structure is shown as an example among the various structures of subpixel (SP) circuits, and the structure and number of transistors and capacitors that make up the subpixel (SP) may be changed in various ways. Meanwhile, each of the plurality of subpixels (SP) may have the same structure, or some of the plurality of subpixels (SP) may have a different structure.

FIG. 5 is a diagram illustrating the configuration of a gate driving integrated circuit for driving a subpixel circuit in a display device according to embodiments of the present disclosure.

Here, the case of supplying the first to third scan signals SCAN1 to SCAN3 and the emission signal EM to drive the subpixel circuit of FIG. 4 is shown as an example.

Referring to FIG. 5 , the display device 100 according to embodiments of the present disclosure may have a plurality of subpixels SP disposed along an area where the first gate line GL1 is located.

A plurality of subpixels SP arranged along the area where the first gate line GL1 is located can be operated by the first gate signal supplied through the first gate line GL1, so the first subpixel line (SP) It can be called SPL1). Accordingly, the first subpixel line SPL1 can be operated by the first gate driving integrated circuit GDICa1 on the left and the first gate driving integrated circuit GDICb1 on the right.

For example, the first gate driving integrated circuit (GDICa1) on the left side supplies the first scan signal (SCAN1) to the third scan signal (SCAN3) on the left side, and the first scan driver (SCDa1) on the left side supplies a light emitting signal on the left side. It may include a first light emitting driver (EMDa1) on the left that supplies (EM).

In addition, the first gate driving integrated circuit (GDICb1) on the right side supplies the first scan signal (SCAN1) to the third scan signal (SCAN3) on the right side, and the first scan driver (SCDb1) on the right side supplies the light emission signal (EM) on the right side. ) may include a first light emitting driver (EMDb1) on the right side that supplies light.

The first scan driver (SCDa1) on the left and the first scan driver (SCDb1) on the right can supply the first scan signal (SCAN1) to the third scan signal (SCAN3) to the first subpixel line (SPL1) at the same timing. there is.

Additionally, the first light emission driver (EMDa1) on the left and the first light emission driver (EMDb1) on the right may supply the light emission signal (EM) to the first subpixel line (SPL1) at the same timing.

At this time, one frame period for displaying an image on the display panel 110 is a recording section in which the data voltage (Vdata) is applied to each subpixel (SP) and recorded, and a recording section is recorded in advance according to the emission signal (EM) after the recording section. It can be divided into light emission sections in which the subpixel (SP) emits light at a set duty ratio.

Generally, the light emitting signal causes the subpixel (SP) to emit light at a duty ratio of 50% or less during the light emission period. At this time, since the recording section is approximately only one horizontal period (1H), most of one frame period corresponds to the light emission section.

Accordingly, the stress of the light emitting driver (EMD) that supplies the light emitting signal (EM) may rapidly increase as the driving time of the display device 100 increases.

The display device 100 of the present disclosure can reduce stress and improve image quality by alternately driving a plurality of light emitting drivers (EMD) connected to the same gate line (GL) on a frame basis.

FIG. 6 is a diagram illustrating the circuit configuration of a light emitting driver in a display device according to embodiments of the present disclosure.

Referring to FIG. 6, in the display device 100 according to embodiments of the present disclosure, the left and right light emitting drivers (EMD) connected to the same gate line (GL) control the charging and discharging of the Q node (Q). A Q node control unit 122 that controls charging and discharging of the QB node (QB), a QB node control unit 124 that controls charging and discharging of the QB node (QB), a carry signal output unit 126 that generates a carry signal (CRY), and a light emitting signal (EM) that generates It may include a light emitting signal output unit 128.

The Q node control unit 122 may include a first transistor (T1), a 1a transistor (T1a), a 2q transistor (T2q), and a 3q transistor (T3q).

The first transistor (T1) and the first transistor (T1a) may be made of a transistor with a dual gate structure, and charge the Q node (Q) to the potential of the light emission start signal (EVST) in response to the light emission clock signal (ECLK). It plays a role. The light emission start signal (EVST) may use a light emission signal output through the output terminal of the light emission driver (EMD) located at the front end.

The 2q transistor (T2q) is connected between the Q node (Q) and the first low-potential voltage (EVSS1), and changes the potential of the Q node (Q) to the first low-potential voltage (EVSS1) by the alternating control signal (ALT). It plays a role in discharging. Therefore, when a low-level alternating control signal (ALT) is applied to the light emitting driver (EMD), the light emitting driver (EMD) maintains the turn-on state and the light emitting signal (EM) can be output at a high level. When the alternating level control signal (ALT) is applied, the light emitting driver (EMD) is turned off and the high level light emitting signal (EM) is not output.

The 3q transistor T3q is turned on when the potential of the Q node Q is at a high level and supplies the first high potential voltage EVDD1 to the common node of the first transistors T1 and T1a. When the first high potential voltage EVDD1 is supplied to the common node of the first transistors T1 and T1a, the voltage difference between the gate voltage of the first transistors T1 and T1a and the common node increases.

Therefore, when the low-level emission clock signal (ECLK) is input to the gate node of the first transistor (T1, T1a) and the first transistor (T1, T1a) is turned off, the gate of the first transistor (T1, T1a) Due to the voltage difference between the voltage and the common node, the first transistors T1 and T1a may be maintained in a completely turned-off state. Accordingly, current leakage of the first transistors (T1, T1a) and the resulting voltage drop of the Q node (Q) are prevented, so that the voltage of the Q node (Q) can be maintained stably.

The QB node control unit 124 may include a fourth transistor (T4), a 41st transistor (T41), a 5th transistor (T5), a 5q transistor (T5q), and a 2qb transistor (T2qb).

The 41st transistor T41 is turned on by the emission reset signal ERST and transmits the first high potential voltage EVDD1.

The fourth transistor T4 is connected between the first high potential voltage EVDD1 and the QB node QB, and the gate node is connected to the drain node of the 41st transistor T41. Additionally, a first capacitor C1 is connected between the gate node of the fourth transistor T4 and the QB node QB. The fourth transistor T4 is turned on by the voltage charged in the first capacitor C1 and supplies the first high potential voltage EVDD1 to the QB node QB.

The first capacitor C1 serves to turn on the fourth transistor T4 in synchronization with the emission reset signal ERST applied to the gate node of the 41st transistor T41.

The fifth transistor T5 and the 5q transistor T5q are connected in series between the gate node of the fourth transistor T4 and the first low potential voltage EVSS1, and the fifth transistor T5 and the 5q transistor ( The common node of T5q) is connected to the QB node (QB). Since the gate nodes of the fifth transistor (T5) and the 5q transistor (T5q) are connected to the Qh node (Qh), the gate node of the fourth transistor (T4) and the QB node ( QB) is discharged to the first low potential voltage (EVSS1) level.

The 2qb transistor (T2qb) is connected between the QB node (QB) and the first low-potential voltage (EVSS1), and changes the potential of the QB node (QB) to the first low-potential voltage (EVSS1) by the alternating control signal (ALT). It plays a role in discharging. Therefore, when the high-level alternating control signal (ALT) is applied to the light emitting driver (EMD), the light emitting driver (EMD) is turned off and the high-level light emitting signal (EM) is not output.

The carry signal output unit 126 includes a sixth pull-up transistor (T6u) and a sixth pull-down transistor (T6d).

The sixth pull-up transistor T6u is connected between the first high potential voltage EVDD1 and the carry signal output node.

The sixth pull-up transistor T6u outputs a high-level carry signal CRY through the carry signal output node based on the first high potential voltage EVDD1 in response to the voltage of the Q node Q. The sixth pull-up transistor T6u is turned on when the voltage of the Q node Q is at a high level and transmits the first high potential voltage EVDD1 at a high level. Accordingly, a high-level carry signal (CRY) is output.

The sixth pull-down transistor (T6d) is connected between the carry signal output node and the first low-potential voltage (EVSS1).

The sixth pull-down transistor T6d outputs a low-level carry signal CRY through the carry signal output node based on the first low potential voltage EVSS1 in response to the voltage of the QB node QB. The sixth pull-down transistor T6d is turned on when the voltage of the QB node QB is at a high level and supplies the first low potential voltage EVSS1. Accordingly, a low-level carry signal (CRY) is output.

The light emitting signal output unit 128 includes a seventh pull-up transistor T7u, a seventh pull-down transistor T7d, and a second capacitor C2.

The seventh pull-up transistor T7u is connected between the second high potential voltage EVDD2 and the light emitting signal output node.

The seventh pull-up transistor T7u outputs a high-level light emitting signal EM through the light emitting signal output node based on the second high potential voltage EVDD2 in response to the voltage of the Q node Q. The seventh pull-up transistor T7u is turned on when the voltage of the Q node Q is at a high level and transmits the second high-level voltage EVDD2. Accordingly, a high-level emission signal (EM) is output.

The seventh pull-down transistor T7d is connected between the light emitting signal output node and the second low-potential voltage EVSS2.

The seventh pull-down transistor T7d outputs a low-level light emitting signal EM through the light emitting signal output node based on the second low potential voltage EVSS2 in response to the voltage of the QB node QB. The seventh pull-down transistor T7d is turned on when the voltage of the QB node QB is at a high level and supplies the second low potential voltage EVSS2. Accordingly, a low-level emission signal (EM) is output.

The second capacitor C2 is connected between the gate node of the seventh pull-up transistor T7u and the light emitting signal output node.

When the light emitting signal (EM) is output, the second capacitor (C2) is synchronized with the high level of the second high potential voltage (EVDD2) and raises the voltage of the Q node (Q) to a level lower than the level of the first high potential voltage (EVDD1). Bootstrap to a high boosting voltage level. When the voltage of the Q node (Q) is bootstrapped, the high-level second high potential voltage (EVDD2) can be output as the light emitting signal (EM) quickly and without distortion.

As such, the display device 100 of the present disclosure includes a 2q transistor (T2q) connected between the Q node (Q) and the first low-potential voltage (EVSS1), and a QB node (QB) and the first low-potential voltage (EVSS1). ) The operation of the light emitting driver (EMD) can be controlled using the 2qb transistor (T2qb) connected between.

At this time, in order to control the operation of the light emitting driver (EMD), the 2q transistor (T2q) connected between the Q node (Q) and the first low potential voltage (EVSS1) may be used, and the 2q transistor (T2q) connected between the Q node (QB) and the first low potential voltage (EVSS1) may be used. 1 The 2qb transistor (T2qb) connected between the low potential voltage (EVSS1) may be used. That is, the light emitting driver (EMD) of the present disclosure may include both the 2q transistor (T2q) and the 2qb transistor (T2qb), or may include only one of the 2q transistor (T2q) and the 2qb transistor (T2qb). there is.

In short, the display device 100 of the present disclosure includes the 2q transistor (T2q) or the 2qb transistor ( By alternating driving through T2qb), the stress caused by the operation of the light emitting driver (EMD) can be alleviated.

FIG. 7 is a diagram illustrating a structure in which light emitting drivers sharing the same gate line are alternately operated in a display device according to embodiments of the present disclosure, and FIG. 8 is a diagram showing a structure in which light emitting drivers sharing the same gate line are alternately operated in a display device according to embodiments of the present disclosure. This diagram shows an example of a signal flow diagram when the light emitting drivers sharing a gate line are operated alternately.

7 and 8, in the display device 100 according to embodiments of the present disclosure, a gate driving integrated circuit for driving a subpixel line located in an area where one gate line extends is located on the left side of the display panel. and may be located on both sides of the right side.

Accordingly, the left scan driver and the right scan driver included in the gate driving integrated circuit sharing the same gate line can supply a scan signal to the same subpixel line through the same scan line.

Additionally, the left light emission driver and the right light emission driver included in the gate driving integrated circuit sharing the same gate line may supply a light emission signal to the same subpixel line through the same light emission signal line.

For ease of understanding, only the light emitting driver that supplies the light emitting signal to the subpixel line is shown here.

For example, the first light emission driver EMDa1 on the left and the first light emission driver EMDb1 on the right may supply the first light emission signal to the first subpixel line SPL1 through the first light emission signal line. Additionally, the second light emission driver (EMDa2) on the left and the second light emission driver (EMDb2) on the right may supply a second light emission signal to the second subpixel line (SPL2) through the second light emission signal line. Additionally, the third light emission driver (EMDa3) on the left and the third light emission driver (EMDb3) on the right may supply a third light emission signal to the third subpixel line (SPL3) through the third light emission signal line. Additionally, the fourth light emission driver (EMDa4) on the left and the fourth light emission driver (EMDb4) on the right can supply the fourth light emission signal to the fourth subpixel line (SPL4) through the fourth light emission signal line.

The display device 100 of the present disclosure can reduce stress on the light emitting driver by alternately driving the left light emitting driver (EMDa) and the right light emitting driver (EMDb) connected to the same light emitting signal line.

For example, during the N frame (Frame N), the right emission driver (EMDb) is turned off and the left emission driver (EMDa) is turned on, so that the subpixel line emits light only through the left emission driver (EMDa). A signal (EM) can be supplied.

The left light emitting driver (EMDa) can operate normally by applying the left alternating control signal (ALTb) at a low level during N frames (Frame N). On the other hand, the right light emitting driver (EMDb) can be turned off by applying the right alternating control signal (ALTb) at a high level during N frames (Frame N).

Accordingly, the right light emitting driver (EMDb) is turned off for N frames (Frame N), thereby reducing stress.

Figure 8 shows a signal flow diagram when the left light emitting driver (EMDa) is turned on and operates normally, and the right light emitting driver (EMDb) is turned off during N frames (Frame N).

On the other hand, during the N+1 frame (Frame N+1), the left light emitting driver (EMDa) is turned off and the right light emitting driver (EMDb) is turned on, so that the subpixel line is transmitted only through the right light emitting driver (EMDb). An luminescent signal (EM) can be supplied to. Accordingly, the left light emitting driver (EMDa) is turned off during N+1 frames (Frame N+1), thereby reducing stress.

Meanwhile, the display device 100 according to embodiments of the present disclosure may simultaneously supply light emitting signals to two adjacent subpixel lines by having one light emitting driver share two adjacent light emitting signal lines.

FIG. 9 is a diagram illustrating an example of a structure in which light emitting drivers share adjacent light emitting signal lines in a display device according to embodiments of the present disclosure.

Referring to FIG. 9, the display device 100 according to embodiments of the present disclosure is provided on the left and right sides of the display panel in order to simultaneously supply a scan signal to one subpixel line arranged in the direction in which the gate line extends. A scan driver can be deployed. Additionally, in order to simultaneously supply light emitting signals to one subpixel line, light emitting drivers can be placed on the left and right sides of the display panel.

At this time, since the scan driver controls the driving timing of the subpixel line, the left scan driver and the right scan driver need to be arranged to correspond to one subpixel line. On the other hand, since the light emission driver controls the light emission time of the subpixel line, adjacent subpixel lines can be shared as needed.

For example, the first scan driver (SCDa1) on the left and the first scan driver (SCDb1) on the right may be arranged to simultaneously supply scan signals (SCAN1, SCAN2, and SCAN3) to the first subpixel line (SPL1). . Additionally, the second scan driver SCDa2 on the left and the second scan driver SCDb2 on the right may be arranged to simultaneously supply scan signals SCAN4, SCAN5, and SCAN6 to the second subpixel line SPL2. Here, assuming the subpixel circuit shown in FIG. 4, a case in which three scan signals are supplied to one subpixel is shown as an example.

On the other hand, the first light emission driver (EMDa1) on the left and the first light emission driver (EMDb1) on the right share the first light emission signal line and the second light emission signal line, so that the first subpixel line (SPL1) and the second subpixel It can be arranged to simultaneously supply the light emitting signal (EM) to the line (SPL2).

In this way, when one light emitting driver shares two adjacent subpixel lines, the number and area of light emitting drivers can be reduced.

The display device 100 of the present disclosure can relieve stress caused by the operation of the light emitting driver by alternately driving the left light emitting driver and the right light emitting driver in a state where one light emitting driver shares two adjacent subpixel lines. You can.

FIG. 10 is a diagram illustrating a structure for alternately driving light emitting drivers sharing adjacent subpixel lines in a display device according to embodiments of the present disclosure, and FIG. 11 is a diagram illustrating a structure of alternately driving light emitting drivers sharing adjacent subpixel lines in a display device according to embodiments of the present disclosure. This diagram shows an example of a signal flow diagram in the case of alternately driving light emitting drivers sharing adjacent subpixel lines.

10 and 11, in the display device 100 according to embodiments of the present disclosure, a gate driving integrated circuit for driving a subpixel line located in an area where one gate line extends is located on the left side of the display panel. and may be located on both sides of the right side.

Accordingly, the left and right scan drivers that share the same scan line can supply scan signals to the same subpixel line through the same scan line.

Additionally, the light emission driver on the left and the light emission driver on the right, which share the same light emission signal line, can supply a light emission signal to the same subpixel line through the same light emission signal line.

At this time, the light emitting driver may share the light emitting signal line that supplies the light emitting signal to adjacent subpixel lines.

For example, the first light emission driver (EMDa1) on the left and the first light emission driver (EMDb1) on the right share the first light emission signal line and the second light emission signal line, so that the first subpixel line (SPL1) and the second light emission signal line It may be arranged to simultaneously supply light emitting signals to the subpixel line SPL2. In addition, the second light emission driver (EMDa2) on the left and the second light emission driver (EMDb2) on the right share the third light emission signal line and the fourth light emission signal line, so that the third subpixel line (SPL3) and the fourth subpixel It can be arranged to simultaneously supply a light emitting signal to the line SPL4.

For ease of understanding, only the light emitting driver that supplies the light emitting signal to the subpixel line is shown here.

Since the first light emission driver (EMDa1) on the left and the first light emission driver (EMDb1) on the right share the first light emission signal line and the second light emission signal line, the first subpixel line (SPL1) and the second subpixel line (SPL2) can supply a light emitting signal. In addition, since the second light emission driver (EMDa2) on the left and the second light emission driver (EMDb2) on the right share the third light emission signal line and the fourth light emission signal line, the third subpixel line (SPL3) and the fourth subpixel line (SPL3) A light emitting signal can be supplied to the pixel line (SPL4).

The display device 100 of the present disclosure can reduce stress on the light emitting driver by alternately driving the left light emitting driver (EMDa) and the right light emitting driver (EMDb) connected to the same light emitting signal line.

For example, during the N frame (Frame N), the right emission driver (EMDb) is turned off and the left emission driver (EMDa) is turned on, so that the subpixel line emits light only through the left emission driver (EMDa). A signal (EM) can be supplied.

The left light emitting driver (EMDa) can operate normally by applying the left alternating control signal (ALTb) at a low level during N frames (Frame N). On the other hand, the right light emitting driver (EMDb) can be turned off by applying the right alternating control signal (ALTb) at a high level during N frames (Frame N).

Accordingly, the right light emitting driver (EMDb) is turned off for N frames (Frame N), thereby reducing stress.

Figure 11 shows a signal flow diagram when the left light emitting driver (EMDa) is turned on and operates normally, and the right light emitting driver (EMDb) is turned off during N frames (Frame N).

On the other hand, during the N+1 frame (Frame N+1), the left light emitting driver (EMDa) is turned off and the right light emitting driver (EMDb) is turned on, so that the subpixel line is transmitted only through the right light emitting driver (EMDb). An luminescent signal (EM) can be supplied to. Accordingly, the left light emitting driver (EMDa) is turned off during N+1 frames (Frame N+1), thereby reducing stress.

Additionally, the display device 100 according to embodiments of the present disclosure may simultaneously supply light emitting signals to two adjacent subpixel lines by having two light emitting drivers share two adjacent light emitting signal lines.

FIG. 12 is a diagram illustrating an example of a structure in which two light-emitting drivers share two adjacent light-emitting signal lines in a display device according to embodiments of the present disclosure.

Referring to FIG. 12, the display device 100 according to embodiments of the present disclosure is provided on the left and right sides of the display panel in order to simultaneously supply a scan signal to one subpixel line arranged in the direction in which the gate line extends. A scan driver can be deployed. Additionally, in order to simultaneously supply light emitting signals to one subpixel line, light emitting drivers can be placed on the left and right sides of the display panel.

At this time, since the scan driver controls the driving timing of the subpixel line, the left scan driver and the right scan driver need to be arranged to correspond to one subpixel line. On the other hand, since the light emission driver controls the light emission time of the subpixel line, adjacent subpixel lines can be shared as needed.

For example, the first scan driver (SCDa1) on the left and the first scan driver (SCDb1) on the right may be arranged to simultaneously supply scan signals (SCAN1, SCAN2, and SCAN3) to the first subpixel line (SPL1). . Additionally, the second scan driver SCDa2 on the left and the second scan driver SCDb2 on the right may be arranged to simultaneously supply scan signals SCAN4, SCAN5, and SCAN6 to the second subpixel line SPL2. Here, assuming the subpixel circuit shown in FIG. 4, a case in which three scan signals are supplied to one subpixel is shown as an example.

On the other hand, the first light emission driver (EMDa1) on the left and the first light emission driver (EMDb1) on the right share the first light emission signal line and the second light emission signal line, so that the first subpixel line (SPL1) and the second subpixel It can be arranged to simultaneously supply the light emitting signal (EM) to the line (SPL2).

In addition, the second light emission driver (EMDa2) on the left and the second light emission driver (EMDb2) on the right also share the first light emission signal line and the second light emission signal line, so that the first subpixel line (SPL1) and the second subpixel It can be arranged to simultaneously supply the light emitting signal (EM) to the line (SPL2).

In this way, when one light emitting driver shares two adjacent subpixel lines, the number and area of light emitting drivers can be reduced.

The display device 100 of the present disclosure can alleviate the stress caused by the operation of the light emitting driver by alternately driving the left light emitting driver and the right light emitting driver in a state where the two light emitting drivers share two adjacent subpixel lines. You can.

FIG. 13 is a diagram illustrating a structure for alternately driving two light-emitting drivers sharing adjacent subpixel lines in a display device according to embodiments of the present disclosure, and FIG. 14 is a diagram illustrating a display device according to embodiments of the present disclosure. , is a diagram illustrating an example of a signal flow when two light emitting drivers sharing adjacent subpixel lines are alternately driven.

13 and 14, in the display device 100 according to embodiments of the present disclosure, a gate driving integrated circuit for driving a subpixel line located in an area where one gate line extends is located on the left side of the display panel. and may be located on both sides of the right side.

Accordingly, the left and right scan drivers that share the same scan line can supply scan signals to the same subpixel line through the same scan line.

Additionally, the light emission driver on the left and the light emission driver on the right, which share the same light emission signal line, can supply a light emission signal to the same subpixel line through the same light emission signal line.

At this time, the two light emitting drivers may share a light emitting signal line that supplies a light emitting signal to adjacent subpixel lines.

For example, the first light emission driver (EMDa1) on the left and the first light emission driver (EMDb1) on the right share the first light emission signal line and the second light emission signal line, so that the first subpixel line (SPL1) and the second light emission signal line It may be arranged to simultaneously supply light emitting signals to the subpixel line SPL2. At this time, the second light emission driver (EMDa2) on the left and the second light emission driver (EMDb2) on the right also share the first light emission signal line and the second light emission signal line, so that the first subpixel line (SPL1) and the second subpixel line (SPL1) It may be arranged to simultaneously supply a light emitting signal to the pixel line SPL2.

For ease of understanding, only the light emitting driver that supplies the light emitting signal to the subpixel line is shown here.

In this case, since the first light emission driver (EMDa1) on the left and the first light emission driver (EMDb1) on the right share the first light emission signal line and the second light emission signal line, the first subpixel line (SPL1) and the second light emission signal line A light emitting signal can be supplied to the subpixel line (SPL2). In addition, since the second light emission driver (EMDa2) on the left and the second light emission driver (EMDb2) on the right also share the first light emission signal line and the second light emission signal line, the first subpixel line (SPL1) and the second subpixel line (SPL1) A light emitting signal can be supplied to the pixel line (SPL2).

In the display device 100 of the present disclosure, since the odd-numbered light-emitting driver (eg, EMDa1) and the even-numbered light-emitting driver (eg, EMDa2) simultaneously share two adjacent light-emitting signal lines, they use the same light-emitting signal line. By alternately driving the shared odd-numbered light-emitting driver (EMD_Odd) and even-numbered light-emitting driver (EMD_Even), the stress on the light-emitting driver can be reduced.

For example, during N frames (Frame N), the even-numbered emission driver (EMD_Even) is turned off and the odd-numbered emission driver (EMD_Odd) is turned on, so that the subpixel line emits light only through the odd-numbered emission driver (EMD_Odd). A signal (EM) can be supplied.

The odd-numbered light emitting driver (EMD_Odd) can operate normally by applying the odd-numbered alternating control signal (ALT_Odd) at a low level during N frames (Frame N). On the other hand, the even-numbered light emitting driver (EMD_Even) can be turned off by applying the even-numbered alternating control signal (ALT_Even) at a high level during N frames (Frame N).

Accordingly, since the even-numbered light emitting driver (EMD_Even) is turned off for N frames (Frame N), stress can be reduced.

Figure 14 shows a signal flow diagram when the odd-numbered light emitting driver (EMD_Odd) is turned on and operates normally, and the even-numbered light emitting driver (EMD_Even) is turned off during N frames (Frame N).

On the other hand, during the N+1 frame (Frame N+1), the odd-numbered emission driver (EMD_Odd) is turned off and the even-numbered emission driver (EMD_Even) is turned on, so that the subpixel line is transmitted only through the even-numbered emission driver (EMD_Even). An luminescent signal (EM) can be supplied to. Accordingly, the odd-numbered light emitting driver (EMD_Odd) is turned off for N+1 frames (Frame N+1), thereby reducing stress.

FIG. 15 is a diagram showing an example of a signal waveform when a light emitting driver alternates turn-on and turn-off operations in a display device according to embodiments of the present disclosure.

Referring to FIG. 15, in the display device 100 according to embodiments of the present disclosure, a plurality of light emitting drivers that supply the light emitting signal (EM) to the subpixel line by sharing the same light emitting signal line supply the light emitting signal to the subpixel line. It may alternately have a turn-on section that supplies (EM) and a turn-off section that does not supply the light emitting signal (EM).

For example, the left and right light emitting drivers, which supply the light emitting signal (EM) to the first subpixel line by sharing the first light emitting signal line, each have turn-on periods and turn-off periods alternately. You can. That is, during the turn-on period in which the left light emitting driver outputs the high level light emitting signal (EM), the right light emitting driver may have a turn-off period in which the right light emitting driver does not output the high level light emitting signal (EM). Conversely, during a turn-off period in which the left light emitting driver does not output a high level light emitting signal (EM), the right light emitting driver may have a turn-on period in which the right light emitting driver outputs a high level light emitting signal (EM).

Here, a specific light emitting driver maintains a turn-on period in which it outputs a high-level light emitting signal (EM) during N frame (Frame N) and N+1 frame (Frame N+1), and M frame (Frame M) The example shows the case of alternately having turn-off periods in which the high-level emission signal (EM) is not output during the M+1 frame (Frame M+1).

One frame period can be divided into a recording period in which data voltage is applied to the subpixel and recorded, and an emission period in which the subpixel emits light at a preset duty ratio according to the emission signal (EM) after the recording period. Generally, the emission signal (EM) causes the subpixel (SP) to emit light at a duty ratio of 50% or less during the emission period. The recording section is approximately only one horizontal period (1H), and most of the one frame period corresponds to the light emission section.

Within the turn-on section in which the light emitting driver is driven, the Q node (Q) of the light emitting driver maintains a high level potential during the light emitting section and can output a high level light emitting signal (EM). At this time, during the light emission section in which the light emission signal EM is output at a high level, stress may be added to the pull-up transistor (eg, T7u in FIG. 4) constituting the light emission driver, thereby increasing the threshold voltage. During the light emission section in which the light emission signal (EM) is output at a high level, the low potential voltage (EVSS) of the light emitting driver may be maintained at the turn-on level (EVSS_ON).

However, during the turn-off period when the light emitting driver is not driving, the Q node (Q) of the light emitting driver is discharged to a low potential voltage (EVSS), so the light emitting signal (EM) maintains a low level potential during the turn-off period. I do it. Accordingly, the stress of the pull-up transistor (eg, T7u in FIG. 4 ) constituting the light emission driver may be relieved during the turn-off period in which the light emission signal EM is maintained at a low level.

Therefore, the turn-off period maintained at a low level of the light emission signal EM can be referred to as the recovery period of the light emitting driver.

Meanwhile, the low-potential voltage (EVSS) applied to the light emitting driver during the turn-off section maintained by the low-level light emission signal (EM) may have the same level as the turn-on level (EVSS_ON) applied during the turn-on section. However, it may have a recovery level (EVSS_R) that is lower than the turn-on level (EVSS_ON).

In order to relieve stress, the pull-up transistor (e.g., T7u in FIG. 4) constituting the light emitting driver uses a low potential voltage (EVSS_R) with a recovery level (EVSS_R) lower than the turn-on level (EVSS_ON) during the turn-off section of the light emitting driver. EVSS) is desirable.

FIG. 16 is a diagram showing an example of the amount of change in threshold voltage of a pull-up transistor according to a method of driving a light-emitting driver in a display device according to embodiments of the present disclosure.

Referring to FIG. 16, in the display device 100 according to embodiments of the present disclosure, the pull-up transistor is changed when the light-emitting drivers are alternately driven (Case 2 and Case 3) compared to when the light-emitting drivers are driven continuously (Case 1). It can be seen that the amount of change in threshold voltage decreases.

At this time, Case 3 represents a case in which the light emitting drivers are alternately driven, but the time for which the light emitting signal (EM) is output within the turn-on section is less than Case 2.

In this way, the display device 100 of the present disclosure has the effect of reducing the stress of the pull-up transistor and stably operating the light emitting driver by alternately driving the light emitting drivers sharing the light emitting signal line.

The embodiments of the present disclosure described above are briefly described as follows.

The display device 100 according to embodiments of the present disclosure includes a gate line GL including at least one scan line and a light emitting signal line extending in a first direction, and a plurality of subpixels arranged in the first direction. It shares a display panel 110 including a subpixel line (SPL) made of (SP) and one light emitting signal line connected to one subpixel line (SPL), and is located on one side of the display panel 110. A gate driving circuit 120 including a first light emitting driver disposed on the other side of the display panel 110 and a second light emitting driver disposed on the other side of the display panel 110, and controlling the first light emitting driver and the second light emitting driver to be driven alternately. It may include a timing controller 140.

The gate driving circuit 120 shares the at least one scan line connected to the subpixel line (SPL), and the first scan driver disposed on one side of the display panel 110 and the display panel 110 It may further include a second scan driver disposed on the other side.

The first light emission driver and the second light emission driver may share two light emission signal lines connected to two adjacent subpixel lines.

The first light emission driver and the second light emission driver include a Q node control unit 122 that controls charging and discharging of the Q node, a QB node control unit 124 that controls charging and discharging of the QB node, and a carry signal that generates a carry signal. A carry signal output unit 124, a light emitting signal output unit 128 that generates the light emitting signal (EM), and an alternating control signal (ALT) connect the Q node or the QB node to a first low potential voltage (EVSS1). ) may include an alternating control transistor that discharges.

The Q node control unit 122 is connected between a first transistor that charges the Q node to the potential of the light emission start signal in response to a light emission clock signal, the Q node and a first low potential voltage (EVSS1), and the alternating It is connected between a first alternating control transistor that discharges the potential of the Q node to the first low potential voltage (EVSS1) by a control signal (ALT), a first high potential voltage (EVDD1) and the Qh node, and the Q It may include a third transistor that supplies the first high potential voltage EVDD1 to the first transistor and the Qh node according to the potential of the node.

The QB node control unit 124 is connected between a fourth transistor that transmits a first high potential voltage (EVDD1) by an emission reset signal, and between the fourth transistor and the first low potential voltage (EVSS1), and the Qh A fifth transistor that discharges the fourth transistor and the QB node to the first low potential voltage (EVSS1) level according to the voltage level of the node is connected between the QB node and the first low potential voltage (EVSS1), , It may include a second alternating control transistor that discharges the potential of the QB node to the first low potential voltage (EVSS1) by the alternating control signal (ALT).

The carry signal output unit 126 is connected between the first high potential voltage (EVDD1) and the carry signal output node, and outputs the first high potential voltage (EVDD1) as a carry signal according to the voltage of the Q node. A first pull-down transistor is connected between a carry signal output node and the first low potential voltage (EVSS1), and outputs the first low potential voltage (EVSS1) as a carry signal according to the voltage of the QB node. May include a transistor.

The light emitting signal output unit 128 is connected between a second high potential voltage (EVDD2) and a light emitting signal output node, and converts the second high potential voltage (EVDD2) into a light emitting signal (EM) according to the voltage of the Q node. It is connected between a second pull-up transistor to output, a light emitting signal output node, and a second low potential voltage (EVSS2), and outputs the second low potential voltage (EVSS2) as a light emitting signal (EM) according to the voltage of the QB node. It may include a second pull-down transistor and a capacitor connected between the gate node of the second pull-up transistor and the light emitting signal output node.

The first light emitting driver and the second light emitting driver may undergo a turn-on period for at least one frame period, and after the turn-on period has elapsed, a turn-off period may proceed for at least one frame period.

The level of the low potential voltage applied during the turn-off period may be lower than the level of the low potential voltage applied during the turn-on period.

In addition, the display device 100 according to embodiments of the present disclosure has a gate line GL including at least one scan line and a light emitting signal line extending in a first direction, and a plurality of gate lines GL arranged in the first direction. It shares a display panel 110 including a subpixel line (SPL) made of subpixels (SP) and two light emitting signal lines connected to two adjacent subpixel lines, and is located on one side of the display panel 110. A gate driving circuit 120 including two first light emitting drivers and two second light emitting drivers disposed on the other side of the display panel 110, and an odd number of the first light emitting drivers and the second light emitting drivers. It may include a timing controller 140 that controls the driver to alternately drive with the even-numbered first light-emitting driver and the second light-emitting driver.

In addition, the gate driving circuit 120 according to embodiments of the present disclosure has a gate line GL including at least one scan line and a light emitting signal line extending in a first direction, and a plurality of gate lines GL arranged in the first direction. In the gate driving circuit 120 that drives the display panel 110 including a subpixel line (SPL) made of subpixels (SP), the gate driving circuit 120 is disposed on one side of the display panel 110 and includes a first subpixel. At least one first light-emitting driver that supplies a light-emitting signal through a first light-emitting signal line connected to the line, and a first light-emitting signal disposed on the other side of the display panel 110 and connected to the first subpixel line At least one second light emitting driver that supplies a light emitting signal through a line, wherein in the at least one first light emitting driver and the at least one second light emitting driver, a first group of light emitting diodes and a second group of light emitting diodes The diode may operate alternately in a turn-on period and a turn-off period.

The first group of light emitting diodes is the at least one first light emitting diode disposed on one side of the display panel 110, and the second group of light emitting diodes is the at least one first light emitting diode disposed on the other side of the display panel 110. It may be one second light emitting diode.

The first group of LEDs may be odd-numbered first and second LEDs, and the second group of LEDs may be even-numbered first and second LEDs.

In addition, the gate driving circuit 120 according to embodiments of the present disclosure has a gate line GL including at least one scan line and a light emitting signal line extending in a first direction, and a plurality of gate lines GL arranged in the first direction. In the gate driving circuit 120 that drives the display panel 110 including a subpixel line (SPL) made of subpixels (SP), it is disposed on one side of the display panel 110 and has two adjacent sub-pixels (SP). Two first light emitting drivers that supply light emitting signals through two light emitting signal lines connected to pixel lines, and two light emitting signals disposed on the other side of the display panel 110 and connected to two adjacent subpixel lines. Two second light emitting drivers supplying a light emitting signal through a line, wherein the odd numbered first light emitting driver and the second light emitting driver and the even numbered first light emitting driver and the second light emitting driver turn- The on section and turn-off section may operate alternately.

The above description is merely an illustrative explanation of the technical idea of the present invention, and various modifications and variations will be possible to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but rather to explain it, and therefore the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the present invention.

100: touch display device
110: display panel
120a, 120b: Gate driving circuit
122: Q node control unit
124: QB node control unit
126: Carry signal output unit
128: Luminous signal output unit
130: data driving circuit
140: Timing controller
150: power management circuit
160: main power management circuit
170: set board
200: Host system

Claims (14)

a display panel including a gate line including at least one scan line and a light emitting signal line extending in a first direction and a subpixel line composed of a plurality of subpixels arranged in the first direction;
a gate driving circuit that shares one light emitting signal line connected to one subpixel line and includes a first light emitting driver disposed on one side of the display panel and a second light emitting driver disposed on the other side of the display panel; and
A display device comprising a timing controller that controls the first light emitting driver and the second light emitting driver to be driven alternately.
According to claim 1,
The gate driving circuit is
The display device further includes a first scan driver disposed on one side of the display panel and a second scan driver disposed on the other side of the display panel, sharing the at least one scan line connected to the subpixel line.
According to claim 1,
The first light emitting driver and the second light emitting driver are
A display device that shares two light-emitting signal lines connected to two adjacent subpixel lines.
According to claim 1,
The first light emitting driver and the second light emitting driver are
A Q node control unit that controls charging and discharging of the Q node;
A QB node control unit that controls charging and discharging of the QB node;
A carry signal output unit that generates a carry signal;
a light emitting signal output unit that generates the light emitting signal; and
A display device comprising an alternating control transistor that discharges the Q node or the QB node to a first low potential voltage by an alternating control signal.
According to claim 4,
The Q node control unit
a first transistor that charges the Q node to the potential of the light emission start signal in response to the light emission clock signal;
a first alternating control transistor connected between the Q node and a first low potential voltage, and discharging the potential of the Q node to the first low potential voltage by the alternating control signal; and
A display device comprising a third transistor connected between a first high potential voltage and the Qh node, and supplying the first high potential voltage to the first transistor and the Qh node according to the potential of the Q node.
According to claim 5,
The QB node control unit
a fourth transistor transmitting a first high potential voltage by a light-emitting reset signal;
a fifth transistor connected between the fourth transistor and the first low-potential voltage, and discharging the fourth transistor and the QB node to the first low-potential voltage level according to the voltage level of the Qh node; and
A display device comprising a second alternating control transistor connected between the QB node and the first low potential voltage, and discharging the potential of the QB node to the first low potential voltage by the alternating control signal.
According to claim 6,
The carry signal output unit
a first pull-up transistor connected between the first high potential voltage and a carry signal output node, and outputting the first high potential voltage as a carry signal according to the voltage of the Q node; and
A display device comprising a first pull-down transistor connected between a carry signal output node and the first low potential voltage, and outputting the first low potential voltage as a carry signal according to the voltage of the QB node.
According to claim 7,
The light emitting signal output unit
a second pull-up transistor connected between a second high-potential voltage and a light-emitting signal output node, and outputting the second high-potential voltage as a light-emitting signal according to the voltage of the Q node;
a second pull-down transistor connected between a light emitting signal output node and a second low potential voltage, and outputting the second low potential voltage as a light emitting signal according to the voltage of the QB node; and
A display device including a capacitor connected between the gate node of the second pull-up transistor and the light emitting signal output node.
According to claim 1,
The first light emitting driver and the second light emitting driver are
The turn-on section lasts for at least one frame period,
A display device in which a turn-off period continues for at least one frame period after the turn-on period has elapsed.
According to clause 9,
A display device wherein the level of the low-potential voltage applied during the turn-off period is lower than the level of the low-potential voltage applied during the turn-on period.
a display panel including a gate line including at least one scan line and a light emitting signal line extending in a first direction and a subpixel line composed of a plurality of subpixels arranged in the first direction;
Shares two light emitting signal lines connected to two adjacent subpixel lines, and includes two first light emitting drivers disposed on one side of the display panel and two second light emitting drivers disposed on the other side of the display panel. gate driving circuit; and
A display device comprising a timing controller that controls odd-numbered first light-emitting drivers and second light-emitting drivers to alternately drive with even-numbered first light-emitting drivers and second light-emitting drivers.
A gate driving circuit that drives a display panel including a gate line including at least one scan line and a light emitting signal line extending in a first direction and a subpixel line composed of a plurality of subpixels arranged in the first direction. Because,
at least one first light emitting driver disposed on one side of the display panel and supplying a light emitting signal through a first light emitting signal line connected to a first subpixel line; and
At least one second light emitting driver disposed on the other side of the display panel and supplying a light emitting signal through a first light emitting signal line connected to the first subpixel line,
In the at least one first light emitting driver and the at least one second light emitting driver, the first group of light emitting diodes and the second group of light emitting diodes are gate driving circuits that alternately operate in turn-on periods and turn-off periods. .
According to claim 12,
The first group of light emitting diodes is
The at least one first light emitting diode is disposed on one side of the display panel,
The second group of light emitting diodes is
A gate driving circuit comprising the at least one second light emitting diode disposed on the other side of the display panel.
According to claim 12,
The first group of light emitting diodes is
The odd-numbered first light-emitting diode and the second light-emitting diode,
The second group of light emitting diodes is
A gate driving circuit comprising even-numbered first and second light-emitting diodes.

Images