CN110969976A

CN110969976A - Display device driving method and display device

Info

Publication number: CN110969976A
Application number: CN201911205632.0A
Authority: CN
Inventors: 吴常志; 孙莹; 许育民
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2020-04-07
Anticipated expiration: 2039-11-29
Also published as: CN110969976B

Abstract

The embodiment of the invention discloses a display device and a driving method thereof. The driving method includes: acquiring an image to be displayed, providing display signals to the pixel units by utilizing the scanning lines and the data lines, and displaying the image to be displayed; loading a grid opening signal to the scanning lines, and sequentially loading corresponding data signals to the data lines; the grid opening signal of one frame of scanning period comprises a plurality of scanning time sequence sections which are sequentially arranged, each scanning time sequence section correspondingly triggers one row of sub-pixels, the enabling level time of each scanning time sequence section is equal, and the time lengths of at least two scanning gaps are different; the scanning interval is the time difference between the starting time of the non-enabling level of the ith scanning time sequence section and the starting time of the enabling level of the (i + 1) th scanning time sequence section; i is a positive integer. According to the technical scheme, the inherent periodicity of the scanning signals can be destroyed, electromagnetic interference is reduced, and the influence of the display panel on other vehicle-mounted electronic products when the display panel is applied as a vehicle-mounted display screen is reduced.

Description

Display device driving method and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a driving method of a display device and a display device.

Background

With the development of Display technology, Liquid Crystal Display (LCD) panels and Organic Light Emitting Diode (OLED) Display panels gradually become two major Display panels in the Display field, and LCD panels and OLED Display panels are widely used in devices (including Display devices) or scenes with integrated Display functions, which can be known by those skilled in the art, such as computers, mobile phones, wearable devices, and vehicles.

Generally, the operation of electronic products causes Interference to other electronic products in the periphery, which may be referred to as Electromagnetic Interference (EMI), and electronic products subjected to the EMI may have degraded performance or even fail to operate normally. Therefore, when the display device is integrated in some equipment or applied to some scenes, for example, when the display device is applied to vehicle-mounted display and used as a vehicle-mounted display screen, the display device can generate electromagnetic interference to other vehicle-mounted electronic products.

Disclosure of Invention

The invention provides a driving method of a display device and the display device, which are used for reducing electromagnetic interference radiated to the periphery by the display device, thereby reducing the electromagnetic interference to other vehicle-mounted electronic products when a display panel is used as a vehicle-mounted display screen.

In a first aspect, an embodiment of the present invention provides a driving method of a display device, where the display device includes a display panel, where the display panel includes scan lines and data lines, where the scan lines and the data lines intersect to define sub-pixel regions, and the sub-pixel regions are provided with sub-pixels; the driving method includes:

acquiring an image to be displayed;

according to the image to be displayed, providing a display signal to the pixel unit by using the scanning line and the data line;

displaying the image to be displayed according to the display signal;

the display signals comprise grid opening signals and data signals, and in one frame of scanning period, the grid opening signals are loaded to the scanning lines, and the corresponding data signals are sequentially loaded to the data lines; the grid opening signal of one frame of scanning period comprises a plurality of scanning time sequence sections which are sequentially arranged, each scanning time sequence section correspondingly triggers one row of sub-pixels, the enabling level time of each scanning time sequence section is equal, and the time lengths of at least two scanning gaps are different; the scanning interval is a time difference value between the starting time of the non-enabled level of the ith scanning time sequence section and the starting time of the enabled level of the (i + 1) th scanning time sequence section; i is a positive integer.

In a second aspect, embodiments of the present invention provide a display device, which is configured to perform the driving method of the display device provided in the first aspect.

In the driving method of the display device provided by the embodiment of the invention, the gate start signal of one frame of scanning period is set to comprise a plurality of scanning time sequence sections which are sequentially arranged, each scanning time sequence section correspondingly triggers one row of sub-pixels, the enabling levels of all the scanning time sequence sections have equal duration, and the duration of at least two scanning gaps is different; the scanning interval is the time difference between the starting time of the non-enabling level of the ith scanning time sequence section and the starting time of the enabling level of the (i + 1) th scanning time sequence section; i is a positive integer, so that the time length of at least one scanning gap in one frame of picture to be displayed is different from the time lengths of other scanning gaps, the period of scanning signals in one frame of picture to be displayed is not completely the same, namely the natural frequency characteristic of the scanning signals is damaged, the electromagnetic interference phenomenon caused by the fixed frequency of the scanning signals can be weakened, namely the electromagnetic interference generated by the scanning signals is improved, the problem that the interference energy radiates to the periphery to cause interference on other electronic products on the vehicle is avoided, the improvement of the performance of other electronic products on the vehicle is facilitated, and the normal operation of vehicle-mounted electronic products is facilitated.

Drawings

FIG. 1 is a timing diagram illustrating a driving method of a display panel according to the related art;

FIG. 2 is a schematic diagram illustrating an EMI effect corresponding to a driving timing of the display panel of FIG. 1;

fig. 3 is a schematic structural diagram of a display panel in a display device according to an embodiment of the present invention;

fig. 4 is a schematic flow chart of a driving method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a driving timing sequence according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another driving timing sequence provided in the embodiment of the present invention;

FIG. 7 is a schematic diagram of another driving timing sequence provided by the embodiment of the present invention;

FIG. 8 is a schematic diagram of another driving timing sequence provided by the embodiment of the present invention;

fig. 9 is a schematic structural diagram of another display device according to an embodiment of the invention;

FIG. 10 is a schematic signal flow diagram of the display device of FIG. 9;

FIG. 11 is a schematic diagram of another driving timing sequence provided by the embodiment of the present invention;

fig. 12 is a schematic structural diagram of another display device according to an embodiment of the invention;

FIG. 13 is a partial enlarged view of the structure of region 950QA in FIG. 12;

FIG. 14 is a schematic diagram of another driving timing sequence provided by the embodiment of the present invention;

fig. 15 is a schematic structural diagram of a display panel in another display device according to an embodiment of the invention;

FIG. 16 is a schematic diagram of a logic circuit of the first scan driving circuit in FIG. 15;

FIG. 17 is a timing diagram illustrating operation of the logic circuit of FIG. 16;

FIG. 18 illustrates an operational state of the latch cell of FIG. 16;

FIG. 19 is another operating state of the latch cell of FIG. 16;

FIG. 20 is a diagram of an operating state of the first scan driving circuit in FIG. 16;

FIG. 21 is a diagram of another operating state of the first scan driving circuit in FIG. 16;

FIG. 22 is a diagram of the first scan driving circuit of FIG. 16 in a further operating state;

FIG. 23 is a schematic diagram of another structure of the signal delay unit in FIG. 16;

FIG. 24 is a schematic diagram of another structure of the signal delay unit of FIG. 16;

FIG. 25 is a schematic diagram of another structure of the signal delay unit of FIG. 16;

FIG. 26 is a schematic diagram of another structure of the signal delay unit in FIG. 16;

FIG. 27 is a schematic diagram of another structure of the signal delay unit of FIG. 16;

FIG. 28 is a diagram illustrating an inverter structure in a display device according to an embodiment of the present invention;

FIG. 29 is a schematic diagram of the time delay principle of the inverter of FIG. 18;

FIG. 30 is a schematic diagram illustrating a comparison between a driving sequence of the prior art and a reference driving sequence according to still another embodiment of the present invention;

fig. 31 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be noted that, for convenience of description, only a part of the structure related to the present invention is shown in the drawings, not all of the structure.

The display device comprises a display panel and a master control system, wherein in the structure of the existing display panel, the display panel comprises a display area and a non-display area; in the display area, scanning lines and data lines are arranged in a crossed manner to limit a sub-pixel area, and sub-pixels are arranged in the sub-pixel area; in the non-display region, driving circuits including a scan driving circuit, which is also commonly referred to as a shift register circuit, and a data driving circuit, which is commonly referred to as a multiplexing circuit, are disposed. The shift register circuit comprises cascade shift registers, the output end of each stage of shift register is electrically connected with a scanning line corresponding to a row of sub-pixels, and the scanning line provides scanning signals (also called grid opening signals) to the same row of scanning lines; the multi-path selection circuit comprises a plurality of multi-path selection units, the control ends of the multi-path selection units are in one-to-one correspondence with the output ends, the output ends are correspondingly connected with the data lines, and the data lines are used for writing data signals into the sub-pixels under the action of the data selection control signal lines.

The principle of the display device generating electromagnetic interference is exemplarily described below with reference to fig. 1 and 2.

Referring to fig. 1 and 2, in the prior art, scanning signals (in fig. 1, values of gate1, gate2, gate3, … …, gate, n may be 4, 5, 6, and other positive integers) are scanned line by line (also referred to as "progressive") one by one; during the scan signal enable period (the high-level period in fig. 1) of the current stage, the clock control signal (shown as MUX0 in fig. 1) controls each data line to write the data signal to the sub-pixel of the current row. Wherein, the scanning time of each line can be called as a line scanning period T_H-syncThe scanning frequency corresponding to the line scanning period is f_H-sync，f_H-sync＝1/T_H-sync(ii) a Taking the multiplexing unit 1:3 as an example (see fig. 1), the MUX0 includes three clock control sequences, and the overall frequency of the clock control signal (also referred to herein as "MUX frequency") is 3 times the scan frequency. Since the scanning frequency of each row of sub-pixels is fixed_H-syncTherefore, energy peaks occur at a plurality of fixed frequency positions of the low frequency band of the vehicle gauge, that is, the energy peaks occur periodically, and a large energy value at the energy peaks radiates outwards, which easily causes that other electronic products on the vehicle cannot work normally due to electromagnetic interference. For example, the EMI test results may be as shown in fig. 2. Wherein, the abscissa X represents frequency in hertz (Hz), and the ordinate Y represents intensity of radiation energy, which can be understood as DB value (i.e. count value) in absolute unit (a.u.), that is, EMI test results are obtained by pure counting method; wherein, L011 and L012 respectively represent the average value and the maximum value of the same specification requirement limit value of the vehicle, and L021 and L022 respectively represent the average value curve and the maximum value curve of the EMI radiation energy at different frequencies obtained by testing. As can be seen from fig. 2, energy peaks occur at the positions of the multiples of the scanning frequency. Therefore, the energy at the energy peak value is radiated to the periphery of the display device, and when the display device is applied to a vehicle-mounted scene, the normal work of other electronic products on a vehicle can be influenced, namely the display device is producedElectromagnetic interference phenomenon is generated.

In view of the above problems, embodiments of the present invention provide a driving method for a display device and a display device, which destroy the inherent periodicity of a scanning signal to disperse the distribution of energy radiated to the periphery of the display device at each frequency position, so as to weaken the energy at the energy peak and further improve the electromagnetic interference phenomenon. Specifically, in the embodiment of the present invention, a gate turn-on signal of one frame of scanning period is set to include a plurality of scanning time sequence segments arranged in sequence, each scanning time sequence segment correspondingly triggers one row of sub-pixels, the enabling level durations of the scanning time sequence segments are all equal, the durations of at least two scanning gaps are different, and the scanning gap is a time difference between the starting time of the non-enabling level of the ith scanning time sequence segment and the starting time of the enabling level of the (i + 1) th scanning time sequence segment; the method can ensure that the time length of at least one scanning gap is different from the time length of other scanning gaps in one frame of picture to be displayed, thereby ensuring that the periods of scanning signals corresponding to each row of sub-pixels in one frame of picture to be displayed are not completely the same, namely, the inherent frequency characteristic of the scanning signals is destroyed, further weakening the electromagnetic interference caused by the fixed frequency of the scanning signals, namely, improving the problem that the electromagnetic interference generated by the scanning signals is radiated to cause interference to other electronic products (such as a vehicle-mounted radio, a vehicle-mounted sound or other vehicle-mounted display screens) on the vehicle, being beneficial to improving the performance of other electronic products on the vehicle, namely being beneficial to realizing the normal operation of the electronic products.

A driving method of a display device and the display device provided by the embodiment of the invention are exemplarily described below with reference to fig. 3 to fig. 31.

Exemplarily, referring to fig. 3, the display device includes a display panel 90, the display panel 90 including a display area 920 and a non-display area 910 surrounding the display area 920; the display panel 90 includes scan lines 931 and data lines 932, where the scan lines 931 and the data lines 932 are arranged to intersect to define a plurality of sub-pixel regions 934, and each sub-pixel region 934 has a sub-pixel 933 disposed therein.

The display area 920 of the display panel 90 is used for displaying an image to be displayed.

For example, the display panel 90 may be an LCD panel, an OLED display panel, or other types of display panels known to those skilled in the art, and the embodiment of the invention is not limited thereto.

The non-display area 910 of the display panel 90 is used to provide a driving circuit, an anti-static circuit, an integrated circuit, and other circuit structures, optical structures, or supporting and fixing structures known to those skilled in the art, which is not limited in the embodiments of the invention.

Illustratively, the non-display area 910 is shown in FIG. 3, by way of example only, as being disposed around the display area 920. In other embodiments, the non-display area 910 may be further arranged to surround the display area 920, or the non-display area 910 is arranged adjacent to the display area 920 in the left-right direction, or the non-display area 910 is arranged adjacent to the display area 920 in the up-down direction, or other relative positions known to those skilled in the art may be arranged, which is not limited in this embodiment of the present invention.

The sub-pixels 933 in the display panel 90 emit light (LCD panel) or light (OLED display panel) so that the display panel can display an image to be displayed.

For example, the scan lines 931 and the data lines 932 in fig. 3 may intersect vertically or not, and the angle at which the scan lines 931 and the data lines intersect may be set according to the actual requirement of the display panel 90, which is not limited in this embodiment of the invention.

It should be noted that fig. 3 shows only the scan lines 931 and the data lines 932 in a straight line as an example. In the actual product structure of the display panel 90, the actual shapes of the scan lines 931 and the data lines 932 may be set according to the actual requirements of the display panel 90, which is not limited in the embodiment of the invention.

Illustratively, only the sub-pixel 933 and the sub-pixel region 934 are exemplarily shown in rectangular form in fig. 3. In an actual product structure of the display panel 90, the shapes of the sub-pixels 933 and the sub-pixel regions 934 can be set according to the wiring manner of the display panel 90 and other requirements, which is not limited in the embodiment of the present invention.

It should be noted that fig. 3 only exemplarily shows that both the scan lines 931 and the data lines 932 extend from the display area 920 to the non-display area 910. In other embodiments, the lengths of the scan lines 931 and the data lines 932 and the relative position relationship between the scan lines and the data lines and the boundary of the display area 920 may also be set according to practical requirements of the display panel 90, which is not limited by the embodiment of the present invention.

It can be understood that the display device not only includes the display panel, but also includes other structural components that can be integrated with the display panel, such as a main control system, a camera, a fingerprint identification module, a touch module, a speaker, and the like, and those skilled in the art can know, and the embodiment of the present invention does not limit this.

Based on the structure of the display panel, referring to fig. 4, the driving method of the display panel includes:

and S110, acquiring an image to be displayed.

The image to be displayed may also be referred to as a picture to be displayed, and the image to be displayed is an image that needs to be displayed by the display panel. For example, the frame of image to be displayed may be a frame of picture in a static image or a frame of picture in a dynamic scene image.

For example, if the display panel is applied to a mobile phone, the mobile phone may include a main board (including a driving system) and an Integrated Circuit (IC) connecting the main board and the display panel. Based on this, the step may include the IC receiving the to-be-displayed picture output by the main board.

For example, if the display panel is applied to a computer, the computer may include a graphics card and an IC connecting the graphics card and the display panel. Based on this, the step may include the IC receiving the picture to be displayed output by the display card.

In other embodiments, when the display panel is applied to other display devices (or called electronic apparatuses, also called electronic products), this step may include the IC obtaining the picture to be displayed by the overall control system of the display device, and the present invention does not limit the actual product structure form of the overall control system.

And S120, providing a display signal to the sub-pixel by using the scanning line and the data line according to the image to be displayed.

The display signals comprise grid opening signals and data signals; the gate-on signal determines the row of the sub-pixel where the data signal can be written, and the magnitude of the data signal determines the display gray scale (which can be understood as the display brightness) of the sub-pixel; the scanning lines are used for providing gate opening signals to the sub-pixels step by step, and the data lines are used for providing data signals to the sub-pixels which are opened in the row.

Wherein, a frame of frame to be displayed is refreshed correspondingly in a frame scanning period. In a frame scanning period, the scanning line 931 arranged row by row can gradually load the gate-on signal to the sub-pixels 933 of the corresponding row, and at this time, the data line 932 writes the data signal into each sub-pixel 933 of the row; and the process of completing the writing of the data signals from the first row of sub-pixels to the last row of sub-pixels correspondingly refreshes a complete picture.

With reference to fig. 3 and 5, the display signals include scan signals (also referred to as Gate signals, which are respectively shown as Gate1 ', Gate2 ', Gate3 ', Gate4 ', and Gate5 ' in fig. 5) and Data signals (also referred to as Data signals, which are not shown in fig. 5), and in one frame of scan period, the scan signals are sequentially loaded to all the scan lines 931, and the corresponding Data signals are sequentially loaded to the Data lines 932; the scan signal of one frame scan period includes a plurality of scan timing segments (sequentially denoted by T in FIG. 5)_G1、T_G2、T_G3And T_G4Shown), each corresponding to a scan timing segment T that triggers a row of sub-pixels 933, illustratively, Gate1_G1Correspondingly triggering a first row of sub-pixels 933; scanning time sequence segment T of Gate2_G2The enabling levels of the scan timing segments (for example, the high level is taken as the enabling level in fig. 5) are all equal, the durations of at least two scan gaps △ TG are different, the scan gap △ TG is the time difference between the starting time of the non-enabling level of the ith (e.g., the 3 rd) scan timing segment and the starting time of the enabling level of the (i + 1) th (e.g., the 4 th) scan timing segment, and i is a positive integer.

It is understood that the duration of the "one-frame scanning period" is the sum of the durations of the scanning periods of all the sub-pixel rows from the first row to the last row, and a one-frame scanning period corresponds to a frame of a picture to be displayed, and the "sequentially arranged multiple scanning time sequence segments" can be understood that for multiple scanning time sequence segments in a one-frame scanning period, each scanning time sequence segment corresponds to one row of sub-pixels, and the triggering start time of the sub-pixels in the next row is delayed by one scanning gap △ TG relative to the triggering end time of the sub-pixels in the previous row.

Wherein, the duration of the enable level of each scanning time sequence section can be understood as the time difference between the start enable time and the end enable time of the scanning signal; illustratively, the time length of the high level duration of each scan signal in fig. 5 may be used.

Wherein, the whole duration of the enabling level and the adjacent scanning interval following the enabling level can be regarded as the scanning period of a scanning signal; i.e. a "scan period" in this context is to be understood as a time interval between start enable instants of two consecutive scan timing segments in a scan signal, i.e. a time interval between start instants of two consecutive enable levels in a data signal. Exemplarily, in FIG. 5, T is respectively_G1、T_G2、T_G3And T_G4Showing a plurality of scan cycles with different times as start enable times; at the same time with T_G0A scanning cycle in the prior art is shown as a comparative example.

The display device is applied to vehicle-mounted display, and is beneficial to improving the performance of other electronic products on a vehicle and realizing normal operation of other vehicle-mounted electronic products.

Illustratively, this step may include the IC providing display signals associated with the image to be displayed to the subpixels using the scan lines and the data lines. When the image to be displayed changes, the display signal changes accordingly.

And S130, displaying the image to be displayed according to the display signal.

In one frame of scanning period, each sub-pixel in the display panel receives the display signal to realize the complete refreshing of the image to be displayed.

Illustratively, the step may include the display panel displaying the image to be displayed according to the display signal.

According to the driving method of the display device provided by the embodiment of the invention, the duration of the enabling level of each scanning time sequence section is equal, and the duration of at least two scanning gaps is different, so that the scanning periods of scanning signals in a frame of picture to be displayed are not completely the same, the radiation energy can be dispersed at more frequency positions, the energy value at a frequency doubling position is reduced, the electromagnetic interference is improved, and the electronic products around the display device can work normally.

The driving method of the display device provided by the embodiment of the invention can also be understood as the scanning period T in the prior art_G0On the basis of the fixed duration, the duration of at least part of the scanning periods is adjusted, so that the duration of at least two scanning periods in a frame of the picture to be displayed is different.

The adjustment manner of the duration of the scanning period can be flexibly set according to the display device and the driving method thereof, and is exemplarily described below with reference to fig. 6 to 8.

Optionally, referring to fig. 6, in a frame scanning period, the durations of the scanning gaps are different.

Therefore, the energy radiated to the periphery by the display device can be distributed at each frequency position in the working frequency band of the display device more dispersedly, so that the energy intensity at the energy peak position can be reduced, and the electromagnetic interference can be improved.

Exemplarily, fig. 6 shows 4 scan gaps △ TG, which are △ TG1, △ TG2, △ TG3 and △ TG4 respectively, in this embodiment, the time lengths of △ TG1, △ TG2, △ TG3 and △ TG4 are not equal, so that the time lengths of each scan period of the scan signals in one frame to be displayed are not equal, thereby improving the electromagnetic interference.

In other embodiments, the number of the scanning gaps and the time length of each scanning gap may also be set according to actual requirements of the display device and the driving method thereof, which is not limited in the embodiments of the present invention.

On the basis, in order to reduce electromagnetic interference and simplify a driving algorithm of the display device, the duration of the scanning gap can be set to show regular arrangement in a complete frame of the picture to be displayed. This regular time period setting is exemplified below with reference to fig. 7 and 8.

Alternatively, referring to fig. 7, the scan gap △ TG includes a first scan gap △ TG1 and a second scan gap △ TG2, the first scan gap △ TG1 is a time difference between a start time of a non-enable level of a 2m-1 (e.g., 1 st) th scan timing segment and a start time of an enable level of a 2m (e.g., 2 nd) th scan timing segment, the second scan gap △ TG2 is a time difference between a start time of a non-enable level of a 2m (e.g., 2 nd) th scan timing segment and a start time of an enable level of a 2m +1 (e.g., 3 rd) th scan timing segment, time lengths of the first scan gap △ TG1 and the second scan gap △ TG2 are unequal, and m is a positive integer.

For example, in a frame of a to-be-displayed image, the sequential arrangement order of the first scanning gap △ TG1 and the second scanning gap △ TG2 may include:

△ TG1, △ TG2, △ TG1, △ TG2, … … (as shown in FIG. 7);

the method can also comprise the following steps:

△TG1、△TG1、△TG2、△TG2、……；。

△TG1、△TG2、△TG2、△TG1、△TG2、△TG2、……；

△TG1、△TG1、△TG1、△TG2、△TG1、△TG1、△TG1、△TG2、……；

or in other sequences as would be known to those skilled in the art, and the embodiments of the present invention are not limited thereto.

Alternatively, referring to fig. 8, the scan gap △ TG includes a first scan gap △ TG1, a second scan gap △ TG2, and a third scan gap △ TG3, the first scan gap △ TG1 is a time difference between a non-enable level start time of a 3n-2 (e.g., 1 st) scan timing segment and an enable level start time of a 3n-1 (e.g., 2 nd) scan timing segment, the second scan gap △ TG2 is a time difference between a non-enable level start time of a 3n-1 (e.g., 2 nd) scan timing segment and an enable level start time of a 3n (e.g., 3 rd) scan timing segment, the third scan gap △ TG3 is a time difference between a non-enable level start time of a 3n (e.g., 3 rd) scan timing segment and an enable level start time of a 3n +1 (e.g., 4 th) scan timing segment, the scan gaps are all positive 638, and 3 are each other.

△ TG1, △ TG2, △ TG3, △ TG1, △ TG2, △ TG3, … … (as shown in FIG. 8);

the method can also comprise the following steps:

△TG1、△TG1、△TG2、△TG2、△TG3、△TG3、……；。

△TG1、△TG2、△TG2、△TG3、△TG1、△TG2、△TG2、△TG3、……；

△TG1、△TG1、△TG2、△TG3、△TG1、△TG1、△TG2、△TG3、……；

It should be noted that, the time lengths of the scan gaps △ TG shown in fig. 7 and 8 only exemplarily include two time lengths or three time lengths different from each other, and the sequencing manner of the scan gaps of different time lengths is shown on this basis, but this does not limit the display device and the driving method thereof provided by the embodiment of the present invention.

In the above-described embodiment, in order to realize the unequal durations of the at least two scanning gaps △ TG in the scanning signals, the signal of at least one node of the display device, which exists in the entire process from the acquisition of the picture to be displayed until the presentation of the picture to be displayed, may be set, which is exemplarily described below in connection with fig. 9 to fig. 30 and in connection with the signal transmission and conversion process during the operation of the display device.

Wherein, the signal transmission process of the display device may include: the master control system transmits an external control signal to the display panel, an integrated circuit in the display panel processes the external control signal to generate a data driving signal and a scanning driving signal, transmits the scanning driving signal to the scanning driving circuit, and transmits the data driving signal to the data driving circuit; the scanning driving circuit generates scanning signals according to the scanning driving signals and loads the scanning signals to the scanning lines, and the data driving circuit gates at least one data selection control switch through the data selection control signals and writes the data signals into the sub-pixels through the data lines. In this paragraph, "external control signal" means that when the display panel is taken as a complete whole, the main control system is another circuit structure independent of the display panel, and the control signal sent from the main control system to the display panel becomes the external control signal.

For example, in the signal transmission process, in order to implement the setting of the scan gap of the scan signal, the external control signal may be adjusted (as exemplarily described below with reference to fig. 9 to 11), or the structure of the integrated circuit may be set to implement the adjustment of the scan driving signal (as exemplarily described below with reference to fig. 12 to 14), or the structure of the scan driving circuit may be set to implement the adjustment of the scan signal (as exemplarily described below with reference to fig. 15 to 30).

Alternatively, referring to fig. 9 to 11, the display panel 90 further includes a first integrated circuitOn the circuit 9610, the display device 80 further includes a first processor 810, the transmitting terminal 811 of the first processor 810 transmits a control signal to the receiving terminal 9611 of the first integrated circuit 9610, and the output terminal 9612 of the first integrated circuit 9610 outputs a scanning signal; the control signal comprises a line synchronization signal HS, and the line synchronization signal HS is used for determining an effective line signal interval; the line sync signal HS includes a plurality of sub-sync signals (exemplarily, denoted by T in fig. 11) arranged in sequence_H1、 T_H2And T_H3Shown), each sub-synchronization signal includes a first blank period (exemplarily, shown in fig. 11 as HBP1, HBP2, and HBP 3), a valid period (exemplarily, shown in fig. 11 as T), which are sequentially connected_HA1、T_HA2And T_HA3Showing) and a second blank period (exemplarily, shown in fig. 11 by HFP1, HFP2, and HFP 3), wherein the active period corresponds to the enable level period of the scan timing period in one-to-one correspondence, the duration of the active period is greater than or equal to the duration of the (effective) write period of the data signal, the second blank period of the q-th (e.g., 1 st) sub-synchronization signal and the first blank period of the q + 1-th (e.g., 2 nd) sub-synchronization signal both correspond to the same scan gap (e.g., the first scan gap △ TG1), the durations of the active periods of the sub-synchronization signals are all equal, and q is a positive integer.

Wherein, the first processor 810 can be an overall control system in an actual product structure. Illustratively, the first Processor 810 may be an Application Processor (AP) side. The first Integrated Circuit 9610 may include an Integrated Circuit (IC) at a position of a lower frame region of the display panel 90, and a shift register Circuit at a position of a left frame and a right frame of the display panel 90.

For example, referring to fig. 10, a transmitting terminal 811 (TX terminal in fig. 10) on the AP side transmits a control signal to a receiving terminal RX of the integrated circuit of the display panel 90, and an internal circuit of the integrated circuit processes the control signal to generate a scan driving signal GDOP and a data driving signal SDOP; the scanning driving signal GDOP is transmitted to the shift register circuit, and after the scanning signal is generated, the scanning signal is loaded to the scanning line.

In the effective time period of the line synchronizing signal HS, all signal outputs received by the receiving end belong to the same line. For example, the control signal further includes a field sync signal, and all the image data outputted from the time when the field sync signal is set high until the field sync signal is pulled low form a frame to be displayed, taking the high level of the field sync signal as an example. Illustratively, the control signals also include an active display DATA strobe signal DE, during which the DATA signal DATA is written to the sub-pixels during an active period (shown as a high period in fig. 11). Illustratively, the control signal further includes a pixel synchronization clock signal PCLK, and each pixel synchronization clock signal PCLK corresponds to one sub-pixel.

Among them, the first blanking period may also be referred to as Horizontal Back Porch (HBP), and the second blanking period may also be referred to as Horizontal Front Porch (HFP); the scanning duration of the sub-pixels of 1 line is equal to the duration of 1 sub-synchronization signal, i.e., the horizontal back porch HBP, the active period (H-active), and the horizontal front porch HFP are included. For example, in fig. 11, the pixel point counts the synchronous clock signal PCLK, and when the count reaches the back porch HBP in the horizontal direction, valid data starts to be transmitted; after counting the horizontal back porch HBP and the valid period H-active, the DATA signal DATA transmission is finished; the counting is continued until the horizontal front lane HFP is completed, i.e., the duration of one complete sub-sync signal has elapsed.

Wherein a duration of one scanning gap is equal to an overall duration of one first blank period and one second blank period which are temporally adjacent. To achieve the adjustment of the duration of the scanning gap, the adjustment of the duration of at least one of the first blank period and the second blank period may include:

in a first manner, only the time lengths of the first blank periods may be set, that is, the time lengths of at least two first blank periods in the sub-synchronization signal are set to be different.

Therefore, when the durations of the second blank periods are equal, the durations of the first blank periods are different, and the durations of the scanning gaps are not completely the same.

For example, referring to fig. 11, the first blanking period may include first blanking period HBP1, first second blanking period HBP2, and first third blanking period HBP3 periods, and the time lengths of at least two of the first blanking period HBP1, first second blanking period HBP2, and first third blanking period HBP3 periods may be set to be unequal.

In other embodiments, the number and duration of the first blank periods may also be set according to actual requirements of the display device and the driving method thereof, which are not limited by the embodiment of the present invention.

In the second mode, only the time lengths of the second blank periods may be set, that is, the time lengths of at least two second blank periods in the sub-synchronization signal are set to be different.

Therefore, when the durations of the first blank periods are equal, the durations of the second blank periods are different, and the durations of the scanning gaps are not completely the same.

For example, referring to fig. 11, the second blank period may include second blank period HFP1, second blank period HFP2, and second blank HFP3 periods, and the time lengths of at least two of the second blank period HFP1, second blank period HFP2, and second blank HFP3 periods may be set to be different.

In other embodiments, the number and duration of the second blank periods may also be set according to actual requirements of the display device and the driving method thereof, which are not limited by the embodiment of the present invention.

In a third manner, the durations of the first blank periods and the second blank periods may be set simultaneously, that is, the durations of at least two first blank periods in the sub-synchronization signals are set to be different, and the durations of at least two second blank periods in the sub-synchronization signals are set to be different.

Therefore, the non-translation of the picture finally presented by the display panel can be ensured while the time lengths of at least two scanning gaps are different; therefore, the electromagnetic interference is reduced, and the normal display of the picture to be displayed by the display panel can be realized.

For example, referring to fig. 11, the time lengths of at least two of the first blanking period HBP1, the first second blanking period HBP2, and the first third blanking period HBP3 may be set to be unequal; and the time length of setting at least two of the second margin HFP1, the second margin HFP2, and the second margin HFP3 periods is not equal.

It should be noted that, in other embodiments, the number and duration of the first blank periods and the number and duration of the second blank periods may be set according to actual requirements of the display device and the driving method thereof, and the embodiment of the present invention is not limited thereto.

On this basis, in order to realize that the duration of each scanning gap in one frame scanning period is not equal, the setting mode of the first blank period and the second blank period may include:

the first method is as follows: in one frame scanning period, the duration of the first blank period in each sub-synchronization signal is different.

Thus, when the durations of the second blank periods are equal, the durations of the scan timing periods in one frame scan cycle may be different.

The second method comprises the following steps: in one frame scanning period, the duration of the second blank period in each sub-synchronization signal is different.

Thus, when the time lengths of the first blank periods are equal, the time lengths of the scanning time periods in one frame scanning period can be different.

The third method comprises the following steps: in one frame scanning period, the first blank periods in each sub-synchronization signal are all different in duration, and the second blank periods in each sub-synchronization signal are all different in duration.

Therefore, the unequal duration of the scanning time sequence segments in one frame scanning period can be realized.

In other embodiments, the durations of the first blank periods in the partial sub-synchronization signals are all equal, and the durations of the second blank periods are all unequal; the durations of the second blank periods in the remaining molecular synchronization signals are all equal, and the durations of the first blank periods are all different.

On the basis, in order to simplify the driving algorithm of the display device while reducing the electromagnetic interference, the regular arrangement of the time length of at least one of the first blank period and the second blank period can be set. Hereinafter, the first blank periods of equal duration are regarded as the same type of first blank period, and the second blank periods of equal duration are regarded as the same type of second blank period.

Optionally, the first blank period includes at least two first blank periods with different durations, and the duration of the first blank period of each duration is equal to but not equal to the duration of the first blank period of another duration; the first blank period intervals of different durations are set.

Illustratively, with continued reference to fig. 11, the first blanking period may comprise three different durations of the first blanking period, shown as first a, second b and c blanking periods HBP1, HBP2 and HBP3, respectively; over time, the ordering may include:

HBP1, HBP2, HBP3, HBP1, HBP2, HBP3, … … (as shown in fig. 11);

the method can also comprise the following steps:

HBP1、HBP2、HBP2、HBP3、HBP1、HBP2、HBP2、HBP3、……；

HBP1、HBP2、HBP1、HBP2、HBP3、HBP1、HBP2、HBP1、HBP2、HBP3、……；

Optionally, the second blank period includes at least two second blank periods with different durations, and the durations of the second blank periods of each duration are equal but not equal to the duration of the second blank period of another duration; the second blank period intervals of different durations are set.

For example, with continued reference to fig. 11, the second blanking period may include three different durations of the second blanking period, shown as second blanking period HFP1, second blanking period HFP2, and second third blanking period HFP3, respectively; over time, the ordering may include:

HFP1, HFP2, HFP3, HFP1, HFP2, HFP3, … … (as shown in fig. 11);

the method can also comprise the following steps:

HFP1、HFP2、HFP2、HFP3、HFP1、HFP2、HFP2、HFP3、……；

HFP1、HFP2、HFP1、HFP2、HFP3、HFP1、HFP2、HFP1、HFP2、HFP3、……；

Optionally, the time length distribution modes of the first blank period and the second blank period may be integrated to implement the regular arrangement of the scanning gaps. Illustratively, the first blank periods comprise at least two first blank periods with different durations, and the duration of the first blank periods of each duration is equal to but not equal to the duration of the first blank periods of the other duration; the first blank periods with different durations are arranged at intervals, the second blank period comprises at least two second blank periods with different durations, the duration of the second blank period of each duration is equal, but not equal to the duration of the second blank period of the other duration; a second blank period interval of different duration is set.

Therefore, flexible configuration of the first blank time interval and the second blank time interval can be realized while the time length of the scanning interval is regularly arranged.

It should be noted that the specific time lengths of the durations of the first blank period and the second blank period may be set according to actual requirements of the display device and the driving method thereof, and the embodiment of the invention does not limit this.

Optionally, with continued reference to fig. 11, the control signal further includes a DATA driving signal DE (i.e., an active display DATA strobe signal DE) for determining a writing period of the DATA signal DATA; the valid write time of the data driving signal DE is within the valid period of the row sync signal HS.

The effective time interval of the line synchronizing signal HS is equal to the duration of the enable level in the scanning time sequence section of the scanning signal, that is, in the effective time interval, the sub-pixels in the sub-pixel row corresponding to the scanning time sequence section are turned on, and the data signal is allowed to be written. By setting the effective writing time of the data driving signal DE in the effective period of the line synchronizing signal HS, the data signal can be ensured to be normally written into the sub-pixel, thereby ensuring that the display panel can normally display the picture to be displayed.

It should be noted that the active period of the row sync signal HS includes the enable level period of each sub-sync signal. The enable level period of each sub-sync signal may have a front margin, or have a rear margin, or have both a front margin and a rear margin with respect to the effective writing time of the data driving signal DE, and may be set according to actual requirements of the display device and the driving method thereof, which is not limited in the embodiment of the invention. It is to be understood that "front margin" in this paragraph is understood as the start timing of the enable level period of the sub-sync signal being earlier than the start timing of the valid write time of the data drive signal DE, and "rear margin" is understood as the end timing of the enable level period of the sub-sync signal being later than the end timing of the valid write time of the data drive signal DE.

The adjustment of the external control signal is exemplarily described above with reference to fig. 9 to 11; the manner in which the scan driving signal is adjusted is exemplarily described below with reference to fig. 12 to 14. The "scan driving signal" herein may include a first clock signal and a second clock signal.

Optionally, referring to fig. 12 to 14, the display panel 90 further includes a second integrated circuit 9620, a first clock signal line 951, a second clock signal line 952, and a plurality of first scan driving circuits 950 arranged IN cascade, the first scan driving circuit 950 includes a first clock input terminal CK, a second clock input terminal XCK, a scan trigger signal receiving terminal IN1, and a scan signal output terminal OUT1, and the scan line 931 is electrically connected to the scan signal output terminal OUT 1; the display device 80 further includes a second processor 820, wherein a transmitting terminal 821 of the second processor 820 transmits a control signal with a fixed period to a receiving terminal 9621 of the second integrated circuit 9620, a first output terminal (not shown in fig. 12) of the second integrated circuit 9621 is electrically connected to the first clock input terminal CK through a first clock signal line 951, and a second output terminal (not shown in fig. 12) of the second integrated circuit 9620 is electrically connected to the second clock input terminal XCK through a second clock signal line 952; the first clock signal line 951 is used for transmitting the first clock signal CKV1, and the second clock signal line 952 is used for transmitting the second clock signal CKV 2.

Illustratively, the display panel 90 further includes a scan shift register trigger signal line 953, the scan shift register trigger signal line 953 is electrically connected to the scan trigger signal receiving terminal IN1 of the first stage of the first scan driver circuit 950, and then the scan trigger signal receiving terminal IN1 of each stage of the first scan driver circuit 950 is electrically connected to the scan signal output terminal OUT1 of the last stage of the first scan driver circuit 950 through the scan shift signal line 9311. The scan driver circuit 950 is configured to generate a scan signal according to clock signals provided by a first clock signal line 951 and a second clock signal line 952; the circuit element structure and the operation principle of the scan driving circuit 950 can adopt any structure and the corresponding operation principle known to those skilled in the art, and are not described in detail nor limited in the embodiments of the present invention.

For example, the structure of the second integrated circuit 9620 can be understood by referring to the above explanation of the first integrated circuit 9610, and the structure of the second processor 820 can be understood by referring to the above explanation of the first processor 810, which is not repeated herein.

On this basis, with continued reference to fig. 12-14, the first clock signal CKV1 includes a plurality of first clock enable level periods T_C1The second clock signal CKV2 includes a plurality of second clock enable level periods T_C2The first clock signal CKV1 and the second clock signal CKV2 have opposite phases to each other, and the first clock enable level period T_C1And a second clock enable level period T_C2Sequentially spaced, and at least two clock gaps (shown in fig. 14 at △ TC1 and △ TC 2) of different durations.

Wherein, the clock gap refers to the adjacent first clock enable level period T_C1And a second clock enable level_C2A clock gap including a first type clock gap △ TC1 and a second type clock gap △ TC2, the first type clock gap △ TC1 being a jth (e.g., 1 st) first clock enable level period T_C1And the (j + 1) th (e.g., 2 nd) second clock enable levelTime interval T_C2The second-type clock gap △ TC2 is the kth (e.g., 1 st) second clock enable level period T_C2And the (k + 1) th (e.g., 2 nd) first clock enable level period T_C1The length of time that lasts between the enabling times of (1); j is a positive integer and k is a positive integer.

It should be noted that, in the above paragraph, the first clock enable level period T_C1And a second clock enable level_C2The difference in the nomenclature of the first type clock gap △ TC1 and the second type clock gap △ TC2 is merely to distinguish that the clock gap is the "first clock enable level period T_C1Is the start time of the non-enable level of (1) or is the second clock enable level period T_C2As the start time.

Wherein, the first clock signal CKV1 and the second clock signal CKV2 are both enabled at a high level, and when the first clock signal CKV1 is at a high level, the second clock signal CKV2 can be at a low level; when the first clock signal CKV1 is low, the second clock signal CKV2 may be high, and the high signal does not appear at the same time. First clock enable level period T_C1And a second clock enable level period T_C2The enable level periods sequentially and intermittently correspond to the scan timing periods of the scan signal.

Illustratively, the first clock enable level period T of the first clock signal CKV1 and the second clock signal CKV1_C1And a second clock enable level period T_C2The sequence of the enable level periods of (1) is: t is_C1、T_C2、 T_C1… …; correspondingly, the order of the scanning signals is: the enable level period of the Gate 1' signal (i.e., the first scan timing period T)_G1Enable level period of (d), the enable level period of the Gate 2' signal (i.e., the second scan timing period T)_G2Enable level period of (d), the enable level period of the Gate 3' signal (i.e., the third scan timing period T)_G3Enable level period) of (c), … ….

Based on this, the clock gaps and the scanning gaps are in one-to-one correspondence, and the time lengths are equal. The time lengths of at least two clock gaps are different, so that the time lengths of at least two scanning gaps are different, the time lengths of scanning time sequence sections corresponding to sub-pixel rows in one frame of scanning period can be different, the time lengths of the scanning time sequence sections can be set differently, the inherent periodicity of scanning signals can be damaged, and electromagnetic interference is reduced.

Optionally, the durations of the first type clock gap △ TC1 are all equal, the durations of the second type clock gap △ TC2 are all equal, and the duration of the first type clock gap △ TC1 is not equal to the duration of the second type clock gap △ TC 2.

Thus, the time lengths of the odd-numbered scanning gaps are equal, the time lengths of the even-numbered scanning gaps are equal, the time lengths of the odd-numbered scanning gaps are not equal to the time lengths of the even-numbered scanning gaps, the odd-numbered scanning gaps can be larger than the even-numbered scanning gaps, and the even-numbered scanning gaps can also be larger than the even-numbered scanning gaps.

Optionally, the durations △ TC1 of the first type of clock gaps are not equal, or the durations △ TC2 of the second type of clock gaps are not equal, or the durations △ TC1 of the first type of clock gaps are not equal, and the durations △ TC2 of the second type of clock gaps are not equal.

Thus, the time lengths of the odd number of scanning gaps are unequal; or the even number of scanning gaps are different in duration; or the time lengths of the odd-numbered scanning gaps are not equal, and the time lengths of the even-numbered scanning gaps are not equal. Therefore, the difference of the scanning gaps is larger, the difference of the duration of the scanning time sequence section is larger, the energy radiated outwards by the display device is favorably and uniformly distributed in the working frequency band of the display device, and the electromagnetic interference is favorably reduced.

The above exemplary illustration shows that the duration of the first type clock gap △ TC1 and the duration of the second type clock gap △ TC2 are separately set, and in other embodiments, they may be set as a whole, i.e., the clock gaps are regularly set, without distinguishing the first type clock gap △ TC1 and the second type clock gap △ TC 2.

Optionally, the clock gaps include at least two clock gaps with different durations, and the durations of the clock gaps with each duration are equal but not equal to the duration of the clock gap with another duration; the clock gaps comprise a first class of clock gaps and a second class of clock gaps, and the clock gaps with different durations are arranged at intervals.

The clock gaps and the scanning gaps are in one-to-one correspondence, and the time lengths are equal. According to the arrangement, the scanning interval is realized in different time lengths so as to reduce electromagnetic interference; the time length distribution of the scanning interval is more regular, thereby being beneficial to reducing the design difficulty of the driving algorithm.

For example, the clock gaps may include three clock gaps of different durations, shown as a clock gap △ TCA, a clock gap △ TCB, and a clock gap △ TCC, respectively, each of which may be unequal in duration, and may be ordered in a manner including:

△TCA、△TCB、△TCC、△TCA、△TCB、△TCC、……；

the method can also comprise the following steps:

△TCA、△TCA、△TCB、△TCB、△TCC、△TCC、……；。

△TCA、△TCB、△TCB、△TCC、△TCA、△TCB、△TCB、△TCC、……；

△TCA、△TCA、△TCB、△TCC、△TCA、△TCA、△TCB、△TCC、……；

It should be noted that the first clock gap △ TCA, the second clock gap △ TCB, and the third clock gap △ TCC may be the first type clock gap △ TC1, and may also be the second type clock gap △ TC2, and the arrangement sequence satisfies the first type clock gap △ TC1 and the second type clock gap △ TC2 arranged at intervals.

Meanwhile, the clock gaps of different kinds are only used for distinguishing the duration of the clock gaps.

In other embodiments, the number of clock gaps and the sorting manner may also be set according to actual requirements of the display device and the driving method thereof, which are neither described nor limited in this embodiment of the present invention.

Optionally, with continued reference to fig. 12 and 14, the second integrated circuit 9620 includes a counter 9622; the second integrated circuit 9620 outputs the next first clock enable level period T after different time intervals according to the count value of the counter 9622_C1Or the next second clock enable level period T_C2Of the signal of (1).

When the second integrated circuit 9620 detects the external H-sync signal, the counter 9622 provided inside the second integrated circuit 9620 starts to output the corresponding first clock signal CKV1 or second clock signal CKV2 after counting is completed, under the condition that the timing of the external control signal (also referred to as "external H-sync time") is kept constant.

Illustratively, if the hysteresis duration corresponding to one count is the same, the enable level period (corresponding to the start time of the enable level of the clock signal including the first clock signal CKV1 and the second clock signal CKV2) of the clock signal including the first clock enable level period T is relatively to the start time of the enable level of the row scan signal HS when the count values of the counter 9622 are different_C1And a second clock enable level period T_C2) The start time lags by different time lengths, and since the time interval between the start times of two consecutive enable levels of the row scan signal HS is fixed, the second integrated circuit 9620 may output the enable level of the first clock signal CKV1 or the second clock signal CKV2 at intervals of different time lengths, and further may realize the unequal durations of the clock gaps by setting different count values, and further realize the unequal durations of the scan gaps, so as to reduce the electromagnetic interference.

Meanwhile, the driving method of the display device provided by the embodiment of the invention only needs to set the difference of the counting values of the counter 9622 in the second integrated circuit 9620, and the method is simple and convenient to implement.

It should be noted that the count value in the counter 9622 may be set according to the actual requirements of the display device and the driving method thereof, and may be 1, 2, 3 or other positive integers known to those skilled in the art, which is not limited in the embodiment of the present invention.

The manner in which the scan drive signals are adjusted is exemplified above in connection with fig. 12-14; the following describes an exemplary design for implementing differentiation of the time length of the scan timing section by setting the structure of the scan driving circuit in conjunction with fig. 15 to 30.

Alternatively, referring to fig. 15 and 16, the display panel 90 further includes a second scan driving circuit 970 arranged in cascade, wherein the second scan driving circuit 970 is configured to output a scan signal to the scan line 931; each stage of the second scan driving circuit 970 includes a latch unit 9701 and a signal delay unit 9702; the latch units 9701 of the second scan driving circuits 970 are the same, and the signal delay units 9702 of at least two of the second scan driving circuits 970 are different, so as to implement the delay of the scan signals of different time lengths.

The second scan driving circuit 970 is configured to generate a scan signal according to a clock signal provided by the first clock signal line 951 and the second clock signal line 952, and the second scan driving circuit 970 changes its structure relative to the first scan driving circuit 950, so as to implement time delay of different time lengths of the scan signal on the premise that a period of the clock signal remains fixed and unchanged.

The latch units 9701 are identical, which means that the circuit operation logic of the latch units 9701 is identical, and the logic structure is as shown in fig. 16; and the time length of the signal delay caused by the latch unit 9701 is the same.

Illustratively, only one of the control clock signals of the latch unit 9701 is provided, such as the first clock signal CKV1 in fig. 16. The latch unit 9701 includes two clock inverters (CKINV) and one inverter, and the two CKINV are always operated in different states, so that the latch unit operates in two different operating states.

Illustratively, the first clock signal CKV1 is highNumber (H), latch unit 9701 is in the transfer state, as shown in FIG. 18, V_OUT＝V_INAnd realizing the level transmission function. When the first clock signal CKV1 is a low level signal (L), the latch unit 9701 is in a latch state, and V is shown in FIG. 19_OUT＝V_OUTAnd realizing the level latch function.

Here, the signal delay units 9702 are different, which means that the circuit operation logic of the signal delay units 9702 is different, and the logic structures of various different circuits are respectively shown in fig. 23 to 27, so that the time lengths of the signal delays caused by the signal delay units 9702 are different.

The delay time of the scan signal is understood to be a time length of a delay between the start time of the enable level of the next scan period and the end time of the enable level of the previous scan period, wherein the time length corresponds to a time length of one scan gap. Therefore, the time length of the scanning interval can be unequal, so that the time length of the scanning time sequence section in the scanning signal can be unequal, the natural frequency characteristic of the scanning signal is damaged, and the electromagnetic interference is reduced.

Next, the operation principle of the second scan driving circuit 970 will be described by way of example with reference to fig. 17, 20, 21, and 22.

Referring to fig. 17, the operation process of the second scan driving circuit 970 may include a first stage ZT1, a second stage ZT2 and a third stage ZT3, and the conversion of the intermediate control signal CTRL (e.g., the incident trigger signal, the first clock signal CKV1 and the second clock signal CKV2 in fig. 17) into the shift signal NEXT (e.g., the first shift signal NEXT1, the second shift signal NEXT2, the third shift signal NEXT3 and the fourth shift signal NEXT4 in fig. 17) and the scan signal GATE (corresponding to the first stage output signal GOUT1, the second stage output signal GOUT2, the third stage output signal GOUT3 and the fourth stage output signal GOUT4 in fig. 17) is completed.

IN the first stage ZT1, the level of the initial trigger signal STV is H, that is, the level of the trigger signal receiving terminal IN is H; the level of the first clock signal CKV1 is H, and the level of the second clock signal CKV2 is L; as shown in fig. 20, the latch unit operates in a transmission state, the second scan driving circuit 970 operates in a level shifting relationship, and the level of the shift signal NEXT is H and the level of the output signal GOUT is L.

IN the second stage ZT2, the level of the initial trigger signal STV is L, that is, the level of the trigger signal receiving terminal IN is L; the level of the first clock signal CKV1 is L, and the level of the second clock signal CKV2 is H; the latch unit operates in a latch state, the second scan driving circuit 970 operates in a level shift relationship as shown in fig. 21, the level of the shift signal NEXT is H, and the level of the output signal GOUT is H.

IN the second stage ZT2, the level of the initial trigger signal STV is L, that is, the level of the trigger signal receiving terminal IN is L; the level of the first clock signal CKV1 is H, and the level of the second clock signal CKV2 is L; as shown in fig. 22, the latch unit operates in a transmission state, the second scan driving circuit 970 operates in a level shifting relationship, and the level of the shift signal NEXT is L and the level of the output signal GOUT is L.

Thus, the scan signal GATE (corresponding to the output signal GOUT) of the current stage is obtained and maintained, and the trigger signal (i.e. the shift signal NEXT) of the NEXT stage is obtained

It should be noted that there is a time interval between the high-level enable period of the first clock signal CKV1 and the high-level enable period of the second clock signal CKV 2; the high level enable period of the initial trigger signal STV covers the 1 st high level enable period of the first clock signal CKV 1; the output signal GOUT is consistent with the NEXT clock pulse, and the high level enabling time interval of the corresponding shift signal NEXT covers the output signal GOUT; the output signal GOUT is obtained by performing logic operation on the shift signal NEXT and a clock signal (the odd-numbered second scan driving circuit 970 corresponds to the second clock signal CKV2, and the even-numbered second scan driving circuit 970 corresponds to the first clock signal CKV 1). Illustratively, the logical operation in fig. 16 includes 1 nand operation and 3 nand operations arranged in this order.

Optionally, in the circuit structure of the second scan driving circuit 970 in the display panel 90, the circuit structure of at least one signal delay unit 9702 is shown in fig. 23, where the signal delay unit 9702 includes a nand gate 7021 and a first inverter 7022, a first input of the nand gate 7021 is electrically connected to a clock signal line (e.g., a first clock signal line 951), a second input of the nand gate 7021 is electrically connected to an output 7011 of the latch unit 9701, an output of the nand gate 7021 is electrically connected to an input of a 1 st first inverter 7022, 3 first inverters 7022 are sequentially connected in series, and an output of a 3 rd first inverter 7022 is electrically connected to a corresponding scan line 931; and at least one other signal delay unit 9702 is shown in fig. 24, where the signal delay unit 9702 includes an and gate 7023, a not gate 7024, and a second inverter 7025, a first input terminal of the and gate 7023 is electrically connected to a clock signal line (e.g., a first clock signal line 951), a second input terminal of the and gate 7023 is electrically connected to an output terminal 7011 of the latch unit 9701, an output terminal of the and gate 7023 is electrically connected to an input terminal of the not gate 7024, an output terminal of the not gate 7024 is electrically connected to a 1 st second inverter 7025, 3 second inverters 7025 are sequentially connected in series, and an output terminal of a 3 rd second inverter 7025 is electrically connected to a corresponding scan line 931.

Thus, by designing different logic circuit structures of the signal delay unit 9702, the delay of the scan signals with different time lengths can be realized, so that the scan signals with different time delay lengths are output, the inherent frequency of the scan signals can be changed, and the reduction of electromagnetic interference is facilitated.

It should be noted that fig. 23 and 24 only exemplarily show that an input terminal of the signal delay unit 9702 is connected to the first clock signal line 951 by using the even-numbered second scan driving circuit 970, and when the second scan driving circuit 970 is an odd-numbered second scan driving circuit 970, the input terminal of the signal delay unit 9702 is connected to the second clock signal line 952.

It is to be understood that fig. 23 only exemplarily shows that the number of the first inverters 7022 is 3, and fig. 24 only exemplarily shows that the number of the second inverters 7025 is 3, but does not constitute a limitation on the number of inverters in the signal delay unit in the display device provided by the embodiment of the present invention. In other embodiments, the number of inverters may be set according to actual requirements of the display device and the driving method thereof, which is not limited in the embodiments of the present invention.

Alternatively, referring to fig. 25-27, the signal delay unit 9702 includes a nand gate 7021 and an inverter unit 7026, a first input of the nand gate 7021 is electrically connected to a clock signal line (e.g., a first clock signal line 951), a second input of the nand gate 7021 is electrically connected to an output 7011 of the latch unit, and is electrically connected to an output of the not gate 7021 and an input of the inverter unit 7026, and an output of the inverter unit 7026 is electrically connected to a corresponding scan signal line 931; the inverter unit 7026 includes a plurality of third inverters 7027 arranged in series, and the number of the third inverters 7027 in the inverter unit 7026 is not equal to the number of the third inverters 7027 in another inverter unit 7026, and the difference in the numbers is an even number.

The third inverters 7027 in the inverter unit 7026 are arranged in series, and one third inverter 7027 may invert the phase of the input signal by 180 degrees and output the inverted signal. When the number of the third inverters 7027 arranged in series in the inverter unit 7026 is an odd number, the output signal of the inverter unit 7026 is phase-inverted by 180 degrees with respect to the input signal thereof; when the number of the third inverters 7027 arranged in series in the inverter unit 7026 is an even number, the output signal of the inverter unit 7026 is phase-inverted by 360 degrees with respect to its input signal, that is, the phase of the output signal is the same as that of its input signal.

For example, the phase inversion is described by taking the high and low levels as an example: when the number of the third inverters 7027 in the inverter unit 7026 is an odd number, the input end of the inverter unit 7026 inputs a low level, and the output end thereof outputs a high level; the input terminal of the inverter unit 7026 inputs a high level, and the output terminal thereof outputs a low level. Based on this, when the phases of the input signals are the same, if the difference between the numbers of the third inverters 7027 in the two inverter units 7026 is an even number, the phases of the output signals thereof are also the same. Therefore, in the embodiment of the present invention, by setting the difference between the numbers of the third inverters 7027 to be an even number, the enable levels of the scan signals in the display signals of the pixel driving circuits in the display panel can be kept consistent, and are all high levels or all low levels, so that the structure of the display panel is simpler, and the driving method of the display device is simpler.

Meanwhile, the third inverter 7027 itself has a propagation delay effect, and the delay duration of the propagation delay depends on the load capacitance existing in the circuit trace of the third inverter 7027 itself and the turn-on condition (e.g., the threshold voltage of the transistor) of the circuit element therein, only the latter of which is discussed herein.

For example, the structure of the inverter (which may refer to the first inverter 7022, the second inverter 7025, or the third inverter 7027 herein) is as shown in fig. 28, and the transmission delay principle thereof is as shown in fig. 29. Referring to fig. 28 and 29, the inverter includes a P-type transistor 9511 and an N-type transistor 9512; the control terminal of the P-type transistor 9511 and the control terminal of the N-type transistor 9512 are electrically connected to an input signal terminal IN 5; a first terminal of the P-type transistor 9511 is electrically connected to a first potential terminal VGH, a first terminal of the N-type transistor 9512 is electrically connected to a second potential terminal VGL, and a potential of the first potential terminal VGH is higher than a potential of the second potential terminal VGL; the second terminal of the P-type transistor 9511 is electrically connected to the second terminal of the N-type transistor 9512, and both are electrically connected to a signal output terminal OUT 5.

For example, the operation principle of the inverter is exemplified by the input signal INV5 inputted to the signal terminal IN5 and the output signal OUTV5 outputted to the signal terminal OUT 5. When the INV5 is a high-level signal, the N-type transistor 9512 is turned on, and the voltage signal at the second voltage terminal VGL is output to the OUT5 terminal, i.e., a low-level signal is output; when the INV5 is a low-level signal, the P-type transistor 9511 is turned on, and the potential signal of the first potential terminal VGH is output to the OUT5 terminal, i.e., a high-level signal is output, thereby achieving phase inversion of the output signal OUTV5 with respect to the input signal INV 5.

Meanwhile, since the transistor has a threshold voltage (shown in fig. 29 as Vth potential), a signal is output only when the input signal INV5 is greater than the Vth potential. Therefore, when the rising edge (rising) of the input signal INV5 rises to the Vth potential, the output signal OUTV5 starts to fall (falling) from the VGH potential, and the interval from the rising edge start time of the input signal INV5 to the falling edge start time (i.e., the falling start time) of the output signal OUTV5 is the length of the delay (delay) time of the transistor.

For example, the transistors in the embodiments of the present invention may be Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs) or other types of transistors known to those skilled in the art, which are not described or limited herein. In other embodiments, the inverter may also adopt other circuit structures known to those skilled in the art to implement the phase inversion logic and the delay effect of the inverter, which are not described nor limited in this embodiment of the present invention.

Wherein, when the structural parameters of the third inverters 7027 are the same, each inverter 7027 can realize a time delay of the same duration. Based on this, when the number of inverters 7027 in different inverter units 7026 is set to be different, time delays of different time lengths can be realized.

Illustratively, the time delay of the signal delay unit 9702 shown in fig. 25 has a duration between that of the signal delay unit 9702 shown in fig. 26 and that of the signal delay unit 9702 shown in fig. 27.

It should be noted that fig. 25-27 only exemplarily show that the number of the inverters 7027 in the inverter unit 7026 is 3, 1, and 5, respectively, but do not constitute a limitation to the display device and the driving method thereof provided by the embodiment of the present invention. In other embodiments, the number of the inverters 7027 in the inverter unit 7026 may also be set according to actual requirements of the display device and the driving method thereof, which is not limited in the embodiments of the present invention.

On the basis, in order to reduce the electromagnetic interference and simultaneously reduce the structural design difficulty of the display device, the number of inverters in the inverter unit can be regularly set; with this arrangement, the regular variation of the scanning time period of the scanning signal can be realized.

Alternatively, with continued reference to fig. 25-27, inverter cell 7026 comprises at least two different inverter cells 7026; the number of the third inverters 7027 in the same inverter unit 7026 is equal, and the number of the third inverters 7027 in different inverter units 7026 is different; the inverter units 7026 of different kinds are arranged at intervals.

The "same kind" and the "different kind" of the inverter unit 7026 are defined as the number of the inverters 7027 therein. That is, if the number of inverters 7027 in inverter cell 7026 is the same, it is the same type of inverter cell 7026; if the number of inverters 7027 in inverter unit 7026 is different, it is a different kind of inverter unit 7026.

For example, fig. 25, 26 and 27 show three different inverter units 7026, which are respectively denoted by 26A, 26B and 26C, and the inverter units may be arranged in a cascade sequence of the second scan driving circuit 970, which includes:

26A, 26B, 26C, … … (shown in FIG. 11);

the method can also comprise the following steps:

26A、26B、26B、26C、26A、26B、26B、26C、……；

26A、26B、26A、26B、26C、26A、26B、26A、26B、26C、……；

For example, the timing front-back variation comparison graph can be as shown in fig. 30, wherein the first clock signal CKV1 and the second clock signal CKV2 have a fixed period, the duration of the fixed period is consistent with the scanning period of the sub-pixel row (the scanning signals of each stage are respectively shown as Gate01, Gate02, Gate03 and Gate 04) obtained when the time delay of the signal delay unit is ignored, and the scanning period of the sub-pixel row (the scanning period is shown as T) obtained when the time delay of the signal delay unit in the prior art is considered_G0It is shown that the scanning signals of the respective stages are respectively shown by Gate1, Gate2, Gate3, and Gate 4) to be uniform. In the driving timing sequence of the display device according to the embodiment of the present invention, the scanning signals of each stage are respectively shown as Gate1 ', Gate 2', Gate3 'and Gate 4'. Bonding ofAs can be seen from fig. 23-27 and fig. 30, since the logic circuit compositions of the signal delay units in the second scan driving circuit corresponding to each row of sub-pixels are not completely consistent, the lengths of the delay times of the scan signals at different levels are not consistent, so that the duration of each scan time period of the scan signals in the driving timing of the display panel is not maintained at a constant value, thereby improving the electromagnetic interference problem caused by the frequency fixing characteristic of the scan signals.

It should be noted that the logic circuits, such as the "latch unit", the "and gate", the "not gate", the "nand gate", and the "inverter", may be implemented by any actual circuit structure known to those skilled in the art, and the embodiments of the present invention are not described or limited herein.

On the basis of the foregoing embodiments, embodiments of the present invention further provide a display device, which can be driven by applying any one of the driving methods provided in the foregoing embodiments, or understood that the display device can execute any one of the driving methods provided in the foregoing embodiments, so that the display device also has the beneficial effects of the driving method provided in the foregoing embodiments, and the same points can be understood with reference to the foregoing understanding, and are not described again below.

For example, the display device 80 may be a mobile phone, a computer, a smart wearable device (e.g., a smart watch), a vehicle-mounted display screen, a vehicle-mounted touch screen, or other types of electronic devices known to those skilled in the art, which is not limited in the present embodiment. When the display device 80 is applied to a vehicle such as an automobile, a ship, or an airplane to serve as a display screen, it may be a local structure independent from the inherent structure of the vehicle, or may be integrated with other structural components of the vehicle, for example, the display device 80 may be integrated with a front windshield, or may be integrated with a table top around an instrument panel, which is not limited in the embodiments of the present invention.

For example, when the display device 80 is applied to a vehicle-mounted display screen, the influence of the display device 80 on other vehicle-mounted electronic products (such as a vehicle-mounted radio, a vehicle-mounted audio system, or other vehicle-mounted display screens) can be reduced by setting the duration of the scanning time sequence not to be maintained as a constant duration value, which is beneficial to realizing the normal operation of the other vehicle-mounted electronic products.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. The driving method of the display device is characterized in that the display device comprises a display panel, the display panel comprises scanning lines and data lines, the scanning lines and the data lines are intersected to define sub-pixel regions, and sub-pixels are arranged in the sub-pixel regions; the driving method includes:

acquiring an image to be displayed;

displaying the image to be displayed according to the display signal;

2. The driving method as claimed in claim 1, wherein the duration of each of the scanning gaps is different from each other in one frame of the scanning period.

3. The driving method according to claim 1, wherein the scan gap comprises a first scan gap and a second scan gap, the first scan gap is a time difference between a non-enable level start time of a 2m-1 th scan time segment and an enable level start time of a 2 m-th scan time segment, the second scan gap is a time difference between a non-enable level start time of a 2 m-th scan time segment and an enable level start time of a 2m +1 th scan time segment, the first scan gap and the second scan gap are not equal in duration, and m is a positive integer.

4. The driving method according to claim 1, wherein the scan gap includes a first scan gap, a second scan gap, and a third scan gap, the first scan gap is a time difference between a non-enable level start time of the 3n-2 th scan timing segment and an enable level start time of the 3n-1 th scan timing segment, the second scan gap is a time difference between a non-enable level start time of the 3n-1 th scan timing segment and an enable level start time of the 3 n-3 th scan timing segment, the third scan gap is a time difference between a non-enable level start time of the 3 n-3 th scan timing segment and an enable level start time of the 3n +1 th scan timing segment, the first scan gap, the second scan gap, and the third scan gap are all unequal in time length to each other, and n is a positive integer.

5. The driving method according to claim 1, wherein the display panel further comprises a first integrated circuit, the display device further comprises a first processor, a transmitting terminal of the first processor sends a control signal to a receiving terminal of the first integrated circuit, and an output terminal of the first integrated circuit outputs the gate-on signal;

the control signal comprises a line synchronization signal which is used for determining an effective line signal interval; the line synchronizing signal comprises a plurality of sub-synchronizing signals which are sequentially arranged, and each sub-synchronizing signal comprises a first blank time interval, an effective time interval and a second blank time interval which are sequentially connected; the effective time interval corresponds to the enabling level time interval of the scanning time sequence section one by one, and the duration of the effective time interval is greater than or equal to the duration of the writing time interval of the data signal; the second blank period of the qth sub-synchronization signal and the first blank period of the q +1 th sub-synchronization signal both correspond to the same scanning gap, the duration of the effective period of each sub-synchronization signal is equal, and q is a positive integer;

wherein the durations of at least two first blank periods in the sub-synchronization signals are different; or

The time lengths of at least two second blank periods in the sub-synchronous signals are different; or

The at least two first blank periods in the sub-synchronization signal have different durations, and the at least two second blank periods in the sub-synchronization signal have different durations.

6. The driving method according to claim 5, wherein the first blank periods in the sub-synchronization signals in the one-frame scanning period are all unequal in duration; or

In the scanning period of the frame, the duration of the second blank period in each sub-synchronization signal is unequal; or

In the one-frame scanning period, the durations of the first blanking periods in each of the sub-synchronization signals are all different, and the durations of the second blanking periods in each of the sub-synchronization signals are all different.

7. The driving method according to claim 5, wherein the first blank period includes at least two different time lengths of the first blank period, the time lengths of the first blank period of each time length being equal but not equal to the time length of the first blank period of the other time length; setting the first blank time interval with different durations; or

The second blank periods comprise at least two second blank periods with different durations, and the duration of the second blank period in each duration is equal to but not equal to the duration of the second blank period in the other duration; setting the second blank time interval with different time lengths; or

The first blank periods comprise at least two first blank periods with different time lengths, and the time lengths of the first blank periods in each time length are equal but not equal to the time length of the first blank period in the other time length; the first blank periods with different durations are arranged at intervals, the second blank period comprises at least two second blank periods with different durations, and the duration of the second blank period in each duration is equal to but not equal to the duration of the second blank period in the other duration; the second blanking interval of different durations is set.

8. The driving method according to claim 5, wherein the control signal further includes a data driving signal for determining a writing period of the data signal;

the effective writing time of the data driving signal is within the effective period of the row synchronization signal.

9. The driving method according to claim 1, wherein the display panel further comprises a second integrated circuit, a first clock signal line, a second clock signal line, and a plurality of first scan driving circuits arranged in cascade, the first scan driving circuits comprising a first clock input terminal, a second clock input terminal, and a gate-on signal output terminal, the scan lines being electrically connected to the gate-on signal output terminal; the display device further comprises a second processor, wherein a sending end of the second processor sends a control signal with a fixed period to a receiving end of the second integrated circuit, a first output end of the second integrated circuit is electrically connected to the first clock input end through the first clock signal line, and a second output end of the second integrated circuit is electrically connected to the second clock input end through the second clock signal line;

the first clock signal line is used for transmitting a first clock signal, and the second clock signal line is used for transmitting a second clock signal; the first clock signal includes a plurality of first clock enable level periods, the second clock signal includes a plurality of second clock enable level periods, the first clock signal and the second clock signal have opposite phases to each other, and the first clock enable level periods and the second clock enable level periods are sequentially arranged at intervals; and the durations of at least two clock gaps are different;

wherein the clock gap refers to a time difference between the adjacent first clock enable level period and the second clock enable level period; the clock gaps comprise a first type of clock gap and a second type of clock gap; the first type of clock gap is the time length lasting between the starting time of the non-enabling level of the jth first clock enabling level period and the starting time of the enabling level of the jth +1 second clock enabling level period, and the second type of clock gap is the time length lasting between the non-enabling time of the kth second clock enabling level period and the enabling time of the kth +1 first clock enabling level period; j is a positive integer and k is a positive integer.

10. The driving method according to claim 9, wherein the first type of clock gaps are all equal in duration, the second type of clock gaps are all equal in duration, and the first type of clock gaps are not equal in duration to the second type of clock gaps.

11. The driving method according to claim 9, wherein the durations of the first type of clock gaps are each unequal; or

The time lengths of the second class of clock gaps are not equal; or

The durations of the first type of clock gaps are unequal, and the durations of the second type of clock gaps are unequal.

12. The driving method according to claim 9, wherein the clock gap includes at least two different durations of the clock gap, the duration of the clock gap of each duration being equal but not equal to the duration of the clock gap of the other duration;

the clock gaps comprise the first type of clock gaps and the second type of clock gaps, and the clock gaps with different durations are arranged at intervals.

13. The driving method according to claim 9, wherein the second integrated circuit includes a counter;

and the second integrated circuit outputs a signal of the next first clock enabling level period or a signal of the next second clock enabling level period after different time intervals according to the counting value of the counter.

14. The driving method according to claim 1, wherein the display panel further comprises a second scan driving circuit arranged in cascade, the second scan driving circuit being configured to output the gate-on signal to the scan lines;

each stage of the second scanning driving circuit comprises a latch unit and a signal delay unit; the latch units of the second scanning driving circuits are the same, and the signal delay units of at least two second scanning driving circuits are different, so that the delay of the grid opening signals with different time lengths is realized.

15. The driving method according to claim 14, wherein at least one of the signal delay units comprises a nand gate and a first inverter, a first input terminal of the nand gate is electrically connected to a clock signal line, a second input terminal of the nand gate is electrically connected to an output terminal of the latch unit, an output terminal of the nand gate is electrically connected to an input terminal of the first inverter, and an output terminal of the first inverter is electrically connected to the corresponding scan line; and

the at least one other signal delay unit comprises an AND gate, a NOT gate and a second phase inverter, wherein a first input end of the AND gate is electrically connected to a clock signal line, a second input end of the AND gate is electrically connected to an output end of the latch unit, an output end of the AND gate is electrically connected to an input end of the NOT gate, an output end of the NOT gate is electrically connected to the second phase inverter, and an output end of the second phase inverter is electrically connected to the corresponding scanning line.

16. The driving method according to claim 14, wherein the signal delay unit includes a nand gate and an inverter unit, a first input terminal of the nand gate is electrically connected to a clock signal line, a second input terminal of the nand gate is electrically connected to an output terminal of the latch unit, an output terminal of the nand gate is electrically connected to an input terminal of the inverter unit, and an output terminal of the inverter unit is electrically connected to the corresponding scan signal line;

the inverter unit comprises a plurality of third inverters which are arranged in series, the number of the third inverters in the inverter unit is not equal to the number of the third inverters in the other inverter unit, and the difference between the numbers is even number.

17. The driving method according to claim 16, wherein the inverter unit includes at least two different inverter units;

the number of the third inverters in the same type of inverter units is equal, and the number of the third inverters in different types of inverter units is different;

different types of the inverter units are arranged at intervals.

18. A display device characterized in that it is adapted to perform the driving method of any of claims 1-17.