CN107689217B

CN107689217B - Gate drive circuit and display device

Info

Publication number: CN107689217B
Application number: CN201610635597.6A
Authority: CN
Inventors: 林松君; 詹建廷; 许佑端; 陈柏毅
Original assignee: Hannstar Display Corp
Current assignee: Hannstar Display Corp
Priority date: 2016-08-05
Filing date: 2016-08-05
Publication date: 2020-08-07
Anticipated expiration: 2036-08-05
Also published as: CN107689217A

Abstract

The invention discloses a gate driving circuit and a display device. The gate driving circuit is used for driving the display panel and comprises shift registers from a 1 st stage to an Nth stage. The shift registers are used for receiving a start signal, and respectively generating and sequentially outputting a 1 st-Nth scanning signal to the display panel, wherein N is a positive integer greater than or equal to 4. The start signal is used to trigger the 1 st and 2 nd shift registers to generate the 1 st and 2 nd scan signals, respectively, and to reset the 3 rd to nth shift registers. The gate driving circuit of the invention can avoid the image display problem caused by the influence of noise, thereby improving the image display quality, the reliability of the shift register, reducing the power consumption and the like.

Description

Gate drive circuit and display device

Technical Field

The present invention relates to a gate driving circuit and a display device, and more particularly, to a gate driving circuit and a display device capable of improving image display quality.

Background

In a flat panel display device, such as a liquid crystal display (L CD) device or an organic light emitting diode (O L ED) display device, a plurality of shift registers are commonly provided to control the gray scales displayed at the same time point by each pixel in the display device.

Disclosure of Invention

The present invention is directed to a gate driving circuit and a display device, which can avoid the problem of image display caused by the influence of noise, so as to improve the image display quality, the reliability of the shift register, and reduce the power consumption.

According to the above-mentioned objective of the present invention, a gate driving circuit for driving a display panel is provided, which includes 1 st to nth shift registers. The shift registers are used for respectively generating and sequentially outputting 1 st to Nth scanning signals to the display panel, each shift register is used for receiving a starting signal, the starting signal is used for triggering the 1 st and 2 nd shift registers to respectively generate 1 st and 2 nd scanning signals and resetting the 3 rd to Nth shift registers, and N is a positive integer greater than or equal to 4.

According to an embodiment of the present invention, the ith stage of the shift registers includes a precharge unit, a pull-up unit and a pull-down unit. The pre-charge unit is used for receiving a first input signal and a second input signal and outputting a pre-charge signal from a node according to the first input signal and the second input signal. The pull-up unit is coupled to the pre-charge unit and is used for receiving the pre-charge signal and the clock signal and outputting the i-th-stage scanning signals of the scanning signals according to the pre-charge signal and the clock signal. The pull-down unit is coupled to the pre-charge unit and the pull-up unit, and is used for receiving the pre-charge signal and the pull-down control signal and controlling the level of the ith scanning signal of the scanning signals according to the pre-charge signal and the pull-down control signal.

According to another embodiment of the present invention, the j-th scan signal of the scan signals is inputted to the pull-down unit of the (j +1) -th shift register of the shift registers, and the (j +1) -th scan signal of the scan signals is inputted to the pull-down unit of the j-th shift register of the shift registers, wherein j is an odd number.

According to another embodiment of the present invention, the precharge unit includes a first transistor and a second transistor. The gate of the first transistor is used for receiving a first input signal, the first source/drain of the first transistor is used for receiving a first reference potential, and the second source/drain of the first transistor is coupled to a node. The gate of the second transistor is used for receiving a second input signal, the first source/drain of the second transistor is used for receiving a second reference potential, and the second source/drain of the second transistor is coupled to the node.

According to another embodiment of the present invention, when i is any positive integer from 1 to 2, the first input signal is a start signal, and the second input signal is an (i +3) th scan signal of the scan signals; when i is any positive integer from 3 to (N-3), the first input signal is an (i-2) th scanning signal of the scanning signals, and the second input signal is an (i +3) th scanning signal of the scanning signals; when i is any positive integer from (N-2) to N, the first input signal is an (i-2) th scan signal of the scan signals, and the second input signal is a start signal or an end signal.

According to another embodiment of the present invention, the pull-up unit includes a third transistor having a gate coupled to the node, a first source/drain for outputting the ith scan signal, and a second source/drain for receiving the clock signal.

According to another embodiment of the present invention, the pull-down unit includes a fourth transistor, a fifth transistor, a sixth transistor. The first source/drain of the fourth transistor is used for receiving the reference potential, and the second source/drain of the fourth transistor is used for receiving the third input signal. The gate of the fifth transistor is coupled to the gate of the fourth transistor, the first source/drain of the fifth transistor is for receiving the reference potential, and the second source/drain of the fifth transistor is for receiving the fourth input signal. The gate of the sixth transistor is coupled to the gate of the fourth transistor, the first source/drain of the sixth transistor is for receiving the reference potential, and the second source/drain of the sixth transistor is for receiving the fifth input signal. The gate of the seventh transistor is coupled to the gate of the fourth transistor, the first source/drain of the seventh transistor is for receiving the reference potential, and the second source/drain of the seventh transistor is for receiving the sixth input signal. The first source/drain of the eighth transistor is used for receiving the pull-down control signal, and the second source/drain of the eighth transistor is coupled to the gate of the fourth transistor. The gate and the first source/drain of the ninth transistor are used for receiving the pull-down control signal, and the second source/drain of the ninth transistor is coupled to the gate of the eighth transistor. A gate of the tenth transistor is configured to receive the seventh input signal, a first source/drain of the tenth transistor is configured to receive the reference potential, and a second source/drain of the tenth transistor is coupled to the gate of the fourth transistor. A gate of the eleventh transistor is configured to receive the third input signal, a first source/drain of the eleventh transistor is configured to receive the reference potential, and a second source/drain of the eleventh transistor is coupled to the gate of the fourth transistor. The gate of the twelfth transistor is configured to receive the fourth input signal, the first source/drain of the twelfth transistor is configured to receive the reference potential, and the second source/drain of the twelfth transistor is coupled to the gate of the eighth transistor. The gate of the thirteenth transistor is used for receiving the third input signal, the first source/drain of the thirteenth transistor is used for receiving the reference potential, and the second source/drain of the thirteenth transistor is coupled to the gate of the eighth transistor.

According to another embodiment of the present invention, when i is 1 or 2, the third input signal is a signal located at a node of a 1 st-stage shift register of the shift registers, the fourth input signal is a 1 st-stage scan signal of the scan signals, the fifth input signal is a signal located at a node of a 2 nd-stage shift register of the shift registers, the sixth input signal is a 2 nd-stage scan signal of the scan signals, and the seventh input signal is a start signal.

According to another embodiment of the present invention, when i is an odd number greater than or equal to 3 and less than or equal to N, the third input signal is a signal located at a node of an i-th stage shift register, the fourth input signal is an i-th stage scan signal, the fifth input signal is a signal located at a node of an (i +1) -th stage shift register among the shift registers, the sixth input signal is an (i +1) -th stage scan signal among the scan signals, and the seventh input signal is an (i-2) -th stage scan signal among the scan signals.

According to another embodiment of the present invention, when i is an even number greater than or equal to 3 and less than or equal to N, the third input signal is a signal at a node of an (i-1) th shift register among the shift registers, the fourth input signal is an (i-1) th scan signal of the scan signals, the fifth input signal is a signal at a node of an i-th shift register, the sixth input signal is an i-th scan signal, and the seventh input signal is an (i-3) th scan signal of the scan signals.

According to another embodiment of the present invention, when i is any positive integer from 3 to N, the ith stage shift register further includes a reset unit coupled to the precharge unit and the pull-up unit for resetting a level of a node of the ith stage shift register before the gate driving circuit generates the 1 st to nth stage scan signals.

According to another embodiment of the present invention, the reset unit includes a fourteenth transistor having a gate for receiving the start signal, a first source/drain for receiving the second reference potential, and a second source/drain coupled to the node.

According to another embodiment of the present invention, the clock signals inputted to two adjacent shift registers of the shift registers are different by 1/4 clock cycles.

According to another embodiment of the present invention, the pull-down control signals inputted to two adjacent shift registers are mutually inverted.

According to the above object of the present invention, a gate driving circuit for driving a display panel includes a plurality of shift registers. The shift registers are used for respectively generating and sequentially outputting a plurality of scanning signals to the display panel, each shift register is used for receiving a start signal, and each shift register is used for generating a driving signal or resetting according to the start signal.

According to another aspect of the present invention, a display device includes a display panel and a first gate driving circuit. The first gate driving circuit is used for driving the display panel and is arranged on one side of the display panel. The first gate driving circuit includes first shift registers of 1 st to nth stages. The first shift registers are used for respectively generating and sequentially outputting 1 st-nth first scanning signals to the display panel, and each of the first shift registers is used for receiving a start signal, wherein the start signal is used for triggering the 1 st-stage first shift register and the 2 nd-stage first shift register to respectively generate 1 st-stage first scanning signals and 2 nd-stage first scanning signals and resetting the 3 rd-nth first shift register, and N is a positive integer greater than or equal to 4.

According to an embodiment of the present invention, the gate driving circuit further includes a second gate driving circuit. The second gate driving circuit is used for driving the display panel and is arranged on the other side of the display panel opposite to the first gate driving circuit. The second gate driving circuit includes 1 st to Nth stages of second shift registers. The second shift registers are used for respectively generating and sequentially outputting a 1 st-nth second scanning signal to the display panel, and each of the second shift registers is used for receiving a start signal, wherein the start signal is used for triggering the 1 st-stage second shift register and the 2 nd-stage second shift register to respectively generate a 1 st-stage second scanning signal and a 2 nd-stage second scanning signal and resetting the 3 rd-nth second shift register.

According to another embodiment of the present invention, the second scan signals have substantially the same timing as the first scan signals.

Compared with the prior art, the invention has the following beneficial effects: the gate driving circuit and the display device of the invention can avoid the image display problem caused by the influence of noise, thereby improving the image display quality, the reliability of the shift register, reducing the power consumption and the like.

Drawings

For a more complete understanding of the embodiments and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a display device according to some embodiments of the invention;

FIG. 2 is a schematic diagram of a gate driving circuit according to some embodiments of the invention;

fig. 3A and 3B are circuit diagrams of stage 1 and stage 2 shift registers of fig. 2, respectively;

fig. 4A and 4B are circuit diagrams of the ith and (i +1) th stage shift registers of fig. 2, respectively;

FIG. 5 is a timing diagram of the gate driving circuit of FIG. 2;

FIG. 6 is a schematic diagram of a display device according to some embodiments of the invention.

Detailed Description

Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the invention.

Fig. 1 is a schematic diagram of a display device 100 according to some embodiments of the invention, the display device 100 may be a liquid crystal display panel of various types, such as a Twisted Nematic (TN) type, an in-plane switching (IPS) type, an FFS (fringe-field switching) type, or a VA (vertical alignment) type, or an organic light emitting diode (O L ED) display panel, but not limited thereto, the display device 100 has a display panel 110 with a plurality of pixels arranged in an array in the display panel 110, which are commonly used to display an image, a source driver 120 for converting image data into source driving signals and transmitting the source driving signals to the pixels in the display area 110, a gate driver 130 for generating gate driving signals and transmitting the gate driving signals to the pixels in the display area 110, and a gate driver 120 for generating gate driving signals and transmitting the gate driving signals to the pixels in the display area 110, the source driving signals and the gate driving signals being provided in the display panel 110, and the gate driver 130 being provided in other embodiments, the display panel 110 and the source driving signals being provided in the display area 110, and the display system 130 being integrated system 130, as shown in the embodiment, the display panel 110, and the display system 130, and the display panel 110, and the display system 130 are shown in fig. 1.

FIG. 2 is a schematic diagram of the gate driving circuit 200 of FIG. 1 according to some embodiments of the present invention, the gate driving circuit 200 is suitable for the display device 100 of FIG. 1 or other similar display devices, and is described below with reference to the display device 100 of FIG. 1. the gate driving circuit 200 is a part of the gate driver 130, and includes clock signal lines L-L, a start signal line S, an end signal line R, and shift registers 210(1) -210 (N) from level 1 to level N, wherein N is a positive integer greater than or equal to 4. further, N is an even number greater than 4, and each two adjacent shift registers of the shift registers 210 (210) -210 (N) are coupled to clock signal lines L-L for providing clock signals C1-C4 to corresponding shift registers 210(1) -210 (N) for providing clock signals C6348 to clock signals C3527-210 (27) -210 (N638 for providing clock signals C27-210 (27) to scanning signals C.210) for scanning through stages N27, 27-210 (27, 11) and 27 for providing clock signals for scanning signals from the scanning signals C.210 (210) from the scanning signals N.210 (210) to 210 (210) for scanning through SC 14) for the scanning through a scanning signal stages V.1-V.210 (210) and 27) for displaying a phase difference between the clock signal stages (76) and a (76) for the scanning signals (V.V.210) for the scanning signals (76) from the stages (76) for the stages (V.V.V.V.V.V.210) are provided by a (76) and N.210 (76) for the stages 210 (76) for the stages (76) and a (76) for the stages (V.V.V.V.V.V.V.V.V.V.V.V.210) for the stages (76) for the scanning signals (76) and the stages (76) for the scanning.

Fig. 3A and 3B are circuit diagrams of the 1 st stage shift register 210(1) and the 2 nd stage shift register 210(2) of fig. 2, respectively. The stage 1 shift register 210(1) and the stage 2 shift register 210(2) include a precharge unit 310, a pull-up unit 320, and a pull-down unit 330.

In the stage 1 shift register 210(1) of FIG. 3A, the pre-charge unit 310 is configured to receive the start signal STV and the stage 4 scan signal SC (4), and output a pre-charge signal from the node X (1) according to the start signal STV and the stage 4 scan signal SC (4). The pre-charge unit 310 includes transistors M1, M2. the gate of the transistor M1 is configured to receive the start signal STV, the first source/drain of the transistor M1 is configured to receive the reference potential VGH, and the second source/drain of the transistor M1 is coupled to the node X (1). The gate of the transistor M2 is configured to receive the stage 4 scan signal SC (4). The first source/drain of the transistor M2 is configured to receive the reference potential VG L, and the second source/drain of the transistor M2 is coupled to the node X (1). the reference potentials VGH and VG L are relatively high-level voltage and low-level voltage, respectively.

In the stage 1 shift register 210(1) of fig. 3A, the pull-up unit 320 is coupled to the precharge unit 310, receives the precharge signal and the clock signal C1, and outputs the stage 1 scan signal SC (1) according to the precharge signal and the clock signal C1. The pull-up unit 320 includes a transistor M3 having a gate coupled to the node X (1), a first source/drain for receiving the clock signal C1, and a second source/drain for outputting the level 1 scan signal SC (1).

In the first-stage shift register 210(1) of fig. 3A, the pull-down unit 330 is coupled to the pre-charge unit 310 and the pull-up unit 320 for receiving the pre-charge signal and the pull-down control signal GPW L1, and controls the level of the first-stage scan signal SC (1) according to the pre-charge signal and the pull-down control signal GPW L1, (330) the pull-down unit 330 includes transistors M L-M13. the first source/drain of transistor M L is coupled to receive the reference potential VG L0, and the second source/drain of transistor M L is coupled to node X (1) and for receiving the pre-charge signal M L. the gate of transistor M L is coupled to the gate of transistor M L, the first source/drain of transistor M L is coupled to receive the reference potential VG L, and the second source/drain of transistor M L is coupled to receive the reference potential VG 361. the gate of transistor M L, the drain of transistor M L is coupled to receive the gate of the pre-charge signal VG L, the drain of transistor M L is coupled to the gate of the pre-charge transistor M L, and the drain of the first-drain of the transistor M L is coupled to receive the pre-charge signal VG 2, the drain of the first-charge signal VG L, the drain of the first-charge signal VG L, the drain of the transistor M L is coupled to receive the drain of the transistor M L, (M L, and the drain of the transistor M L, the first-charge transistor M L is coupled to receive the drain of the first pre-charge transistor M L, (M L, and the drain of the transistor M L, the drain of the transistor M L, and the drain of the transistor M L is coupled to receive the drain of the transistor M L, (M L, and the drain of the transistor M L, and the drain of the transistor M L, and the drain of the transistor M L, the drain of the transistor M L is coupled to receive the drain of the transistor M L, (M L, and the transistor M L, the drain of the transistor M L, and the shift register 210 is coupled to receive the drain of the.

In the stage 2 shift register 210(2) of FIG. 3B, the pre-charge unit 310 is configured to receive the start signal STV and the stage 5 scan signal SC (5), and output a pre-charge signal from the node X (2) according to the start signal STV and the stage 5 scan signal SC (5). The gate of the transistor M1 is configured to receive the start signal STV, the first source/drain of the transistor M1 is configured to receive the reference signal VGH, and the second source/drain of the transistor M1 is coupled to the node X (2). The gate of the transistor M2 is configured to receive the stage 5 scan signal SC (5), the first source/drain of the transistor M2 is configured to receive the reference signal VG L, and the second source/drain of the transistor M2 is coupled to the node X (2).

In the 2 nd stage shift register 210(2) of fig. 3B, the pull-up unit 320 is coupled to the precharge unit 310, which receives the precharge signal and the clock signal C2, and outputs the 2 nd stage scan signal SC (2) according to the precharge signal and the clock signal C2. The gate of the transistor M3 is coupled to the node X (2), the first source/drain of the transistor M3 is for receiving the clock signal C2, and the second source/drain of the transistor M3 is for outputting the 2 nd scan signal SC (2).

In the 2 nd stage shift register 210(2) of fig. 3B, the pull-down unit 330 is coupled to the pre-charge unit 310 and the pull-up unit 320 for receiving the pre-charge signal and the pull-down control signal GPW 2, and controls the level of the 2 nd stage scan signal SC (2) according to the pre-charge signal and the pull-down control signal GPW 2, the pull-down control signals GPW 01 and GPW 12 are inverted with respect to each other, the first source/drain of the transistor M is coupled to receive the reference potential VG 2, the second source/drain of the transistor M is coupled to the node X (1) in the 1 st stage shift register 210(1), and is configured to receive the pre-charge signal of the 1 st stage shift register 210(1), the gate of the transistor M is coupled to the gate of the transistor M, the first source/drain of the transistor M is configured to receive the reference potential VG 3, the second source/drain of the transistor M is configured to receive the first source VG 3, the gate of the 1 st stage scan signal SC (1) is coupled to the gate of the transistor M, the transistor M is coupled to receive the gate of the pre-charge transistor M, the drain of the transistor M is coupled to receive the reference potential VG, the drain of the gate of the first source/drain of the transistor M is coupled to receive the drain of the transistor M, the drain of the transistor M is coupled to receive the drain of the first stage scan signal VG 2, the drain of the transistor M, and is coupled to receive the drain of the transistor M, the drain of the transistor M is coupled to receive the drain of the first stage scan transistor M, and is coupled to receive the drain of the transistor M, and the transistor M, the drain of the transistor M2, the drain of the transistor M, and is coupled to receive the drain of the transistor M, and is coupled to receive the drain of the transistor M, the drain of the transistor M, and is coupled to receive the transistor M, and the drain of the transistor M, and the drain of the transistor M, the drain of the transistor M, and is coupled to receive the transistor M, the drain of the transistor M, the transistor M is coupled.

Fig. 4A and 4B are circuit diagrams of the ith stage shift register 210(i) and the (i +1) th stage shift register 210(i +1) of fig. 2, respectively, where i is an odd number of 3 to (N-1). The ith stage shift register 210(i) and the (i +1) th stage shift register 210(i +1) include a precharge unit 410, a pull-up unit 420, a pull-down unit 430, and a reset unit 440, wherein electronic circuit elements in the precharge unit 410, the pull-up unit 420, and the pull-down unit 430 correspond to electronic circuit elements in the precharge unit 310, the pull-up unit 320, and the pull-down unit 330, respectively.

IN the ith stage of the shift register 210(i) of FIG. 4A, the pre-charge unit 410 is configured to receive the input signals IN1, IN2, and output a pre-charge signal from the node X (i) according to the input signals IN1, IN2, the gate of the transistor M1 is configured to receive the input signal IN1, the first source/drain of the transistor M1 is configured to receive the reference signal VGH, and the second source/drain of the transistor M1 is coupled to the node X (i). the gate of the transistor M2 is configured to receive the input signal IN2, the first source/drain of the transistor M2 is configured to receive the reference signal VG L, and the second source/drain of the transistor M2 is coupled to the node X (i).

In the ith stage of shift register 210(i) of fig. 4A, the pull-up unit 420 is coupled to the pre-charge unit 410, and is configured to receive the pre-charge signal and the clock signal CN1, and output the ith scan signal sc (i) according to the pre-charge signal and the clock signal CN1, the gate of the transistor M3 is coupled to the node x (i), the first source/drain of the transistor M3 is configured to receive the clock signal CN1, and the second source/drain of the transistor M3 is configured to output the ith scan signal sc (i), if (i +1) is a multiple of 4, the clock signal CN1 is the clock signal C3. provided by the clock signal line L3, otherwise, if (i +1) is not a multiple of 4, the clock signal CN1 is the clock signal C1 provided by the clock signal line L1.

In the i-th stage shift register 210(i) of FIG. 4A, the pull-down unit 430 is coupled to the pre-charge unit 410 and the pull-up unit 420 for receiving the pre-charge signal and the pull-down control signal GPW L1, and controls the level of the i-th stage scan signal SC (i) according to the pre-charge signal and the pull-down control signal GPW L1. the first source/drain of the transistor M4 is coupled to the gate of the transistor M L0, the first source/drain of the transistor M L is coupled to receive the reference potential VG L, and the second source/drain of the transistor M L is coupled to the node X (i) and for receiving the pre-charge signal VG + VG, the gate of the transistor M L is coupled to the gate of the transistor M L, the first source/drain of the transistor M L is coupled to receive the reference potential VG L, the second source/drain of the transistor M L is coupled to the gate of the transistor M L + VG L, the gate of the transistor M L is coupled to the gate of the transistor M L + L, the shift register M L is coupled to receive the gate of the pre-M + VG, the drain of the transistor M L, the drain of the transistor M L is coupled to receive the reference potential VG + VG, the drain of the gate of the drain of the transistor M L, the drain of the transistor M L, the drain of the drain L, the drain of the shift register 210 is coupled to receive the drain of the transistor M L, the drain of the transistor M L, the drain of the drain L, the drain of the transistor M L, the drain of the drain L is coupled to receive the drain of the shift register 72, the drain of the transistor M L, the drain of the shift transistor M L and the drain of the shift register 72, the drain of the transistor M L, the drain of the transistor M L is coupled to receive the transistor M L, the drain of the shift register 72, the drain of the transistor M L, the drain of the transistor M L, the shift register 72, the drain of the shift register 72, the drain of the transistor M L, the drain of the shift transistor M L, the drain of the shift register 72.

In the ith stage of shift register 210(i) of fig. 4A, the reset unit 440 is coupled to the precharge unit 410 and the pull-up unit 420 for receiving the start signal STV and resetting the level of the node x (i) (i.e., resetting the precharge signal) according to the start signal STV. the reset unit 440 includes a transistor M14 having a gate for receiving the start signal STV, a first source/drain for receiving the reference potential VG L, and a second source/drain coupled to the node x (i).

IN the (i +1) th stage shift register 210(i +1) of FIG. 4B, the pre-charge unit 410 is configured to receive the input signals IN3, IN4, and output a pre-charge signal from the node X (i +1) according to the input signals IN3, IN4, the gate of the transistor M1 is configured to receive the input signal IN3, the first source/drain of the transistor M1 is configured to receive the reference signal VGH, and the second source/drain of the transistor M1 is coupled to the node X (i +1), the gate of the transistor M2 is configured to receive the input signal IN4, the first source/drain of the transistor M2 is configured to receive the reference signal VG L, and the second source/drain of the transistor M2 is coupled to the node X (i + 1).

In the (i +1) th stage 210(i +1) of the shift register of fig. 4B, the pull-up unit 420 is coupled to the pre-charge unit 410, which receives the pre-charge signal and the clock signal CN2, and outputs the scan signal SC (i +1) according to the pre-charge signal and the clock signal CN2, the gate of the transistor M3 is coupled to the node X (i +1), the first source/drain of the transistor M3 is used for receiving the clock signal C2, and the second source/drain of the transistor M3 is used for outputting the scan signal SC (2). if (i +1) is a multiple of 4, the clock signal CN1 is the clock signal C4 provided by the clock signal line L4. conversely, if (i +1) is not a multiple of 4, the clock signal CN1 is the clock signal C2 provided by the clock signal line L2.

In the (i +1) th stage shift register 210(i +1) of FIG. 4B, the pull-down unit 430 is coupled to the precharge unit 410 and the pull-up unit 420 for receiving the precharge signal and the pull-down control signal GPW L2, and controls the level of the (i +1) th stage scan signal SC (i +1) according to the precharge signal and the pull-down control signal GPW L2. the first source/drain of the transistor M4 is coupled to receive the reference potential VG L0, and the second source/drain of the transistor M L is coupled to the node X (i) in the i-th stage shift register 210(i), and is used for receiving the precharge signal VG L, and the gate of the transistor M L is coupled to the gate of the transistor M L, the first source/drain of the transistor M L is coupled to receive the reference potential VG 361, and the gate of the transistor M L is coupled to the source/drain of the precharge transistor M L, and is coupled to the gate of the first source/drain of the transistor M L, and is coupled to the drain of the drain L for receiving the precharge signal SC-drain of the precharge signal VG L, (M L, and is coupled to the drain of the transistor M L, and is coupled to the drain of the first drain L, and is coupled to the drain of the drain L, and is coupled to receive the drain of the transistor M L, and the drain of the transistor M L, and is coupled to receive the precharge transistor M L, and the drain of the transistor M L, and the drain of the transistor M L is coupled to receive the drain of the drain L, and the drain of the transistor M L, and the drain of the drain L, and the transistor M L is coupled to receive the drain of the precharge signal SC L, and is coupled to receive the drain of the transistor M L (M L, and the transistor M L is coupled to receive the precharge transistor M L, and the drain of the drain L, and the drain of the drain L is coupled to the drain of.

In the (i +1) th stage shift register 210(i +1) of fig. 4B, the reset unit 440 is coupled to the precharge unit 410 and the pull-up unit 420 for receiving the start signal STV and resetting the level of the node X (i +1) (i.e., resetting the precharge signal) according to the start signal STV, the gate of the transistor M14 is for receiving the start signal STV, the first source/drain of the transistor M14 is for receiving the reference potential VG L, and the second source/drain of the transistor M14 is coupled to the node X (i + 1).

If the shift register 210(i) is an odd-numbered shift register among the 3 rd to (N-5) th shift registers 210(3) to 210(N-5), the input signals IN1 to IN4 are the (i-2) th scan signal SC (i-2), the (i +3) th scan signal SC (i +3), the (i-1) th scan signal SC (i-1), and the (i +4) th scan signal SC (i +4), respectively. If the shift register 210(i) is the (N-3) th stage shift register 210(N-3), the input signals IN 1-IN 4 are the (N-5) th scan signal SC (N-5), the Nth scan signal SC (N), the (N-4) th scan signal SC (N-4), and the end signal RST, respectively. When the shift register 210(i) is the (N-1) th stage shift register 210(N-1), the input signals IN1 to IN4 are the (N-3) th stage scan signal SC (N-3), the end signal RST, the (N-2) th stage scan signal SC (N-2), and the end signal RST, respectively.

It should be noted that in other embodiments, the gate driving circuit 200 may not have the end signal line R. In this case, the transistor M2 in the (N-2) -th to Nth stage shift registers 210(N-2) -210 (N) is used for receiving the start signal STV.

Fig. 5 is a timing diagram of the gate driving circuit 200 of fig. 2. For the sake of convenience of explanation, fig. 5 shows only the timing changes of some signals of the 1 st to 5 th shift registers 210(1) to 210 (5). As shown in fig. 5, when the start signal STV rises from low level to high level at time point t0, the node X (1) of the 1 st stage shift register 210(1) and the node X (2) of the 2 nd stage shift register 210(2) both rise from low level to first high level, and the node X (3) of the 3 rd stage shift register 210(3) to the node X (5) of the 5 th stage shift register 210(5) are maintained at low level by the reset unit 440. At time t2 (i.e., after two time units have elapsed; every two adjacent time points differ by one time unit), the start signal STV goes from high to low, and the clock signal C1 goes from low to high. At this time, the node X (1) of the 1 st stage shift register 210(1) is raised from the first high level to the second high level, and the 1 st stage scan signal SC (1) is raised from the low level to the high level. At a time point t4, the clock signal C1 goes down from high level to low level, so that the 1 st stage scan signal SC (1) goes down from high level to low level, and the node X (1) of the 1 st stage shift register 210(1) goes down from the second high level to the first high level. At time t5, the scan signal SC (4) of the 4 th stage is asserted by the clock signal C4 to go from low to high, so that the node X (1) of the 1 st stage shift register 210(1) goes from the first high level to low level.

The clock signals C1-C4 sequentially rise from low level to high level at time points t2, t3, t4 and t5, the period of each clock signal C1-C4 is four time units, and the high level duration and the low level duration of each clock signal C1-C4 respectively occupy two time units. The level of the clock signals C1-C4 changes, so that the 1 st scan signal SC (1) to the 5 th scan signal SC (5) sequentially go from low to high and sequentially go from high to low.

The present invention is characterized in that the reset unit 440 in the 3 rd to nth shift registers 210(3) -210 (N) resets the levels of the nodes X (3) -X (N) in the 3 rd to nth shift registers 210(3) -210 (N) respectively before the generation of the 1 st to nth scan signals SC (1) -SC (N) and when the start signal STV is raised to a high level, and eliminates the floating state of the nodes X (3) -X (N), thereby preventing the nodes X (3) -X (N) from being affected by noise to generate small spikes, preventing the generation of image display problems (such as the appearance of fine horizontal stripes, the noise interference problem and the flicker phenomenon) caused by the spikes of the reference potential VG L, further improving the image display quality, the reliability of the shift registers, and reducing the power consumption.

The technical contents described in the above embodiments can also be applied to a display device that is driven simultaneously on both the left and right sides. Referring to fig. 6, a schematic diagram of a display device 600 is shown. The display device 600 includes a display panel 610, a source driver 620, and

gate drivers

630A, 630B. The display device 600 is similar to the display device 100 of fig. 1, with the difference that the display device 600 has two

gate drivers

630A, 630B. As shown in fig. 6, the

gate drivers

630A and 630B are respectively disposed on the left and right sides of the display panel 610 and are commonly used for transmitting the gate driving signals to the display panel 610. In other embodiments, the positions of the

gate drivers

630A and 630B may be adjusted according to different design requirements. The

gate drivers

630A and 630B may include the same number of shift registers, and the timings of the scan signals output therefrom are the same. In some embodiments, the

gate drivers

630A and 630B each include the gate driving circuit 200 shown in fig. 2, and the scan signals output by the

gate drivers

630A and 630B have substantially the same timing. The display panel 610 and the source driver 620 are substantially the same as the display panel 110 and the source driver 120 of fig. 1, respectively, and therefore, the description thereof is omitted.

Although the present invention has been described with reference to the above embodiments, it should be understood that the scope of the present invention is not limited to the above embodiments, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention.

Claims

1. A gate driving circuit for driving a display panel, the gate driving circuit comprising:

the display device includes a plurality of shift registers from 1 st to Nth, the plurality of shift registers are used for respectively generating and sequentially outputting scanning signals from 1 st to Nth to the display panel, each shift register is used for receiving a start signal, the start signal is used for triggering the 1 st and 2 nd shift registers of the plurality of shift registers to respectively generate scanning signals from 1 st and 2 nd of the plurality of scanning signals, the start signal is used for resetting the 3 rd to Nth shift registers of the plurality of shift registers, and N is a positive integer greater than or equal to 4.

2. The gate driver circuit according to claim 1, wherein an i-th stage shift register of the plurality of shift registers includes:

a precharge unit to receive a first input signal and a second input signal and to output a precharge signal from a node according to the first input signal and the second input signal;

a pull-up unit coupled to the pre-charge unit, the pull-up unit configured to receive the pre-charge signal and a clock signal and output an i-th scan signal of the plurality of scan signals according to the pre-charge signal and the clock signal; and

the pull-down unit is coupled to the pre-charge unit and the pull-up unit, and is configured to receive the pre-charge signal and a pull-down control signal and control a level of an i-th scan signal of the plurality of scan signals according to the pre-charge signal and the pull-down control signal.

3. The gate driving circuit of claim 2, wherein a j-th scan signal of the plurality of scan signals is input to a pull-down cell of a (j +1) -th shift register of the plurality of shift registers, and a (j +1) -th scan signal of the plurality of scan signals is input to a pull-down cell of a j-th shift register of the plurality of shift registers, wherein j is an odd number.

4. The gate drive circuit of claim 2, wherein the pre-charge unit comprises:

a first transistor having a gate for receiving the first input signal, a first source/drain for receiving a first reference potential, and a second source/drain coupled to the node; and

a second transistor having a gate for receiving the second input signal, a first source/drain for receiving a second reference potential, and a second source/drain coupled to the node.

5. A gate drive circuit as claimed in claim 4,

when i is any positive integer from 1 to 2, the first input signal is the start signal, and the second input signal is an (i +3) th-stage scan signal of the plurality of scan signals;

when i is any positive integer from 3 to (N-3), the first input signal is an (i-2) th scan signal from the plurality of scan signals, and the second input signal is an (i +3) th scan signal from the plurality of scan signals; and

when i is any positive integer from (N-2) to N, the first input signal is an (i-2) th-stage scan signal from the plurality of scan signals, and the second input signal is the start signal or the end signal.

6. The gate driving circuit of claim 2, wherein the pull-up unit comprises:

a third transistor having a gate coupled to the node, a first source/drain for outputting the i-th scan signal, and a second source/drain for receiving the clock signal.

7. The gate drive circuit of claim 2, wherein the pull-down unit comprises:

a fourth transistor having a first source/drain for receiving a reference potential and a second source/drain for receiving a third input signal;

a fifth transistor having a gate coupled to the gate of the fourth transistor, a first source/drain for receiving the reference potential, and a second source/drain for receiving a fourth input signal;

a sixth transistor having a gate coupled to the gate of the fourth transistor, a first source/drain for receiving the reference potential, and a second source/drain for receiving a fifth input signal;

a seventh transistor having a gate coupled to the gate of the fourth transistor, a first source/drain for receiving the reference potential, and a second source/drain for receiving a sixth input signal;

an eighth transistor having a first source/drain for receiving the pull-down control signal and a second source/drain coupled to the gate of the fourth transistor;

a ninth transistor having a gate and a first source/drain for receiving the pull-down control signal, and a second source/drain coupled to the gate of the eighth transistor;

a tenth transistor having a gate for receiving a seventh input signal, a first source/drain for receiving the reference potential, and a second source/drain coupled to the gate of the fourth transistor;

an eleventh transistor having a gate for receiving the third input signal, a first source/drain for receiving the reference potential, and a second source/drain coupled to the gate of the fourth transistor;

a twelfth transistor having a gate for receiving the fourth input signal, a first source/drain for receiving the reference potential, and a second source/drain coupled to the gate of the eighth transistor; and

a thirteenth transistor having a gate for receiving the third input signal, a first source/drain for receiving the reference potential, and a second source/drain coupled to the gate of the eighth transistor.

8. The gate driver circuit according to claim 7, wherein when i is 1 or 2, the third input signal is a signal at a node of a 1 st-stage shift register among the plurality of shift registers, the fourth input signal is a 1 st-stage scan signal among the plurality of scan signals, the fifth input signal is a signal at a node of a 2 nd-stage shift register among the plurality of shift registers, the sixth input signal is a 2 nd-stage scan signal among the plurality of scan signals, and the seventh input signal is the start signal.

9. The gate driving circuit according to claim 7, wherein when i is an odd number greater than or equal to 3 and less than or equal to N, the third input signal is a signal at a node of the i-th stage shift register, the fourth input signal is the i-th stage scan signal, the fifth input signal is a signal at a node of an (i +1) -th stage shift register among the plurality of shift registers, the sixth input signal is an (i +1) -th stage scan signal among the plurality of scan signals, and the seventh input signal is an (i-2) -th stage scan signal among the plurality of scan signals.

10. The gate driving circuit according to claim 7, wherein when i is an even number greater than or equal to 3 and less than or equal to N, the third input signal is a signal at a node of an (i-1) th stage shift register among the plurality of shift registers, the fourth input signal is an (i-1) th stage scan signal of the plurality of scan signals, the fifth input signal is a signal at a node of the i-th stage shift register, the sixth input signal is the i-th stage scan signal, and the seventh input signal is an (i-3) th stage scan signal of the plurality of scan signals.

11. The gate driving circuit according to claim 4, wherein when i is any positive integer from 3 to N, the i-th stage shift register further comprises:

a reset unit coupled to the precharge unit and the pull-up unit, the reset unit being configured to reset a level of a node of the i-th stage shift register before the gate driving circuit generates the 1 st to N-th stage scan signals.

12. The gate drive circuit of claim 11, wherein the reset unit comprises:

a fourteenth transistor having a gate for receiving the start signal, a first source/drain for receiving the second reference potential, and a second source/drain coupled to the node.

13. The gate driving circuit according to claim 2, wherein the clock signals input to two adjacent shift registers of the plurality of shift registers are different by 1/4 clock cycles.

14. The gate driving circuit of claim 2, wherein the pull-down control signals input to two adjacent shift registers of the plurality of shift registers are opposite in phase.

15. A gate driving circuit for driving a display panel, the gate driving circuit comprising:

the display device comprises a plurality of stages of shift registers, a plurality of driving circuits and a plurality of reset circuits, wherein the plurality of shift registers are used for respectively generating and sequentially outputting a plurality of scanning signals to the display panel, each shift register is used for receiving a starting signal, and each shift register is used for generating a driving signal or resetting according to the starting signal.

16. A display device, comprising:

a display panel, and;

the first gate driving circuit is configured to drive the display panel and is disposed at one side of the display panel, the first gate driving circuit includes first shift registers of 1 st to nth stages, the first shift registers are configured to generate and sequentially output first scanning signals of 1 st to nth stages to the display panel, and each of the first shift registers is configured to receive a start signal, wherein the start signal is configured to trigger the first shift registers of 1 st and 2 nd stages of the first shift registers to generate first scanning signals of 1 st and 2 nd stages of the first scanning signals, respectively, and the start signal is configured to reset the first shift registers of 3 rd to nth stages of the first shift registers, and N is a positive integer greater than or equal to 4.

17. The display device of claim 16, further comprising:

the second gate driving circuit is configured to drive the display panel and disposed on the other side of the display panel opposite to the first gate driving circuit, and includes first-stage 1 to second-stage N second shift registers, the second shift registers are configured to respectively generate and sequentially output first-stage 1 to second-stage N second scan signals to the display panel, and each second shift register is configured to receive the start signal, where the start signal is configured to trigger the first-stage 1 and second-stage 2 second shift registers of the second shift registers to respectively generate first-stage 1 and second-stage 2 second scan signals of the second scan signals, and the start signal is configured to reset second-stage 3 to second-stage N second shift registers of the second shift registers.

18. The display device according to claim 17, wherein the plurality of second scan signals respectively have substantially the same timing as the plurality of first scan signals.