KR102268519B1 - Gate In Panel structure for dual output - Google Patents

Abstract

The present invention relates to a dual output GIP structure capable of securing a narrow bezel by reducing the area of a gate in panel (GIP), comprising a shift register including a plurality of stages, each stage having a different phase At least five clock pulses among a plurality of clock pulses having a , two scan pulses or two start pulses output from the first and second output terminals of the previous stage, and a scan pulse output from the first output terminal of the next stage It is characterized in that it receives and outputs two scan pulses.

Description

Dual output GIP structure {Gate In Panel structure for dual output}

The present invention relates to a display device, and more particularly, to a dual output GIP structure capable of securing a narrow bezel by reducing the area of a gate in panel (GIP).

A typical liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

1 is a configuration circuit diagram showing a driving device of a general liquid crystal display device.

In general, as shown in FIG. 1 , a liquid crystal display device includes a liquid crystal panel 2 displaying an image, and a gate driver 6 driving gate lines GL1 to GLn of the liquid crystal panel 2 . and the data driver 4 driving the data lines DL1 to DLm of the liquid crystal panel 2 and the image data RGB inputted from the outside are arranged and supplied to the data driver 4 and the gate and a timing controller 8 for generating data control signals GCS and DCS to control the gate and data drivers 6 and 4, respectively.

The liquid crystal panel 2 is connected to a thin film transistor (TFT) formed in each pixel area defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm and the thin film transistor. and a liquid crystal capacitor Clc. The liquid crystal capacitor Clc includes a pixel electrode connected to the thin film transistor and a common electrode disposed with the pixel electrode and liquid crystal interposed therebetween. The thin film transistor supplies an image signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn.

The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage SVcom applied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. Implement gradation. In this case, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween, and a parasitic capacitor Cgs may be further formed between the source electrode and the gate line GL of the thin film transistor.

The data driver 4 includes a data control signal DCS from the timing controller 8 , for example, a source start signal (SSP), a source shift clock (SSC), and a source output signal. The data arranged from the timing controller 8 is converted into an analog voltage, that is, an image signal using a Source Output Enable (SOE) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the data aligned through the timing controller 8 according to the SSC, and then in response to the SOE signal 1 to which the scan pulse is supplied to each of the gate lines GL1 to GLn. An image signal corresponding to one horizontal line is supplied to each of the data lines DL1 to DLm in each horizontal period.

The gate driver 6 sequentially drives each of the gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 8 . Specifically, the gate driver 4 includes a gate start signal (GSP) that is a gate control signal (GCS), a gate shift clock (GSC), and a gate output enable (GOE) signal. The driving is performed so that scan pulses of the level of the gate high voltage VGH are sequentially supplied to each of the gate lines GL1 to GLn by using the same. In addition, the gate low voltage is supplied during the remaining period when the scan pulse is not supplied.

The timing controller 8 controls the data driver 4 and the gate driver 6 according to external image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync, DE. Specifically, the timing controller 8 aligns the image data RGB input from the outside to be suitable for driving the liquid crystal panel 2 and supplies it to the data driver 4 . The gate control signal GCS and the data control signal (GCS) and the data control signal (GCS) using at least one of a synchronization signal input from the outside, that is, a dot clock (DCLK), a data enable signal (DE), and horizontal and vertical synchronization signals (Hsync, Vsync) DCS) and supply it to the gate driver 6 and the data driver 4, respectively.

The gate driver 6 includes a shift register to sequentially output the scan pulses as described above.

The shift register includes a plurality of stages for sequentially outputting scan pulses to each of the gate lines GL1 to GLn based on a plurality of clock pulses provided from the timing controller.

The shift register may be built into the display panel. That is, the display panel has a display unit for displaying an image and a non-display unit surrounding the display unit, and the shift register SR may be built in the non-display unit (GIP).

The scan pulses generated from the respective stages are not only supplied to any one gate line, but also supplied to at least one of the rear stage and the front stage.

Each of the stages includes a plurality of transistors including a pull-up switching device and a pull-down switching device for outputting a scan pulse, and a bootstrapping capacitor.

FIG. 2 is a circuit diagram of a conventional stage composed of seven switching elements T1, T3c, T3n, T3r, T6, T7c, and T7d and one boost-stamping capacitor CB.

That is, the n-th stage is controlled according to the scan pulse {Gout(n-2)} output from the (n-2)-th stage as shown in FIG. 2 and the scan pulse {Gout(n-2)} a first switching device T1 for charging the set node Q, and a second switching device T1 for discharging the set node Q controlled according to the scan pulse Gout(n+2) output from the n+2th stage The switching element T3n and a scan pulse output from the (n-1)-th stage controlled according to any one {CLK(n-1)} of a plurality of clock pulses representing different phases {Gout(n-1) )} a third switching device T3c for charging the set node Q, a fourth switching device T3r for discharging the set node Q controlled according to a reset signal Reset, and the Q A capacitor CB for bootstrapping the voltage of the node and one {CLK(n)} of a plurality of clock pulses indicating different phases controlled according to the voltage of the set node Q are output to an output terminal a fifth switching element T6, which is controlled according to any one of a plurality of clock pulses indicating different phases {CLK(n+2)}, and a sixth switching element T7c for discharging the output terminal; and a seventh switching element T7d for outputting one of a plurality of clock pulses (CLK(n)), which is controlled according to the voltage of the output terminal, indicating the different phases, as a scan pulse, to the output terminal.

The operation of the conventional n-th stage configured as described above is as follows.

3 is a timing diagram of input/output waveforms of a conventional stage.

When the high pulse of the scan pulse {Gout(n-2)} output from the (n-2)th stage is input to the first switching element T1, the first switching element T1 is turned on and the scan pulse { Gout(n-2)} is charged to the set node Q. And, when a high pulse of one clock pulse {CLK(n+2)} among a plurality of clock pulses having different phases is input to the sixth switching device T7c, the sixth switching device T7c is turned on. Discharge the output stage.

In this state, one clock pulse {CLK(n-1)} among a plurality of clock pulses having different phases in the third switching element T3c and a scan pulse output from the n-1 th stage {Gout( n-1)} is input, and the third switching element T3c is turned on during a high period of the clock pulse {CLK(n-1)}, and the scan pulse {Gout(n−) 1)} is charged. Then, the set node Q maintains a high state.

When the set node Q maintains a high state, the fifth switching element T6 is turned on and bootstrapped by the capacitor CB, and the different signals input to the source terminal of the fifth switching element T6 are turned on. One clock pulse {CLK(n)} among a plurality of clock pulses having a phase is output to an output terminal. At this time, the seventh switching element T7d is also turned on so that the clock pulse CLK(n) is output to the output terminal as the scan pulse Gout(n).

Then, the fourth switching element T3r is turned on by the reset signal to discharge the set node Q, and at the same time, one clock pulse {CLK(n+2)} among the plurality of clock pulses is generated by the sixth switching element When input to (T7c), the sixth switching element (T7c) is also turned on to discharge the output terminal.

In the above, a ripple may be generated in the sed node Q due to capacitive coupling of the parasitic capacitor of the fifth switching element T6. However, the ripple of the set node Q is prevented by the capacitor CB.

By the above operation, each conventional stage is controlled according to a plurality of clock pulses and scan pulses output from the previous and subsequent stages to output one scan pulse.

However, such a conventional GIP structure has the following problems.

That is, as described above, since each stage is composed of a plurality of switching elements and bootstrapping capacitors, the area of the GIP is large and the bezel is also increased. In particular, since the bootstrapping capacitor has to have a capacitance of about 2pF to 3pF, it occupies an area of about 15% in the GIP, so the area of the GIP becomes large, and there is a limitation in implementing a narrow bezel.

The present invention is to solve the problems of the related art, and it is possible to reduce the GIP area by outputting two scan pulses in one stage without using a bootstrapping capacitor that occupies a large area, and to implement a narrow bezel. The purpose of this is to provide a dual output GIP structure.

A dual output GIP structure according to the present invention for achieving the above object includes a shift register including a plurality of stages, and each stage includes at least five clock pulses among a plurality of clock pulses having different phases; , receiving two scan pulses or two start pulses output from the first and second output ends of the previous stage and the scan pulses output from the first output end of the next stage, and outputting two scan pulses. have.

Here, each stage includes two scan pulses output from the first and second output terminals of the previous stage and a scan pulse output from the first output terminal of the subsequent stage, or a gate start pulse, and a plurality of clocks having different phases a set node controller configured to receive at least three clock pulses from among the pulses to control the set node Q; and a first scan pulse controlled according to a state of the set node to transmit at least one clock pulse from among the plurality of clock pulses. and a first output unit for outputting , and a second output unit for outputting at least one of the plurality of clock pulses as a second scan pulse controlled according to the state of the set node.

The set node control unit of the nth stage transmits a scan pulse output from the second output terminal of the (n-1)th stage controlled by a first clock pulse among a plurality of clock pulses having different phases to the set node ( A first switching device for charging Q), a second switching device for discharging the set node (Q) controlled according to a scan pulse output from the first output terminal of the (n+2)-th stage, and a reset signal (Reset) ), a third switching element for discharging the set node Q, and a scan pulse output from the first output terminal of the (n-1)-th stage and two of the plurality of clock pulses having different phases. and a PD node controller that is controlled according to clock pulses to prevent ripple of the set node.

The PD node controller includes a first capacitor connected to one electrode of the scan pulse output from the first output terminal of the (n-1)-th stage and the other electrode connected to the PD node, and the different phases are applied to one electrode. a second capacitor to which a second clock pulse from among the plurality of clock pulses is input and the other electrode is connected to the PD node; and a fourth switching element controlled according to the voltage of the PD node to discharge the set node Q; , characterized in that it comprises a fifth switching element which is controlled by a third clock pulse among the plurality of clock pulses having different phases to discharge the PD node.

The third switching element is controlled by any one of the plurality of clock pulses having different phases instead of the reset signal.

The first output unit of the n-th stage is controlled according to the voltage of the set node and outputs a fourth clock pulse among a plurality of clock pulses having different phases as a first scan signal to a first output terminal and a switching element, and a seventh switching element controlled according to a third clock pulse among the plurality of clock pulses having different phases to discharge the first output terminal.

The first output unit of the n-th stage may further include an eighth switching element that is controlled according to the voltage of the first output terminal and outputs the fourth clock pulse to the first output terminal.

The second output unit of the n-th stage outputs a second clock pulse from among the plurality of clock pulses having different phases controlled according to the voltage of the set node Q as a second scan pulse to a second output terminal and a ninth switching device that discharges the second output terminal by being controlled according to a fifth clock pulse among the plurality of clock pulses having different phases.

The second output unit of the n-th stage may further include an eleventh switching device that is controlled according to the voltage of the second output terminal and outputs the second clock pulse to a second output terminal.

In the dual output GIP structure according to the present invention having the same characteristics as singgi, the following effects are obtained.

First, since the dual output GIP structure according to the present invention outputs two scan pulses in one stage, the size of the GIP can be reduced and a narrow bezel can be implemented.

Second, in the conventional GIP structure, a bootstrapping capacitor having a capacity of 2pF to 3pF is used, but in the dual output GIP structure according to the present invention, the bootstrapping capacitor is not used and about 1/10 of the bootstrapping capacitor is used. By using two capacitors of the same size, the ripple of the set node can be prevented, so the size of the GIP can be reduced and a narrow bezel can be implemented.

1 is a configuration diagram showing a driving device of a general liquid crystal display device;
2 is a circuit diagram of a conventional stage;
3 is a timing diagram of input/output waveforms of a conventional stage;
4 is a configuration diagram of a shift register according to the present invention;
5 is a circuit diagram of a stage according to the present invention;
6 is an input/output waveform timing diagram of the nth stage according to the present invention;
7 is a timing diagram for explaining coupling cancellation of capacitance by the PD node of the nth stage according to the present invention;

A display device for division driving according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

4 is a block diagram of a shift register according to the present invention.

The shift register according to the present invention includes a plurality of stages (... ST_n-1 to ST_n+2), as shown in FIG. 4 .

Each stage has two output terminals (a first output terminal and a second output terminal) to independently output two scan pulses.

Each stage includes at least five clock pulses among the plurality of clock pulses CLK1 to CLK6, and two scan pulses (or two start pulses Vst and Vst1) output from the first and second output terminals of the previous stage; , receives the scan pulse output from the first output stage of the next stage.

That is, the n-th stage ST_n includes at least five clock pulses among the plurality of clock pulses CLK1 to CLK6 and two scans output from the first and second output terminals of the n-1 th stage ST_n-1. A pulse {Gout(2n-2) and Gout(2n-1)} and a scan pulse {Gout(2n+4)} output from the first output terminal of the n+2th stage ST_n+2 are received.

5 is a diagram showing the configuration of any one stage according to the first embodiment of the present invention.

Each stage, as shown in FIG. 5, includes two scan pulses output from the first and second output terminals of the previous stage, a scan pulse output from the first output terminal of the subsequent stage, or a gate start pulse, and a plurality of clocks a set node (Q node) controller 10 receiving at least three clock pulses from among the pulses CLK1 to CLK6 to control the set node, and the plurality of clock pulses CLK1 controlled according to the state of the set node to CLK6) a first output unit 20 for outputting at least one clock pulse as a first scan pulse, and at least one of the plurality of clock pulses CLK1 to CLK6 controlled according to the state of the set node and a second output unit 30 for outputting a clock pulse as a second scan pulse.

The set node (Q node) control unit 10 of each stage (nth stage) does not use a bootstrap capacitor unlike in the related art. Instead, the scan pulse {Gout(2n-2)} output from the first output terminal of the (n-1)th stage and two clock pulses {CLK(n+1) among the plurality of clock pulses having different phases ), CLK(n+3)}} and further includes a PD node controller 11 to prevent ripple of the set node. The PD node unit 11 includes a PD node (PD) for preventing ripple of the set node, and first and second capacitors (Cout, Cpd) that are 1/10 the size of the bootstrapping capacitor. is composed

That is, the set node (Q node) control unit 10 of the nth stage ST_n is controlled by any one clock pulse {CLK(n-1)} among a plurality of clock pulses representing different phases ( a first switching element T3C for charging the scan pulse Gout(2n-1) output from the second output terminal of the n-1)-th stage ST_n-1 to the set node Q; and (n+2); ) a second switching element T3n for discharging the set node Q controlled according to the scan pulse Gout(2n+4) output from the first output terminal of the th stage ST_n+2, and a reset signal ( Reset) and a third switching element T3r for discharging the set node Q, and a scan pulse {Gout output from the first output terminal of the (n-1)th stage ST_n-1 to one electrode (2n-2)} is inputted, the other electrode has a first capacitor Cout connected to the PD node PD, and one of the plurality of clock pulses indicating different phases is one of the clock pulses {CLK (n+1)} is input and the other electrode is controlled according to the voltage of the second capacitor Cpd connected to the PD node PD and the voltage of the PD node PD to discharge the set node Q. A fourth switching element T2 and a fifth switching element controlled by one of a plurality of clock pulses representing different phases {CLK(n+3)} to discharge the PD node PD (T1) is provided.

Here, instead of the reset signal Reset applied to the gate electrode of the third switching element T3r, any one of the plurality of clock pulses representing different phases {CLK(n+4)} may be used. .

The first output unit 20 of the n-th stage ST_n is controlled according to the voltage of the set node Q, so that any one of a plurality of clock pulses representing different phases {CLK(n) )} is controlled according to any one of a sixth switching element T6_1 outputting to the first output terminal, and one of a plurality of clock pulses representing different phases {CLK(n+3)}, so that the first A seventh switching element T7c_1 for discharging an output terminal, and an eighth switching element for outputting one {CLK(n)} of a plurality of clock pulses indicating different phases controlled according to the voltage of the output terminal to an output terminal (T7d_1) is provided.

The second output unit 30 of the n-th stage ST_n is controlled according to the voltage of the set node Q, so that any one of a plurality of clock pulses representing different phases {CLK(n) +1)} to the second output terminal, the ninth switching element T6_2 and the second output terminal controlled according to any one {CLK(n+4)} of a plurality of clock pulses representing different phases a tenth switching element T7c_2 for discharging a, and an eleventh switching for outputting any one {CLK(n+1)} of a plurality of clock pulses representing different phases controlled according to the voltage of the output terminal to an output terminal The element T7d_2 is provided.

Here, the eighth switching element T7d_1 of the first output terminal 20 and the eleventh switching element T7d_2 of the second output terminal 30 may not be provided.

The operation of the dual output GIP structure according to the present invention configured as described above is as follows.

6 is an input/output waveform timing diagram of an nth stage according to the present invention, and FIG. 7 is a timing diagram for explaining coupling cancellation of capacitance by a PD node of an nth stage according to the present invention.

Hereinafter, it will be described using the configuration of the nth stage.

First, a plurality of clock pulses {CLK(n-1), CLK(n), CLK(n+1), CLK(n+2), CLK(n+3), CLK(n+) used in the present invention 4)}, as shown in FIG. 6 , are sequentially output with different phases, and are shifted by 1/3 section to overlap the adjacent clock pulses by 2/3 sections. Although 6 clock signals are illustrated in FIG. 6 , the present invention is not limited thereto and may be variously applied such as 4 clocks or 8 clocks.

When a high pulse of one of the plurality of clock pulses representing different phases {CLK(n-1)} is input to the first switching device T3c, the first switching device T3c is turned on. The scan pulse Gout(2n-1) output from the second output terminal 30 of the (n-1)-th stage is charged to the set node Q. When the set node Q is charged as described above, the first output unit 20 and the second output unit 30 respectively output scan pulses Gout2n, Gout(2n+1).

That is, the sixth switching element T6_1 and the eighth switching element T7d_1 of the first output unit 20 of the n-th stage ST_n are turned on to generate a plurality of clock pulses indicating different phases. Any one {CLK(n)} is output to the first output terminal as a scan pulse {Gout2n).

In addition, when the set node Q is charged as described above, the ninth switching device T6_2 and the eleventh switching device T7d_2 of the second output unit 30 of the n-th stage ST_n are turned on. to output one of the plurality of clock pulses representing different phases {CLK(n+1)} as a scan pulse {Gout2n+1) to the second output terminal.

The sixth switching element T6_1 and the eighth switching element T7d_1 of the first output unit 20 and the ninth switching element T6_2 and the eleventh switching element of the second output unit 30 (T7d_2) is turned on when the set node Q is charged, but the clock pulse {CLK(n)} is applied to the first output terminal 20, and the clock pulse {CLK( n+1)} is applied, the scan pulse Gout2n} output from the first output terminal 20 and the scan pulse Gout(2n+1)} output from the second output terminal 30 have different phases have

Then, when the high pulse of the scan pulse Gout(2n+4) output from the first output terminal 20 of the (n+2)-th stage ST_n+2 is applied to the second switching element T3n , the second switching element T3n is turned on to discharge the set node Q to a low voltage Vss, and the third switching element T3r is also turned on by the reset signal Reset to turn on the set node ( Q) is discharged to a low voltage (Vss).

In addition, when a high pulse of one of the plurality of clock pulses representing different phases {CLK(n+3)} is input to the seventh switching element T7c_1, the seventh switching element T7c_1 is turned on to discharge the first output terminal 20 .

In addition, when a high pulse of one of the plurality of clock pulses representing different phases {CLK(n+4)} is input to the eleventh switching element T7c_2, the eleventh switching element T7c_2 is turned on to discharge the second output terminal.

At this time, in the present invention, since the conventional capacitor CB for bootstrapping is not formed, a ripple may be generated in the set node Q.

In order to solve this problem, in the present invention, the PD node unit 11 is formed.

That is, when one of the plurality of clock pulses representing different phases {CLK(n+1)} is input to the second capacitor Cpd, any one of the plurality of clock pulses representing the different phases is input to the second capacitor Cpd. The PD node PD is initially charged by one clock pulse {CLK(n+1)}, and any one clock pulse {CLK(n+3) } is input to the fifth switching element T1, and the charging is maintained. When the PD node PD is charged by one of a plurality of clock pulses representing different phases {CLK(n+1)}, the fourth switching element T2 is turned on to turn on the set node Discharge (Q). And, when a high pulse of any one of the plurality of clock pulses representing different phases {CLK(n+3)} is input to the fifth switching device T1, the fifth switching device T1 is turned on to discharge the PD node, and the fourth switching element T2 is turned off.

Accordingly, since a ripple may be generated at a point in time when the set node Q needs to maintain a low state, the fourth switching element T2 is turned on at a point in time when the ripple may be generated and the set node Q is turned on. is discharged, so that no ripple is generated in the set node Q.

Meanwhile, when the set node Q is charged, the fourth switching element T2 maintains a turned-off state, so that the set node Q is normally charged.

That is, one of the scan pulses Gout(2n-2) output from the first output terminal of the (n-1)th stage ST_n-1 and the plurality of clock pulses indicating different phases { CLK(n+1)} is input to the first capacitor Cout and the second capacitor Cpd, respectively. However, when the scan pulse {Gout(2n-2)} is compared with the clock pulse {CLK(n+1)}, the scan pulse {Gout( Since the rising edge of 2n-2) corresponds to the rising edge of the clock pulse CLK(n+1)}, the falling edge of the scan pulse Gout(2n-2)) corresponds to the set node Q ) is charged, the scan pulse {Gout(2n-2)} and the clock pulse {CLK(n+1)} are canceled so that the PD node PD maintains a low state and the fourth switching element (T2) maintains the turned-off state so that the set node (Q) is normally charged.

As a result, in the PD node PD, the scan pulse {Gout(2n-2)} is in a low state, the clock pulse {CLK(n+1)} is in a high state, and the clock pulse {CLK(n+3)} It is charged only when is in the high state, and maintains the discharged state for the rest of the period.

By the above operation, each stage according to the present invention outputs two scan pulses according to a plurality of clock pulses and scan pulses output from the previous and subsequent stages.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

Claims (9)

A shift register comprising a plurality of stages,
Each stage includes at least five clock pulses among a plurality of clock pulses having different phases, two scan pulses or two start pulses output from the first and second output stages of the previous stage, and the first stage of the next stage. Receives the scan pulse output from the output terminal, and outputs two scan pulses,
Each stage includes two scan pulses output from the first and second output terminals of the previous stage and a scan pulse output from the first output terminal of the rear stage, or a gate start pulse, and a plurality of clock pulses having different phases a set node control unit for receiving at least three clock pulses from among and controlling the set node (Q);
a first output unit which is controlled according to the state of the set node and outputs at least one of the plurality of clock pulses as a first scan pulse;
and a second output unit which is controlled according to the state of the set node and outputs at least one of the plurality of clock pulses as a second scan pulse. delete The method of claim 1,
The set node control unit of the n-th stage is controlled by a first clock pulse among a plurality of clock pulses having different phases and transmits the scan pulse output from the second output terminal of the (n-1)-th stage to the set node Q ) and a first switching element charging the
A second switching element that is controlled according to the scan pulse output from the first output terminal of the (n+2)-th stage to discharge the set node Q, and the set node Q that is controlled according to a reset signal Reset a third switching element for discharging
and a PD node controller that is controlled according to the scan pulse output from the first output terminal of the (n-1)-th stage and two clock pulses among the plurality of clock pulses having different phases to prevent ripple of the set node; Dual output GIP structure, characterized in that configured by. 4. The method of claim 3,
The PD node control unit includes a first capacitor connected to one electrode of the scan pulse output from the first output terminal of the (n-1)-th stage and the other electrode connected to the PD node;
a second capacitor to which a second clock pulse from among the plurality of clock pulses having different phases is input to one electrode and the other electrode is connected to the PD node;
a fourth switching element controlled according to the voltage of the PD node to discharge the set node (Q);
and a fifth switching element which is controlled by a third clock pulse among the plurality of clock pulses having different phases to discharge the PD node. 4. The method of claim 3,
wherein the third switching element is controlled by any one of the plurality of clock pulses having different phases instead of the reset signal. The method of claim 1,
The first output unit,
a sixth switching element that is controlled according to the voltage of the set node and outputs a fourth clock pulse among the plurality of clock pulses having different phases as a first scan signal to a first output terminal;
and a seventh switching element which is controlled according to a third clock pulse among the plurality of clock pulses having different phases to discharge the first output terminal. 7. The method of claim 6,
and the first output unit further comprises an eighth switching element that is controlled according to the voltage of the first output terminal and outputs the fourth clock pulse to the first output terminal. According to claim 1,
The second output unit,
a ninth switching element which is controlled according to the voltage of the set node (Q) and outputs a second clock pulse from among the plurality of clock pulses having different phases as a second scan pulse to a second output terminal;
and a tenth switching element which is controlled according to a fifth clock pulse among the plurality of clock pulses having different phases to discharge the second output terminal. 9. The method of claim 8,
The second output unit,
and an eleventh switching element controlled according to the voltage of the second output terminal to output the second clock pulse to the second output terminal.

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