KR101830604B1 - Flat panel display device - Google Patents

Abstract

The present invention relates to a flat panel display capable of easily designing a narrow bezel, comprising: a display panel which defines pixels at intersections of n gate lines and m (n, m is a natural number of 2 or more) data lines; A gate driver having n / 2 stages which are built in the display panel and sequentially output a plurality of scan pulses; And sequentially supplying the plurality of scan pulses to the odd-numbered gate lines in the first sub-frame by sequentially switching the plurality of scan pulses, and sequentially supplying the plurality of scan pulses to the even-numbered gate lines in the second sub- part; A data driver for supplying a data voltage to the m data lines; And a timing control unit for controlling the driving timing of the gate driver, the data driver, and the switch unit.

Description

[0001] FLAT PANEL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a flat panel display device in which narrow bezel design is easy.

2. Description of the Related Art In recent years, flat panel displays have been widely used as display devices due to their excellent image quality, light weight, thinness, and low power. As flat panel display devices, there are a liquid crystal display (LCD) device and an organic light emitting diode (OLED) display device. Most of these devices are commercialized and commercially available.

A flat panel display device includes a display panel in which a plurality of pixels are arranged in a matrix form, a gate driver for driving gate lines of the display panel, a data driver for driving data lines of the display panel, And a control unit. Here, the gate driver can be embedded in the display panel to reduce the volume and weight, which is referred to as a GIP (Gate In Panel) type flat panel display.

On the other hand, the flat panel display device has been widely used for a computer monitor, a wall-mounted TV, and the like, and studies have been actively made to reduce weight and volume while having a wide display area. Therefore, the narrow bezel design of the outer edge except for the display area in which the image is displayed is essential.

However, in the GIP type flat panel display device, the gate driver occupies a large portion in the bezel region, which is an obstacle in realizing the narrow bezel.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a flat panel display capable of easily designing a narrow bezel.

According to an aspect of the present invention, there is provided a flat panel display comprising: a display panel for defining pixels at intersections of n gate lines and m (n, m is a natural number of 2 or more) data lines; A gate driver having n / 2 stages which are built in the display panel and sequentially output a plurality of scan pulses; And sequentially supplying the plurality of scan pulses to the odd-numbered gate lines in the first sub-frame by sequentially switching the plurality of scan pulses, and sequentially supplying the plurality of scan pulses to the even-numbered gate lines in the second sub- part; A data driver for supplying a data voltage to the m data lines; And a timing control unit for controlling the driving timing of the gate driver, the data driver, and the switch unit.

Wherein the data driver supplies odd data voltages to the m data lines so as to be synchronized with the scanning time of the odd gate lines in the first sub frame period, And supplying the even data voltages to the m data lines so as to be synchronized with the data lines.

The switch unit includes MUXs connected to the output terminals of the n / 2 stages, respectively. The MUXs include a first switching element for connecting the output terminal of each stage and the odd gate lines to each other in response to a first control signal, Numbered gate lines in response to a first control signal, a second switching element for supplying a gate-low voltage to the odd-numbered gate lines in response to a second control signal, And a fourth switching element for supplying the gate-low voltage to the even-numbered gate lines in response to a fourth control signal.

Wherein the first and fourth control signals are outputted in a high state in the first sub frame period to turn on the first and fourth switching elements and output in a low state in the second sub frame period, And the second and third control signals are output in a low state in the first sub frame period to turn off the second and third switching elements, and the second and third switching elements are turned off, And the second and third switching elements are turned on in a high state during a frame period.

The supply lines of the first and fourth control signals are electrically connected to each other and the supply lines of the second and third control signals are electrically connected to each other.

And the first to fourth control signals are outputted from the timing control unit.

And a blank period is set between the first and second sub frame periods.

In the present invention, since the gate driver 4 includes n / 2 stages ST, the number of stages can be reduced to 1/2. In the GIP type flat panel display device, the gate driver occupies a large portion in the bezel region. The present invention reduces the number of the stages ST, thereby reducing the space occupied by the gate driver 4 in the bezel region, There is an effect that the design is facilitated.

1 is a configuration diagram of a flat panel display according to an embodiment of the present invention.
2 is a detailed view of the gate driver 4 and the switch unit 10 shown in FIG.
3 is a detailed view of the switch unit 10 shown in Fig.
4 is a driving waveform diagram of the switch unit 10 shown in Fig.

Hereinafter, a flat panel display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a flat panel display according to an embodiment of the present invention.

1 includes a display panel 2, a gate driving unit 4, a data driving unit 6, a timing control unit 8, and a switch unit 10.

The display panel 2 defines pixels P at the intersection of n gate lines GL and m (n and m are natural numbers of 2 or more) data lines DL. Each pixel P is supplied with a data voltage from the data line DL in response to a scan pulse supplied from the gate line GL and displays an image according to the data voltage.

The gate driver 4 sequentially outputs scan pulses using a gate control signal GCS provided from the timing controller 8, that is, a gate start pulse Vst and a plurality of clock pulses CLK. To this end, the gate driver 4 has n / 2 stages ST1 to STn / 2, and these circuits are embedded in the display panel 2. [

On the other hand, n / 2 scan pulses output from the n / 2 stages ST1 to STn / 2 are switched by the switch unit 10 and supplied to the odd-numbered gate lines GL in the first sub- And supplied to the even-numbered gate lines GL in the second sub-frame period. That is, since the embodiment of the present invention includes n / 2 stages ST1 to STn / 2 for driving the n gate lines GL, the number of stages ST can be reduced to simplify the circuit.

Specifically, the conventional gate driver requires n stages corresponding to n gate lines. On the other hand, in the embodiment of the present invention, since the gate driver 4 includes the n / 2 stages ST, the number thereof can be reduced to 1/2. At this time, as described above, in the GIP type flat panel display device, the gate driver occupies a large portion in the bezel region, which is an obstacle to the narrow bezel design. Accordingly, the present invention has an advantage that the space occupied by the gate driving unit 4 in the bezel region can be reduced by reducing the number of the stages ST, and the narrow bezel design can be facilitated. The gate driver 4 of the present invention will be described later in detail.

The data driver 6 converts the video data RGB input from the timing controller 8 into a data voltage in accordance with the data control signal DCS supplied from the timing controller 8 and supplies the converted data voltage to a plurality of data lines (DL).

The data driver 6 supplies the odd data voltages to the m data lines DL so as to be synchronized with the scanning time of the odd gate lines GL in the first sub frame period, Numbered data voltages to the m data lines DL so as to be synchronized with the scanning point of the scanning lines GL.

The timing control unit 8 controls the driving timings of the gate driving unit 4, the data driving unit 6, and the switch unit 10. [

More specifically, the timing controller 8 controls the data control using a synchronizing signal input from the outside, that is, a horizontal synchronizing signal HSync, a vertical synchronizing signal VSync, a dot clock DCLK, a data enable signal DE, And outputs a signal DCS. The data control signal DCS includes a source output enable (SOE) for controlling the output period of the data driver 6, a source start pulse (SSP) for instructing the start of data sampling, A source shift clock (SSC) for controlling sampling timing of data, and the like.

Further, the timing control section 8 outputs the gate control signal GCS using the synchronization signal. Here, the gate control signal GCS includes a gate start pulse Vst and a plurality of clock pulses CLK.

Then, the timing controller 8 outputs the switching control signal SCS by using the synchronizing signal. Here, the switching control signal SCS is a pulse-shaped signal for turning on or off the switching element provided in the switch unit 10.

Hereinafter, the gate driving unit 4 and the switch unit 10 according to the embodiment will be described in more detail.

2 is a detailed view of the gate driver 4 and the switch unit 10 shown in FIG.

2, the gate driver 4 includes first to n / 2 stages ST1 to STn / 2 for generating scan pulses in response to a plurality of clock pulses CLK and a gate start pulse Vst Respectively. The gate driver 4 sequentially outputs scan pulses from the first stage ST1 to the n / 2-th stage STn / 2. On the other hand, a plurality of clock pulses CLK are outputted with different phase differences, and any number of clock pulses may be used if the number of clock pulses is two or more.

Each stage ST is supplied with any one of a plurality of clock pulses CLK, a gate start pulse Vst, a high potential voltage VDD and a low potential voltage VSS. At this time, neighboring stages receive different clock pulses (CLK).

The high-potential voltage VDD and the low-potential voltage VSS are direct-current voltages, and the high-potential voltage VDD has a relatively higher potential than the low-potential voltage VSS. For example, the high-potential voltage VDD may exhibit a positive polarity and the low-potential voltage VSS may exhibit a negative polarity. Further, the low potential voltage VSS may be a ground voltage. At this time, the low potential voltage VSS is equal to the potential of the low state of the clock pulse CLK.

Each stage ST outputs a high-level scan pulse in response to the scan pulse of the previous single stage ST. However, the first stage ST1 is provided with the gate start pulse Vst since the previous single stage does not exist.

In addition, each stage ST outputs a scan pulse in a low state in response to the scan pulse of the next stage ST. However, the n / 2 stage STn / 2 outputs a scan pulse in a low state in response to a signal supplied from a dummy stage (not shown).

The switch unit 10 includes MUXs connected to output stages of the stages ST of the gate driver 4, that is, first to n / 2 MUXs (MUX1 to MUXn / 2). Each of the MUXs MUX switches the scan pulse output from the corresponding stage ST and supplies the scan pulse to the odd gate lines GL in the first sub frame period and the even gate lines GL . Hereinafter, the switch unit 10 will be described in more detail.

FIG. 3 is a detailed view of the switch unit 10 shown in FIG. 2, and FIG. 4 is a drive waveform diagram of the switch unit 10 shown in FIG.

Referring to FIG. 3, each of the MUXs MUX responds to the switching control signal SCS, that is, the first to fourth control signals SCS1 to SCS4, GL of the first to fourth switching elements T1 to T4.

The first switching device T1 connects the output terminal of each stage ST and the odd gate line GL to each other in response to the first control signal SCS1.

The second switching element T2 supplies the gate-low voltage VGL to the odd-numbered gate lines GL in response to the second control signal SCS2.

The third switching element T3 connects the output terminal of each stage ST and the even gate line GL to each other in response to the third control signal SCS3.

The fourth switching element T4 supplies a gate low voltage VGL to the even gate lines GL in response to the fourth control signal SCS4.

Hereinafter, the operation of the MUX including the first to fourth switching devices T1 to T4 will be described.

Referring to FIG. 4, the gate driver 4 and the switch unit 10 divide one frame into first and second subframes. The gate driver 10 outputs scan pulses from the first stage ST1 to the n / 2-th stage STn / 2 once for each sub-frame. Therefore, the gate start pulse Vst is supplied at the start time of the subframe.

The scan pulses sequentially generated in the gate driver 10 are supplied to the odd gate lines GL in the first subframe and to the even gate lines GL in the second subframe.

To this end, the first and fourth control signals SCS1 and SCS4 are outputted in a high state in a first sub-frame and in a low state in a second sub-frame. The second and third control signals SCS2 and SCS3 are outputted in a low state in the first sub-frame and in a high state in the second sub-frame.

Then, in the first sub frame period, the first and fourth switching elements T1 and T4 are turned on and the second and third switching elements T2 and T3 are turned off. Then, the scan pulse outputted from each stage ST is supplied to the odd gate line GL, and the gate low voltage VGL is supplied to the even gate line GL.

Also, in the second sub frame period, the first and fourth switching elements T1 and T4 are turned off and the second and third switching elements T2 and T3 are turned on. Then, the scan pulse outputted from each stage ST is supplied to the even-numbered gate line GL, the gate-low voltage VGL is supplied to the odd-numbered gate line GL, and the voltage of the pixel connected to the corresponding gate line .

Meanwhile, a blank period is set between the first and second sub frame periods, in order to prevent a delay error that may occur at the time when each sub frame period is charged.

Meanwhile, the first and fourth control signals SCS1 and SCS4 have the same voltage state applied to each subframe. Likewise, the second and third control signals SCS2 and SCS4 have the same voltage state applied to each subframe. Therefore, the embodiment electrically connects the supply lines of the first and fourth control signals SCS1 and SCS4 to each other, and electrically connects the supply lines of the second and third control signals SCS2 and SCS3 to each other.

The connection of the supply lines of the first to fourth control signals SCS1 to SCS4 may be performed at a pad input terminal to which various control signals are supplied from the timing control unit 8 to the display panel 2. [ That is, the timing controller 8 controls the transmission line and the pin for generating the first and fourth control signals SCS1 and 4 and the second and third control signals SCS2 and SCS3 to drive the switch unit 10, One transmission line and one generation pin may be provided. Therefore, the embodiment can reduce the number of pins for driving the switch unit 10, simplify the circuit, and reduce the cost.

As described above, in the embodiment of the present invention, the number of stages of the gate driver 4 can be reduced to 1/2 by providing n / 2 stages ST. In the GIP type flat panel display device, the gate driver occupies a large portion in the bezel region. In the embodiment, the number of the stages ST is reduced, the space occupied by the gate driver 4 in the bezel region can be reduced, There is an effect that the design is facilitated.

Meanwhile, in the embodiment, the MUX provided in the switch unit 10 is output as two channels, thereby reducing the number of stages provided in the gate driver 4 to 1/2, but the number of output channels of the MUX is not limited to two Do not. That is, the present invention is not limited to the number of the output channels of the MUX, and the number of stages provided in the gate driving unit 4 according to the number of output channels of the MUX may be 1/4, 1/8, And the number of stages can be reduced in the form of 3/4, 7/8, etc. by changing the number of input channels and output channels of the MUX together.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

2: display panel 4: gate driver
6: Data driver 8: Timing controller
10:

Claims (7)

a display panel that defines pixels at the intersection of n gate lines and m (n, m is a natural number of 2 or more) data lines;
A gate driver having n / 2 stages which are built in the display panel and sequentially output a plurality of scan pulses;
And sequentially supplying the plurality of scan pulses to the odd-numbered gate lines in the first sub-frame by sequentially switching the plurality of scan pulses, and sequentially supplying the plurality of scan pulses to the even-numbered gate lines in the second sub- part;
A data driver for supplying a data voltage to the m data lines;
And a timing controller for controlling driving timings of the gate driver, the data driver, and the switch unit,
The data driver
Numbered gate lines in the first sub-frame period to the m data lines so that odd-numbered data voltages are synchronized with the scanning points of the odd-numbered gate lines,
Numbered data lines to the m data lines so as to be synchronized with the scanning time of the even-numbered gate lines in the second sub-frame period,
The switch unit
And MUXs connected to the output of each of the n / 2 stages,
Numbered gate lines in response to a first control signal, and a second switching device coupled between the output terminal of each stage and the odd-numbered gate lines in response to a first control signal, A third switching element for connecting the output terminal of each stage and the even gate line to each other in response to a third control signal and a second switching element for connecting the gate low voltage to the even gate And a fourth switching element for supplying the fourth switching element to the line. delete delete The method according to claim 1,
Wherein the first and fourth control signals are outputted in a high state in the first sub frame period to turn on the first and fourth switching elements and output in a low state in the second sub frame period, And the fourth switching element are turned off,
And the second and third control signals are outputted in a low state in the first sub frame period to turn off the second and third switching elements and output in a high state in the second sub frame period, And the third switching element are turned on. 5. The method of claim 4,
Wherein the supply lines of the first and fourth control signals are electrically connected to each other and the supply lines of the second and third control signals are electrically connected to each other. 6. The method of claim 5,
And the first to fourth control signals are outputted from the timing control unit. The method according to claim 1,
And a blank period is set between the first sub frame period and the second sub frame period.

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