KR102268965B1 - Gate shift register and display device using the same - Google Patents

Abstract

The present invention relates to a gate shift register capable of improving reliability by preventing multi-output and a display device using the same, wherein the gate shift register according to the present invention is selectively connected to lines to which a plurality of clock signals are supplied, a node controller for controlling voltages of first and second nodes in response to a carry signal and a reset signal, each of the plurality of stages sequentially outputting pulses; according to the voltage level of the first node a pull-up transistor for outputting the scan pulse to an output terminal, and a pull-down transistor for supplying a gate-off voltage to the output terminal according to a voltage level of the second node, wherein the node control unit responds to a blank signal provided during a blank period. and a blank driving transistor for charging the voltage of the second node in response.

Description

GATE SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME

The present invention relates to a gate shift register, and to a gate shift register capable of improving reliability by preventing multiple outputs, and a display device using the same.

Recently, a display device that is widely used includes a liquid crystal display device, an organic light emitting display device, and the like.

In general, a display device includes a display panel for displaying an image, a gate driver for supplying scan pulses to gate lines of the display panel, a data driver for supplying data voltages to data lines of the display panel, and a gate driver and a timing controller for controlling the data driver.

The gate driver includes a gate shift register for driving a plurality of gate lines, and the gate shift register includes a plurality of stages for sequentially outputting scan pulses.

Each of the plurality of stages includes a pull-up transistor and a pull-down transistor as an output buffer unit. The pull-up transistor is switched according to the voltage of the first node charged by the carry signal provided from the previous stage to output a scan pulse to an output terminal. The pull-down transistor is switched according to the voltage of the second node charged by the reset signal to supply a gate-off voltage to the output terminal. Here, the pull-down transistor is designed to maintain the turn-on state for most of the period except for the period in which the scan pulse is output during one frame period in which each stage is driven. However, the conventional gate shift resistor has a problem in that a leakage current is generated through transistors connected to the second node as the driving time increases, so that the voltage at the second node becomes unstable. When the voltage of the second node becomes unstable, the pull-down transistor does not operate normally, which causes multi-output generation.

The multi-output is generated because the output terminal is not discharged in time due to a malfunction of the pull-down transistor, and is a phenomenon in which a plurality of scan pulses are output to the output terminal by a coupling phenomenon between the first node and the pull-up transistor. In general, since a plurality of stages are connected in a cascade manner, when a multi-output is generated from a specific stage, subsequent stages may also generate a multi-output. As a result, the multi-output deteriorates the reliability of the gate shift register and further deteriorates the image quality of the display device.

Meanwhile, unlike TVs and monitors that use commercial power among recent display devices, cell phones, laptops, tablet PCs, smart watches, etc. operate by receiving power from a portable battery, so it is an important task to reduce power consumption. As a part of it, low-frequency driving technology is attracting attention. The low-frequency driving technology is a technology for reducing power consumption by displaying an image at a frequency lower than 60 Hz in a low-frequency mode set by a user or a condition in which a specific image pattern is input.

However, when the low-frequency driving technique as described above is applied, the leakage current of the aforementioned gate shift resistor is further increased as the blank period is lengthened. Accordingly, as the malfunction of the pull-down transistor increases, the problem of deterioration of the reliability of the gate shift register due to the multi-output increases.

The present invention has been devised to solve the above-described problems, and an object of the present invention is to provide a gate shift register capable of improving reliability by preventing multi-output and a display device using the same.

In addition to the technical problems of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those skilled in the art from such description and description.

A gate shift register and a display device using the same according to the present invention for achieving the above technical problem include a plurality of stages selectively connected to lines to which a plurality of clock signals are supplied, and sequentially outputting scan pulses, Each of the plurality of stages includes a node controller for controlling voltages of first and second nodes in response to a carry signal and a reset signal, a pull-up transistor for outputting the scan pulse to an output terminal according to the voltage level of the first node, and and a pull-down transistor for supplying a gate-off voltage to the output terminal according to the voltage level of the second node, wherein the node controller charges the voltage of the second node in response to a blank signal provided during a blank period. It may include a transistor.

According to the means for solving the above problems, the present invention has the following effects.

The gate shift register of the present invention charges the voltage of the second node to which the gate electrode of the pull-down transistor provided in each stage is connected to the gate-on voltage by using the blank signal provided during the blank period. Accordingly, according to the present invention, it is possible to improve driving reliability by preventing malfunction of the pull-down transistor due to leakage current of the second node and multi-output resulting therefrom. In particular, the present invention can increase reliability by preventing voltage instability at the second node when a low-frequency driving technique that lengthens the blank period is applied, thereby preventing malfunction of the pull-down transistor and multi-output resulting therefrom.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below or will be clearly understood by those of ordinary skill in the art from such description and description.

1 is a block diagram of a display device having a gate shift register according to the present invention.
FIG. 2 is a block diagram of a gate shift register constituting the gate driver 4 shown in FIG. 1 .
3A and 3B are driving waveform diagrams of the gate shift register shown in FIG. 2 .
FIG. 4 is a configuration circuit diagram of an arbitrary k-th stage STk shown in FIG. 2 .
5A to 5D are diagrams for explaining a method of driving the stage STk shown in FIG. 2 in stages.
6 is a view for explaining the operation of the stage according to the blank signal.

The meaning of the terms described herein should be understood as follows. The singular expression is to be understood as including the plural expression unless the context clearly defines otherwise, and the terms "first", "second", etc. are used to distinguish one element from another, The scope of rights should not be limited by these terms. It should be understood that terms such as “comprise” or “have” do not preclude the possibility of addition or existence of one or more other features or numbers, steps, operations, components, parts, or combinations thereof. The term “at least one” should be understood to include all possible combinations from one or more related items. For example, the meaning of "at least one of the first, second, and third items" means 2 of the first, second, and third items as well as each of the first, second, or third items. It means a combination of all items that can be presented from more than one. The term "on" is meant to include not only cases in which a component is formed directly on top of another component, but also a case in which a third component is interposed between these components.

Hereinafter, a preferred example of a gate shift register and a display device using the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a display device having a gate shift register according to the present invention.

Referring to FIG. 1 , a display device according to the present invention includes a display panel 2 , a gate driver 4 , a data driver 6 , and a timing controller 8 .

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL that intersect each other, and a plurality of pixels P are provided in the intersection regions of the GL and DL. Each pixel P displays an image according to an image signal (data voltage) supplied from the data line DL in response to the scan pulse G supplied from the gate line GL.

The gate driver 4 is a gate in panel (GIP) type gate driver and is disposed in a non-display area of the display panel 2 . The gate driver 4 includes a gate shift register that supplies scan pulses G to the plurality of gate lines GL according to the plurality of gate control signals GCS provided from the timing controller 8 . The plurality of gate control signals GCS include a plurality of clock signals CLK1-4 having different phases and a gate start signal VST instructing the start of driving of the gate driver 4 . The gate shift register will be described in detail later with reference to FIGS. 2 to 6 .

The data driver 6 converts digital image data RGB input from the timing controller 8 into a data voltage using a reference gamma voltage, and supplies the converted data voltage to a plurality of data lines DL. This data driver 6 is controlled according to a plurality of data control signals DCS provided from the timing controller 8 .

The timing controller 8 aligns image data RGB input from the outside according to the size and resolution of the display panel 2 and supplies it to the data driver 6 . The timing controller 8 uses a plurality of synchronization signals SYNC input from the outside, for example, a dot clock DCLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync. The gate and data control signals GCS and DCS are generated and supplied to the gate driver 4 and the data driver 6, respectively.

FIG. 2 is a block diagram of a gate shift register constituting the gate driver 4 shown in FIG. 1 . 3A and 3B are driving waveform diagrams of the gate shift register shown in FIG. 2 .

Referring to FIG. 2 , the gate shift register according to an embodiment of the present invention includes a plurality of cascadingly connected stages ST (ST1, ST2, ST3, ...). The plurality of stages ST are selectively connected to lines to which a plurality of clock signals CLK1-4 are supplied, and sequentially output scan pulses G; G1, G2, G3, ...).

Specifically, each of the plurality of stages ST receives at least one selected from among the plurality of clock signals CLK1-4, a gate-on voltage VGH, a gate-off voltage VGL, and a blank signal BS. .

As shown in FIG. 3A , the plurality of clock signals CLK1-4 may include four-phase clock signals that are shifted by a predetermined period and output, that is, first to fourth clock signals CLK1-4. Three of the first to fourth clock signals CLK1-4 are selected and supplied to each stage ST. For example, the first, third, and fourth clock signals CLK1, 3, and 4 are supplied to the 4k-3 (k is a natural number)-th stages ST1, ST5, ST9, .... The second, fourth, and first clock signals CLK2, 4, 1 are supplied to the 4k-2th stages ST2, ST6, ST10, .... The third, first, and second clock signals CLK3, 1, and 2 are supplied to the 4k-1th stages ST3, ST7, ST11, .... The fourth, second, and third clock signals CLK4, 2, and 3 are supplied to the 4k-th stages ST4, ST8, ST12, ....

As illustrated in FIG. 3B , the blank signal BS may be a source output enable signal SOE provided from the timing controller 8 as a signal provided during the blank period BP. Here, the blank period BP is a period set after the scan period SP in which the scan pulses G are outputted from the plurality of stages ST once.

In particular, in the gate shift register of the present invention, the second node QB to which the gate electrode of the pull-down transistor PD provided in each stage ST is connected by using the blank signal BS provided during the blank period BP. ) to the gate-on voltage (VGH). Accordingly, according to the present invention, a malfunction of the pull-down transistor PD due to the leakage current of the second node QB and multi-output resulting therefrom are prevented, thereby improving driving reliability.

FIG. 4 is a configuration circuit diagram of an arbitrary k-th stage STk shown in FIG. 2 .

Referring to FIG. 4 , the stage STk receives the first, third, and fourth clock signals CLK1, 3, and 4 from among the plurality of clock signals CLK1-4 and generates a k-th scan pulse Gk. configured to output.

Specifically, the stage STk includes the node control unit 100 and the output buffer unit 200 .

The output buffer unit 200 includes a pull-up transistor PU that outputs the scan pulse Gk to an output terminal OUT according to the voltage level of the first node Q, and a voltage of the second node QB. and a pull-down transistor PD that supplies a gate-off voltage VGL to the output terminal OUT according to a level. Specifically, the pull-up transistor PU has a gate electrode connected to the first node Q, a first electrode connected to a supply line of a first clock signal CLK1 as a k-th clock signal, and an output terminal. and a second electrode. The pull-down transistor PD includes a gate electrode connected to the second node QB, a first electrode connected to the output terminal OUT, and a second electrode connected to the gate-off voltage VGL supply line. include

The node controller 100 controls voltages of the first and second nodes Q and QB in response to the carry signal and the reset signal. To this end, the node control unit 100 is configured to include a first node charging unit, a first node discharging unit, a second node charging unit, and a second node discharging unit.

The first node charger charges the voltage of the first node Q in response to the carry signal and the fourth clock signal CLK4. To this end, the first node charging unit includes first and second transistors T1 and T2.

The first transistor T1 outputs a gate-on voltage VGH in response to the carry signal. The second transistor T2 supplies the gate-on voltage VGH output from the first transistor T1 to the first node Q in response to a fourth clock signal CLK4 . Here, the carry signal may be a scan pulse Gk-1 provided from at least one previous stage ST or a gate start signal VST provided from the outside.

The second node discharge unit discharges the voltage of the second node QB to the gate-off voltage VGL according to the carry signal and the voltage level of the first node Q. To this end, the second node discharge unit includes third to fifth transistors T3 to T5.

The third transistor T3 includes a gate electrode to which the gate-on voltage VGH is applied, and connects the first node Q and the gate electrode of the fourth transistor T4 to each other. The fourth transistor T4 supplies the gate-off voltage VGL to the second node QB according to the voltage level of the first node Q connected through the third transistor T3 . The fifth transistor T5 supplies the gate-off voltage VGL to the second node QB in response to the carry signal.

The first node discharge unit discharges the voltage of the first node Q to the gate-off voltage VGL according to the voltage level of the second node QB. To this end, the first node discharge unit includes sixth and seventh transistors T6 and T7.

The sixth transistor T6 outputs the gate-off voltage VGL according to the voltage level of the second node QB. The seventh transistor T7 includes a gate electrode to which the gate-on voltage VGH is applied, and supplies the gate-off voltage VGL provided through the sixth transistor T6 to the first node Q. .

The second node charger charges the voltage of the second node QB in response to the reset signal. To this end, the second node charging unit includes the eighth transistor T8.

The eighth transistor T8 supplies a gate-on voltage VGH to the second node QB in response to the reset signal. Here, the reset signal may be a third clock signal CLK3 or a scan pulse Gk+2 output from at least one next stage.

In particular, the node controller 100 according to an embodiment of the present invention generates a blank driving transistor BDT for charging the voltage of the second node QB in response to the blank signal BS provided during the blank period BP. include more The blank driving transistor BDT is turned on during the blank period BP to charge the voltage of the second node QB to the gate-on voltage VGH.

5A to 5D are diagrams for explaining a method of driving the stage STk shown in FIG. 2 in stages. Hereinafter, a method of driving the gate shift register according to an exemplary embodiment of the present invention will be described with reference to FIGS. 5A to 5D .

First, referring to FIG. 6A , in a first period P1 , a scan pulse Gk-1 provided from the previous stage ST or a gate start signal VST provided from the outside is supplied as a carry signal, and a fourth The clock signal CLK4 is input to the stage STk in the state of the gate-on voltage VGH. Then, the first and second transistors T1 and T2 are turned on, and the first node Q is precharged to the gate-on voltage VGH through the first and second transistors T1 and T2. Then, the fourth transistor T4 is turned on, and the gate-off voltage VGL is supplied to the second node QB. Meanwhile, the fifth transistor T5 is turned on in response to the carry signal to supply the gate-off voltage VGL to the second node QB. Accordingly, the second node QB is discharged to the gate-off voltage VGL, and the pull-down transistor PD is turned off.

Subsequently, referring to FIG. 6B , in the second period P2 , the first clock signal CLK1 is input to the stage STk in the state of the gate-on voltage VGH. Then, the voltage level of the first node Q is bootstrapped by the parasitic capacitance of the pull-up transistor PU connected to the supply line of the first clock signal CLK1 and is higher than the gate-on voltage VGH. raised to the level Accordingly, the pull-up transistor PU is completely turned on, and the pull-up transistor PU supplies the first clock signal CLK1 as the k-th scan pulse Gk to the output terminal OUT.

Subsequently, referring to FIG. 6C , in a third period P3 , the first clock signal CLK1 transitions from the gate-on voltage VGH to the gate-off voltage VGL, and thus is output to the output terminal OUT. The scan pulse Gk becomes the gate-off voltage VGL. At this time, the voltage of the first node Q continues to maintain a voltage pre-charged by the capacitor C provided between the first node Q and the output terminal OUT.

Subsequently, referring to FIG. 6D , in the fourth period P4 , the third clock signal CLK3 or the scan pulse Gk+2 output from at least one next stage is input to the stage STk as a reset signal. do. Then, the gate-on voltage VGH is supplied to the second node QB through the eighth transistor T8. Then, the sixth transistor T6 is turned on, and the gate-off voltage VGL is supplied to the first node Q. Accordingly, the first node Q is discharged to the gate-off voltage VGL, and the pull-up transistor PU is turned off. Meanwhile, as the voltage level of the second node QB is charged to the gate-on voltage VGH, the pull-down transistor PD is turned on. Accordingly, the pull-down transistor PD supplies the gate-off voltage VGL to the output terminal OUT. The pull-down transistor PD is turned on until the carry signal is input to the corresponding stage STk in the next frame period to supply the gate-off voltage VGL to the output terminal OUT. Accordingly, the operation of the stage STk during the scan period SP is completed.

Meanwhile, in the blank period BP after the scan period SP ends, the blank signal BS is generated and is simultaneously supplied to all stages ST. Then, as shown in FIG. 6 , the blank driving transistors BDT provided in each stage ST are turned on to supply the gate-on voltage VGH to the second node QB. Accordingly, each stage ST of the present invention prevents instability of the second node QB due to leakage current, thereby preventing malfunction of the pull-down transistor PD and multi-output resulting therefrom, thereby improving driving reliability. have.

As described above, the gate shift register of the present invention charges the voltage of the second node to which the gate electrode of the pull-down transistor provided in each stage is connected to the gate-on voltage using the blank signal provided during the blank period. . Accordingly, according to the present invention, it is possible to improve driving reliability by preventing malfunction of the pull-down transistor due to leakage current of the second node and multi-output resulting therefrom. In particular, the present invention can increase reliability by preventing voltage instability at the second node when a low-frequency driving technique that lengthens the blank period is applied, thereby preventing malfunction of the pull-down transistor and multi-output resulting therefrom.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical matters of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention.

100: node control unit 200: output buffer unit
BS: blank signal

Claims (11)

a plurality of stages selectively connected to lines to which a plurality of clock signals are supplied and sequentially outputting scan pulses;
Each of the plurality of stages includes a node controller for controlling voltages of the first and second nodes in response to a carry signal and a reset signal, a pull-up transistor for outputting the scan pulse to an output terminal according to the voltage level of the first node, and a pull-down transistor for supplying a gate-off voltage to the output terminal according to the voltage level of the second node;
and the node control unit is turned on in response to a blank signal provided during a blank period, and includes a blank driving transistor configured to charge a voltage of the second node with a gate-on voltage of the blank signal. The method of claim 1,
the pull-up transistor comprises a gate electrode connected to the first node, a first electrode connected to a supply line of a kth clock signal, and a second electrode connected to an output terminal;
and the pull-down transistor comprises a gate electrode connected to the second node, a first electrode connected to the output terminal, and a second electrode connected to the gate-off voltage supply line. 3. The method of claim 2,
The node controller
a first node charging unit charging the voltage of the first node in response to the carry signal and the k+3th clock signal;
a second node discharge unit configured to discharge the voltage of the second node to the gate-off voltage according to the carry signal and the voltage level of the first node;
a first node discharge unit configured to discharge the voltage of the first node to the gate-off voltage according to the voltage level of the second node;
a second node charging unit charging the voltage of the second node in response to the reset signal; and
and the blank driving transistor. 4. The method of claim 3,
The first node charging unit
a first transistor for outputting a gate-on voltage in response to the carry signal; and
and a second transistor configured to supply a gate-on voltage output from the first transistor to the first node in response to the k+3th clock signal. 4. The method of claim 3,
The second node discharge unit
a third transistor including a gate electrode to which a gate-on voltage is applied and connecting the first node and the gate electrode of the fourth transistor to each other;
a fourth transistor supplying the gate-off voltage to the second node according to a voltage level of a first node connected through the third transistor; and
and a fifth transistor configured to supply the gate-off voltage to the second node in response to the carry signal. 4. The method of claim 3,
The first node discharge unit
a sixth transistor outputting the gate-off voltage according to the voltage level of the second node; and
and a seventh transistor including a gate electrode to which a gate-on voltage is applied to supply a gate-off voltage provided through the sixth transistor to the first node. 4. The method of claim 3,
The second node charging unit
and an eighth transistor for supplying a gate-on voltage to the second node in response to the reset signal. The method of claim 1,
wherein the blank signal is a source output enable signal provided from a timing controller. 3. The method of claim 2,
The reset signal is a k+2th clock signal or a scan pulse output from at least one next stage. 3. The method of claim 2,
The carry signal is a scan pulse output from at least one previous stage or a gate start signal provided from the outside. a display panel having a plurality of gate lines; and
a pull-up transistor embedded in a non-display area of the display panel to output a scan pulse to an output terminal according to a voltage level of a first node to drive the plurality of gate lines, and the output terminal according to a voltage level of a second node a gate shift resistor comprising a pull-down transistor for supplying a gate-off voltage to;
The gate shift register is configured to charge a voltage of the second node with a gate-on voltage of the blank signal in response to a blank signal provided from a timing controller during a blank period.

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