KR102138664B1 - Display device - Google Patents

Abstract

A display device according to an exemplary embodiment of the present invention provides a display device that differently applies a gate signal by separating a video area and a still image area from a display area, and determines input data to determine the data to be changed and the gate drive It is possible to provide a display device that can reduce power consumption by driving and driving data and a gate drive in an unchanged region.
A display device according to an exemplary embodiment of the present invention includes: a panel having n (n is a natural number) gate lines; A timing control unit generating a clock signal and a driving mode control signal; And a gate driver applying a gate signal to each of the gate lines in response to the clock signal and the driving mode control signal. Including, wherein the driving mode control signal is a signal having a different logic value according to a still screen or a video screen, and a display device for determining whether to output a gate signal to the gate lines according to the logic value.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

Recently, in the field of electronic information display devices, flat display devices have replaced conventional cathode ray tube display devices (CRTs), such as LCD (Liquid Crystal Display), PDP (Plasma Display Panel) ), Field Emission Display (FED) and Organic Light Emitting Diodes (OLED).

In particular, an active matrix type display device in which a thin film transistor is used as a switching element is suitable for displaying a dynamic image.

In order to control the turn-on/off operation of the above-described thin film transistor, a typical display device is provided with a gate driver for generating and providing a scan signal, and data providing a data signal for representing the gradation of an image A driving unit is provided.

1 is a block diagram showing the basic configuration of a conventional display device.

As shown, a conventional display device is made up of a panel 1 for displaying an image and driving units 4 and 5.

In the panel 1, a plurality of gate lines GL and a plurality of data lines DL are intersected in a matrix form on a substrate using glass, and a plurality of pixels are defined at an intersection, and a data signal applied to the pixels is used. The image is displayed accordingly.

The panel 1 is divided into a display area (A/A) in which pixels are formed to form an image, and a non-display area (N/A) surrounding the display area (A/A).

The driving units 4 and 5 include a gate driving unit 4 and a data driving unit 5.

The gate driver 4 controls turn on/off of switching elements of pixels arranged on the panel 1 in response to a gate control signal GCS supplied from a timing controller (not shown). do.

The gate driving unit 4 outputs the gate driving voltage VG to the panel 1 through the gate line GL to sequentially turn on the pixel switching elements line by line, thereby providing data driving circuits for each horizontal cycle. The data signal supplied from 5) is supplied to the pixel.

The data driver 5 modulates the image data of the digital waveform into the data signal of the analog waveform in response to the data control signal DCS supplied from the timing control unit.

Next, a data signal corresponding to one horizontal period is simultaneously supplied to the panel 1 through all data lines DL for each horizontal period, so that each pixel displays the gradation of the image.

In the display device having such a structure, the gate driver 4 has a relatively simple structure compared to the data driver 5, and the gate driver is a separate IC to reduce the volume, weight, and manufacturing cost of the display device. The gate-in-panel (Gate) is manufactured on the non-display area (N/A) in the form of a thin film transistor when the substrate of the panel 1 is manufactured, instead of bonding to the panel 1 by implementing -In-Panel, GIP) method was proposed.

In addition, as illustrated in FIG. 1, the gate driving unit 4 is built into the display device on the left and right sides of the panel 10 in a GIP method, and an overlap period between each front and rear gate driving voltage is provided to precharging the gate line. A structure in which the switching element is stably turned on through has been applied.

In addition, a method of applying a driving frequency of the display device to 120Hz or more, not 60Hz, has been proposed for the display device to realize high image quality. However, such a display device has a problem in that power consumption increases with an increase in driving frequency.

In particular, when the video was implemented, the image quality was improved through high-frequency operation, but there was a problem in that unnecessary power consumption was increased by uniformly performing high-frequency operation on a still image or a screen in which a still image and a video exist together.

In order to solve the above problem, a display device according to an exemplary embodiment of the present invention provides a display device for differently applying a gate signal by dividing a moving picture area and a still image area in a display area.

In addition, a display device capable of reducing power consumption is provided by determining input data and driving data and a gate drive in an area to be changed, and driving data and a gate drive in an unchanged area.

Also, a display device capable of reducing power consumption is provided by realizing high-frequency driving only in a region in which the scan signal is supplied to the gate line, and driving low frequency in a region in which the scan signal is not supplied.

A display device according to an exemplary embodiment of the present invention includes: a panel in which n (n is a natural number) gate lines are formed; A timing control unit generating a clock signal and a driving mode control signal; And a gate driver applying a gate signal to each of the gate lines in response to the clock signal and the driving mode control signal. Including, wherein the driving mode control signal is a signal having a different logic value according to a still screen or a video screen, and a display device for determining whether to output a gate signal to the gate lines according to the logic value.

In the display device according to an exemplary embodiment of the present invention, the gate driver includes a gate signal generator and a gate controller, and the gate signal generator outputs a gate signal to the gate controller in response to the clock signal, and the gate controller The display device determines whether or not a gate signal is output to the gate line according to a logic value of the driving mode control signal.

The display device according to an embodiment of the present invention, the gate control unit includes a comparison unit composed of an AND gate, a switching unit and first and second switches controlled according to the output signals of the switching unit, and the comparison unit comprises the gate signal The logic value of the output signal from the generation unit is compared with the logic value of the drive mode control signal, and the corresponding output is output to the switching unit, and the switching unit is selected from among the first and second switches according to the output value of the comparison unit. A display device that turns on one and turns off the other.

The display device according to an exemplary embodiment of the present invention outputs the clock signal to a gate line corresponding to the first switch when the first switch is turned on, and when the second switch is turned on, A display device that discharges the signal of the gate line corresponding to the second switch.

In the display device according to an exemplary embodiment of the present invention, among the gate lines, a gate signal is provided to the second gate lines among first gate lines corresponding to a video region and second gate lines corresponding to a still image region. Display device that is not output.

A display device according to an exemplary embodiment of the present invention includes: a panel in which n (n is a natural number) gate lines are formed; A timing control unit generating first to fourth clock signals and a driving mode control signal; A first gate driver for applying a gate high logic signal to one side of the odd-numbered gate lines in correspondence with the high logic of the first and second clock signals and the drive mode control signal; And a second gate driver that applies the gate high logic signal to one side of the even-numbered gate line in response to high logic of the third and fourth clock signals and the driving mode control signal. The signal is a display device that is a high logic signal on a video screen.

In the display device according to the exemplary embodiment of the present invention, the first to fourth clock signals may include:

A display device characterized in that each has a high logic signal period of 2 horizontal periods (2H), and 1 horizontal period (1H) overlaps between the front and rear signals.

In the display device according to an exemplary embodiment of the present invention, each of the first and second gate drivers includes a gate signal generator and a gate controller, and the gate signal generator is a gate signal corresponding to the first to fourth clock signals. Is output to the gate control unit, and the gate control unit determines whether to output a gate signal to the gate line according to a logic value of the driving mode control signal.

The display device according to an embodiment of the present invention, the gate control unit includes a comparison unit composed of an AND gate, a switching unit and first and second switches controlled according to the output signals of the switching unit, and the comparison unit comprises the gate signal The logic value of the output signal from the generation unit is compared with the logic value of the drive mode control signal, and the corresponding output is output to the switching unit, and the switching unit is selected from among the first and second switches according to the output value of the comparison unit. A display device that turns on one and turns off the other.

In the display device according to the exemplary embodiment of the present invention, the timing control unit is a display device that drives a low frequency when a still screen is displayed.

A display device according to an exemplary embodiment of the present invention provides a display device that differently applies a gate signal by separating a video area and a still image area from a display area, and determines input data to determine the data to be changed and the gate drive Drive, and provide a display device that can reduce power consumption without driving the data and gate drive in an unchanged area, and realize high frequency driving only in the area where the scan signal is supplied to the gate line. In a region in which the signal is not supplied, low-frequency driving may be provided, thereby providing a display device capable of reducing power consumption.

1 is a block diagram showing the basic configuration of a conventional display device.
2 is a view showing a display device and a driving unit thereof according to an embodiment of the present invention.
3 is a view showing a gate driver of a display device according to an exemplary embodiment of the present invention.
4 is a view illustrating a first gate driver of a display device according to an exemplary embodiment of the present invention.
5 is a diagram showing the operation of the first gate driver.
6 is a circuit diagram of a gate driver of a display device according to an exemplary embodiment of the present invention.
7 is a diagram illustrating a main period operation process of the gate signal generation unit.
8 is a view for explaining the operation method of the display device of the present invention.

Hereinafter, with reference to the drawings of the display device according to an embodiment of the present invention will be described in detail. The embodiments introduced below are provided as examples in order to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. Throughout the specification, the same reference numbers indicate the same components.

2 is a view showing a display device and a driving unit thereof according to an embodiment of the present invention.

Referring to FIG. 2, the display device 100 according to an exemplary embodiment of the present invention includes a panel 210 displaying an image, a timing controller 200 receiving a timing signal from an external system and generating various control signals, Gates and data drivers 310, 320, and 400 that control the panel 210 in response to the control signal may be included.

In the panel 210, n (n is a natural number) gate line GL and a plurality of data lines DL are intersected in a matrix form on a substrate using glass, and a plurality of pixels are defined at the intersection.

Each pixel is provided with a thin film transistor (TFT), a liquid crystal capacitor (Clc), and a storage capacitor (Cst), and all pixels form one display area (A/A).

Areas in which pixels are not defined are divided into non-display areas (N/A).

The timing controller 200 includes an image signal RGB transmitted from an external system, a clock signal DCLK, a horizontal sync signal Hsync, a vertical sync signal Vsync, a data enable signal DE, and a driving mode control signal A signal such as (Mode Control Signal:MCS) may be applied to generate control signals of the gate driver 140 and the data driver 150.

Here, the horizontal synchronization signal (Hsync) is a signal indicating the time it takes to display one horizontal line of the screen, and the vertical synchronization signal (Vsync) is a signal indicating the time it takes to display a screen of one frame, and a data enable signal. (DE) is a signal indicating a period during which the data voltage is supplied to the pixels defined in the panel 210.

In addition, the driving mode control signal MCS is a signal for determining whether to output a scan signal by dividing a video area and a still image area for each area of the display area A/A.

In addition, the timing controller 200 may generate a control signal GCS of the gate drivers 310 and 320 and a control signal DCS of the data driver 400 in synchronization with the input timing signal.

In addition, the timing controller 200 generates a plurality of clock signals CLK 1 to CLK 4 that determine the driving timing of each stage of the gate drivers 310 and 320 and provides them to the gate drivers 310 and 320.

Here, the first to fourth clock signals CLK 1 to CLK4 are signals in which a high period progresses for 2 horizontal periods (2H) and 1 horizontal period (1H) overlaps with each other.

The timing controller 200 sorts and modulates the received image data RGB data in a form that the data driver 400 can process and outputs.

Here, the aligned image data RGBv may be in a form in which a color coordinate correction algorithm for improving image quality is applied.

Two gate driving units 310 and 320 may be provided at both ends of the panel 210 and in the non-display area N/A.

Each gate driver 310, 320 may be formed of a plurality of stages including shift registers.

When the substrate of the panel 210 is manufactured, the gate driving units 310 and 320 may be embedded in a non-display area in a thin-film pattern in a gate-in-panel (GIP) method.

The first and second gate drivers 310 and 320 may include a plurality of gate lines formed on the panel 210 in response to the gate control signal GCS and the driving mode control signal MCS input from the timing controller 200 ( Through GL 1 to GL n), the gate high voltage VGH can be alternately output every 2 horizontal periods (2H).

Here, the output gate high voltage VGH may be maintained for 2 horizontal periods 2H, and the front and rear gate high voltage VGH may overlap for 1 horizontal period 1H.

This is for precharging the gate lines GL 1 to GL n, and more stable pixel charging can be performed when a data voltage is applied.

To this end, first and second clock signals CLK 1 and CLK 2 having 2 horizontal periods 2H are applied to the first gate driver 310, respectively, and the first and second clock drivers 320 are applied to the first gate driver 310. Two clock signals CLK 1 and CLK 2 and one horizontal period 1H overlap, and third and fourth clock signals CLK 2 and CLK 4 having 2 horizontal periods 2H may be applied.

As an example, when the first gate driver 310 outputs the gate high voltage VGH to the n-th gate line GLn, after the first horizontal period 1H, the second gate driver 320 is an n+1th gate The gate high voltage VGH may be output through the line GLn+1.

That is, the first gate driver 310 may provide a gate signal to an odd-numbered gate line, and the second gate driver 320 may provide a gate signal to an even-numbered gate line.

3 is a diagram illustrating a gate driver of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the gate driver 300 of the display device according to an exemplary embodiment of the present invention includes first and second gate drivers 310 and 320, and the first and second gate drivers 310 and 320 ) Each may include a gate signal generator 330 and a gate controller 340.

Clock signals CLK1, CLK2, CLK3, and CLK4 and power signals VDD and VSS are input to the gate signal generator 330, and may generate and supply a gate signal to the gate controller 340. have.

The gate signal generator 331 located at the top of the gate signal generator 330 may receive a start signal VST to generate a gate signal, and the gate signal generator 332 of the next stage is the front end. The gate signal may be generated by receiving a signal from the gate signal generator 321.

The gate signal generated in this way is input to the gate control unit 340, and the gate control unit 340 may determine whether to output the gater signal according to the signal of the driving mode control signal MCS.

The driving mode control signal (MCS) may be supplied from a timing control unit, and is divided into a still image and a video screen among screens displayed on the panel 210, and in the case of a still screen, becomes a low logic signal and is a video screen. In this case, it becomes a signal of high logic, so that the gate signal is applied only in the region where the video screen appears, and the data signal can be updated accordingly.

4 is a diagram illustrating a first gate driver of a display device according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating an operation of the first gate driver.

Referring to FIG. 4, the first gate driver 310 of the display device according to an exemplary embodiment of the present invention includes a plurality of gate signal generators 331, 332, 333, ..., and the plurality of gate signal generators 331, 332, 333,...) and corresponding gate control parts 341, 342, 343, ....

Each of the gate controllers 341, 342, 343, .... may include an AND gate comparison unit 350, 351, 352, ..., and a switching unit 360, 361, 362,... as a logic circuit.

4 and 5, an operation process of the first gate driver 310 will be described.

<1st time period (T1)>

During the first time period T1, a high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350, and the driving mode control signal MCS is generated. When having high logic, the first comparator 350 may output a high logic signal to the first switching unit 360.

Conversely, a high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350, but when the driving mode control signal MCS has a low logic, the first The comparator 350 may output a low logic signal to the first switching unit 360.

When the first switching unit 360 receives a high logic signal from the first comparator 350, the first switch S1 is turned on, so that the first clock signal CLK1 is the first gate line GL1. ), and at the same time, the second switch S2 may be turned off.

In addition, when the first switching unit 360 receives a low logic signal from the first comparator 350, the first switch S1 is turned off, the second switch S2 is turned on, and the second switching unit 360 is turned on. Signals on one gate line GL1 can be discharged.

<2nd time period (T2)>

During the second time period T2, the first switching unit 360 applies the high logic signal to the first switch S1 when the high logic signal is applied from the first comparison unit 350, and the second A signal of low logic is output to the switch S2.

<3rd time period (T3)>

During the third time period T3, while the high logic clock signal CLK1 is applied to the first switch S1 of the first gate control unit 341, the first switch S1 according to the bootstrap. The Q node rises and may output a gate signal to the first gate line GL1.

<4th time period (T4)>

During the fourth time period T4, a high logic driving mode control signal MCS is applied to the second comparison unit 351 of the second gate control unit 342, and the second gate signal generation unit 332 The second comparison unit 351 outputs a high logic signal to the second switching unit 361 by a high logic signal, and the high logic is operated in the same manner as the operation of the first switching unit 361 described above. The clock signal CLK2 of may be output to the third gate line GL3 through the first switch S1 of the second gate control unit 342 as a gate signal.

<Section 5 (T5)>

During the fifth time period T5, since the driving mode control signal MCS has a low logic, the third comparison unit 352 generates a high logic gate signal and a low logic generated by the third gate signal generation unit 333. By receiving the driving mode control signal (MCS) of the, and provides the output of the low logic to the third switching unit 362, the third switching unit 362 is the first switch (S1) of the third gate control unit 343 ) Is turned off, and the second switch S2 is turned on, so that a gate signal that is a scan signal is not output to the fifth gate line.

Through this operation, since a gate signal is not applied to a specific area of the display area A/A, the data line DL corresponding to the corresponding gate line is not driven and power consumption can be reduced accordingly. .

Further, only the region in which the scan signal is supplied to the gate line realizes high frequency driving, and the region in which the scan signal is not supplied is subjected to low frequency driving, thereby reducing power consumption.

6 is a circuit diagram of a gate driver of a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the gate driver of the display device according to an exemplary embodiment of the present invention may include gate signal generators 331 and 332 and gate controllers 341 and 342.

The first gate signal generator 331 and the second gate signal generator 332 have the same structure.

<Circuit connection of the gate signal generator>

The connection relationship between the gate signal generators 331 and 332 will be described in detail.

The first gate signal generator 331 may include first to thirteenth transistors T1 to T13.

The first transistor T1 is controlled by the start signal VST and may be connected between the first power source VDD1 maintaining a high voltage and the control terminal of the third transistor T3.

The second transistor T2 may be connected between the second power source VVD2 and the third transistor T3. When the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the second transistor T2 are connected to the second power source VDD2, and thus may operate like a diode.

The third transistor T3 may be turned on by the first power source VDD when the first transistor T1 is turned on by the start signal VST, and between the second transistor T2 and the ground power source VSS. Can be connected to.

The fourth transistor T4 is controlled by a signal applied from the switching unit 360 of the gate control unit 341, can be connected between the Q node and the ground power supply VSS, and is applied from the switching unit 360 When the fourth transistor T4 is turned on by a signal, ground power is applied to the Q node, and the Q node may be discharged.

The fifth transistor T5 is controlled by the third power supply VDD3 and may be connected between the QBo node and the ground power supply VSS.

The second power supply VDD2 and the third power supply VDD3 are signals having opposite logics, for example, when the second power supply VDD2 is a high logic signal, the third power supply VDD3 is When the second power supply VDD2 is a low logic signal, the third power supply VDD3 may be a high logic signal.

The sixth transistor T6 is controlled by the voltage of the QBo node, and may be connected between the Q node and the ground power supply VSS.

The seventh transistor T7 is controlled according to the voltage of the Q node, and may be connected between the terminal to which the first clock signal CLK1 is applied and the eighth transistor T8.

The eighth transistor T8 is controlled by the voltage of the QBo node, and may be connected between the seventh transistor T7 and the ground power VSS.

The ninth transistor T9 may be connected between the seventh transistor T7 and the ground power supply VSS.

The tenth transistor T10 is connected between the Q node and the ground power source VSS, and can be controlled by the QBe node voltage.

The eleventh transistor T11 is controlled by the second power supply VDD2 and may be connected between the QBe node and the ground power supply VSS.

The twelfth transistor T12 may be connected between the third power source VDD3 and the QBe node. In addition, when the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the twelfth transistor T12 are connected to the third power source VDD3, so that they may operate like a diode.

The thirteenth transistor T13 is controlled by the voltage of the Q node and may be connected between the twelfth transistor T12 and the ground power supply VSS.

Second, third, fifth, sixth and eighth transistors (T2, T3, T5, T8) and 12th, 13th, 11th, 11th, and 9th transistors (T12, T13, T11, T9) Is symmetrical to each other, and since the applied second and third power sources VDD2 and VDD3 are opposite to each other, the second and third power sources VDD2 and VDD3 having opposite logics may alternately operate. have.

<Connection of gate control unit>

The connection relationship between the gate controllers 341 and 342 will be described in detail.

Since the first and second gate control units 341 and 342 have the same structure, the first gate control unit 341 will be described.

The first gate control unit 341 may include a first comparison unit 350, a first switching unit 360, and first and second switches S1 and S2, as the first gate line GL1. The output signal can be exported.

The first comparator receives, as an input, a signal of a driving mode control signal (MCS) and a Q node, and a result of whether the signal of the driving mode control signal (MCS) and the Q node is the same logic or a different logical signal is first It can be provided to the switching unit 360.

The first switching unit 360 is connected to the first transistor T1 of the first comparator 350 and the second gate signal generator 322 which is a gate signal generator of the next stage, and outputs the first and second signals. It can be exported to the second switch (S1, S2).

The first switch S1 may be connected between the terminal to which the first clock signal CLK1 is applied and the first gate line GL1, and the second switch S2 may include the first switch S1 and ground power. It can be connected between the (VSS) terminal.

7 is a diagram illustrating a main period operation process of the gate signal generation unit.

6 and 7, VSS is a ground power supply, first and second power supplies, VDD1 and VDD2, are high logic signals, and a third power supply, VDD3 is a low logic signal.

<1st time period (T1)>

During the first time period T1, when the start signal VST is applied in a state in which the first power source VDD1 is supplied, the first transistor T1 is turned on, and accordingly, the signal of high logic is the third transistor T3. ), the third transistor T3 is turned on.

When the third transistor T3 is turned on, a ground voltage may be charged to the QBo node.

As the ground voltage is applied to the QBo node, the sixth and eighth transistors T6 and T8 are turned off.

On the other hand, with the turn-on of the first transistor T1, the Q node is charged with the first power supply VDD1, and the capacitor C is charged with a voltage.

<2nd time period (T2)>

During the second time period T2, when the first clock signal CLK1 becomes high logic, the voltage of the Q node is amplified by the bootstrap, which can be applied to the first comparator 350.

The first comparator 350 may determine whether to supply the scan signal to the first gate line GL1 according to the logic value of the driving mode signal MCS and the voltage of the Q node.

8 is a view for explaining the operation method of the display device of the present invention.

Referring to FIG. 8, as an example, a video area A and a still screen area B are shown in the display area A/A.

In the display device, a case in which a data signal is required to be updated with a moving image is basically described, although a still image is basically displayed.

When the gate signal is applied to the gate line corresponding to the video region A, the thin film transistor of each pixel is turned on to apply a data signal to the data line corresponding to the corresponding gate line.

In the drawing, the gate signals generated by the gate signal generators 331 and 332 corresponding to the first to third gate lines GL1 to GL3 are gated to each gate line according to the high logic driving mode control signal MCS. The signal can be supplied and the data signal can be updated accordingly.

Although the gate signal is generated in the gate signal generators 333, 334, ... corresponding to the gate lines GL4 to GLn corresponding to the still image B, the driving mode control signal MCS has a low logic signal. , The data signal of the still image B is not updated.

The driving mode control signal MCS is generated from a timing control unit, and an input data signal RGB is determined to control a logic value of the driving mode control signal MCS according to whether it is a still screen or a video screen. .

Through this method, the gate signal can be applied differently by dividing the moving image region and the still image region on the display area A/A, and determining the input data to drive the data and the gate drive of the changed region. By not driving the data and gate drive of the unchanged area, power consumption can be reduced, and only the area where the scan signal is supplied to the gate line realizes high-frequency driving, and the area where the scan signal is not supplied is low frequency. By driving, power consumption can be reduced.

In the detailed description of the present invention described above, the present invention has been described with reference to preferred embodiments of the present invention, but those skilled in the art or those skilled in the art will appreciate the invention described in the claims below. It will be understood that various modifications and changes may be made to the present invention without departing from the spirit and technical scope. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Hereinafter, with reference to the drawings of the display device according to an embodiment of the present invention will be described in detail. The embodiments introduced below are provided as examples in order to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. Throughout the specification, the same reference numbers indicate the same components.
2 is a view showing a display device and a driving unit thereof according to an embodiment of the present invention.
Referring to FIG. 2, the display device 100 according to an exemplary embodiment of the present invention includes a panel 210 displaying an image, a timing controller 200 receiving a timing signal from an external system and generating various control signals, Gates and data drivers 310, 320, and 400 that control the panel 210 in response to the control signal may be included.
In the panel 210, n (n is a natural number) gate line GL and a plurality of data lines DL are intersected in a matrix form on a substrate using glass, and a plurality of pixels are defined at the intersection.
Each pixel is provided with a thin film transistor (TFT), a liquid crystal capacitor (Clc), and a storage capacitor (Cst), and all pixels form one display area (A/A).
Areas in which pixels are not defined are divided into non-display areas (N/A).
The timing controller 200 includes an image signal RGB transmitted from an external system, a clock signal DCLK, a horizontal sync signal Hsync, a vertical sync signal Vsync, a data enable signal DE, and a driving mode control signal A signal such as (Mode Control Signal:MCS) may be applied to generate control signals of the gate driver 140 and the data driver 150.
Here, the horizontal synchronization signal (Hsync) is a signal indicating the time it takes to display one horizontal line of the screen, and the vertical synchronization signal (Vsync) is a signal indicating the time it takes to display a screen of one frame, and a data enable signal. (DE) is a signal indicating a period during which the data voltage is supplied to the pixels defined in the panel 210.
In addition, the driving mode control signal MCS is a signal for determining whether to output a scan signal by dividing a video area and a still image area for each area of the display area A/A.
In addition, the timing controller 200 may generate a control signal GCS of the gate drivers 310 and 320 and a control signal DCS of the data driver 400 in synchronization with the input timing signal.
In addition, the timing controller 200 generates a plurality of clock signals CLK 1 to CLK 4 that determine the driving timing of each stage of the gate drivers 310 and 320 and provides them to the gate drivers 310 and 320.
Here, the first to fourth clock signals CLK 1 to CLK4 are signals in which a high period progresses for 2 horizontal periods (2H) and 1 horizontal period (1H) overlaps with each other.
The timing controller 200 sorts and modulates the received image data RGB data in a form that the data driver 400 can process and outputs.
Here, the aligned image data RGBv may be in a form in which a color coordinate correction algorithm for improving image quality is applied.
Two gate driving units 310 and 320 may be provided at both ends of the panel 210 and in the non-display area N/A.
Each gate driver 310, 320 may be formed of a plurality of stages including shift registers.
When the substrate of the panel 210 is manufactured, the gate driving units 310 and 320 may be embedded in a non-display area in a thin-film pattern in a gate-in-panel (GIP) method.
The first and second gate drivers 310 and 320 may include a plurality of gate lines formed on the panel 210 in response to the gate control signal GCS and the driving mode control signal MCS input from the timing controller 200 ( Through GL 1 to GL n), the gate high voltage VGH can be alternately output every 2 horizontal periods (2H).
Here, the output gate high voltage VGH may be maintained for 2 horizontal periods 2H, and the front and rear gate high voltage VGH may overlap for 1 horizontal period 1H.
This is for precharging the gate lines GL 1 to GL n, and more stable pixel charging can be performed when a data voltage is applied.
To this end, first and second clock signals CLK 1 and CLK 2 having 2 horizontal periods 2H are applied to the first gate driver 310, respectively, and the first and second clock drivers 320 are applied to the first gate driver 310. Two clock signals CLK 1 and CLK 2 and one horizontal period 1H overlap, and third and fourth clock signals CLK 2 and CLK 4 having 2 horizontal periods 2H may be applied.
As an example, when the first gate driver 310 outputs the gate high voltage VGH to the n-th gate line GLn, after the first horizontal period 1H, the second gate driver 320 is an n+1th gate The gate high voltage VGH may be output through the line GLn+1.
That is, the first gate driver 310 may provide a gate signal to an odd-numbered gate line, and the second gate driver 320 may provide a gate signal to an even-numbered gate line.
3 is a diagram illustrating a gate driver of a display device according to an exemplary embodiment of the present invention.
Referring to FIG. 3, the gate driver 300 of the display device according to an exemplary embodiment of the present invention includes first and second gate drivers 310 and 320, and the first and second gate drivers 310 and 320 ) Each may include a gate signal generator 330 and a gate controller 340.
Clock signals CLK1, CLK2, CLK3, and CLK4 and power signals VDD and VSS are input to the gate signal generator 330, and may generate and supply a gate signal to the gate controller 340. have.
The gate signal generator 331 located at the top of the gate signal generator 330 may receive a start signal VST to generate a gate signal, and the gate signal generator 332 of the next stage is the front end. The gate signal may be generated by receiving a signal from the gate signal generator 321.
The gate signal generated in this way is input to the gate control unit 340, and the gate control unit 340 may determine whether to output the gater signal according to the signal of the driving mode control signal MCS.
The driving mode control signal (MCS) may be supplied from a timing control unit, and is divided into a still image and a video screen among screens displayed on the panel 210, and in the case of a still screen, becomes a low logic signal and is a video screen. In this case, it becomes a signal of high logic, so that the gate signal is applied only in the region where the video screen appears, and the data signal can be updated accordingly.
4 is a diagram illustrating a first gate driver of a display device according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating an operation of the first gate driver.
Referring to FIG. 4, the first gate driver 310 of the display device according to an exemplary embodiment of the present invention includes a plurality of gate signal generators 331, 332, 333, ..., and the plurality of gate signal generators 331, 332, 333,...) and corresponding gate control parts 341, 342, 343, ....
Each of the gate controllers 341, 342, 343, .... may include an AND gate comparison unit 350, 351, 352, ..., and a switching unit 360, 361, 362,... as a logic circuit.
4 and 5, an operation process of the first gate driver 310 will be described.
<1st time period (T1)>
During the first time period T1, a high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350, and the driving mode control signal MCS is generated. When having high logic, the first comparator 350 may output a high logic signal to the first switching unit 360.
Conversely, a high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350, but when the driving mode control signal MCS has a low logic, the first The comparator 350 may output a low logic signal to the first switching unit 360.
When the first switching unit 360 receives a high logic signal from the first comparator 350, the first switch S1 is turned on, so that the first clock signal CLK1 is the first gate line GL1. ), and at the same time, the second switch S2 may be turned off.
In addition, when the first switching unit 360 receives a low logic signal from the first comparator 350, the first switch S1 is turned off, the second switch S2 is turned on, and the second switching unit 360 is turned on. Signals on one gate line GL1 can be discharged.
<2nd time period (T2)>
During the second time period T2, the first switching unit 360 applies the high logic signal to the first switch S1 when the high logic signal is applied from the first comparison unit 350, and the second A signal of low logic is output to the switch S2.
<3rd time period (T3)>
During the third time period T3, while the high logic clock signal CLK1 is applied to the first switch S1 of the first gate control unit 341, the first switch S1 according to the bootstrap. The Q node rises and may output a gate signal to the first gate line GL1.
<4th time period (T4)>
During the fourth time period T4, a high logic driving mode control signal MCS is applied to the second comparison unit 351 of the second gate control unit 342, and the second gate signal generation unit 332 The second comparison unit 351 outputs a high logic signal to the second switching unit 361 by a high logic signal, and the high logic is operated in the same manner as the operation of the first switching unit 361 described above. The clock signal CLK2 of may be output to the third gate line GL3 through the first switch S1 of the second gate control unit 342 as a gate signal.
<Section 5 (T5)>
During the fifth time period T5, since the driving mode control signal MCS has a low logic, the third comparison unit 352 generates a high logic gate signal and a low logic generated by the third gate signal generation unit 333. By receiving the driving mode control signal (MCS) of the, and provides the output of the low logic to the third switching unit 362, the third switching unit 362 is the first switch (S1) of the third gate control unit 343 ) Is turned off, and the second switch S2 is turned on, so that a gate signal that is a scan signal is not output to the fifth gate line.
Through this operation, since a gate signal is not applied to a specific area of the display area A/A, the data line DL corresponding to the corresponding gate line is not driven and power consumption can be reduced accordingly. .
Further, only the region in which the scan signal is supplied to the gate line realizes high frequency driving, and the region in which the scan signal is not supplied is subjected to low frequency driving, thereby reducing power consumption.
6 is a circuit diagram of a gate driver of a display device according to an exemplary embodiment of the present invention.
Referring to FIG. 6, the gate driver of the display device according to an exemplary embodiment of the present invention may include gate signal generators 331 and 332 and gate controllers 341 and 342.
The first gate signal generator 331 and the second gate signal generator 332 have the same structure.
<Circuit connection of the gate signal generator>
The connection relationship between the gate signal generators 331 and 332 will be described in detail.
The first gate signal generator 331 may include first to thirteenth transistors T1 to T13.
The first transistor T1 is controlled by the start signal VST and may be connected between the first power source VDD1 maintaining a high voltage and the control terminal of the third transistor T3.
The second transistor T2 may be connected between the second power source VVD2 and the third transistor T3. When the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the second transistor T2 are connected to the second power source VDD2, and thus may operate like a diode.
The third transistor T3 may be turned on by the first power source VDD when the first transistor T1 is turned on by the start signal VST, and between the second transistor T2 and the ground power source VSS. Can be connected to.
The fourth transistor T4 is controlled by a signal applied from the switching unit 360 of the gate control unit 341, can be connected between the Q node and the ground power supply VSS, and is applied from the switching unit 360 When the fourth transistor T4 is turned on by a signal, ground power is applied to the Q node, and the Q node may be discharged.
The fifth transistor T5 is controlled by the third power supply VDD3 and may be connected between the QBo node and the ground power supply VSS.
The second power supply VDD2 and the third power supply VDD3 are signals having opposite logics, for example, when the second power supply VDD2 is a high logic signal, the third power supply VDD3 is When the second power supply VDD2 is a low logic signal, the third power supply VDD3 may be a high logic signal.
The sixth transistor T6 is controlled by the voltage of the QBo node, and may be connected between the Q node and the ground power supply VSS.
The seventh transistor T7 is controlled according to the voltage of the Q node, and may be connected between the terminal to which the first clock signal CLK1 is applied and the eighth transistor T8.
The eighth transistor T8 is controlled by the voltage of the QBo node, and may be connected between the seventh transistor T7 and the ground power VSS.
The ninth transistor T9 may be connected between the seventh transistor T7 and the ground power supply VSS.
The tenth transistor T10 is connected between the Q node and the ground power source VSS, and can be controlled by the QBe node voltage.
The eleventh transistor T11 is controlled by the second power supply VDD2 and may be connected between the QBe node and the ground power supply VSS.
The twelfth transistor T12 may be connected between the third power source VDD3 and the QBe node. In addition, when the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the twelfth transistor T12 are connected to the third power source VDD3, so that they may operate like a diode.
The thirteenth transistor T13 is controlled by the voltage of the Q node and may be connected between the twelfth transistor T12 and the ground power supply VSS.
Second, third, fifth, sixth and eighth transistors (T2, T3, T5, T8) and 12th, 13th, 11th, 11th, and 9th transistors (T12, T13, T11, T9) Is symmetrical to each other, and since the applied second and third power sources VDD2 and VDD3 are opposite to each other, the second and third power sources VDD2 and VDD3 having opposite logics may alternately operate. have.
<Connection of gate control unit>
The connection relationship between the gate controllers 341 and 342 will be described in detail.
Since the first and second gate control units 341 and 342 have the same structure, the first gate control unit 341 will be described.
The first gate control unit 341 may include a first comparison unit 350, a first switching unit 360, and first and second switches S1 and S2, as the first gate line GL1. The output signal can be exported.
The first comparator receives, as an input, a signal of a driving mode control signal (MCS) and a Q node, and a result of whether the signal of the driving mode control signal (MCS) and the Q node is the same logic or a different logical signal is first. It can be provided to the switching unit 360.
The first switching unit 360 is connected to the first transistor T1 of the first comparator 350 and the second gate signal generator 322 which is a gate signal generator of the next stage, and outputs the first and second signals. It can be exported to the second switch (S1, S2).
The first switch S1 may be connected between the terminal to which the first clock signal CLK1 is applied and the first gate line GL1, and the second switch S2 may be connected to the first switch S1 and ground power. It can be connected between the (VSS) terminal.
7 is a diagram illustrating a main period operation process of the gate signal generation unit.
6 and 7, VSS is a ground power supply, first and second power supplies, VDD1 and VDD2, are high logic signals, and a third power supply, VDD3 is a low logic signal.
<1st time period (T1)>
During the first time period T1, when the start signal VST is applied in a state in which the first power source VDD1 is supplied, the first transistor T1 is turned on, and accordingly, the signal of high logic is the third transistor T3. ), the third transistor T3 is turned on.
When the third transistor T3 is turned on, a ground voltage may be charged to the QBo node.
As the ground voltage is applied to the QBo node, the sixth and eighth transistors T6 and T8 are turned off.
On the other hand, with the turn-on of the first transistor T1, the Q node is charged with the first power supply VDD1, and the capacitor C is charged with a voltage.
<2nd time period (T2)>
During the second time period T2, when the first clock signal CLK1 becomes high logic, the voltage of the Q node is amplified by the bootstrap, which can be applied to the first comparator 350.
The first comparator 350 may determine whether to supply the scan signal to the first gate line GL1 according to the logic value of the driving mode signal MCS and the voltage of the Q node.
8 is a view for explaining the operation method of the display device of the present invention.
Referring to FIG. 8, as an example, a video area A and a still screen area B are shown in the display area A/A.
In the display device, a case in which a data signal is required to be updated with a moving image is basically described, although a still image is basically displayed.
When the gate signal is applied to the gate line corresponding to the video region A, the thin film transistor of each pixel is turned on to apply a data signal to the data line corresponding to the corresponding gate line.
In the drawing, the gate signals generated by the gate signal generators 331 and 332 corresponding to the first to third gate lines GL1 to GL3 are gated to each gate line according to the high logic driving mode control signal MCS. The signal can be supplied and the data signal can be updated accordingly.
Although the gate signal is generated in the gate signal generators 333, 334, ... corresponding to the gate lines GL4 to GLn corresponding to the still image B, the driving mode control signal MCS has a low logic signal. , The data signal of the still image B is not updated.
The driving mode control signal MCS is generated from a timing control unit, and an input data signal RGB is determined to control a logic value of the driving mode control signal MCS according to whether it is a still screen or a video screen. .
Through this method, the gate signal can be applied differently by dividing the moving image area and the still image area on the display area A/A, and determining the input data to drive the data and the gate drive of the changed area. By not driving the data and gate drive in the unchanged area, power consumption can be reduced, and only the area where the scan signal is supplied to the gate line realizes high-frequency driving, and the area where the scan signal is not supplied is low frequency. By driving, power consumption can be reduced.
In the detailed description of the present invention described above, the present invention has been described with reference to preferred embodiments of the present invention, but those skilled in the art or those skilled in the art will appreciate the invention described in the claims below. It will be understood that various modifications and changes may be made to the present invention without departing from the spirit and technical scope. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

a panel in which n (n is a natural number) gate lines are formed;
A timing control unit generating a clock signal and a driving mode control signal;
A first gate driver applying a gate signal to each of some of the gate lines among the gate lines in response to the clock signal and the driving mode control signal; And
And a second gate driver applying a gate signal to each of the remaining gate lines among the gate lines in response to the clock signal and the driving mode control signal.
The driving mode control signal is a signal having a different logic value according to a still screen or a video screen, and it is determined whether a gate signal is output to each of the gate lines according to the logic value.
A display device in which a gate signal is supplied only to a portion of the gate lines connected to the first gate driver, corresponding to the video screen. According to claim 1,
Each of the first gate driver and the second gate driver includes a gate signal generator and a gate controller,
The gate signal generator outputs a gate signal to the gate controller in response to the clock signal,
The gate control unit determines whether a gate signal is output to the gate line according to a logic value of the driving mode control signal. According to claim 2,
The gate control unit includes a comparison unit composed of an AND gate, a switching unit, and first and second switches controlled according to output signals of the switching unit,
The comparison unit compares the logic value of the output signal from the gate signal generation unit with the logic value of the drive mode control signal, and outputs the corresponding output to the switching unit,
The switching unit turns on one of the first and second switches according to the output value of the comparator, and turns off the other. According to claim 3,
When the first switch is turned on, the clock signal is output to a gate line corresponding to the first switch,
When the second switch is turned on, a display device that discharges a signal of a gate line corresponding to the second switch. According to claim 1,
Among the gate lines, a display device for which a gate signal is not output to the second gate lines among first gate lines corresponding to a video region and second gate lines corresponding to a still image region. a panel in which n (n is a natural number) gate lines are formed;
A timing control unit generating first to fourth clock signals and a driving mode control signal;
A first gate driver configured to apply a gate high logic signal to one side of the odd-numbered gate lines in correspondence with high logic of the first and second clock signals and the drive mode control signal; And
And a second gate driver that applies the gate high logic signal to one side of the even-numbered gate line in correspondence to the high logic of the third and fourth clock signals and the driving mode control signal,
The driving mode control signal is a high logic signal in the video screen,
A display device in which the gate high logic signal is supplied only to a part of the odd numbered gate lines corresponding to a moving picture screen among the odd numbered gate lines connected to the first gate driver. The method of claim 6,
The first to fourth clock signals,
A display device characterized in that each has a high logic signal period of 2 horizontal periods (2H), and 1 horizontal period (1H) overlaps between the front and rear signals. The method of claim 6,
Each of the first and second gate drivers includes a gate signal generator and a gate controller,
The gate signal generation unit outputs a gate signal to the gate control unit corresponding to the first to fourth clock signals,
The gate control unit determines whether a gate signal is output to the gate line according to a logic value of the driving mode control signal. The method of claim 8,
The gate control unit includes a comparison unit composed of an AND gate, a switching unit, and first and second switches controlled according to output signals of the switching unit,
The comparison unit compares the logic value of the output signal from the gate signal generation unit with the logic value of the drive mode control signal, and outputs the corresponding output to the switching unit,
The switching unit turns on one of the first and second switches according to the output value of the comparator, and turns off the other. The method of claim 6,
The timing control unit is a low-frequency driving display device when the still image.

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