KR20150066981A - Display device - Google Patents

Abstract

According to an embodiment of the present invention, a display device divides a video are and a stopped image area in a display area and applies a gate signal differently, determines inputted data and drives data in a changed area and a gate driver, and not drives data in a non-changed area and the gate driver, thereby reducing power consumption. The display device comprises: a panel in which n number (n is a natural number) of gate lines are formed; a timing control unit generating a clock signal and a driving mode control signal; and the gate driver applying the gate signal to each gate line by corresponding to the clock signal and the driving mode control signal, wherein the driving mode control signal is a signal which differentiates a logic value according to a stopped screen or a video screen, and whether the gate signal is outputted or not is determined on each gate line.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device.

2. Description of the Related Art Recently, in the field of electronic information display devices, a flat display device has replaced a conventional cathode ray tube (CRT) display device. Examples of such flat display devices include a liquid crystal display (LCD), a plasma display panel ), A field emission display (FED), and an organic light emitting diode (OLED).

Particularly, an active matrix display device in which a thin film transistor (Thin Film Transistor) is used as a switching device is suitable for displaying dynamic images.

In order to control the turn-on / off operation of the above-described thin film transistor, a typical display device is provided with a gate driver for generating and providing a scan signal, and data for providing a data signal for indicating the gradation of the image A driving unit is provided.

1 is a block diagram showing a basic configuration of a conventional display device.

As shown in the figure, the conventional display device comprises a panel 1 for displaying an image and drivers 4 and 5.

The panel 1 has a structure in which a plurality of gate lines GL and a plurality of data lines DL are crossed in a matrix form on a substrate using a glass and a plurality of pixels are defined at intersections, Thereby displaying an image.

Such a panel 1 is divided into a display area A / A where pixels are formed to implement an image and a non-display area N / A surrounding the display area A / A.

The driving parts (4, 5) include a gate driving part (4) and a data driving part (5).

The gate driver 4 controls turn on / off of the switching elements of the pixels arranged on the panel 1 in response to the gate control signal GCS supplied from the timing controller (not shown) do.

The gate driving unit 4 outputs the gate driving voltage VG to the panel 1 through the gate line GL and sequentially turns on the switching elements of the pixels in a line by line manner so that the data driving circuit 5 to be supplied to the pixel.

The data driver 5 modulates the image data of the digital waveform into a data signal of the analog waveform in response to the data control signal DCS supplied from the timing controller.

Next, the data signal corresponding to one horizontal period is supplied to the panel 1 simultaneously through all the data lines DL every horizontal period, and each pixel displays the gradation of the image.

In the display device having such a structure, the gate driver 4 is relatively simple in structure compared to the data driver 5, and in order to reduce the volume, weight, and manufacturing cost of the display device, Panel gate (Gate) which is fabricated on the non-display area N / A in the form of a thin film transistor when the substrate of the panel 1 is manufactured, -In-Panel, GIP) method has been proposed.

1, the gate driver 4 is embedded in the left and right sides of the panel 10 in a GIP manner, and precharging is performed on the gate lines by setting an overlap interval between the gate driving voltages of the front and rear sides, So that the switching element can be stably turned on via the switching element.

Also, in order to realize a high image quality, a display apparatus has been proposed in which a driving frequency of a display apparatus is applied at 120 Hz or more instead of 60 Hz. However, such a display device has a problem in that power consumption increases with an increase in driving frequency.

Especially, when the moving picture is implemented, the picture quality is improved through the high frequency operation. However, there is a problem that the unnecessary power consumption is increased because the high frequency operation is uniformly performed on the still picture or the screen where the still picture and the moving picture coexist.

According to an embodiment of the present invention, there is provided a display device for distinguishing a moving picture area and a still picture area from each other in a display area and applying different gate signals to each other.

The present invention also provides a display device capable of judging input data to drive data in a changed area and a gate drive, and to save power consumption by not driving data in an unchanged area and a gate drive.

Also, a display device capable of realizing high-frequency driving only in a region where a scan signal is supplied to the gate line and low-frequency driving in an area not supplied with a scan signal can reduce power consumption.

A display device according to an embodiment of the present invention includes a panel in which n (n is a natural number) gate lines are formed; A timing controller for generating a clock signal and a drive mode control signal; And a gate driver for applying a gate signal to each of the gate lines corresponding to the clock signal and the drive mode control signal; Wherein the drive mode control signal is a signal whose logic value differs according to a still image or a moving picture screen, and whether or not a gate signal is output to the gate lines is determined according to a logical value.

The gate driver may include a gate signal generator and a gate controller. The gate signal generator may output a gate signal corresponding to the clock signal to the gate controller, Determines whether or not a gate signal is output to the gate line according to a logical value of the drive mode control signal.

The display apparatus according to an embodiment of the present invention is characterized in that the gate control section includes a comparison section composed of AND gates, a switching section and first and second switches controlled in accordance with the output signal of the switching section, Wherein the comparing unit compares the logical value of the output signal from the generating unit with the logical value of the driving mode control signal and outputs an output according to the logical value of the driving mode control signal to the switching unit, One of which is turned on and the other is turned off.

The display device according to an embodiment of the present invention outputs the clock signal to the gate line corresponding to the first switch when the first switch is turned on and when the second switch is turned on, And discharges the signal of the gate line corresponding to the second switch.

A display device according to an exemplary embodiment of the present invention includes a first gate line corresponding to a moving image area and a second gate line corresponding to a still image area among the gate lines, Display device that is not output.

A display device according to an embodiment of the present invention includes: a panel in which n (n is a natural number) gate lines are formed; A timing controller for generating first to fourth clock signals and a drive mode control signal; A first gate driver for applying a gate high logic signal to one side of the odd gate lines in response to the high logic of the first and second clock signals and the drive mode control signal; And a second gate driver for applying the gate high logic signal to one side of the even-numbered gate line in correspondence with the high logic of the third and fourth clock signals and the drive mode control signal, And the signal is a high logic signal when the moving image is displayed.

In the display device according to the embodiment of the present invention,

And a horizontal period (1H) between the front and rear signals is overlapped with each other.

Each of the first and second gate drivers includes a gate signal generator and a gate controller. The gate signal generator generates a gate signal corresponding to the first through fourth clock signals, To the gate control unit, and the gate control unit determines whether to output a gate signal to the gate line according to a logic value of the drive mode control signal.

The display apparatus according to an embodiment of the present invention is characterized in that the gate control section includes a comparison section composed of AND gates, a switching section and first and second switches controlled in accordance with the output signal of the switching section, Wherein the comparing unit compares the logical value of the output signal from the generating unit with the logical value of the driving mode control signal and outputs an output according to the logical value of the driving mode control signal to the switching unit, One of which is turned on and the other is turned off.

In the display device according to the embodiment of the present invention, the timing control section drives low frequency when the still image is displayed.

A display device according to an embodiment of the present invention includes a display device for distinguishing a moving picture area and a still picture area from each other in a display area and applying gate signals differently to each other, And the gate drive is not driven. Therefore, a display device capable of reducing power consumption is provided. High frequency driving is realized only in a region where a scan signal is supplied to the gate line, A region where the signal is not supplied can provide a display device capable of reducing power consumption by performing low-frequency driving.

1 is a block diagram showing a basic configuration of a conventional display device.
2 is a diagram showing a display device and a driving unit thereof according to an embodiment of the present invention.
3 is a view illustrating a gate driver of a display device according to an embodiment of the present invention.
4 is a diagram illustrating a first gate driver of a display device according to an embodiment of the present invention.
5 is a diagram showing the operation of the first gate driver;
6 is a circuit diagram of a gate driver of a display device according to an embodiment of the present invention;
7 is a diagram showing a main period operation process of the gate signal generator;
8 is a view for explaining an operation method of the display device of the present invention.

Hereinafter, the display device according to the embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

2 is a diagram illustrating a display device and a driving unit thereof according to an embodiment of the present invention.

Referring to FIG. 2, a display device 100 according to an embodiment of the present invention includes a panel 210 for displaying an image, a timing controller 200 for receiving various timing signals from an external system and generating various control signals, And a gate and a data driver 310, 320, and 400 for controlling the panel 210 in response to a control signal.

The panel 210 crosses n (n is a natural number) gate lines GL and a plurality of data lines DL in a matrix form on a substrate using a glass, and defines a plurality of pixels at intersections.

Each pixel is provided with a thin film transistor (TFT), a liquid crystal capacitor Clc and a storage capacitor Cst, and all the pixels form one display area A / A.

A region where pixels are not defined is divided into a non-display region (N / A).

The timing controller 200 receives a video signal RGB transmitted from an external system and a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable signal DE, And a mode control signal (MCS) to generate control signals for the gate driving unit 140 and the data driving unit 150.

Here, the horizontal synchronization signal Hsync is a signal indicating the time taken to display one horizontal line of the screen, the vertical synchronization signal Vsync is a signal indicating the time taken to display a frame of one frame, (DE) is a signal indicating a period of supplying the data voltage to the pixel defined in the panel 210. [

The driving mode control signal MCS is a signal for determining whether to output a scan signal by dividing the moving image area and the still image area by the area of the display area A / A.

The timing controller 200 may generate the control signals GCS of the gate drivers 310 and 320 and the control signal DCS of the data driver 400 in synchronization with the input timing signals.

The timing controller 200 generates a plurality of clock signals CLK 1 to CLK 4 for determining the driving timings of the stages of the gate drivers 310 and 320 and supplies them to the gate drivers 310 and 320.

Here, the first to fourth clock signals CLK 1 to CLK 4 are signals in which a high period is performed for two horizontal periods (2H), and one horizontal period (1H) is overlapped with each other.

The timing controller 200 arranges and modulates the received image data (RGB DATA) in a form that can be processed by the data driver 400, and outputs the modulated RGB data.

Here, the aligned image data RGBv may be a color coordinate correction algorithm for improving image quality.

Two gate drivers 310 and 320 may be provided at both ends of the panel 210 and in the non-display area N / A.

Each of the gate drivers 310 and 320 may include a plurality of stages including shift registers.

The gate driving units 310 and 320 may be incorporated in a gate-in-panel (GIP) manner on a non-display area in the form of a thin film pattern when the panel 210 is manufactured.

The first and second gate drivers 310 and 320 are connected to a plurality of gate lines (not shown) formed in the panel 210 in response to a gate control signal GCS and a driving mode control signal MCS input from the timing controller 200. [ The gate high voltage VGH may alternately be outputted for every two horizontal periods 2H through GL 1 to GL n.

Here, the output gate high voltage VGH is held for two horizontal periods (2H), and the front gate and the gate high voltage (VGH) can be overlapped for one horizontal period (1H).

This is for precharging the gate lines GL1 to GLn, and it is possible to more stably charge the pixel when the data voltage is applied.

The first and second clock signals CLK 1 and CLK 2 having two horizontal periods 2H are applied to the first gate driver 310 and the first and second clock signals CLK 1 and CLK 2 are applied to the second gate driver 320, The third and fourth clock signals CLK 2 and CLK 4 having two horizontal periods 2H are overlapped and one horizontal period 1H is overlapped with the two clock signals CLK 1 and CLK 2.

For example, when the first gate driver 310 outputs the gate high voltage VGH to the n-th gate line GLn, the second gate driver 320 supplies the (n + 1) -th gate And can output the gate high voltage VGH to the line GLn + 1.

That is, the first gate driver 310 may provide a gate signal to odd gate lines, and the second gate driver 320 may provide gate signals to even gate lines.

3 is a view illustrating a gate driver of a display device according to an embodiment of the present invention.

3, the gate driver 300 of the display device according to the exemplary embodiment of the present invention includes first and second gate drivers 310 and 320, and the first and second gate drivers 310 and 320 May include a gate signal generator 330 and a gate controller 340.

The gate signal generator 330 receives the clock signals CLK1, CLK2, CLK3 and CLK4 and the power supply signals VDD and VSS and generates a gate signal to supply the gate signal to the gate controller 340 have.

The gate signal generating unit 331 located at the uppermost one of the gate signal generating units 330 can receive the start signal VST and generate a gate signal, It is possible to generate a gate signal by receiving a signal from the gate signal generation unit 321 of FIG.

The gate signal generated in this manner is input to the gate control unit 340, and the gate control unit 340 can determine whether to output the gate signal according to the signal of the drive mode control signal MCS.

The driving mode control signal MCS can be supplied from the timing control unit and distinguishes the still picture from the moving picture picture on the screen displayed on the panel 210. If the still picture is a still picture, The gate signal is applied only in the region where the moving picture screen is displayed and the data signal can be updated accordingly.

FIG. 4 is a diagram illustrating a first gate driver of a display device according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating an operation of a first gate driver. Referring to FIG.

Referring to FIG. 4, the first gate driver 310 of the display device according to the exemplary embodiment of the present invention includes a plurality of gate signal generators 331, 332, 333, ... and a plurality of gate signal generators 331, 332, 333, ..., and corresponding gate control units 341, 342, 343,.

Each of the gate control units 341, 342, 343, ... may include logic units such as AND gates comparators 350, 351, 352, ... and switching units 360, 361, 362,.

The operation of the first gate driver 310 will be described with reference to FIGS. 4 and 5. FIG.

≪ First Time Zone (T1) >

A high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350 during the first time period T1 and the drive mode control signal MCS The first comparator 350 may output the high logic signal to the first switching unit 360. [

On the other hand, when a high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350 but the drive mode control signal MCS has low logic, The comparing unit 350 may output the low logic signal to the first switching unit 360. [

When the first switching unit 360 receives the high logic signal from the first comparator 350, the first switch S1 is turned on and the first clock signal CLK1 is supplied to the first gate line GL1 , And can be turned off to the second switch S2.

When the first switching unit 360 receives a low logic signal from the first comparator 350, the first switch S1 is turned off, the second switch S2 is turned on, 1 to discharge the signal on the gate line GL1.

≪ Second time zone (T2) >

During the second time period T2, the first switching unit 360 applies a high logic signal to the first switch S1 when the high logic signal is applied from the first comparator 350, And outputs a low logic signal to the switch S2.

≪ Third time zone (T3) >

The clock signal CLK1 of high logic is applied to the first switch S1 of the first gate control unit 341 during the third time period T3 and the clock signal CLK1 of the high logic is applied to the first switch S1 of the first switch S1 according to the bootstrap. The Q node rises and can output the gate signal to the first gate line GL1.

≪ Fourth time zone (T4) >

The drive mode control signal MCS of the high logic is applied to the second comparator 351 of the second gate control unit 342 during the fourth time period T4, The second comparator 351 outputs a high logic signal to the second switching unit 361 by the high logic signal and in a manner similar to the operation of the first switching unit 361 described above, The clock signal CLK2 of the second gate control unit 342 may be output as the gate signal to the third gate line GL3 through the first switch S1 of the second gate control unit 342. [

≪ 5th time zone (T5) >

The third comparator 352 compares the gate signal of the high logic generated in the third gate signal generator 333 with the gate signal of the low logic generated in the third gate signal generator 333 because the drive mode control signal MCS has the logic low during the fifth time period T5, The third switching unit 362 receives the drive mode control signal MCS of the third gate control unit 343 and the output of the low logic to the third switching unit 362, , The second switch S2 is turned on, and the gate signal which is the scan signal is not outputted to the fifth gate line.

Through such operation, since the gate signal is not applied to the specific region of the display area A / A, the data line DL corresponding to the gate line is not driven, and the power consumption can be reduced accordingly .

Also, the power consumption can be reduced by realizing high-frequency driving only in a region where a scan signal is supplied to the gate line and low-frequency driving in a region where no scan signal is supplied.

6 is a circuit diagram of a gate driver of a display device according to an embodiment of the present invention.

Referring to FIG. 6, the gate driver of the display apparatus according to the embodiment of the present invention may include gate control units 341 and 342 of the gate signal generators 331 and 332.

The first gate signal generator 331 and the second gate signal generator 332 have the same structure.

≪ Connection relation of circuit of gate signal generating section >

The connection relationship of the gate signal generators 331 and 332 will be described in detail.

The first gate signal generator 331 may include first to thirteenth transistors T1 to T13.

The first transistor T1 is controlled by the start signal VST and may be connected between the first power source VDD1 that maintains a high voltage and the control terminal of the third transistor T3.

The second transistor T2 may be connected between the second power source VVD2 and the third transistor T3. When the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the second transistor T2 may be connected to the second power source VDD2 to operate as a diode.

The third transistor T3 may be turned on by the first power source VDD when the first transistor T1 is turned on by the start signal VST and may be turned on by the first transistor T3 between the second transistor T2 and the ground power source VSS Lt; / RTI >

The fourth transistor T4 is controlled by a signal applied from the switching unit 360 of the gate control unit 341 and can be connected between the Q node and the ground power supply VSS, When the fourth transistor T4 is turned on by a signal, ground power is applied to the Q node, so that the Q node can be discharged.

The fifth transistor T5 is controlled by the third power source VDD3 and may be connected between the QBo node and the ground power source VSS.

For example, when the second power source VDD2 is a high logic signal, the third power source VDD3 is a signal having a logic opposite to that of the second power source VDD2 and the third power source VDD3. And the third power source VDD3 may be a signal of high logic when the second power source VDD2 is a signal of low logic.

The sixth transistor T6 is controlled by the voltage of the QBo node and can be connected between the Q node and the ground power supply VSS.

The seventh transistor T7 is controlled according to the voltage of the Q node and may be connected between the terminal to which the first clock signal CLK1 is applied and the eighth transistor T8.

The eighth transistor T8 may be controlled by the voltage of the QBo node and may be connected between the seventh transistor T7 and the ground terminal VSS.

The ninth transistor T9 may be connected between the seventh transistor T7 and the ground power supply VSS.

The tenth transistor T10 is connected between the Q node and the ground power supply VSS and can be controlled by the QBe node voltage.

The eleventh transistor T11 is controlled by the second power source VDD2 and may be connected between the QBe node and the ground power source VSS.

The twelfth transistor T12 may be connected between the third power source VDD3 and the QBe node. When the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the twelfth transistor T12 may be connected to the third power supply VDD3 to operate as a diode.

The thirteenth transistor T13 may be controlled by the voltage of the Q node and may be connected between the twelfth transistor T12 and the ground power supply VSS.

Thirteenth, eleventh, eleventh, and ninth transistors T12, T13, T11, and T9 are coupled to the first, second, third, fifth, sixth and eighth transistors T2, T3, T5, T8, The second and third power sources VDD2 and VDD3 are opposite to each other and can be alternately operated by the second and third power sources VDD2 and VDD3 having opposite logic have.

 ≪ Connection relation of gate control unit >

The connection relations of the gate control units 341 and 342 will be described in detail.

Since the first and second gate control units 341 and 342 have the same structure, the first gate control unit 341 will be mainly described.

The first gate control unit 341 may include a first comparator 350 and a first switch 360 and first and second switches S1 and S2 and may be connected to the first gate line GL1 Output signals can be exported.

The first comparator receives as inputs the driving mode control signal MCS and the signal of the Q node and outputs a result according to whether the driving mode control signal MCS and the signal of the Q node are either the same logic or different logic signals, And may be provided to the switching unit 360.

The first switching unit 360 is connected to the first comparator 350 and the first transistor T1 of the second gate signal generator 322 which is the gate signal generator of the next stage, And can be outputted to the second switches S1 and S2.

The first switch S1 may be connected between the terminal to which the first clock signal CLK1 is applied and the first gate line GL1 and the second switch S2 may be connected between the first switch S1 and the ground power source (VSS) terminal.

FIG. 7 is a diagram illustrating an operation procedure of the gate signal generation unit during one week.

6 and 7, VSS is a ground power source, the first and second power sources VDD1 and VDD2 are high logic signals, and the third power source VDD3 is a low logic signal.

≪ First Time Zone (T1) >

During the first time period T1, when the start signal VST is applied while the first power source VDD1 is supplied, the first transistor T1 is turned on, so that the high logic signal is supplied to the third transistor T3 , And the third transistor T3 is turned on.

When the third transistor T3 is turned on, the ground voltage can be charged to the QBo node.

The sixth and eighth transistors T6 and T8 are turned off while a ground voltage is applied to the QBo node.

On the other hand, when the first transistor T1 is turned on, the Q node is charged with the first power source VDD1, and the capacitor C is charged with the voltage.

≪ Second time zone (T2) >

During the second time interval T2, when the first clock signal CLK1 becomes high logic, the voltage at the Q node is boosted by bootstrapping, which can be applied to the first comparator 350. [

The first comparator 350 may determine whether to supply the scan signal to the first gate line GL1 according to the logic value of the drive mode signal MCS and the logic value of the voltage of the Q node.

FIG. 8 is a diagram for explaining an operation method of the display apparatus of the present invention.

Referring to FIG. 8, for example, the moving picture area A and the still picture area B are displayed in the display area A / A.

In the display device, a case where a still image is displayed basically but only a partial area such as a clock needs updating of a data signal as a moving image will be described.

When a gate signal is applied to a gate line corresponding to the moving picture area A, a thin film transistor of each pixel is turned on and a data signal is applied to a data line corresponding to the gate line.

The gate signals generated by the gate signal generators 331 and 332 corresponding to the first to third gate lines GL1 to GL3 in the drawing are applied to the respective gate lines in accordance with the drive mode control signal (MCS) A signal can be supplied, and the data signal can be updated accordingly.

Even if a gate signal is generated in the gate signal generating units 333, 334, ... corresponding to the gate lines GL4 to GLn corresponding to the still picture B, since the drive mode control signal MCS has a low logic signal , The data signal of the still picture B is not updated.

The driving mode control signal MCS may be generated from the timing control unit to discriminate the input data signal RGB and may control the logic value of the driving mode control signal MCS according to whether it is a still image or a moving image .

In this manner, the moving picture area and the still picture area on the display area A / A can be distinguished from each other and the gate signal can be applied differently. The input data is determined, , The power consumption can be reduced because the data and the gate drive of the unchanged region are not driven and only the region where the scan signal is supplied to the gate line realizes the high frequency drive and the region where the scan signal is not supplied is the low frequency By driving, the power consumption can be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Hereinafter, the display device according to the embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.
2 is a diagram illustrating a display device and a driving unit thereof according to an embodiment of the present invention.
Referring to FIG. 2, a display device 100 according to an embodiment of the present invention includes a panel 210 for displaying an image, a timing controller 200 for receiving various timing signals from an external system and generating various control signals, And a gate and a data driver 310, 320, and 400 for controlling the panel 210 in response to a control signal.
The panel 210 crosses n (n is a natural number) gate lines GL and a plurality of data lines DL in a matrix form on a substrate using a glass, and defines a plurality of pixels at intersections.
Each pixel is provided with a thin film transistor (TFT), a liquid crystal capacitor Clc and a storage capacitor Cst, and all the pixels form one display area A / A.
A region where pixels are not defined is divided into a non-display region (N / A).
The timing controller 200 receives a video signal RGB transmitted from an external system and a clock signal DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable signal DE, And a mode control signal (MCS) to generate control signals for the gate driving unit 140 and the data driving unit 150.
Here, the horizontal synchronization signal Hsync is a signal indicating the time taken to display one horizontal line of the screen, the vertical synchronization signal Vsync is a signal indicating the time taken to display a frame of one frame, (DE) is a signal indicating a period of supplying the data voltage to the pixel defined in the panel 210. [
The driving mode control signal MCS is a signal for determining whether to output a scan signal by dividing the moving image area and the still image area by the area of the display area A / A.
The timing controller 200 may generate the control signals GCS of the gate drivers 310 and 320 and the control signal DCS of the data driver 400 in synchronization with the input timing signals.
The timing controller 200 generates a plurality of clock signals CLK 1 to CLK 4 for determining the driving timings of the stages of the gate drivers 310 and 320 and supplies them to the gate drivers 310 and 320.
Here, the first to fourth clock signals CLK 1 to CLK 4 are signals in which a high period is performed for two horizontal periods (2H), and one horizontal period (1H) is overlapped with each other.
The timing controller 200 arranges and modulates the received image data (RGB DATA) in a form that can be processed by the data driver 400, and outputs the modulated RGB data.
Here, the aligned image data RGBv may be a color coordinate correction algorithm for improving image quality.
Two gate drivers 310 and 320 may be provided at both ends of the panel 210 and in the non-display area N / A.
Each of the gate drivers 310 and 320 may include a plurality of stages including shift registers.
The gate driving units 310 and 320 may be incorporated in a gate-in-panel (GIP) manner on a non-display area in the form of a thin film pattern when the panel 210 is manufactured.
The first and second gate drivers 310 and 320 are connected to a plurality of gate lines (not shown) formed in the panel 210 in response to a gate control signal GCS and a driving mode control signal MCS input from the timing controller 200. [ The gate high voltage VGH may alternately be outputted for every two horizontal periods 2H through GL 1 to GL n.
Here, the output gate high voltage VGH is held for two horizontal periods (2H), and the front gate and the gate high voltage (VGH) can be overlapped for one horizontal period (1H).
This is for precharging the gate lines GL1 to GLn, and it is possible to more stably charge the pixel when the data voltage is applied.
The first and second clock signals CLK 1 and CLK 2 having two horizontal periods 2H are applied to the first gate driver 310 and the first and second clock signals CLK 1 and CLK 2 are applied to the second gate driver 320, The third and fourth clock signals CLK 2 and CLK 4 having two horizontal periods 2H are overlapped and one horizontal period 1H is overlapped with the two clock signals CLK 1 and CLK 2.
For example, when the first gate driver 310 outputs the gate high voltage VGH to the n-th gate line GLn, the second gate driver 320 supplies the (n + 1) -th gate And can output the gate high voltage VGH to the line GLn + 1.
That is, the first gate driver 310 may provide a gate signal to odd gate lines, and the second gate driver 320 may provide gate signals to even gate lines.
3 is a view illustrating a gate driver of a display device according to an embodiment of the present invention.
3, the gate driver 300 of the display device according to the exemplary embodiment of the present invention includes first and second gate drivers 310 and 320, and the first and second gate drivers 310 and 320 May include a gate signal generator 330 and a gate controller 340.
The gate signal generator 330 receives the clock signals CLK1, CLK2, CLK3 and CLK4 and the power supply signals VDD and VSS and generates a gate signal to supply the gate signal to the gate controller 340 have.
The gate signal generating unit 331 located at the uppermost one of the gate signal generating units 330 can receive the start signal VST and generate a gate signal, It is possible to generate a gate signal by receiving a signal from the gate signal generation unit 321 of FIG.
The gate signal generated in this manner is input to the gate control unit 340, and the gate control unit 340 can determine whether to output the gate signal according to the signal of the drive mode control signal MCS.
The driving mode control signal MCS can be supplied from the timing control unit and distinguishes the still picture from the moving picture picture on the screen displayed on the panel 210. If the still picture is a still picture, The gate signal is applied only in the region where the moving picture screen is displayed and the data signal can be updated accordingly.
FIG. 4 is a diagram illustrating a first gate driver of a display device according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating an operation of a first gate driver. Referring to FIG.
Referring to FIG. 4, the first gate driver 310 of the display device according to the exemplary embodiment of the present invention includes a plurality of gate signal generators 331, 332, 333, ... and a plurality of gate signal generators 331, 332, 333, ..., and corresponding gate control units 341, 342, 343,.
Each of the gate control units 341, 342, 343, ... may include logic units such as AND gates comparators 350, 351, 352, ... and switching units 360, 361, 362,.
The operation of the first gate driver 310 will be described with reference to FIGS. 4 and 5. FIG.
≪ First Time Zone (T1) >
A high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350 during the first time period T1 and the drive mode control signal MCS The first comparator 350 may output the high logic signal to the first switching unit 360. [
On the other hand, when a high gate signal (scan signal) is output from the first gate signal generator 331 to the first comparator 350 but the drive mode control signal MCS has low logic, The comparing unit 350 may output the low logic signal to the first switching unit 360. [
When the first switching unit 360 receives the high logic signal from the first comparator 350, the first switch S1 is turned on and the first clock signal CLK1 is supplied to the first gate line GL1 , And can be turned off to the second switch S2.
When the first switching unit 360 receives a low logic signal from the first comparator 350, the first switch S1 is turned off, the second switch S2 is turned on, 1 to discharge the signal on the gate line GL1.
≪ Second time zone (T2) >
During the second time period T2, the first switching unit 360 applies a high logic signal to the first switch S1 when the high logic signal is applied from the first comparator 350, And outputs a low logic signal to the switch S2.
≪ Third time zone (T3) >
The clock signal CLK1 of high logic is applied to the first switch S1 of the first gate control unit 341 during the third time period T3 and the clock signal CLK1 of the high logic is applied to the first switch S1 of the first switch S1 according to the bootstrap. The Q node rises and can output the gate signal to the first gate line GL1.
≪ Fourth time zone (T4) >
The drive mode control signal MCS of the high logic is applied to the second comparator 351 of the second gate control unit 342 during the fourth time period T4, The second comparator 351 outputs a high logic signal to the second switching unit 361 by the high logic signal and in a manner similar to the operation of the first switching unit 361 described above, The clock signal CLK2 of the second gate control unit 342 may be output as the gate signal to the third gate line GL3 through the first switch S1 of the second gate control unit 342. [
≪ 5th time zone (T5) >
The third comparator 352 compares the gate signal of the high logic generated in the third gate signal generator 333 with the gate signal of the low logic generated in the third gate signal generator 333 because the drive mode control signal MCS has the logic low during the fifth time period T5, The third switching unit 362 receives the drive mode control signal MCS of the third gate control unit 343 and the output of the low logic to the third switching unit 362, , The second switch S2 is turned on, and the gate signal which is the scan signal is not outputted to the fifth gate line.
Through such operation, since the gate signal is not applied to the specific region of the display area A / A, the data line DL corresponding to the gate line is not driven, and the power consumption can be reduced accordingly .
Also, the power consumption can be reduced by realizing high-frequency driving only in a region where a scan signal is supplied to the gate line and low-frequency driving in a region where no scan signal is supplied.
6 is a circuit diagram of a gate driver of a display device according to an embodiment of the present invention.
Referring to FIG. 6, the gate driver of the display apparatus according to the embodiment of the present invention may include gate control units 341 and 342 of the gate signal generators 331 and 332.
The first gate signal generator 331 and the second gate signal generator 332 have the same structure.
≪ Connection relation of circuit of gate signal generating section >
The connection relationship of the gate signal generators 331 and 332 will be described in detail.
The first gate signal generator 331 may include first to thirteenth transistors T1 to T13.
The first transistor T1 is controlled by the start signal VST and may be connected between the first power source VDD1 that maintains a high voltage and the control terminal of the third transistor T3.
The second transistor T2 may be connected between the second power source VVD2 and the third transistor T3. When the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the second transistor T2 may be connected to the second power source VDD2 to operate as a diode.
The third transistor T3 may be turned on by the first power source VDD when the first transistor T1 is turned on by the start signal VST and may be turned on by the first transistor T3 between the second transistor T2 and the ground power source VSS Lt; / RTI >
The fourth transistor T4 is controlled by a signal applied from the switching unit 360 of the gate control unit 341 and can be connected between the Q node and the ground power supply VSS, When the fourth transistor T4 is turned on by a signal, ground power is applied to the Q node, so that the Q node can be discharged.
The fifth transistor T5 is controlled by the third power source VDD3 and may be connected between the QBo node and the ground power source VSS.
For example, when the second power source VDD2 is a high logic signal, the third power source VDD3 is a signal having a logic opposite to that of the second power source VDD2 and the third power source VDD3. And the third power source VDD3 may be a signal of high logic when the second power source VDD2 is a signal of low logic.
The sixth transistor T6 is controlled by the voltage of the QBo node and can be connected between the Q node and the ground power supply VSS.
The seventh transistor T7 is controlled according to the voltage of the Q node and may be connected between the terminal to which the first clock signal CLK1 is applied and the eighth transistor T8.
The eighth transistor T8 may be controlled by the voltage of the QBo node and may be connected between the seventh transistor T7 and the ground terminal VSS.
The ninth transistor T9 may be connected between the seventh transistor T7 and the ground power supply VSS.
The tenth transistor T10 is connected between the Q node and the ground power supply VSS and can be controlled by the QBe node voltage.
The eleventh transistor T11 is controlled by the second power source VDD2 and may be connected between the QBe node and the ground power source VSS.
The twelfth transistor T12 may be connected between the third power source VDD3 and the QBe node. When the illustrated transistor is a MOSFET, the gate terminal and the drain terminal of the twelfth transistor T12 may be connected to the third power supply VDD3 to operate as a diode.
The thirteenth transistor T13 may be controlled by the voltage of the Q node and may be connected between the twelfth transistor T12 and the ground power supply VSS.
Thirteenth, eleventh, eleventh, and ninth transistors T12, T13, T11, and T9 are coupled to the first, second, third, fifth, sixth and eighth transistors T2, T3, T5, T8, The second and third power sources VDD2 and VDD3 are opposite to each other and can be alternately operated by the second and third power sources VDD2 and VDD3 having opposite logic have.
≪ Connection relation of gate control unit >
The connection relations of the gate control units 341 and 342 will be described in detail.
Since the first and second gate control units 341 and 342 have the same structure, the first gate control unit 341 will be mainly described.
The first gate control unit 341 may include a first comparator 350 and a first switch 360 and first and second switches S1 and S2 and may be connected to the first gate line GL1 Output signals can be exported.
The first comparator receives as inputs the driving mode control signal MCS and the signal of the Q node and outputs a result according to whether the driving mode control signal MCS and the signal of the Q node are either the same logic or different logic signals, And may be provided to the switching unit 360.
The first switching unit 360 is connected to the first comparator 350 and the first transistor T1 of the second gate signal generator 322 which is the gate signal generator of the next stage, And can be outputted to the second switches S1 and S2.
The first switch S1 may be connected between the terminal to which the first clock signal CLK1 is applied and the first gate line GL1 and the second switch S2 may be connected between the first switch S1 and the ground power source (VSS) terminal.
FIG. 7 is a diagram illustrating an operation procedure of the gate signal generation unit during one week.
6 and 7, VSS is a ground power source, the first and second power sources VDD1 and VDD2 are high logic signals, and the third power source VDD3 is a low logic signal.
≪ First Time Zone (T1) >
During the first time period T1, when the start signal VST is applied while the first power source VDD1 is supplied, the first transistor T1 is turned on, so that the high logic signal is supplied to the third transistor T3 , And the third transistor T3 is turned on.
When the third transistor T3 is turned on, the ground voltage can be charged to the QBo node.
The sixth and eighth transistors T6 and T8 are turned off while a ground voltage is applied to the QBo node.
On the other hand, when the first transistor T1 is turned on, the Q node is charged with the first power source VDD1, and the capacitor C is charged with the voltage.
≪ Second time zone (T2) >
During the second time interval T2, when the first clock signal CLK1 becomes high logic, the voltage at the Q node is boosted by bootstrapping, which can be applied to the first comparator 350. [
The first comparator 350 may determine whether to supply the scan signal to the first gate line GL1 according to the logic value of the drive mode signal MCS and the logic value of the voltage of the Q node.
FIG. 8 is a diagram for explaining an operation method of the display apparatus of the present invention.
Referring to FIG. 8, for example, the moving picture area A and the still picture area B are displayed in the display area A / A.
In the display device, a case where a still image is displayed basically but only a partial area such as a clock needs updating of a data signal as a moving image will be described.
When a gate signal is applied to a gate line corresponding to the moving picture area A, a thin film transistor of each pixel is turned on and a data signal is applied to a data line corresponding to the gate line.
The gate signals generated by the gate signal generators 331 and 332 corresponding to the first to third gate lines GL1 to GL3 in the drawing are applied to the respective gate lines in accordance with the drive mode control signal (MCS) A signal can be supplied, and the data signal can be updated accordingly.
Even if a gate signal is generated in the gate signal generating units 333, 334, ... corresponding to the gate lines GL4 to GLn corresponding to the still picture B, since the drive mode control signal MCS has a low logic signal , The data signal of the still picture B is not updated.
The driving mode control signal MCS may be generated from the timing control unit to discriminate the input data signal RGB and may control the logic value of the driving mode control signal MCS according to whether it is a still image or a moving image .
In this manner, the moving picture area and the still picture area on the display area A / A can be distinguished from each other and the gate signal can be applied differently. The input data is determined, , The power consumption can be reduced because the data and the gate drive of the unchanged region are not driven and only the region where the scan signal is supplied to the gate line realizes the high frequency drive and the region where the scan signal is not supplied is the low frequency By driving, the power consumption can be reduced.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

(n is a natural number) gate lines;
A timing controller for generating a clock signal and a drive mode control signal; And
A gate driver for applying a gate signal to each of the gate lines corresponding to the clock signal and the drive mode control signal; Lt; / RTI >
Wherein the drive mode control signal is a signal whose logic value changes according to a still image or a moving picture screen, and whether or not a gate signal is output to the gate lines is determined according to a logic value. The method according to claim 1,
Wherein the gate driver includes a gate signal generator and a gate controller,
Wherein the gate signal generator outputs a gate signal to the gate controller in response to the clock signal,
Wherein the gate control unit determines whether to output a gate signal to the gate line according to a logic value of the drive mode control signal. 3. The method of claim 2,
Wherein the gate control unit includes a comparator configured by an AND gate, a switching unit, and first and second switches controlled according to an output signal of the switching unit,
Wherein the comparator compares the logic value of the output signal from the gate signal generator with the logic value of the drive mode control signal and outputs an output according to the logic value to the switching unit,
Wherein the switching unit turns on one of the first and second switches and turns off the other one according to an output value of the comparing unit. The method of claim 3,
And outputs the clock signal to the gate line corresponding to the first switch when the first switch is turned on,
And discharges a signal of a gate line corresponding to the second switch when the second switch is turned on. The method according to claim 1,
Wherein gate signals are not output to the second gate lines among the first gate lines corresponding to the moving picture area and the second gate lines corresponding to the still picture area among the gate lines. (n is a natural number) gate lines;
A timing controller for generating first to fourth clock signals and a drive mode control signal;
A first gate driver for applying a gate high logic signal to one side of the odd gate lines in response to the high logic of the first and second clock signals and the drive mode control signal; And
And a second gate driver for applying the gate high logic signal to one side of the even-numbered gate line in response to the high logic of the third and fourth clock signals and the drive mode control signal,
And the drive mode control signal is a logic high signal when the moving image is displayed. The method according to claim 6,
Wherein the first to fourth clock signals include:
And a horizontal period (1H) between the front and rear signals is overlapped with each other. The method according to claim 6,
Wherein each of the first and second gate drivers includes a gate signal generator and a gate controller,
Wherein the gate signal generator outputs a gate signal to the gate controller in response to the first to fourth clock signals,
Wherein the gate control unit determines whether to output a gate signal to the gate line according to a logic value of the drive mode control signal. 9. The method of claim 8,
Wherein the gate control unit includes a comparator configured by an AND gate, a switching unit, and first and second switches controlled according to an output signal of the switching unit,
Wherein the comparator compares the logic value of the output signal from the gate signal generator with the logic value of the drive mode control signal and outputs an output according to the logic value to the switching unit,
Wherein the switching unit turns on one of the first and second switches and turns off the other one according to an output value of the comparing unit. The method according to claim 6,
Wherein the timing control unit is driven at a low frequency in a still picture.

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