KR20090006997A - A display device - Google Patents

Abstract

A display device capable of enhancing image quality by maintaining target voltage of pixel is provided to improve image quality at still image and moving image by differently driving gate line according to kind of image. A data driver(502) supplies a data signal to a display part(500) displaying an image. A gate driver(501) supplies at least 2 kind of scan pulse to the display part. The display part includes a plurality of gate lines(GL1-GLn), a plurality of data lines(DL1-DLm), and a pixel(PXL). Each pixel includes a thin film transistor, a pixel electrode, a common electrode, and a liquid crystal cell. The thin film transistor switches a data signal. The pixel electrode receives a switched data signal. The common electrode receives a common voltage. The liquid crystal cell controls a light transmission. At least 2 kind of scan pulse outputted from the gate driver is supplied to each gate line. A data signal outputted from the data driver is supplied to each data line.

Description

Display device {A display device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device capable of improving the charging characteristic of a pixel and improving image quality by driving a gate line differently according to an attribute of an image.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by vertical crossings of the gate lines and the data lines. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

Each of the pixel electrodes is connected to the data line via a source terminal and a drain terminal of a thin film transistor (TFT) which is a switching element. The thin film transistor is turned on by a gate on voltage applied to the gate terminal via the gate line, so that the data signal of the data line is charged to the pixel electrode.

The driving circuit may include a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for supplying a control signal for controlling the gate driver and the data driver, and a liquid crystal display device. It is provided with a power supply for supplying a variety of driving voltages used in.

The gate driver sequentially supplies scan pulses to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a data signal to each of the data lines whenever a scan pulse is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to a data signal for each pixel.

Here, the gate driver includes a shift register to sequentially output the scan pulses as described above.

The shift register sequentially outputs the scan pulses and sequentially supplies the scan pulses to the gate lines, thereby sequentially driving the gate lines.

On the other hand, as the liquid crystal display becomes larger, the length of the gate line also becomes longer. As the length of the gate line increases, the resistance and capacitance components of the gate line also increase. Then, the scan pulse supplied to the gate line by the resistance and capacitance components may be distorted. If the scan pulse is distorted by the resistance and capacitance components, the rise time of the scan pulse is increased and the waveform thereof is distorted. Since the distorted scan pulse has a longer rise time than the ideal scan pulse, the effective charge time maintained at the target voltage is relatively short. When the scan pulse whose waveform is distorted is applied to the gate electrode of the thin film transistor, the turn-on time of the thin film transistor is shortened, so that the turned-on thin film transistor receives the data voltage from the data line. The switching time is also shortened.

As a result, the charging time of the data signal supplied to the pixel is shortened, thereby making it difficult to maintain the pixel at the target voltage within the effective period, thereby causing a problem of deterioration in image quality.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by precharging before the pixel is fully charged, the pixel can be maintained at the target voltage within the effective period, thereby improving the image quality. It is an object of the present invention to provide a display device. In addition, an object of the present invention is to improve the quality of an image by supplying different types of scan pulses by dividing a still image and a moving image.

According to an aspect of the present invention, there is provided a display device including: a display having a plurality of pixels defined by a plurality of gate lines and a plurality of data lines crossing each other; An image determining unit that determines whether the image to be displayed on the display unit is a still image or a moving image; A gate driver for driving the gate lines in any one of a first method and a second method according to a determination result from the image determining unit; The gate driver drives each gate line once for one frame period according to the first scheme; According to the second method, the gate driver drives each gate line at least twice in one frame period.

In addition, a display device according to the present invention for achieving the above object, the display unit having a plurality of pixels defined by a plurality of gate lines and a plurality of data lines crossing each other; A gate driver for driving the gate lines by mixing the first and second gate lines; The gate driver drives each gate line once for one frame period according to the first scheme; According to the second method, the gate driver drives each gate line at least twice in one frame.

The display device according to the present invention supplies at least two types of scan pulses (scan pulse for precharge and scan pulse for main charge) to each gate line. At this time, the two types of scan pulses are supplied to the respective gate lines when a data signal of the same polarity is supplied to the data lines. Thus, each pixel is charged at least twice with a data signal of the same polarity. Accordingly, the display device of the present invention can reach the pixel voltage of each pixel to the target voltage within the effective charging period.

Further, by driving the gate line differently according to the attribute of the image, the quality of the image in the still image and the moving image can be improved.

Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display unit 500 for displaying an image, a data driver 502 for supplying a data signal to the display unit 500, and And a gate driver 501 for supplying at least two scan pulses to the display unit 500.

The display unit 500 may include a plurality of gate lines GL1 to GLn arranged in one direction and a plurality of data lines DL1 to DLm arranged to vertically cross the gate lines GL1 to GLn. And pixels PXL formed in each pixel region defined by the gate lines GL1 through GLn and the data lines DL1 through DLm. Hereinafter, the configuration of each pixel PXL will be described in more detail.

Although not shown in the drawings, each pixel PXL includes a thin film transistor that receives a scan pulse from a corresponding gate line and switches a data signal from the corresponding data line, a pixel electrode that receives a switched data signal from the thin film transistor; And a liquid crystal cell which is formed between the common electrode receiving a common voltage from the outside and the pixel electrode and the common electrode to adjust the light transmittance according to the difference voltage (pixel voltage) between the data voltage and the common voltage.

On the other hand, at least two scan pulses output from the gate driver 501 are supplied to the respective gate lines. The data signal output from the data driver 502 is supplied to each data line.

Here, the scan pulse and the data signal will be described in more detail as follows.

FIG. 2 is a diagram illustrating a scan pulse supplied to each gate line of FIG. 1 and a data signal supplied to a first data line.

As shown in FIG. 2, two types of scan pulses, namely, precharge scan pulses Vpre1 to Vpren and main charge scan pulses Vtg1 to Vtgn are supplied to each gate line GL1 to GLn. .

Each of the precharge scan pulses Vpre1 to Vpren is a signal for precharging each pixel PXL connected to the gate lines GL1 to GLn by driving the gate lines GL1 to GLn. The scan pulse for main charge is a signal for driving each of the gate lines GL1 to GLn to charge each pixel PXL connected to each of the gate lines GL1 to GLn to a target voltage.

 Here, each of the precharge scan pulses Vpre1 to Vpren is sequentially output, so that each gate line GL1 to GLn is driven in turn.

That is, the second precharge scan pulse Vpre2 is delayed by a time corresponding to one horizontal period than the first precharge scan pulse Vpre1, and the third precharge scan pulse Vpre3 is output for the second precharge charge. The output pulse is delayed by a time corresponding to one horizontal period than the scan pulse Vpre2, and the scan pulse for the n-1 precharge Vpren-1 is in one horizontal period than the scan pulse for the n-2 precharge. The output is delayed by the corresponding time.

Also, since the scan pulses Vtg1 to Vtgn for each main charge are also output in turn, the gate lines GL1 to GLn are driven in turn.

That is, the second main charging scan pulse Vtg2 is output by being delayed by a time corresponding to one horizontal period than the first main charging scan pulse Vtg1, and the third main charging scan pulse Vtg3 is outputted as the second main charging scan pulse Vtg3. 2 is delayed by a time corresponding to one horizontal period than the scan pulse for the main charge (Vtg2), ..., the n-1 main charge scan pulse (Vtgn-1) is the scan for the n-2 main charge The output is delayed for one horizontal period than the pulse.

Here, each of the main charging scan pulses Vtg1 to Vtgn supplied to each of the gate lines GL1 to GLn is delayed by two horizontal periods than the respective precharging scan pulses Vpre1 to Vpren.

That is, the first main charging scan pulse Vtg1 is output by being delayed by a time corresponding to two horizontal periods than the first preliminary charging scan pulse Vpre1, and the second main charging scan pulse Vtg2 is outputted as a second. It is output by being delayed by a time corresponding to two horizontal periods than two precharge scan pulses Vpre2, and the third main charge scan pulse Vtg3 corresponds to two horizontal periods than the third precharge scan pulse Vpre3. The output pulse is delayed by a time, ..., the n-1 main charging scan pulse (Vtgn-1) is delayed by a time corresponding to two horizontal periods than the n-1 precharge scanning pulse (Vpren-1) The scan pulse Vtgn for the nth main charge is output by being delayed by a time corresponding to two horizontal periods than the scan pulse Vpren for the nth precharge.

Therefore, the kth (k is a natural number) gate line and the k + 2th gate line are simultaneously driven with each other. Specifically, during the same period, one of the kth gate line and the k + 2th gate line is driven by the precharge scan pulse, and the other gate line is driven by the main charge scan pulse.

For example, in the third horizontal period T3, the first gate line GL1 and the third gate line GL3 are simultaneously driven. In this case, the first gate line GL1 is driven by the first main scan scan pulse Vtg1, and the third gate line GL3 is driven by the third precharge scan pulse Vpre3.

In the fourth horizontal period T4, the second gate line GL2 and the fourth gate line GL4 are simultaneously driven. In this case, the second gate line GL2 is driven by the second main charge scan pulse Vtg2, and the fourth gate line GL4 is driven by the fourth precharge scan pulse Vpre4.

The amplitudes of the precharge scan pulses Vpre1 to Vpren and the amplitudes of the main charge scan pulses Vtg1 to Vtgn may be different from each other. For example, the amplitude of the precharge scan pulses Vpre1 to Vpren may be larger than the amplitude of the main charge scan pulses Vtg1 to Vtgn, or vice versa.

The above-described scan pulse is output from the gate driver 501. For this operation, the gate driver 501 includes a shift register.

The shift register includes a plurality of stages (not shown) connected dependently to each other. Each stage is connected one to one to each gate line GL1 to GLn.

Each stage receives the precharge scan pulse and the main charge scan pulse from the previous stage, and outputs the delayed precharge scan pulse and the main charge scan pulse by a time corresponding to one horizontal period.

Here, since no stage exists in front of the first of the stages, the first stage is supplied with the first start pulse Vst1 and the second start pulse Vst2 from the outside, and the first stage is supplied with the first stage. The start pulse Vst1 and the second start pulse Vst2 are shifted and output so as to be delayed by a time corresponding to one horizontal period.

Here, the operation of the shift register in more detail as follows.

First, the first start pulse Vst1 is output from the timing controller in a period preceding the first horizontal period T1 by one horizontal time, that is, in the initial period. This first start pulse Vst1 is a start signal for outputting the scan pulse for precharging.

This first start pulse Vst1 is supplied to the first stage. Then, the first stage shifts the first start pulse Vst1 and outputs the first pre-charge scan pulse Vpre1. That is, the first stage receives the first start pulse Vst1 in the initial period and outputs the first precharge scan pulse Vpre1 in the first horizontal period T1. The first precharge scan pulse Vpre1 is supplied to the first gate line GL1 and the second stage in the first horizontal period T1.

Subsequently, the second stage receives the first precharge scan pulse Vpre1 from the first stage, shifts it, and outputs the second precharge scan pulse Vpre2. That is, the second stage receives the first precharge scan pulse Vpre1 in the first horizontal period T1 and outputs the second precharge scan pulse Vpre2 in the second horizontal period T2. Then, the second precharge scan pulse Vpre2 is supplied to the second gate line GL2 and the third stage in the second horizontal period T2.

Next, the third stage receives the second precharge scan pulse Vpre2 from the second stage, shifts it, and outputs the third precharge scan pulse Vpre3. That is, the third stage receives the second precharge scan pulse Vpre2 in the second horizontal period T2 and outputs the third precharge scan pulse Vpre3 in the third horizontal period T3. The third precharge scan pulse Vpre3 is supplied to the third gate line GL3 and the fourth stage in the third horizontal period T3.

In this way, the remaining stages in turn output a scan pulse for nematode.

Meanwhile, in the second horizontal period T2, the second start pulse Vst2 is output from the timing controller. This second start pulse Vst2 is a start signal for outputting the main pulse scan pulse. This second start pulse Vst2 is supplied to the first stage. Then, the first stage shifts the second start pulse Vst2 and outputs the first main scan scan pulse Vtg1. That is, the first stage receives the second start pulse Vst2 in the second horizontal period T2 and outputs the first main scan scan pulse Vtg1 in the third horizontal period T3. The first main charge scan pulse Vtg1 is supplied to the first gate line GL1 and the second stage in the third horizontal period T3.

Subsequently, the second stage receives the first main charging scan pulse Vtg1 from the first stage, shifts it, and outputs the second main charging scan pulse Vtg2. That is, the second stage receives the first main charging scan pulse Vtg1 in the third horizontal period T3 and outputs the second main scanning scan pulse Vtg2 in the fourth horizontal period T4. In the fourth horizontal period T4, the second main charge scan pulse Vtg2 is supplied to the second gate line GL2 and the third stage.

Next, the third stage receives the second main charge scan pulse Vtg2 from the second stage, shifts it, and outputs the third main charge scan pulse Vtg3. That is, the third stage receives the second main charge scan pulse Vtg2 in the fourth horizontal period T4 and outputs the third main charge scan pulse Vtg3 in the fifth horizontal period T5. The third main charge scan pulse Vtg3 is supplied to the third gate line GL3 and the fourth stage in the fifth horizontal period T5.

In this manner, the remaining stages sequentially output the main pulse scan pulses.

That is, each stage sequentially outputs the precharge scan pulse and the main charge scan pulse by the first start pulse Vst1 and the second start pulse Vst2 supplied in different periods.

Meanwhile, for this operation, the gate driver 501 may have two shift registers.

3 is a diagram illustrating first and second shift registers included in the gate driver of FIG. 1.

That is, as illustrated in FIG. 3, the gate driver 501 sequentially outputs the first to nth precharge scan pulses VPren in response to the first start pulse Vst1. And a second shift register 701b which sequentially outputs the first to nth main scan scan pulses Vtgn in response to the second start pulse Vst2.

Here, the first shift register 701a has stages as described above, and the second shift register 701b also has stages as described above. The first stage of the first shift register 701a is supplied with the first start pulse Vst1, and the first stage of the second shift register 701b is supplied with the second start pulse Vst2.

As described above, since the first start pulse Vst1 is output in the initial period and the second start pulse Vst2 is output in the second horizontal period T2, the first shift register 701a is It operates first and second shift register 701b operates later.

On the other hand, the polarity of the data signal is reversed every horizontal period. That is, as shown in FIG. 6, the data signals Vdata1, Vdata3, Vdata5, Vdata7, Vdata9, ..., Vdatam-1 exhibit positive polarity in the odd horizontal period, and the data in the even horizontal period. The signals Vdata2, Vdata4, Vdata6, Vdata8, ..., and Vdatam exhibit negative polarity.

Here, the data signals Vdata1 to Vdatam are output from the data driver 502, and the data driver 502 may have either a dot inversion method or a line inversion method.

First, the operation of the dot inversion type data driver 502 will be described.

The dot inversion data driver 502 supplies one horizontal line of data signals Vdata1 to Vdatam to all data lines every horizontal period, and the data driver 502 is provided between adjacent data lines. Supply data signals of different polarities. In addition, the data driver 502 outputs the data signal group supplied in the odd-numbered horizontal period and the data signal group supplied in the even-numbered horizontal period to have different polar patterns.

For example, the data driver 502 supplies a positive data signal to each odd data line and a negative data signal to an even data line in a first horizontal period T1 which is an odd horizontal period. . The data driver 502 supplies a negative data signal to each odd-numbered data line and a positive data signal to each even-numbered data line in the second horizontal period T2 which is the even-numbered horizontal period.

Accordingly, the pixels PXL adjacent in the vertical direction, the pixels PXL adjacent in the left and right directions, and the pixels PXL adjacent in the diagonal direction all exhibit different polarities.

Next, the operation of the line inversion type data driver 502 will be described.

The data driver 502 of the line inversion method divides one horizontal line of data signals Vdata1 to Vdatam into all data lines every horizontal period, and the data driver 502 is identical to all data lines. Supply a polarity data signal. In addition, the data driver 502 outputs the data signal group supplied in the odd-numbered horizontal period and the data signal group supplied in the even-numbered horizontal period to have different polar patterns.

For example, the data driver 502 supplies a positive data signal to all data lines in the first horizontal period T1, which is the odd horizontal period. The data driver 502 supplies a negative data signal to all data lines in the second horizontal period T2 which is the even-numbered horizontal period.

Accordingly, the pixels PXL adjacent to each other in the vertical direction have different polarities.

In the present invention, any one of the above-described dot inversion data driver 502 and line inversion data driver 502 can be used.

The operation of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above is as follows.

4A to 4F are diagrams for describing an operation of pixels included in a portion C of FIG. 1 for each horizontal period.

In the first horizontal period T1, as shown in FIG. 2, the first precharge scan pulse Vpre1 and the first polarity first data signal Vdata1 are output.

As shown in FIG. 4A, the first precharge scan pulse Vpre1 is supplied to the first gate line GL1, and the positive first data signal Vdata1 is supplied to the first data line DL1. do.

Then, the first pixel PXL1 connected to the first gate line GL1 and the first data line DL1 may receive the first data signal having the positive polarity in response to the first precharge scan pulse Vpre1. Vdata1) is supplied. Therefore, the first pixel PXL1 is precharged with a positive voltage in the first horizontal period T1.

Here, the positive first data signal Vdata1 is a dummy data signal, and precharges the first pixel PXL1 with a positive voltage.

Subsequently, in the second horizontal period T2, as illustrated in FIG. 2, the second precharge scan pulse Vpre2 and the negative second data signal Vdata2 are output.

As shown in FIG. 4B, the second precharge scan pulse Vpre2 is supplied to the second gate line GL2, and the negative second data signal Vdata2 is connected to the first data line DL1. Supplied to.

Then, the second pixel PXL2 connected to the second gate line GL2 and the first data line DL1 may receive the second data signal (eg, negative polarity) in response to the first precharge scan pulse Vpre1. Vdata2) is supplied. Therefore, the second pixel PXL2 is precharged with a negative voltage in the second horizontal period T2.

Here, the negative second data signal Vdata2 is a dummy data signal, and precharges the second pixel PXL2 with a negative voltage.

Next, in the third horizontal period T3, as shown in FIG. 2, the third precharge scan pulse Vpre3, the first main scan scan pulse Vtg1, and the positive third data signal Vdata3. ) Is output. The positive third data signal Vdata3 is a signal for displaying an image on the first pixel PXL1.

As shown in FIG. 4C, the third precharge scan pulse Vpre3 is supplied to the third gate line GL3, and the first main scan scan pulse Vtg1 is the first gate line GL1. The third data signal Vdata3 having the positive polarity is supplied to the first data line DL1.

Accordingly, the third gate line GL3 and the first gate line GL1 are simultaneously driven in the third horizontal period T3.

Then, the third pixel PXL3 connected to the third gate line GL3 and the first data line DL1 has the positive third data signal Vdata3 in response to the third precharge scan pulse Vpre3. Is supplied). Therefore, in the third horizontal period T3, the third pixel PXL3 is precharged with a positive voltage.

In addition, the first pixel PXL1 connected to the first gate line GL1 and the first data line DL1 may receive the third data signal Vdata3 in response to the first main scan scan pulse Vtg1. Get supplied. Therefore, in the third horizontal period T3, the first pixel PXL1 is fully charged with a positive voltage and displays an image according to the third data signal Vdata3.

Next, in the fourth horizontal period T4, as shown in FIG. 2, the fourth precharge scan pulse Vpre4, the second main scan scan pulse Vtg2, and the negative fourth data signal ( Vdata4) is output. The negative fourth data signal Vdata4 is a signal for displaying an image on the second pixel PXL2.

As shown in FIG. 4D, the fourth precharge scan pulse Vpre4 is supplied to the fourth gate line GL4, and the second main scan scan pulse Vtg2 is the second gate line GL2. The fourth data signal Vdata4 of the negative polarity is supplied to the first data line DL1.

Accordingly, the fourth gate line GL4 and the second gate line GL2 are simultaneously driven in the fourth horizontal period T4.

Then, the fourth pixel PXL4 connected to the fourth gate line GL4 and the first data line DL1 may receive the negative fourth data signal in response to the fourth precharge scan pulse Vpre4. Vdata4). Accordingly, the fourth pixel PXL4 is precharged with a negative voltage in the fourth horizontal period T4.

In addition, the second pixel PXL2 connected to the second gate line GL2 and the first data line DL1 has a negative fourth data signal in response to the second main scan scan pulse Vtg2. Vdata4). Therefore, in the fourth horizontal period T4, the second pixel PXL2 is fully charged with a negative voltage and displays an image according to the fourth data signal Vdata4.

Next, in the fifth horizontal period T5, as illustrated in FIG. 2, the fifth precharge scan pulse Vpre5, the third main scan scan pulse Vtg3, and the fifth positive data signal Vdata5 are positive. ) Is output. Here, the positive fifth data signal Vdata5 is a signal for displaying an image on the third pixel PXL3.

As shown in FIG. 4E, the fifth precharge scan pulse Vpre5 is supplied to the fifth gate line GL5, and the third main scan scan pulse Vtg3 is applied to the third gate line GL3. The fifth data signal Vdata5 is supplied to the first data line DL1.

Accordingly, the fifth gate line GL5 and the third gate line GL3 are simultaneously driven in the fifth horizontal period T5.

Then, the fifth pixel PXL5 connected to the fifth gate line GL5 and the first data line DL1 has the positive fifth data signal Vdata5 in response to the fifth precharge scan pulse Vpre5. Is supplied). Thus, in the fifth horizontal period T5, the fifth pixel PXL5 is precharged with a positive voltage.

In addition, the third pixel PXL3 connected to the third gate line GL3 and the first data line DL1 has a positive fifth data signal Vdata5 in response to the third main scan scan pulse Vtg3. Is supplied). Accordingly, in the fifth horizontal period T5, the third pixel PXL3 is fully charged with a positive voltage and displays an image according to the fifth data signal Vdata5.

Next, in the sixth horizontal period T6, as illustrated in FIG. 2, the sixth precharge scan pulse Vpre6, the fourth main scan scan pulse Vtg4, and the negative sixth data signal ( Vdata6) is output. The sixth data signal Vdata6 of the negative polarity is a signal for displaying an image on the fourth pixel PXL4 (PXL).

As shown in FIG. 4F, the sixth precharge scan pulse Vpre6 is supplied to the sixth gate line GL6, and the fourth main charge scan pulse Vtg4 is applied to the fourth gate line GL4. The sixth data signal Vdata6 is supplied to the first data line DL1.

Accordingly, the sixth gate line GL6 and the fourth gate line GL4 are simultaneously driven in the sixth horizontal period T6.

Then, the sixth pixel PXL6 connected to the sixth gate line GL6 and the first data line DL1 may receive the sixth data signal of the negative polarity in response to the sixth precharge scan pulse Vpre6. Vdata6). Therefore, the sixth pixel PXL6 is precharged with a negative voltage in the sixth horizontal period T6.

In addition, the fourth pixel PXL4 connected to the fourth gate line GL4 and the first data line DL1 has a negative sixth data signal in response to the fourth main scan scan pulse Vtg4. Vdata6). Therefore, in the sixth horizontal period T6, the fourth pixel PXL4 is fully charged with a negative voltage and displays an image according to the sixth data signal Vdata6.

In this manner, the remaining gate lines GL7 to GLn are sequentially driven, and each pixel PXL connected to the gate lines GL7 to GLn is charged.

As can be seen from the above description, each pixel PXL is precharged and fully charged with a voltage of the same polarity. Therefore, the charging time of each pixel PXL is shortened, whereby the pixel voltage of each pixel PXL can be maintained at the target voltage within the effective charging period.

Meanwhile, the precharge scan pulses supplied to the same gate line may be output with a delay of four horizontal periods than the scan pulses for the main charge.

FIG. 5 is a diagram illustrating waveforms of another scan pulse supplied to each gate line of FIG. 1.

As shown in FIG. 5, the first main charging scan pulse Vtg1 is delayed by a time corresponding to four horizontal periods than the first precharging scanning pulse Vpre1, and the second main charging scan pulse Vtg1 is output. Vtg2 is delayed by a time corresponding to four horizontal periods than the second precharge scan pulse Vpre2, and the third main charge scan pulse Vtg3 is four times longer than the third precharge scan pulse Vpre3. The output pulse is delayed by a time corresponding to the horizontal period, and the n-th main charging scan pulse Vtgn-1 is in two horizontal periods than the n-th precharging scan pulse VPren-1. The output pulse is delayed by a corresponding time, and the scan pulse Vtgn for the nth main charge is delayed and output by a time corresponding to four horizontal periods than the scan pulse Vpren for the nth precharge.

Therefore, the kth (k is a natural number) gate line and the k + 4th gate line are simultaneously driven with each other. Specifically, one of the kth gate line and the k + 4th gate line is driven by the precharge scan pulse, and the other gate line is driven by the main charge scan pulse in the same period.

For example, in the fifth horizontal period T5, the first gate line GL1 and the fifth gate line GL5 are simultaneously driven. In this case, the first gate line GL1 is driven by the first main scan scan pulse Vtg1, and the fifth gate line GL5 is driven by the fifth precharge scan pulse Vpre5.

In the sixth horizontal period T6, the second gate line GL2 and the sixth gate line GL6 are simultaneously driven. In this case, the second gate line GL2 is driven by the second main charge scan pulse Vtg2, and the sixth gate line GL6 is driven by the sixth precharge scan pulse Vpre6.

Here, as the difference between the time point at which the precharge-only scan pulse is output and the time point at which the main charge-only scan pulse is output, the image according to the data signal supplied to the preceding pixel rather than the data signal corresponding to each pixel (incorrect image) ) Will take longer to display.

Therefore, it is preferable that the difference between the output time of the precharge scan pulse and the output time of the main charge scan pulse is four horizontal periods or less.

On the other hand, two or more pre-scan scan pulses supplied to one gate line may be used.

FIG. 6 is a diagram illustrating waveforms of another scan pulse supplied to each gate line of FIG. 1.

As shown in FIG. 6, each gate line GL1 to GLn is supplied with a scan pulse for primary precharge, a scan pulse for secondary precharge, and a scan pulse for main charge.

At this time, the scan pulses Vpre1 to Vpren for each primary precharge are sequentially output. That is, the second primary precharge scan pulse Vpre2 is output by being delayed by a time period corresponding to one horizontal period than the first primary precharge scan pulse Vpre1, and the third primary precharge scan pulse Vpre3 is outputted as the second pulse. The output is delayed by a time corresponding to one horizontal period than the second primary precharge scan pulse Vpre2, and the n-1 primary precharge scan pulse VPren-1 is scanned for the n-2 primary precharge scan. Output is delayed by one time period than pulse.

In addition, scan pulses Vpre1` to Vpren` for each secondary nematode are output in turn. That is, the second secondary precharge scan pulse Vpre2` is output by being delayed by a time corresponding to one horizontal period than the first secondary precharge scan pulse Vpre1`, and the third secondary precharge scan pulse Vpre3`. Is delayed by a time corresponding to one horizontal period than the second secondary precharge scan pulse Vpre2`, and the n-1 secondary precharge scan pulse Vpren-1` is output as n- 2 It is output delayed by the time corresponding to one horizontal period than the scan pulse for secondary nematode.

In addition, scan pulses Vtg1 to Vtgn for each main charging are output in turn. That is, the second main charging scan pulse Vtg2 is output by being delayed by a time corresponding to one horizontal period than the first main charging scan pulse Vtg1, and the third main charging scan pulse Vtg3 is outputted as the second main charging scan pulse Vtg3. 2 is delayed by a time corresponding to one horizontal period than the scan pulse for the main charge (Vtg2), ..., the n-1 main charge scan pulse (Vtgn-1) is the scan for the n-2 main charge Output is delayed by one time period than pulse.

Here, each of the main charging scan pulses Vtg1 to Vtgn supplied to each of the gate lines GL1 to GLn is delayed by two horizontal periods than the second precharging scanning pulses Vpre1` to Vpren` and output. do. That is, the first main charging scan pulse Vtg1 is output by being delayed by a time corresponding to two horizontal periods than the first secondary precharging scanning pulse Vpre1 ′, and the second main charging scan pulse Vtg2 is output. Is delayed by a time corresponding to two horizontal periods than the second secondary precharge scan pulse Vpre2`, and the third main scan scan pulse Vtg3 is output than the third secondary precharge scan pulse Vpre3`. Delayed by a time corresponding to two horizontal periods are output, ..., the n-1 main charge scan pulse (Vtgn-1) is two times than the n-1 secondary precharge scan pulse (Vpren-1`) The output is delayed by a time corresponding to a horizontal period, and the n-th main charge-only scan pulse Vtgn is output by being delayed by a time corresponding to two horizontal periods than the n-th secondary pre-charge-only scan pulse Vpren`.

In addition, each of the secondary precharge scan pulses Vpre1` to Vpren` supplied to each gate line GL1 to GLn is delayed by two horizontal periods longer than the respective primary precharge scan pulses Vpre1 to Vpren` and outputs. do. That is, the first secondary precharge scan pulse Vpre1` is output by being delayed by a time corresponding to two horizontal periods than the first primary precharge scan pulse Vpre1, and the second secondary precharge scan pulse Vpre2`. ) Is delayed and output by a time corresponding to two horizontal periods than the second primary precharge scan pulse Vpre2, and the third secondary precharge scan pulse Vpre3` is output than the third primary precharge scan pulse Vpre3. The output delayed by a time corresponding to two horizontal periods, ..., the n-1 secondary precharge scan pulse (Vpren-1`) is more than the n-1 primary precharge scan pulse (Vpren-1) The output pulse is delayed by a time corresponding to a horizontal period, and the scan pulse Vpren ′ for the n-th secondary nematode is output by a delay corresponding to two horizontal periods than the scan pulse Vpren for the n-th primary nematode.

Therefore, the kth (k is a natural number) gate line and the k + 2th gate line are simultaneously driven with each other. Specifically, one of the k th gate line and the k + 2 th gate line is driven by the secondary precharge scan pulse, and the other gate line is driven by the primary precharge scan pulse. In the second same period, one of the k th gate line and the k + 2 th gate line is driven by the primary precharge scan pulse, and the other gate line is driven by the main charge scan pulse.

For example, in the third horizontal period T3, the first gate line GL1 and the third gate line GL3 are simultaneously driven. In this case, the first gate line GL1 is driven by the first secondary precharge scan pulse Vpre1 ′, and the third gate line GL3 is driven by the third primary precharge scan pulse Vpre3.

The first gate line GL1 and the third gate line GL3 are simultaneously driven in the fifth horizontal period T5. In this case, the first gate line GL1 is driven by the first main scan scan pulse Vtg1, and the third gate line GL3 is driven by the third secondary precharge scan pulse Vpre3 ′.

Similarly, in the fourth horizontal period T4, the second gate line GL2 and the fourth gate line GL4 are simultaneously driven. In this case, the second gate line GL2 is driven by the second secondary precharge scan pulse Vpre2 ′, and the fourth gate line GL4 is driven by the fourth primary precharge scan pulse Vpre4.

The second gate line GL2 and the fourth gate line GL4 are simultaneously driven in the sixth horizontal period T6. In this case, the second gate line GL2 is driven by the second main charge scan pulse Vtg2, and the fourth gate line GL4 is driven by the fourth secondary precharge scan pulse Vpre4 ′.

Accordingly, each pixel PXL is stably charged through two precharges.

Of course, each pixel PXL may be precharged three or more times by increasing the number of scan pulses for precharging supplied to the gate lines GL1 to GLn.

FIG. 7 is a diagram illustrating a change in pixel voltage according to a change in the polarity of the data voltage of FIG. 2. As shown in the figure, the polarity of the data signal supplied to the n-th pixel PXLn during the precharge period is shown. The polarity of the data signal supplied to the nth pixel PXLn is the same during the main charging period. That is, the data signals supplied to the precharge section and the main charge section are both positive voltages.

Therefore, the pixel voltage of the nth pixel PXLn sufficiently reaches the target voltage within the effective charging period.

On the other hand, the image displayed on the display unit 500 is divided into a still image and a moving image. An image displayed on the display unit 500 is represented by the above-described data signal. When the image is a still image, it means that the data signals for a certain frame period are maintained at almost the same value, and that the image is a moving image. It means that the data signals during a certain frame period have different values.

In the case of the still picture, as described above, since there is almost no change in the data signal, if the pixel cell PXL is precharged using the precharge scan pulses Vpre1 to Vpren, the screen quality may be deteriorated. That is, the pixel cells PXL are supplied with data signals of other pixel cells PXL instead of their own data signals by the scan pulses Vpre1 to Vpren for exclusive use, so that other pixel cells are not images corresponding to the pixel cells PXL for a while. (PXL) is displayed, but the still image is a long-lasting unchanged image, so that an incorrect image (an image of another pixel cell (PXL)) in each pixel cell (PXL) is easily visible to the user's eyes. Is recognized. Therefore, when the still image is driven using the scan pulses Vpre1 to Vpren for charge, the quality of the image may be deteriorated.

On the other hand, in the case of moving images, since the data signal is severely changed, even if the pixel cells PXL are precharged using the precharge scan pulses Vpre1 to Vpren, the screen is severely changed. The wrong picture in) is not well perceived by the user's eyes.

In order to solve this problem, in the second embodiment of the present invention, it is determined whether the image to be displayed on the screen is a still image or a moving image, and then the precharge scan pulses Vpre1 to Vpren are applied according to the determined result. The neural scanning pulses Vpre1 to Vpren are not applied.

For convenience of description, a method of not applying the precharge scan pulses Vpre1 to Vpren is defined as a first method, and a method of applying the precharge scan pulses Vpre1 to Vpren is defined as a second method.

That is, according to the first method, the scan pulse is supplied once to each gate line GL1 to GLn for one frame period. This scan pulse corresponds to the above-described main charge scan pulses Vtg1 to Vtgn. In other words, in FIG. 2, FIG. 5, or FIG. 10, the precharge scan pulses are removed, and only the main charge scan pulses remain, which is the scan pulse corresponding to the first method.

On the other hand, according to the second method, the scan pulse is supplied to the gate lines GL1 to GLn more than once in one frame period. In other words, the scan pulses shown in Fig. 2, 5 or 10 are scan pulses according to the second scheme.

As a method for distinguishing whether the image is a still image or a moving image, there may be the following method. That is, an average change value of the data signal for a few frame periods is calculated, and this calculated value is compared with a preset reference set value so that the calculated value is within the reference set value and is displayed on the screen for the several frame period. The image to be defined may be defined as a still image, whereas if the calculated value is out of the reference setting value, the image may be defined as a moving image.

For example, if the difference between the data signals constituting the image during the first frame period and the data signals constituting the image during the second frame period is within the reference setting value, the first and second frame periods during the first and second frame periods. The image of? May be viewed as a still image, whereas if the difference value between the data signals constituting the image during the first frame period and the data signals constituting the image during the second frame period is out of the reference setting value, Images can be viewed as moving pictures.

As a method of distinguishing the still image from the moving image, any one of various known methods may be used.

8 is a diagram showing a display device according to a second embodiment of the present invention, and further includes an image discriminating unit 811 as shown in the figure.

The image discriminating unit 811 sequentially receives data signals input from the outside in units of frames, data signals corresponding to the pixel cells PXL of the nth frame, and pixel cells PXL of the n + 1th frame. ) Are stored, and data signals corresponding to the pixel cells PXL of the nth frame are updated with data signals to be supplied to the pixel cells PXL of the nth + 3th frame. Let's do it.

That is, the image discriminating unit 811 sequentially receives data signals sequentially input from a timing controller (not shown) in units of frames, and controls the two frame periods to be supplied to the pixel cells PXL of adjacent frames. Store data signals sequentially. The data signals of one frame which are sequentially stored among the data signals of the sequentially stored frames are updated with the data signals of the next frame which are input after the data signals of the two frames.

In other words, the image determining unit 811 includes two storage units. When the timing controller outputs first data signals (data signals to be supplied to the pixel cells PXL of the first frame), The image discriminating unit 811 receives the first data signals and stores the first data signals in a first storage unit. Subsequently, when the timing controller TC outputs second data signals (data signals to be supplied to the pixel cells PXL of the second frame), the image discriminating unit 811 supplies the second data signals. Receive and store in the second storage. Subsequently, when the timing controller TC outputs third data signals (data signals to be supplied to the pixel cell PXL of the third frame), the image discriminating unit 811 receives the third data signals. This is stored in the first storage unit. In this case, the first data signals are deleted from the first storage unit, and the third data signals are written.

The image discriminating unit 811 compares the data signals of the previous frame with the data signals of the current frame, and then determines whether the data signals of the current frame are still or moving images based on the comparison result. This determination method is to calculate the difference value between the data signals of the previous frame and the data signals of the current frame as described above, and to check whether this calculated value is located within the reference setting value. After this checking operation, if the image of the current frame is determined to be a still image, the image discriminating unit 811 outputs a first control signal CS1, whereas if the image of the current frame is determined to be a moving image, the image discriminating unit 811 outputs a second control signal CS2. The first or second control signals CS1 and CS2 from the image discriminating unit 811 are supplied to the gate driver 501. Then, the gate driver 501 outputs scan pulses corresponding to the first scheme in response to the first control signal CS1, and scan pulses corresponding to the second scheme in response to the second control signal CS2. Output them. Accordingly, the pixel cells PXL in the frame period having a still picture are supplied with one scan pulse during this frame period, and the pixel cells PXL in the frame period having a moving picture are twice or more during this frame period. Receive each scan pulse.

Thus, according to the display device according to the second embodiment of the present invention, it is possible to improve both the quality of the image when the still image and the quality of the image when the moving image.

9 is a diagram for describing a method of driving a display device according to a third exemplary embodiment of the present invention.

The driving method of the display device according to the third embodiment of the present invention is a method of driving by mixing the first method and the second method regardless of whether the image is a still picture or a moving picture.

For example, as illustrated in FIG. 9, the display unit 500 is driven in a first manner in a third q + 1 (q is a natural number including 0) frame (first, fourth, and seventh frames). The display unit 500 may be driven in a second manner during the remaining frame periods (second, third, fifth, and sixth frames).

Although not shown in the drawing, the display unit 500 may be driven in the first manner during the odd frame period, and the display unit 500 may be driven in the second manner during the even-numbered frame period.

In addition, the display unit 500 may be driven by irregularly applying the first and second methods in frame period units. For example, several frame periods may apply the first scheme, and other several frame periods may apply the second scheme.

Thus, according to the display device according to the third embodiment of the present invention, by combining and driving the first and second methods, it is possible to improve both the quality of the image in the still image and the image quality in the moving image.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 illustrates a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a scan pulse supplied to each gate line of FIG. 1 and a data signal supplied to a first data line.

FIG. 3 illustrates first and second shift registers included in the gate driver of FIG. 1. FIG.

4A through 4F are diagrams for describing an operation of pixels included in a portion C of FIG. 1 for each horizontal period.

FIG. 5 illustrates waveforms of another scan pulse supplied to each gate line of FIG.

FIG. 6 illustrates waveforms of another scan pulse supplied to each gate line of FIG. 1. FIG.

FIG. 7 is a diagram for describing a change in pixel voltage according to a change in polarity of the data voltage of FIG. 2.

8 illustrates a display device according to a second exemplary embodiment of the present invention.

9 is a view for explaining a method of driving a display device according to a third embodiment of the present invention.

Claims (10)

A display unit having a plurality of pixels defined by a plurality of gate lines and a plurality of data lines crossing each other; An image determining unit that determines whether the image to be displayed on the display unit is a still image or a moving image; A gate driver for driving the gate lines in any one of a first method and a second method according to a determination result from the image determining unit; The gate driver drives each gate line once for one frame period according to the first scheme; And, According to the second method, the gate driver drives each gate line at least twice in one frame period. The method of claim 1, If the image is a still image, the gate driver drives the gate lines according to the first scheme; And, And the gate driver drives the gate lines according to the second method when the image is a moving image. The method of claim 1, Each data line is supplied with a data signal of a different polarity in a period adjacent to each other; According to the second method, the gate driver supplies at least two scan pulses to an arbitrary gate line in a period in which the polarities of the data signals supplied to the arbitrary data lines are the same. The method of claim 2, Each scan pulse output from the gate driver according to the second method is two types, each of Precharge scan pulses for driving each gate line to precharge the pixels connected to the gate lines; And, And a scan pulse for main charge for driving each gate line to charge a pixel connected to each gate line to a target voltage. The method of claim 4, wherein The gate driver according to the second scheme, From the first period, the precharge scan pulses are sequentially supplied to the respective gate lines, and the main charge scan pulses are sequentially supplied to the respective gate lines from the second k-1 (k is a natural number greater than 1). Display device. The method of claim 5, wherein The precharge scan pulses supplied to the respective gate lines are output with a delay corresponding to a period corresponding to the precharge scan pulses immediately supplied to the previous gate lines; A display device for main charge scanning pulses supplied to each gate line is delayed by a time corresponding to a period longer than the main charge scanning pulse supplied to the previous gate line. The method of claim 5, wherein The main charging scan pulse supplied to the same gate line is delayed by a time corresponding to two periods than the precharging scan pulse supplied to the same gate line. The method of claim 2, Each scan pulse output from the gate driver according to the second method is three types, each of Primary precharge scan pulses for driving the respective gate lines to first precharge the pixels connected to the gate lines; Secondary precharge scan pulses for driving the respective gate lines to secondary precharge the pixels connected to the gate lines; And, And a scan pulse for main charging for driving each gate line to charge a pixel connected to each gate line to a target voltage. A display unit having a plurality of pixels defined by a plurality of gate lines and a plurality of data lines crossing each other; A gate driver for driving the gate lines by mixing the first and second gate lines; The gate driver drives each gate line once for one frame period according to the first scheme; And, According to the second method, the gate driver drives each gate line at least twice during one frame. The method of claim 9, And the gate driver drives the gate lines in a first manner in an odd frame period and drives the gate lines in a second manner in an even number period.

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