KR102276247B1 - Shift resistor and Liquid crystal display device using the same - Google Patents

Abstract

The present invention relates to a display device, and in particular, a shift register capable of driving a low refresh rate (LRR) for each line, improving image quality when driving at a low refresh rate (LRR), and minimizing a bezel size, and a liquid crystal using the same A display device, comprising: a carry pulse output unit and a scan pulse output unit for independently outputting carry pulses and scan pulses; and a Q node ripple removal pass for preventing Q node ripple; Carry pulses, at least two clock pulses for carry, and at least two clock pulses for scan are used.

Description

Shift resistor and liquid crystal display device using the same {Shift resistor and Liquid crystal display device using the same}

The present invention relates to a display device, and in particular, a shift register capable of driving a low refresh rate (LRR) for each line, improving image quality when driving at a low refresh rate (LRR), and minimizing a bezel size, and a liquid crystal using the same It is about the display device.

A typical liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

1 is a configuration circuit diagram showing a driving device of a general liquid crystal display device.

In general, as shown in FIG. 1 , a liquid crystal display device includes a liquid crystal panel 2 displaying an image, and a gate driver 6 driving gate lines GL1 to GLn of the liquid crystal panel 2 . and the data driver 4 driving the data lines DL1 to DLm of the liquid crystal panel 2 and the image data RGB inputted from the outside are arranged and supplied to the data driver 4 and the gate and a timing controller 8 for generating data control signals GCS and DCS to control the gate and data drivers 6 and 4, respectively.

The liquid crystal panel 2 is connected to a thin film transistor (TFT) formed in each pixel area defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm and the thin film transistor. and a liquid crystal capacitor Clc. The liquid crystal capacitor Clc includes a pixel electrode connected to the thin film transistor and a common electrode disposed with the pixel electrode and liquid crystal interposed therebetween. The thin film transistor supplies an image signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn.

The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage SVcom applied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. Implement gradation. In this case, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween, and a parasitic capacitor Cgs may be further formed between the source electrode and the gate line GL of the thin film transistor.

The data driver 4 includes a data control signal DCS from the timing controller 8 , for example, a source start signal (SSP), a source shift clock (SSC), and a source output signal. The data arranged from the timing controller 8 is converted into an analog voltage, that is, an image signal using a Source Output Enable (SOE) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the data aligned through the timing controller 8 according to the SSC, and then in response to the SOE signal 1 to which the scan pulse is supplied to each of the gate lines GL1 to GLn. An image signal corresponding to one horizontal line is supplied to each of the data lines DL1 to DLm in each horizontal period.

The gate driver 6 sequentially drives each of the gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 8 . Specifically, the gate driver 4 includes a gate start signal (GSP) that is a gate control signal (GCS), a gate shift clock (GSC), and a gate output enable (GOE) signal. The driving is performed so that scan pulses of the level of the gate high voltage VGH are sequentially supplied to each of the gate lines GL1 to GLn by using the same. In addition, the gate low voltage is supplied during the remaining period when the scan pulse is not supplied.

The timing controller 8 controls the data driver 4 and the gate driver 6 according to external image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync, DE. Specifically, the timing controller 8 aligns the image data RGB input from the outside to be suitable for driving the liquid crystal panel 2 and supplies it to the data driver 4 . The gate control signal GCS and the data control signal (GCS) and the data control signal (GCS) using at least one of a synchronization signal input from the outside, that is, a dot clock (DCLK), a data enable signal (DE), and horizontal and vertical synchronization signals (Hsync, Vsync) DCS) and supply it to the gate driver 6 and the data driver 4, respectively.

The gate driver 6 includes a shift register to sequentially output the scan pulses as described above.

The shift register includes a plurality of stages for sequentially outputting scan pulses to each of the gate lines GL1 to GLn based on a plurality of clock pulses provided from the timing controller.

The shift register may be built into the display panel. That is, the display panel has a display unit for displaying an image and a non-display unit surrounding the display unit, and the shift register SR may be built in the non-display unit (GIP).

The scan pulses generated from the respective stages are not only supplied to any one gate line, but also supplied to at least one of the rear stage and the front stage.

In each stage, the number of transistors is reduced in order to implement a narrow bezel, but a plurality of transistors including a pull-up switching element and a pull-down switching element for basically outputting a scan pulse, and one bootstrap capacitor is comprised of

On the other hand, recently, a low refresh rate (LRR) driving method has been proposed to minimize power consumption because the driving frequency is changed according to an image to be displayed.

That is, a method of driving at a frame frequency of 30 Hz to 60 Hz when the full screen displays a moving image or a partial moving image, and driving at a frame frequency of 1 Hz when the entire screen displays a still image was proposed.

Driving at a frame frequency of 60 Hz means that the liquid crystal capacitor (Clc) of each sub-pixel is charged 60 times per second, and driving at a frame frequency of 1 Hz means that the liquid crystal capacitor (Clc) of each sub-pixel is charged once per second. in case of charging.

Figure 2 (a) is a case showing the gate start pulse (Vst) and scan pulse (Vg_out1....Vg_outn) when driving at a 60Hz frame frequency, Figure 2 (b) is a gate start when driving at a 1Hz frame frequency A case where the pulse Vst and the scan pulse Vg_out1....Vg_outn are shown.

When driving at a frequency of 1 Hz, scan pulses of all gates are output at the same 1H timing as when driving at a frequency of 60 Hz, and then the scan pulses are held without driving for the remainder of one frame. Therefore, power consumption is lower when driving at 1Hz frequency than when driving at 60Hz frequency.

However, since the entire area of the display device is driven at the same frequency, low frequency (1 Hz) driving is possible only for still images in which the entire screen does not actually change, and when the screen changes even in a small area, low frequency (1 Hz) driving is possible. ) cannot be driven, and it must be driven at a high frequency (60Hz). Accordingly, there is a problem in that unnecessary power is consumed because high-frequency driving is performed even though the area occupied by the still image on the entire screen is wider than the area occupied by the moving image.

The present invention is intended to solve the problems of the related art, and it is possible to drive the display panel at different driving frequencies for each line, as well as a shift register capable of improving image quality by preventing ripple of the Q node from occurring. and to provide a liquid crystal display using the same.

The shift register according to the present invention for achieving the above object includes a carry pulse output unit and a scan pulse output unit for each stage independently outputting a carry pulse and a scan pulse, and a Q for preventing ripple of the Q node It has a node ripple removal pass and is characterized by using at least two carry pulses, at least two carry clock pulses, and at least two scan clock pulses.

In addition, it is characterized by implementing a narrow bezel by minimizing the circuit configuration of each stage.

In the shift register and the liquid crystal display using the same according to the present invention having the same characteristics as the singe, the following effects are obtained.

In other words, each stage has a Q node ripple removal path to prevent Q node ripple, so it is possible to drive LRR (Low Refresh Rate) for each line, as well as to prevent Q node ripple, thereby improving image quality. .

In addition, since the circuit configuration of each stage is minimized, a narrow bezel can be implemented.

1 is a configuration circuit diagram showing a driving device of a general liquid crystal display device;
2(a) and 2(b) are timing diagrams of gate start pulses and scan pulses according to a driving mode of a conventional liquid crystal display device;
3 is a screen configuration diagram for explaining an LRR driving method
4 is a driving circuit diagram of a display device previously filed by the present applicant;
5 is a timing diagram of various signals input/output and output signals when implementing a video in the shift register of FIG.
6 is a timing diagram of various signals input/output and output signals when a still image is implemented in the shift register of FIG. 4;
7 is a detailed configuration diagram of the shift register SR shown in FIG.
8 is a configuration diagram of any one stage of the shift register shown in FIG.
9 is a detailed configuration diagram of a shift register (SR) according to the first embodiment of the present invention;
10 is a block diagram of any one stage according to the first embodiment of the present invention;
11 is a detailed configuration diagram of a shift register (SR) according to a second embodiment of the present invention;
12 is a block diagram of any one stage according to the second embodiment of the present invention;

A shift register according to the present invention having the above characteristics and a liquid crystal display using the same will be described in more detail with reference to the accompanying drawings.

First, FIG. 3 is a screen configuration diagram for explaining an LRR driving method according to the present invention.

In order to reduce unnecessary power, the present applicant has previously applied for a shift register of a gate driver for driving to partially display a moving image and a still image in an image displayed on the entire screen, as described in FIG. 3 . (See Patent Application No.: 10-2014-0177397, Application Date: December 10, 2014, Title of Invention: Display Device and Method of Driving the Display Device).

4 is a view showing a shift register according to an embodiment of the present invention previously filed, FIG. 5 is a timing diagram of various signals input/output and output signals when implementing a video in the shift register of FIG. 4, and FIG. 6 is A timing diagram of various signals input/output and output signals when a still image is implemented in the shift register of FIG. 4 is shown.

As shown in FIG. 4, the shift register of the previously applied gate driver of the present invention includes i number of carry clock pulses (C-CLK_#) and j number of scan clock pulses (S-) from the timing controller TC. CLK_#) are provided. Specifically, the timing controller TC sequentially outputs i (i is a natural number greater than 1) clock pulses C-CLK_# for carry, and also scans j (j is a natural number greater than 1). The clock pulses (S-CLK_#) are sequentially output and supplied to the shift register (SR). In other words, the timing controller TC outputs i-phase carry clock pulses and j-phase scan clock pulses. As an example, in FIGS. 5 and 6 , six-phase carry clock pulses C-CLK_1 to C-CLK_6 having different phase differences, and six-phase scan clock pulses S- CLK_1 to S-CLK_6) are output. However, the present invention is not limited thereto, and various configurations such as 4 phases and 8 phases may be used.

5 and 6 , the pulse widths of the i carry clock pulses do not overlap each other, and the j scan clock pulses do not overlap each other in their pulse widths. However, as another embodiment, the output timing of the i number of carry clock pulses may be adjusted so that the pulse widths between the carry clock pulses output in adjacent periods overlap each other, and similarly, scan clock pulses output in adjacent periods The output timing of the clock pulses for the i carry may be adjusted so that the pulse widths between them overlap each other.

The shift register SR sequentially generates a plurality of outputs based on i clock pulses for carry and j clock pulses for scan provided from the timing controller TC. To this end, the shift register SR is It includes multiple stages that sequentially generate multiple such outputs. The output generated from each stage is composed of a pair of carry pulses and scan pulses corresponding to each other. In the pair of carry pulses and scan pulses, the carry pulses are supplied to at least one of the rear stage and the front stages, while the scan pulses are supplied to any one gate line.

At this time, the timing controller TC controls the scan clock pulse so that scan pulses of different driving frequencies are output to the gate lines corresponding to the still image and the gate lines corresponding to the moving image of the displayed image. .

For example, as shown in FIG. 5 , the timing controller TC may include a plurality of scan clock pulses in stages for outputting scan pulses to gate lines of a portion corresponding to the moving image among the displayed image. (S-CLK_1 to S-CLK_6) are output at 60Hz.

However, as shown in FIG. 6 , the timing controller TC outputs a plurality of scan clock pulses S to the stages outputting scan pulses to gate lines of a portion corresponding to a still image among the displayed image. -CLK_1 to S-CLK_6) are output at 1 Hz.

A more specific method will be described later.

FIG. 7 is a detailed configuration diagram of the shift register SR shown in FIG. 4 previously filed.

As shown in FIG. 7 , the previously applied shift register SR of the present invention includes a plurality of stages ST_n-2 to ST_n+2. Here, each stage includes a total of six terminals (I, II, III, IV, V, VI).

A carry clock pulse of any one of the plurality of carry clock pulses C-CLK_1 to C-CLK_6 is applied to the fourth terminal IV of each stage, and the first terminal I is output from the previous stage A carry pulse (or start pulse (Vst)) is applied, and one carry pulse (one of CRPn-2 to CRPn+2) is output through the second terminal (II; hereinafter, carry pulse output terminal (COT)). do.

In addition, a scan clock pulse of any one of the plurality of scan clock pulses S-CLK_1 to S-CLK_6 is applied to the 5th terminal V of each stage, and the 6th terminal is used from the next stage. The output carry pulse is applied, and one scan pulse (one of the scan pulses SCPn-2 to SCPn+2) is output through the third terminal (III, hereinafter, the scan pulse output terminal (SOT)).

Accordingly, the carry pulses and scan pulses as described above are independently output from the second and third terminals of each stage, respectively.

If the six-phase carry clock pulses (C-CLK_1 to C-CLK_6) and scan clock pulses (S-CLK_1 to S-CLK_6) are provided to the shift register as shown in FIGS. 5 and 6 above, For example, the 6k+1th (k is a natural number including 0) stages among all stages including the n-2th to n+2th stages ST_n-2 to ST_n+2 are clock pulses for the first carry. (C-CLK_1) and a clock pulse for the first scan (S-CLK_1), the 6k+2th stages receive a clock pulse for the second carry (C-CLK_2) and a clock pulse for the second scan (S-CLK_2), The 6k+3th stages receive a clock pulse for the third carry (C-CLK_3) and a clock pulse for the third scan (S-CLK_3), and the 6k+4th stages receive a clock pulse for the fourth carry (C-CLK_4) and the second The 4th scan clock pulse (S-CLK_4), the 6k+5th stages are the 5th carry clock pulse (C-CLK_5) and the 5th scan clock pulse (S-CLK_5), and the 6k+6th stages are The sixth carry clock pulse C-CLK_6 and the sixth scan clock pulse S-CLK_6 may be supplied.

Each stage uses a carry pulse to control the operation of a stage located at its rear end and a stage located at its front end. In addition, each stage drives a gate line connected thereto by using a scan pulse. Meanwhile, although not shown, a dummy stage for supplying a carry pulse to the last stage may be further provided at a rear end of the last stage. Depending on the configuration of the shift register SR, the number of dummy stages may be plural instead of one. Since this dummy stage is not connected to the gate line, it does not output a scan pulse.

The shift register SR may be built in the display panel. That is, the display panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register SR may be built in the non-display portion (GIP).

8 is a view showing the configuration of any one stage according to the present invention previously filed.

Each stage separately includes a carry pulse output unit 10 and a scan pulse output unit 20 as shown in FIG. 8 .

The carry pulse output unit 10 of each stage (nth stage) includes a carry pulse (CRP_n-1 or start pulse (Vst) output from the previous stage) and a carry pulse (CRP_n+1) output from the next stage The node control unit 11 for controlling the Q node and the QB node according to , receives the carry clock pulse (C-CLK_#) of any one of the plurality of carry clock pulses (C-CLK_1 to C-CLK_6) and a carry pulse output unit 12 for outputting a carry pulse CRP_n according to the voltages of the Q node and QB node of the node control unit 11 .

In addition, the scan pulse output unit 20 of each stage (nth stage) includes a carry pulse CRP_n-1 or a start pulse Vst output from the previous stage and a carry pulse CRP_n+ output from the next stage. The node controller 21 for controlling the Q node and the QB node according to 1), and the carry clock pulse S-CLK_# of any one of the plurality of scan clock pulses S-CLK_1 to S-CLK_6 and a scan pulse output unit 22 for receiving and outputting a scan pulse SCP_n according to the voltages of the Q node and QB node of the node control unit 21 .

Accordingly, when a moving image is partially present in a still image, gate lines corresponding to the moving image are driven at 60 Hz, and gate lines corresponding to the remaining still images are driven at 1 Hz.

That is, in order to drive the gate lines corresponding to the moving image at 60 Hz, as shown in FIG. 5 , the timing controller TC uses the i-phase carry clock pulses C-CLK_1 to C-CLK_6. ) and the j-phase scan clock pulses (S-CLK_1 to S-CLK_6) are output to the corresponding stage of the gate driver at a frequency of 60 Hz.

And, in order to drive the gate lines corresponding to the still image at 1 Hz, as shown in FIG. 6 , clock pulses C-CLK_1 to C-CLK_6 for carry of the i-phase in the timing controller TC is output to the corresponding stage of the gate driver at a frequency of 60 Hz, and the j-phase scan clock pulses S-CLK_1 to S-CLK_6 are output at a frequency of 1 Hz.

As such, regardless of the moving image and the still image, the timing controller TC outputs the i-phase carry clock pulses C-CLK_1 to C-CLK_6 at 60 Hz, and the moving image is driven. In a section, the j-phase scan clock pulses (S-CLK_1 to S-CLK_6) are output at a frequency of 60 Hz, and in the section in which a still image is driven, the j-phase scan clock pulses (S-CLK_1 to S-CLK_6) are output. ) at a frequency of 1 Hz, low-frequency driving is possible for each gate line (block) even when a moving image is partially present.

However, in the present invention previously filed, as shown in FIG. 8 , a path for removing the ripple of the Q node is not formed in the carry pulse output unit 10 and the scan pulse output unit 20 , Image quality may be deteriorated due to ripple.

That is, a ripple is generated in the Q-node by the carry clock pulse (C-CLK(n)) and the scan clock pulse (S-CLK(n) supplied to the output unit. The ripple of the Q node Since a path is not formed to remove , image quality may be deteriorated due to generation of ripples.

According to the present invention, the display panel can be driven at different driving frequencies for each line, and each stage forms a path to remove the ripple of the Q node to prevent the generation of ripple of the Q node. An object of the present invention is to provide a shift register capable of improving image quality.

9 is a detailed configuration diagram of a shift register SR according to the first embodiment of the present invention.

As shown in FIG. 9 , the shift register SR according to the first embodiment of the present invention includes a plurality of stages ST_n-2 to ST_n+2.

In each stage, three carry clock pulses among the plurality of carry clock pulses (C-CLK_1 to C-CLK_6), carry pulses (or start pulses (Vst)) output from the previous and previous stages, and , three scan clock pulses among the plurality of scan clock pulses S-CLK_1 to S-CLK_6 and a carry pulse output from the next stage are applied. Then, one carry pulse is output through the carry pulse output terminal COT), and one scan pulse is outputted through the scan pulse output terminal SOT.

The six-phase carry clock pulses C-CLK_1 to C-CLK_6 and scan clock pulses S-CLK_1 to S-CLK_6 are the same as described in FIGS. 5 and 6, but three There is a difference in that a carry clock pulse and three scan clock pulses are applied, and three carry pulses output from front and rear are applied.

Each stage uses a carry pulse to control the operation of a stage located at its rear end and a stage located at its front end. In addition, each stage drives a gate line connected thereto by using a scan pulse. Meanwhile, although not shown, a dummy stage for supplying a carry pulse to the last stage may be further provided at a rear end of the last stage. Depending on the configuration of the shift register SR, the number of dummy stages may be plural instead of one. Since this dummy stage is not connected to the gate line, it does not output a scan pulse.

10 is a diagram showing the configuration of any one stage according to the first embodiment of the present invention.

Each stage separately includes a carry pulse output unit 10 and a scan pulse output unit 20 as shown in FIG. 10 .

The carry pulse output unit 10 of each stage (n-th stage) includes the carry pulses CRP_n-1 and CRP_n-2 (or start pulse Vst) output from the previous stage, and the carry pulse output from the next stage. (CRP_n+2) and a node controller (C-CLK_1 to C-CLK_6) for controlling the Q node according to the carry clock pulse C-CLK_(n-1) of the plurality of carry clock pulses C-CLK_1 to C-CLK_6 11) and two carry clock pulses C-CLK_(n) and C-CLK_(n+2) among the plurality of carry clock pulses C-CLK_1 to C-CLK_6, and the node controller receives A carry pulse output unit 12 for outputting a carry pulse CRP_n according to the voltage of the Q node of (11) is provided.

In addition, the scan pulse output unit 20 of each stage (n-th stage) receives the carry pulses CRP_(n-1) and C-CRP_(n-2) output from the previous stage (or the start pulse Vst). )), the carry pulse CRP_n+2 output from the next stage, and the scan clock pulse S-CLK_(n-1) of any one of the plurality of scan clock pulses S-CLK_1 to S-CLK_6. ), the node controller 21 for controlling the Q node, and two scan clock pulses S-CLK_(n), S-CLK_ among the plurality of scan clock pulses S-CLK_1 to S-CLK_6. (n+2)) and a scan pulse output unit 22 for outputting a scan pulse SCP_n according to the voltage of the Q node of the node control unit 21 .

Here, the circuit configuration of the carry pulse output unit 10 and the scan pulse output unit 20 will be described in more detail as follows.

As shown in FIG. 10 , the node control unit 11 of the carry pulse output unit 10 includes the carry pulse {CRP_ output from the carry pulse output unit 10 of the (n-2)th stage ST_n-2. The first switching device T1 controlled according to (n-2) to charge the carry pulse {CRP_(n-2)} to the node Q, and the carry pulse of the n+2th stage ST_n+2 The second switching element T3n that is controlled according to the carry pulse {CRP_(n+2)} output from the output unit 10 to discharge the node Q, and a plurality of carry clock pulses representing different phases The carry pulse {CRP_(n) controlled according to any one of {C-CLK(n-1)} and output from the carry pulse output unit 10 of the (n-1)th stage ST_(n-1) -1)} a third switching element T3c for charging the node Q, and a fourth switching element for discharging the node Q controlled according to a reset signal Reset or a start signal Vst ( T3r).

The output unit 12 of the carry pulse output unit 10 includes a capacitor C for bootstrapping the voltage of the Q node, and a plurality of voltages controlled according to the voltage of the node Q to indicate the different phases. A fifth switching element T6 that outputs any one of the carry clock pulses {C-CLK(n)} to an output terminal, and any one of a plurality of carry clock pulses indicating different phases {C-CLK (n+2)} and a sixth switching element T7c and a seventh switching element T7d for discharging the output terminal.

The scan pulse output unit 20 also has the same configuration as the carry pulse output unit 10 , but has a difference in that a scan clock pulse is applied instead of a carry clock pulse.

That is, the node control unit 21 of the scan pulse output unit 20 is configured according to the carry pulse {CRP_(n-2) output from the carry pulse output unit 10 of the (n-2)th stage ST_n-2. The first switching device T1 is controlled to charge the carry pulse {CRP_(n-2)} to the node Q, and output from the carry pulse output unit 10 of the n+2th stage ST_n+2 The second switching element T3n that is controlled according to the carry pulse {CRP_(n+2)} to discharge the node Q, and any one of a plurality of scan clock pulses indicating different phases {S- The carry pulse {CRP_(n-1)} output from the carry pulse output unit 10 of the (n-1)-th stage ST_(n-1) is controlled according to CLK(n-1)} to the node A third switching element T3c that charges the Q, and a fourth switching element T3r that is controlled according to a reset signal or a start signal Vst to discharge the node Q.

The output unit 22 of the scan pulse output unit 20 includes a capacitor C for bootstrapping the voltage of the Q node, and a plurality of capacitors C that are controlled according to the voltage of the node Q to indicate the different phases. A fifth switching element T6 that outputs any one of the scan clock pulses {S-CLK(n)} to an output terminal, and any one of a plurality of scan clock pulses indicating different phases {S-CLK (n+2)} and a sixth switching element T7c and a seventh switching element T7d for discharging the output terminal.

The operation of the nth stage according to the first embodiment of the present invention configured as described above will be described below.

First, the operation of the carry pulse output unit 10 will be described as follows.

When the high pulse of the carry pulse {CRP_(n-2)} output from the carry pulse output unit 10 of the (n-2)th stage ST_(n-2) is input to the first switching element T1, The first switching device T1 is turned on to charge the carry pulse {CRP_(n-2)} to the node Q. And, one carry clock from among a plurality of carry clock pulses having different phases When the high pulse of the pulse {C-CLK(n+2)} is input to the sixth switching element T7c, the sixth switching element T7c is turned on to discharge the output terminal.

In this state, one clock pulse {C-CLK(n-1)} among a plurality of carry clock pulses having different phases in the third switching device T3c and the n-1th stage ST_(n) The carry pulse {CRP_(n-1)} output from the carry pulse output unit 10 of -1) is input, and the third carry pulse {C-CLK(n-1)} is in the high section of the carry clock pulse {C-CLK(n-1)}. The switching element T3c is turned on to charge the carry pulse CRT_(n-1) in the node Q. Then, the node Q maintains a high state.

When the node Q maintains the high state, the fifth switching element T6 is turned on and bootstrapped by the capacitor C, and different phases input to the source terminal of the fifth switching element T6 are turned on. One of the carry clock pulses {C-CLK(n)} among the plurality of carry clock pulses having ? is output to the output terminal as a carry pulse CRP_n.

In addition, the fourth switching element T3r is turned on by the reset signal or the start signal to discharge the node Q, and at the same time, one of the plurality of carry clock pulses {C-CLK(n+2)) } is input to the sixth switching element T7c, the sixth switching element T7c is also turned on to discharge the output terminal.

The operation of the scan pulse output unit 20 also operates in the same manner as that of the carry pulse output unit 10 , except that the input clock pulses have different phases from each other. A plurality of scan clock pulses S-CLK_1 to S- CLK_6), the operation of the scan pulse output unit 20 is omitted.

Therefore, as described with reference to FIGS. 5 and 6 , regardless of a moving image and a still image, the timing controller TC performs the i-phase carry clock pulses C-CLK_1 to C-CLK_6 Outputs at 60 Hz, and outputs the j-phase scan clock pulses (S-CLK_1 to S-CLK_6) at a frequency of 60 Hz in a section in which a moving image is driven, and outputs the j-phase scan clock in a section in which a still image is driven. Since the pulses S-CLK_1 to S-CLK_6 are output at a frequency of 1 Hz, low-frequency driving is possible for each gate line (block) even when a moving image is partially present.

In addition, in the third switching element T3c, any one of a plurality of carry clock pulses {C-CLK(n-1)} and (n-1) representing different phases regardless of driving a moving image or a still image Since the carry pulse {CRP_(n-1)} output from the carry pulse output unit 10 of the th stage ST_(n-1) is applied at 60 Hz, a path is formed to remove a ripple that may be generated in the Q node Therefore, it is possible to provide a shift register capable of improving image quality.

In FIG. 10 , the carry pulse output unit 10 and the scan pulse output unit 20 each separately include the node control units 11 and 21 , but they may be shared.

That is, as described in FIG. 7 of the patent application (patent application number: 10-2014-0177397) previously filed by the present applicant, any one stage (n-th stage) is a carry pulse output from the previous stage ( CRP_n-1, CRP_n-2) (or start pulse (Vst)), a carry pulse (CRP_n+2) output from the next stage, and any of the plurality of carry clock pulses (C-CLK_1 to C-CLK_6) The node controller 11 controls the Q node according to one carry clock pulse C-CLK_(n-1), and two carry among the plurality of carry clock pulses C-CLK_1 to C-CLK_6 Carry pulse output unit 12 that receives the clock pulses C-CLK_(n) and C-CLK_(n+2) and outputs a carry pulse CRP_n according to the voltage of the Q node of the node control unit 11 and, by receiving two scan clock pulses S-CLK_(n) and S-CLK_(n+2) among the plurality of scan clock pulses S-CLK_1 to S-CLK_6, the node control unit ( The scan pulse output unit 22 for outputting the scan pulse SCP_n according to the voltage of the Q node in 11) may be provided.

Since it is configured as described above, the circuit configuration of each stage can be further reduced, so that a narrow bezel can be implemented.

In the shift register of the first embodiment of the present invention as described with reference to FIGS. 9 and 10, the third switching element T3c forms a path for removing a ripple that may be generated at the Q node, so that image quality can be improved while , since a pulse of 60 Hz is always applied to the gate electrode and the source electrode of the third switching device T3c, the third switching device T3c is deteriorated and a path for removing the ripple of the Q node cannot be formed. have.

Accordingly, a path for removing ripple that may be generated in the Q node may be separately formed without using the third switching element T3c.

As described above, an embodiment in which a path for removing a ripple that may be generated in the Q node is separately formed will be described as follows.

11 is a detailed configuration diagram of a shift register SR according to a second embodiment of the present invention, and FIG. 12 is a diagram showing the configuration of any one stage according to the second embodiment of the present invention.

As shown in FIG. 11 , the shift register SR according to the second embodiment of the present invention includes a plurality of stages ST_n-2 to ST_n+2.

In each stage, two carry clock pulses among the plurality of carry clock pulses C-CLK_1 to C-CLK_6, a carry pulse (or start pulse Vst) output from the previous stage, and the plurality of carry clock pulses Two scan clock pulses among the scan clock pulses S-CLK_1 to S-CLK_6 and a carry pulse output from the next stage are applied. Then, one carry pulse is output through the carry pulse output terminal COT), and one scan pulse is output through the scan pulse output terminal SOT.

The six-phase carry clock pulses C-CLK_1 to C-CLK_6 and scan clock pulses S-CLK_1 to S-CLK_6 are the same as described in FIGS. 5 and 6, but two There is a difference in that a carry clock pulse and two scan clock pulses are applied, and two carry pulses output from front and rear ends are applied.

Each stage uses a carry pulse to control the operation of a stage located at its rear end and a stage located at its front end. In addition, each stage drives a gate line connected thereto by using a scan pulse. Meanwhile, although not shown, a dummy stage for supplying a carry pulse to the last stage may be further provided at a rear end of the last stage. Depending on the configuration of the shift register SR, the number of dummy stages may be plural instead of one. Since this dummy stage is not connected to the gate line, it does not output a scan pulse.

Each stage according to the second embodiment of the present invention includes a carry pulse output unit 10 and a scan pulse output unit 20 separately as shown in FIG. 12 .

The carry pulse output unit 10 of each stage (nth stage) includes a carry pulse CRP_n-2 (or start pulse Vst) output from the previous stage and a carry pulse CRP_n+2 output from the next stage. ), the node controller 11 for controlling the Q node, and two carry clock pulses C-CLK_(n), C-CLK_ among the plurality of carry clock pulses C-CLK_1 to C-CLK_6. and a carry pulse output unit 12 that receives (n+2) and outputs a carry pulse CRP_n according to the voltage of the Q node of the node control unit 11 .

In addition, the scan pulse output unit 20 of each stage (nth stage) outputs the carry pulse C-CRP_(n-2) (or start pulse Vst) output from the previous stage and the next stage. The node controller 21 controls the Q node according to the carry pulse CRP_n+2, and two scan clock pulses S-CLK_ among the plurality of scan clock pulses S-CLK_1 to S-CLK_6. and a scan pulse output unit 22 that receives (n), S-CLK_(n+2)) and outputs a scan pulse SCP_n according to the voltage of the Q node of the node control unit 21 .

Here, the circuit configuration of the carry pulse output unit 10 and the scan pulse output unit 20 will be described in more detail as follows.

As shown in FIG. 12 , the node control unit 11 of the carry pulse output unit 10 includes the carry pulse {CRP_ output from the carry pulse output unit 10 of the (n-2)-th stage ST_n-2. The first switching device T1 controlled according to (n-2) to charge the carry pulse {CRP_(n-2)} to the node Q, and the carry pulse of the n+2th stage ST_n+2 A second switching element T3n that is controlled according to the carry pulse {CRP_(n+2)} output from the output unit 10 to discharge the node Q, and a reset signal or a start signal Vst A third switching element T3r that is controlled according to and discharges the node Q, a capacitor C2 that stores a discharge signal input from the outside, and a discharge signal stored in the capacitor C2. Accordingly, a fourth switching device T3c that forms a path for removing the ripple generated at the node Q, and a fifth switching device that discharges the discharge signal stored in the capacitor C2 according to the voltage of the Q node (T3q) is provided.

The output unit 12 of the carry pulse output unit 10 includes a capacitor C1 for bootstrapping the voltage of the Q node, and a plurality of capacitors C1 that are controlled according to the voltage of the node Q to indicate the different phases. A sixth switching device T6 for outputting any one of the carry clock pulses {C-CLK(n)} to an output terminal, and any one of a plurality of carry clock pulses representing different phases {C-CLK (n+2)} and a seventh switching element T7c and an eighth switching element T7d for discharging the output terminal.

The scan pulse output unit 20 also has the same configuration as the carry pulse output unit 10 , but has a difference in that a scan clock pulse is applied instead of a carry clock pulse.

That is, the node control unit 21 of the scan pulse output unit 20 is configured according to the carry pulse CRP_(n-2) output from the carry pulse output unit 10 of the (n-2)th stage ST_n-2 The first switching device T1 is controlled to charge the carry pulse {CRP_(n-2)} to the node Q, and output from the carry pulse output unit 10 of the n+2th stage ST_n+2 The second switching element T3n is controlled according to the carried pulse {CRP_(n+2)} to discharge the node Q, and the node (Reset) is controlled according to the reset signal (Reset) or the start signal (Vst) A third switching element T3r for discharging Q), a capacitor C2 for storing a discharge signal input from the outside, and a discharge signal stored in the capacitor C2 at the node Q A fourth switching element (T3c) for forming a path for removing the generated ripple, and a fifth switching element (T3q) for discharging the discharge signal stored in the capacitor (C2) according to the voltage of the Q node do.

The output unit 22 of the scan pulse output unit 20 includes a capacitor C1 for bootstrapping the voltage of the Q node, and a plurality of voltages controlled according to the voltage of the node Q to indicate the different phases. A sixth switching element T6 that outputs any one of the scan clock pulses {S-CLK(n)} to an output terminal, and any one of a plurality of scan clock pulses indicating different phases {S-CLK (n+2)} and a seventh switching element T7c and an eighth switching element T7d for discharging the output terminal.

Similarly, in FIG. 12 , the carry pulse output unit 10 and the scan pulse output unit 20 each separately include the node control units 11 and 21 , but these may be used in common.

That is, as described in FIG. 7 of the patent application (patent application number: 10-2014-0177397) previously filed by the present applicant, any one stage (n-th stage) is a carry pulse output from the previous stage ( CRP_n-2) (or start pulse (Vst)) and the node controller 11 for controlling the Q node according to the carry pulse (CRP_n+2) output from the next stage, and the plurality of carry clock pulses (C) Receives two carry clock pulses (C-CLK_(n) and C-CLK_(n+2) among -CLK_1 to C-CLK_6), and according to the voltage of the Q node of the node controller 11, the carry pulse (CRP_n) ), and two scan clock pulses S-CLK_(n) and S-CLK_(n) among the plurality of scan clock pulses S-CLK_1 to S-CLK_6. +2)), the scan pulse output unit 22 may be provided to output the scan pulse SCP_n according to the voltage of the Q node of the node control unit 11 .

Similarly, since the configuration as described above can further reduce the circuit configuration of each stage, a narrow bezel can be implemented.

The operation of the nth stage according to the second embodiment of the present invention configured as described above will be described below.

First, the operation of the carry pulse output unit 10 will be described as follows.

When the high pulse of the carry pulse {CRP_(n-2)} output from the carry pulse output unit 10 of the (n-2)th stage ST_(n-2) is input to the first switching element T1, The first switching element T1 is turned on to charge the carry pulse {CRP_(n-2)} to the node Q. And, one carry clock from among a plurality of carry clock pulses having different phases When the high pulse of the pulse {C-CLK(n+2)} is input to the seventh switching element T7c, the seventh switching element T7c is turned on to discharge the output terminal.

As such, when the node Q maintains the high state, the sixth switching element T6 is turned on and bootstrapped by the capacitor C1, and each other inputted to the source terminal of the sixth switching element T6 is turned on. One carry clock pulse C-CLK(n) among a plurality of carry clock pulses having different phases is output to the output terminal as a carry pulse CRP_n.

And, when the carry pulse CRP_(n+2) in the high state is output from the carry pulse output unit 10 of the n+2th stage ST_n+2, the second switching element T3n is turned on and the node ( At the same time as discharging Q), when one of the plurality of carry clock pulses {C-CLK(n+2)} is input to the seventh switching element T7c, the sixth switching element T7c is also turned on. Also, the third switching element T3r is turned on by a reset signal or a start signal to discharge the output terminal, thereby discharging the node Q.

The operation of the scan pulse output unit 20 also operates in the same manner as that of the carry pulse output unit 10 , except that the input clock pulses have different phases from each other. A plurality of scan clock pulses S-CLK_1 to S- CLK_6), the operation of the scan pulse output unit 20 is omitted.

Therefore, as described with reference to FIGS. 5 and 6 , regardless of a moving image and a still image, the timing controller TC performs the i-phase carry clock pulses C-CLK_1 to C-CLK_6 Outputs at 60 Hz, and outputs the j-phase scan clock pulses (S-CLK_1 to S-CLK_6) at a frequency of 60 Hz in a section in which a moving image is driven, and outputs the j-phase scan clock in a section in which a still image is driven. Since the pulses S-CLK_1 to S-CLK_6 are output at a frequency of 1 Hz, low-frequency driving is possible for each gate line (block) even when a moving image is partially present.

At this time, when a discharge signal is externally input to the capacitor C2, the capacitor C2 is charged, and the fourth switching element T3c is turned on according to the voltage charged in the capacitor C2. It is turned on to form a path for removing the ripple generated at the node Q. In addition, the fifth switching element T3q is turned on according to the voltage of the Q node to discharge the discharge signal stored in the capacitor C2.

Accordingly, one discharge signal is applied to the capacitor C2 when driving a moving image, and two discharge signals are applied to the capacitor C2 when driving a still image.

In this way, since a path for removing a ripple that may be generated in the Q node is separately formed, deterioration of the switching element can be prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of

Claims (9)

having a plurality of stages,
Each stage is
Carry outputting a carry pulse by receiving one carry pulse (or start pulse) output from the previous stage, one carry pulse output from the next stage, and two carry clock pulses among a plurality of carry clock pulses a pulse output;
Receives one carry pulse (or start pulse) output from the previous stage, one carry pulse output from the next stage, and two scan clock pulses among a plurality of scan clock pulses to output a scan pulse a scan pulse output unit,
The carry pulse output unit or scan pulse output unit,
A first switching device that is controlled according to the carry pulse output from the carry pulse output unit of the previous stage to charge the carry pulse to the node (Q);
A first capacitor for storing a discharge signal input from the outside;
a fourth switching element for forming a path for removing the ripple generated at the node (Q) according to the discharge signal stored in the first capacitor;
a fifth switching element for discharging the discharge signal stored in the first capacitor according to the voltage of the Q node;
a second capacitor for bootstrapping the voltage of the Q node;
a sixth switching element controlled according to the voltage of the node Q to output any one of the plurality of carry clock pulses or one of the plurality of scan clock pulses to an output terminal;
and a seventh switching element which is controlled according to another one of the plurality of carry clock pulses or another one of the plurality of scan clock pulses to discharge the output terminal. delete delete having a plurality of stages,
Each stage is
A node controller for controlling the Q node according to one carry pulse (or start pulse) output from the previous stage and one carry pulse output from the next stage;
a carry pulse output unit for receiving two carry clock pulses among the plurality of carry clock pulses and outputting a carry pulse according to the voltage of the Q node of the node controller;
a scan pulse output unit for receiving two scan clock pulses among a plurality of scan clock pulses and outputting a scan pulse according to the voltage of the Q node of the node controller;
The carry pulse output unit or scan pulse output unit,
A first switching device that is controlled according to the carry pulse output from the carry pulse output unit of the previous stage to charge the carry pulse to the node (Q);
A first capacitor for storing a discharge signal input from the outside;
a fourth switching element for forming a path for removing the ripple generated at the node (Q) according to the discharge signal stored in the first capacitor;
a fifth switching element for discharging the discharge signal stored in the first capacitor according to the voltage of the Q node;
a second capacitor for bootstrapping the voltage of the Q node;
a sixth switching element controlled according to the voltage of the node Q to output any one of the plurality of carry clock pulses or one of the plurality of scan clock pulses to an output terminal;
and a seventh switching element which is controlled according to another one of the plurality of carry clock pulses or another one of the plurality of scan clock pulses to discharge the output terminal. having a plurality of stages,
Each stage is
Carry pulse receiving one carry pulse (or start pulse) output from the previous stage, one carry pulse output from the rear stage, and two carry clock pulses among the plurality of carry clock pulses to output a carry pulse output and
A scan pulse for outputting a scan pulse by receiving one carry pulse (or start pulse) output from the previous stage, one carry pulse output from the rear stage, and two scan clock pulses among the plurality of scan clock pulses an output unit,
The carry pulse output unit or the scan pulse output unit,
A first switching device that is controlled according to the carry pulse output from the carry pulse output unit of the previous stage to charge the carry pulse to the node (Q);
a second switching element which is controlled according to the carry pulse output from the carry pulse output unit of the subsequent stage to discharge the node Q;
a third switching element controlled according to a reset signal (Reset) or a start signal (Vst) to discharge the node (Q);
A first capacitor for storing a discharge signal input from the outside;
a fourth switching element for forming a path for removing the ripple generated at the node (Q) according to the discharge signal stored in the first capacitor;
a fifth switching element for discharging the discharge signal stored in the first capacitor according to the voltage of the Q node;
a second capacitor for bootstrapping the voltage of the Q node;
a sixth switching element controlled according to the voltage of the node Q to output any one of the plurality of carry clock pulses or one of the plurality of scan clock pulses to an output terminal;
and a seventh switching element which is controlled according to another one of the plurality of carry clock pulses or another one of the plurality of scan clock pulses to discharge the output terminal. delete delete having a plurality of stages,
Each stage is
A node controller for controlling the Q node according to the carry pulse (or start pulse (Vst)) output from the previous stage and the carry pulse output from the rear stage;
a carry pulse output unit for receiving two carry clock pulses among a plurality of carry clock pulses and outputting a carry pulse according to the voltage of the Q node of the node controller;
a scan pulse output unit for receiving two scan clock pulses among a plurality of scan clock pulses and outputting a scan pulse according to the voltage of the Q node of the node controller;
The carry pulse output unit or the scan pulse output unit,
A first switching element controlled according to the carry pulse output from the carry pulse output unit of the previous stage to charge the carry pulse to the node (Q);
a second switching element that is controlled according to the carry pulse output from the carry pulse output unit of the subsequent stage to discharge the node Q;
a third switching element controlled according to a reset signal (Reset) or a start signal (Vst) to discharge the node (Q);
A first capacitor for storing a discharge signal input from the outside;
a fourth switching element forming a path for removing the ripple generated at the node (Q) according to the discharge signal stored in the first capacitor;
a fifth switching element for discharging the discharge signal stored in the first capacitor according to the voltage of the Q node;
a second capacitor for bootstrapping the voltage of the Q node;
a sixth switching element controlled according to the voltage of the node Q to output any one of the plurality of carry clock pulses or one of the plurality of scan clock pulses to an output terminal;
and a seventh switching element which is controlled according to another one of the plurality of carry clock pulses or another one of the plurality of scan clock pulses to discharge the output terminal. a display panel including a plurality of gate lines and a plurality of data lines intersecting the respective gate lines;
a gate driver including the shift register of claim 1 , 4 , 5 or 8 and sequentially driving the plurality of gate lines;
A plurality of carry clock pulses and a plurality of scan clock pulses are supplied to the gate driver, but when a still image is partially present on a moving image screen, when driving gate lines corresponding to the moving image, the plurality of carry clock pulses are supplied. A clock pulse and a plurality of scan clock pulses are supplied at a frequency for driving a moving image, and when the gate lines corresponding to the still image are driven, the plurality of carry clock pulses are supplied at a frequency for driving a moving image, and the A liquid crystal display comprising a timing controller for supplying a plurality of scan clock pulses at a frequency lower than a frequency for driving the moving image.

Images