KR20200049251A - A display conmprising a shift register - Google Patents

Abstract

The present invention relates to a display device including a shift register and, more specifically, to a display device including a shift register capable of implementing an ultra-narrow bezel by reducing the number of transistors (TFT) of a gate in panel (GIP). The display device comprises: a start circuit unit; a reset circuit unit; a Q1 node and a Q2 node; an inverter circuit unit; a first output circuit unit; and a second output circuit unit.

Description

Display device including shift register {A display conmprising a shift register}

The present invention relates to a display device including a shift register, and more specifically, to reduce the number of transistors (TFT) of a gate in panel (GIP), and includes a shift register capable of realizing a very small narrow bezel. It relates to a display device.

A typical display device includes a pixel circuit formed for each pixel, and the pixel circuit emits light by controlling a magnitude of a current flowing through the light emitting element by switching a driving transistor according to a data voltage.

The gate driving circuit of such a display device includes a shift register for sequentially supplying gate pulses to a plurality of gate lines. The shift register includes a plurality of stages including a plurality of transistors, and the stages are connected cascade to each other to sequentially output gate pulses.

Recently, a gate in panel (GIP) structure in which a transistor constituting a shift resistor of a gate driving circuit is embedded in a substrate of a display panel in the form of a thin film transistor has been applied.

Each stage includes a Q node and a QB node, and in order to charge and discharge the Q node and the QB node, a start circuit portion connected to a start pulse received from a previous stage, a reset circuit portion connected to a reset pulse received from a next stage, An inverter circuit portion for inverting the Q node and the QB node, an output circuit portion controlled by the Q node and outputting an output voltage is required. In addition, several transistors are required in each circuit, and in the case of oxide GIP, additional transistors are needed to prevent leakage current.

As a result, a large number of transistors are required for each stage, and a myriad of stages are required from the viewpoint of the entire display device, which increases the size of the bezel.

An object of the present application is to provide a display device including a shift register capable of implementing an ultra-small narrow bezel by reducing the number of transistors of the GIP.

The present invention is a display device including a shift register, a start circuit unit for receiving a start pulse; A reset circuit unit receiving a reset pulse; A Q1 node and a Q2 node to which a voltage is applied by the start circuit unit and a voltage is discharged by the reset circuit unit; An inverter circuit unit that inverts voltages applied to the Q1 node and the Q2 node and outputs the QB node; A first output circuit unit outputting a first output by the Q1 node; And a second output circuit part outputting a second output by the Q2 node. A display device including a shift register is provided.

It further includes a start sink TFT controlled by the start pulse and connected between the Q1 node and the Q2 node.

When the start pulse is at the gate-on voltage level, the start sink TFT is turned on and the Q1 node and the Q2 node are synchronized to charge the voltage by the start circuit section.

And a reset sink TFT controlled by the reset pulse and connected between the Q1 node and the Q2 node.

When the reset pulse is at the gate-on voltage level, the reset sink TFT is turned on and the Q1 node and the Q2 node are synchronized to discharge the voltage by the reset circuit portion.

It further includes a QB sink TFT controlled by the QB node and connected between the Q1 node and the Q2 node.

When a gate-on voltage level is applied to the QB node by the inverter circuit unit, the QB sink TFT is turned on and the Q1 node and the Q2 node are synchronized to maintain a low voltage state by the reset circuit unit.

The start circuit portion includes: a first start TFT controlled by the start pulse and connected to the Q1 node; A second start TFT controlled by the start pulse and connected between the start pulse and the first start TFT; And a third start TFT controlled by the Q1 node and connected between the high voltage and the first start TFT.

The reset circuit portion may include: a first reset TFT controlled by the reset pulse and connected to the Q1 node; A second reset TFT controlled by the reset pulse and connected between the first reset TFT and a low voltage; A third reset TFT controlled by the QB node and connected to the Q1 node; And a fourth reset TFT controlled by the QB node and connected between the third reset TFT and the low voltage.

The inverter circuit portion includes: a first inverter TFT controlled by a high voltage and connected to the high voltage; A second inverter TFT controlled by the Q1 node and connected between the first inverter and the Q1 node; A third inverter TFT controlled by the output of the first inverter TFT and connected between the high voltage and the QB node; And a fourth inverter TFT controlled by the Q1 node and connected between the QB node and a low voltage.

The first output circuit portion includes: a first pull-up TFT controlled by the Q1 node and connected between a first clock and a first output; A first capacitor connected between a gate electrode and a source electrode of the first pull-up TFT; And a first pull-down TFT controlled by the QB node and connected between a low voltage and the first output, wherein the second output circuitry is: controlled by the Q2 node and between the second clock and the second output. A second pull-up TFT connected; A second capacitor connected between a gate electrode and a source electrode of the second pull-up TFT; And a second pull-down TFT controlled by the QB node and connected between the low voltage and the second output.

The capacity of the first capacitor is larger than that of the second capacitor.

An additional capacitor is connected to the Q2 node.

According to the present invention, the number of transistors of the GIP can be reduced.

In addition, according to the present invention, an ultra-small narrow bezel can be implemented.

In addition, according to the present invention, even if the resolution of the display device is high, it is possible to escape the limitation of the vertical design space.

Further, according to the present invention, the complexity of the GIP circuit can be lowered and the area can be reduced.

1 is a view showing a display device according to an exemplary embodiment of the present invention.
2 is a view showing a gate driver according to the present invention.
3 is a view comparing a shift register according to the present invention with a conventional shift register.
4 is a view showing a large shift register according to the present invention in FIG.
5 is a view for explaining a start circuit part in a shift register according to the present invention.
6 is a view for explaining a reset circuit unit in the shift register according to the present invention.
7 is a view for explaining an inverter circuit portion in the shift register according to the present invention.
8 is a view for explaining three sink TFTs and output circuits in a shift register according to the present invention.
9 is a view for explaining a shift register according to the present invention.
10 is a timing diagram for explaining the operation of the shift register according to the present invention.
11 is a view for explaining the voltage of the Q1 node and the Q2 node according to the present invention.

Hereinafter, with reference to the accompanying drawings, specific details for the practice of the present invention will be described.

1 is a view showing a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel (PANEL), a data driver (DD), a gate driver (GD), and a timing controller (TC).

The display panel PANEL includes a plurality of pixels PXL, i horizontally and j vertically. The display panel PANEL is connected to the data driver DD through i data lines DL1 to DLi. The display panel PANEL is connected to the gate driver GD through j gate lines GL1 to GLj. That is, j pixels PXL arranged along one vertical line are commonly connected to one data line DL1, DL2, and the like. Further, i pixels PXL arranged along one horizontal line are commonly connected to one gate line GL1, GL2, and the like. The plurality of pixels PXL includes a plurality of red pixels R for displaying a red image, a plurality of green pixels G for displaying a green image, and a plurality of blue pixels B for displaying a blue image. Includes The plurality of pixels PXL are arranged in a matrix form on the display unit of the display panel PANEL. Each of the plurality of pixels PXL includes a thin film transistor (TFT) and a pixel electrode. The gate electrode of the thin film transistor is connected to the gate line to which the pixel is connected, the drain electrode of the thin film transistor is connected to the data line to which the pixel is connected, and the source electrode of the thin film transistor is connected to the pixel electrode.

The display panel PANEL is implemented as a liquid crystal display panel or an organic light emitting display panel according to the configuration of the pixel circuit of the pixel PXL. For example, when the display panel (PANEL) is implemented as a liquid crystal display panel, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, a FFS (Fringe Field Switching) mode, or an ECB (Electrically) Controlled Birefringence) mode. As another example, when the display panel (PANEL) is implemented as an organic light emitting display panel, the display panel (PANEL) is operated in a top-emission method or a bottom-emission method. A liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, or a plasma display panel may be selected as the display panel (PANEL) of the display device. However, it should be understood that the present invention is not limited to any one.

According to one embodiment, the pixels PXL may be formed in a stripe structure on the display panel PANEL. In this case, one pixel PXL may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and further may include a white sub-pixel.

According to another embodiment, the pixels PXL may be formed in a pentile structure on the display panel PANEL. In this case, one pixel PXL may include one red sub-pixel, two green sub-pixels, and one blue sub-pixel arranged in a planar polygonal shape. For example, the pixels PXL having a pentile structure may be arranged such that one red sub-pixel, two green pixels, and one blue sub-pixel have a flat octagonal shape, in which case the blue sub-pixel is It has the largest size and the green sub-pixel may have the smallest size.

Each pixel operates in the order of an initialization section, a sampling section, an offset voltage forming section, a data writing section, and a light emitting section, and emits light by a data current corresponding to the data voltage supplied to the data line DL.

The data driver DD transmits i image data for displaying an image to i data lines DL1 to DLi. The data driver DD receives image data from the timing controller TC and transmits the image data to the data lines DL1 to DLi. That is, the data driver DD displays red, green, and blue image data corresponding to i pixels of one horizontal line (GL1, GL2, etc.) driven by the gate driver GD data lines DL1 to DLi. ) To the display panel (PANEL). At this time, the data driver DD may divide the i image data twice in one horizontal period 1H and sequentially output the data. That is, some of the i image data are simultaneously output for the first half period (1 / 2H) of one horizontal period, and simultaneously for the second half period (2 / 2H) of one horizontal period.

The gate driver GD sequentially drives j gate lines GL1 to GLj during one frame period, i pixels PXL commonly connected to a corresponding gate line for each horizontal period in which each gate line is driven. ). The gate driver GD sequentially supplies gate signals to each of the gate lines GL1 to GLi. In addition, the gate driver GD may supply a control signal having a voltage level determined for each of the initialization period, sampling period, offset voltage formation period, data writing period, and emission period of each pixel PXL to each pixel PXL. have. The control signal may include an initialization signal, a sampling signal, a scan signal, and a light emission signal.

According to one embodiment, the gate driver GD generates a scan signal whose phase is sequentially shifted while having the same period and supplies it to the gate line. In addition, the gate driver GD generates an initialization signal whose phases are sequentially shifted while having the same period and supplies them to the sensing line. Further, the gate driver GD generates a sampling control signal whose phase is sequentially shifted while having the same period and supplies it to the reference line. In addition, the gate driver GD generates a carry signal in which phases are sequentially shifted while having the same period, and the first gate off voltage level and the second gate having phase differences from each other based on at least two different carry signals. A light emission signal including an off voltage level is generated and supplied to the light emission line.

The gate driver GD may be formed in the non-display areas on the left side and / or the right side of the substrate along with the manufacturing process of the thin film transistor of the pixel PXL. For example, the gate driver GD is formed in the left non-display area of the substrate and operates according to a single feeding method to supply scan control signals to the plurality of gate lines GL. For another example, the gate driver GD is formed in the non-display areas on the left and right sides of the substrate, and operates according to a double feeding method to supply scan control signals to each of the plurality of gate lines GL. have. For another example, the gate driver GD is formed in the non-display areas on the left and right sides of the substrate, and the scan control signal is applied to each of the plurality of gate lines GL operating in accordance with the double-feeding interlacing method. Can supply.

The timing controller TC receives image data from the host system. Data driver (DD) and gate driver (based on timing signals such as vertical sync signal (V_Sync), horizontal sync signal (H_Sync), data enable signal (DE), and main clock signal (Pixel Clock) input from the host system) GD) to control the operation timing.

In addition, the display device according to the present invention is small, medium-sized, such as television, set-top box, navigation, video player, Blu-ray player, personal computer, wearable device, home theater, mobile phone and virtual reality display (VR) Or it can be implemented in large format.

2 is a view showing a gate driver according to the present invention.

Referring to FIG. 2, the gate driver according to the present invention includes a shift register unit SR, clock line units CLKs, and power line units VDD and VSS.

The shift register unit SR includes a plurality of stages ST1 to STn, and each stage ST1 to STn is connected to at least two gate lines. For example, stage ST1 is connected to two gate lines GL1 and GL2, and stage STn is connected to two gate lines GL2n-1 and GL2n. For convenience of description, one stage is illustrated as being connected to two gate lines, and an embodiment in which three or more gate lines are connected to one stage is also to be understood as being included in the technical spirit of the present invention.

Each of the plurality of stages ST1 to STn is enabled in response to the front end output signal (gate start pulse) Vst from the previous stage, and responds to the rear end output signal (or gate reset pulse) Vrst from the subsequent stage. Is reset. To this end, each of the plurality of stages ST1 to STn includes a plurality of thin film transistors including an oxide semiconductor layer. Here, the oxide semiconductor layer may be made of zinc oxide (ZnO), indium zinc oxide (InZnO), or indium gallium zinc oxide (InGaZnO ₄ ).

The clock line unit CLKs includes a plurality of clock signal lines to which a plurality of clock signals whose phases are sequentially delayed is supplied from the timing controller TC. The plurality of clock signal lines are selectively connected to each of the plurality of stages ST1 to STn to supply at least one clock signal to each of the plurality of stages ST1 to STn.

3 is a view comparing a shift register according to the present invention with a conventional shift register.

The left side of Fig. 3 shows a conventional shift register, and the right side shows a shift register according to the present invention.

In the conventional shift register, one stage ST1 or ST2 is provided to output one output Vout1 or Vout2. Specifically, the conventional shift register includes a plurality of stages (ST1, ST2, etc.), each stage includes a Q node and a QB node, and for charging and discharging the Q node and the QB node, a start circuit unit ( Ts), a reset circuit portion Tr, an inverter circuit portion INV, and an output circuit portion OC. Consequently, a conventional shift register requires one stage to output one output (Vout1 or Vout2), and two stages to output two outputs (Vout2 and Vout2).

In contrast, the shift register according to the present invention is provided with one stage ST1 to output two outputs Vout1 and Vout2. Specifically, the shift register according to the present invention includes a plurality of stages (ST1, etc.), each stage includes two Q nodes (Q1, Q2) and one QB node, and the Q nodes (Q1, Q2) ) And a QB node for charging and discharging, including one start circuit part Ts, one reset circuit part Tr, one inverter circuit part INV, and two output circuit parts OC1 and OC2. Specifically, the start circuit unit Ts receives the start pulse Vst received from the previous stage to charge the Q nodes Q1 and Q2. At this time, the QB node is maintained at a low voltage by the inverter circuit portion INV. In addition, the reset circuit unit Tr receives the reset pulse Vrst received from the subsequent stage and discharges the Q node while simultaneously maintaining the low voltage of the Q node. The inverter circuit unit INV is connected between the Q nodes Q1 and Q2 and the QB node, and inverts the voltage applied to the Q nodes Q1 and Q2 and applies them to the QB node. The output circuit units OC1 and OC2 are controlled by the Q nodes Q1 and Q2 and output the applied clock voltages to the outputs Vout1 and Vout2.

Further, the shift register according to the present invention has three TFTs between the Q1 node and the Q2 node. These three TFTs are start sync TFT (Tssync) for switching the start pulse between Q1 node and Q2 node, reset sync TFT (Trsync) for switching the reset pulse between Q1 node and Q2 node, and QB node as Q1 node And a QB sink TFT (Tqbsync) for switching between and Q2 nodes. Specifically, the start sink TFT (Tssync) is controlled by the start pulse Vst and is connected between the Q1 node and the Q2 node. The reset sink TFT (Trsync) is controlled by a reset pulse (Vrst), and is connected between the Q1 node and the Q2 node. The QB sink TFT (Tqbsync) is controlled by the QB node and connected between the Q1 node and the Q2 node. The detailed operation of these three TFTs will be described later. Consequently, the shift register according to the present invention requires only one stage to output two outputs (Vout1 and Vout2).

That is, one stage of the shift register according to the present invention is a structure in which the start circuit unit Ts, the reset circuit unit Tr, the inverter circuit unit INV, and the QB node are shared in two stages of the conventional shift register. . For example, if it is assumed that the start circuit portion Ts includes three TFTs, the reset circuit portion Tr includes four TFTs, and the inverter circuit portion INV includes four TFTs, the present invention In the shift register, three TFTs (Tssync, Trsync, Tqbsync) are added instead of a total of 11 TFTs, so that a total of 8 TFTs can be reduced. Accordingly, the display device including the shift register according to the present invention can realize an ultra-small narrow bezel by reducing the number of transistors of the GIP, and may escape from the limitations of the vertical design space even when the resolution of the display device is increased. In addition, the complexity of the GIP circuit is lowered, and the area of the GIP circuit can be reduced.

4 is a view showing a large shift register according to the present invention in FIG.

The shift register according to the present invention includes a plurality of stages ST1 to STn.

The shift register according to the present invention is provided with one stage ST1 to output two outputs Vout1 and Vout2. Each stage includes two Q nodes (Q1, Q2) and one QB node, and one start circuit (Ts) and one reset circuit for charging and discharging the Q nodes (Q1, Q2) and QB nodes (Tr), one inverter circuit portion INV, and two output circuit portions OC1 and OC2. Specifically, the start circuit unit Ts receives the start pulse Vst received from the previous stage to charge the Q nodes Q1 and Q2. At this time, the QB node is maintained at a low voltage by the inverter circuit portion INV. In addition, the reset circuit unit Tr receives the reset pulse Vrst received from the subsequent stage and discharges the Q nodes Q1 and Q2 while simultaneously maintaining the low voltages of the Q nodes Q1 and Q2. The inverter circuit unit INV is connected between the Q nodes Q1 and Q2 and the QB node, and inverts the voltage applied to the Q nodes Q1 and Q2 and applies them to the QB node. The output circuit units OC1 and OC2 are controlled by the Q nodes Q1 and Q2 and output the applied clock voltages to the outputs Vout1 and Vout2.

Further, the shift register according to the present invention has three TFTs between the Q1 node and the Q2 node. These three TFTs are controlled by a start pulse and include a start sync TFT (Tssync) connecting the Q1 node and the Q2 node. That is, in the start sink TFT (Tssync), the gate electrode is connected to the start pulse Vst, the drain electrode is connected to the Q1 node, and the source electrode is connected to the Q2 node. In addition, the three TFTs are controlled by a reset pulse and include a reset sync TFT (Trsync) connecting the Q1 node and the Q2 node. That is, in the reset sink TFT (Trsync), the gate electrode is connected to the reset pulse Vrst, the drain electrode is connected to the Q1 node, and the source electrode is connected to the Q2 node. In addition, the three TFTs are controlled by the QB node and include a QB sink TFT (Tqbsync) connecting the Q1 node and the Q2 node. That is, the QB sink TFT (Tqbsync) has a gate electrode connected to the QB node, a drain electrode connected to the Q1 node, and a source electrode connected to the Q2 node. The detailed operation of these three sink TFTs will be described later.

5 is a view for explaining a start circuit part in a shift register according to the present invention.

The start circuit unit Ts according to the present invention includes three TFTs (Ts1, Ts2, Ts3), receives a start pulse Vst to charge a voltage to the Q1 node, and receives a high voltage (VDD) to receive the Q1 node. Maintain voltage.

The first start TFT Ts1 is controlled by the start pulse Vst, and is connected between the second start TFT Ts2 and the Q1 node.

The second start TFT Ts2 is controlled by the start pulse Vst, and is connected between the start pulse Vst and the first start TFT Ts1.

The third start TFT Ts3 is controlled by the Q1 node, and is connected between the high voltage VDD and the first start TFT Ts1.

The operation of the start circuit section Ts will be described. When the start pulse Vst is a gate-on voltage level, the first start TFT Ts1 and the second start TFT Ts2 are turned on. Accordingly, a start pulse Vst is applied to the Q1 node. That is, the Q1 node is charged by the start pulse Vst. In addition, the third start TFT (Ts3) is turned on and accordingly the high voltage (VDD) is connected to the Q1 node, so that even if leakage occurs by another TFT, the voltage of the Q1 node can be maintained by the high voltage (VDD). have.

As a result, when the start pulse Vst is applied by the operation of the start circuit unit Ts, the Q1 node is charged.

6 is a view for explaining a reset circuit unit in the shift register according to the present invention.

The reset circuit unit Tr according to the present invention includes four TFTs Tr1, Tr2, Tr3, Tr4, discharges the voltage charged in the Q1 node to a low voltage VSS, and sets the voltage of the Q1 node to a low state. Keep it.

The first reset TFT Tr1 is controlled by a reset pulse Vrst and is connected between the Q1 node and the second reset TFT Tr2.

The second reset TFT Tr2 is controlled by the reset pulse Vrst and is connected between the first reset TFT Tr1 and the low voltage VSS.

The third reset TFT (Tr3) is controlled by the QB node and is connected between the Q1 node and the fourth reset TFT (Tr4).

The fourth reset TFT Tr4 is controlled by the QB node and is connected between the third reset TFT Tr3 and the low voltage VSS.

The operation of the reset circuit portion Tr will be described. When the reset pulse Vrst is at the gate-on voltage level, the first reset TFT Tr1 and the second reset TFT Tr2 are turned on. Accordingly, the Q1 node is connected to the low voltage VSS through the first reset TFT Tr1 and the second reset TFT Tr2, and the voltage charged in the Q1 node is discharged. When the Q1 node is at a low voltage level, a high voltage is applied to the QB node by the inverter, and accordingly, the third reset TFT Tr3 and the fourth reset TFT Tr4 are turned on. Accordingly, since the Q1 node is connected to the low voltage VSS through the third reset TFT Tr3 and the fourth reset TFT Tr4, the low voltage state of the Q1 node is maintained.

As a result, when the reset pulse Vrst is applied by the operation of the reset circuit unit Tr, the Q1 node discharges the charged voltage and maintains the low state.

7 is a view for explaining an inverter circuit portion in the shift register according to the present invention.

The inverter circuit part INV according to the present invention includes four TFTs (Ti1, Ti2, Ti3, Ti4), and inverts the voltage state between the Q1 node and the QB node.

The first inverter TFT Ti1 is controlled by the high voltage VDD and is connected between the high voltage VDD and the second inverter TFT Ti2.

The second inverter TFT (Ti2) is controlled by the Q1 node and is connected between the first inverter TFT (Ti1) and the Q1 node.

The third inverter TFT Ti3 is controlled by the output (source node) of the first inverter TFT Ti1 and is connected between the high voltage VDD and the QB node.

The fourth inverter TFT (Ti4) is controlled by the Q1 node, and is connected between the QB node and the low voltage (VSS).

The operation of the inverter circuit portion INV will be described. When a high voltage is applied to the Q1 node, the fourth inverter TFT (Ti4) is turned on. Accordingly, since the QB node is connected to the low voltage VSS, a low voltage is applied. When a low voltage is applied to the Q1 node, the fourth inverter TFT (Ti4) is turned off, and the second inverter TFT (Ti2) is also turned off. The first inverter TFT (Ti1) is turned on and thereby the third inverter TFT (Ti3) is turned on so that the QB node is connected to the high voltage (VDD), so a high voltage is applied.

As a result, the inverter circuit portion INV inverts the voltage state between the Q1 node and QB.

8 is a view for explaining three sink TFTs and output circuits in a shift register according to the present invention.

The three TFTs in the shift register according to the present invention include a start sync TFT (Tssync), a reset sync TFT (Trsync), and a QB sync TFT (Tqbsync). Further, the output circuit portion in the shift register according to the present invention includes a first output circuit portion OC1 and a second output circuit portion OC2.

The operation of the three sink TFTs (Tssync, Trsync, Tqbsync) will be described.

The start sync TFT (Tssync) is controlled by the start pulse Vst and is connected between the Q1 node and the Q2 node.

The reset sink TFT (Trsync) is controlled by the reset pulse Vrst and is connected between the Q1 node and the Q2 node.

The QB sink TFT (Tqbsync) is controlled by the QB node and connected between the Q1 node and the Q2 node.

When the start pulse Vst is a gate-on voltage level, the start sink TFT Tssync is turned on. As described above, when the start pulse Vst is at the gate-on voltage level, the Q1 node is charged by the start pulse Vst. Since the start sync TFT (Tssync) is turned on, the Q2 node connected to the Q1 node is Q1 It is charged in synchronization with the node.

When the reset pulse Vrst is at the gate-on voltage level, the reset sink TFT Trsync is turned on. As described above, when the reset pulse Vrst is at the gate-on voltage level, the voltage charged in the Q1 node is discharged. Since the reset sink TFT (Trsync) is turned on, the Q2 node connected to the Q1 node is synchronized with the Q1 node. Is discharged.

When the QB node is at a high voltage, the QB sink TFT (Tqbsync) is turned on. As described above, when the reset pulse Vrst is at the gate-on voltage level, the Q1 node and the Q2 node are discharged because the reset sink TFT (Trsync) is turned on. On the other hand, even when the reset pulse Vrst is at the gate-off voltage level, there is a time period in which the discharge of the Q1 node and the Q2 node must be maintained, which is implemented by the QB sink TFT (Tqbsync). Specifically, when the reset pulse Vrst is applied, the Q1 node and the Q2 node are discharged to become a low voltage, and a high voltage is applied to the QB node by the inverter circuit unit INV. The gate electrode of the QB sink TFT (Tqbsync) is connected to the QB node, so that the QB sink TFT (Tqbsync) is turned on. Accordingly, the Q1 node and the Q2 node may be connected to each other by a QB sink TFT (Tqbsync) to maintain a low voltage. That is, the connection of the Q1 node and the Q2 node is also performed in a section in which the reset sink TFT (Trsync) is turned on and then turned off (for example, a section in which the reset pulse Vrst becomes the gate-on voltage level and then becomes the gate-off voltage level). maintain. That is, in the section where the reset pulse Vrst is the gate-on voltage level, the Q1 node and the Q2 node are connected by the reset sink TFT (Trsync) being turned on, and then the reset pulse Vrst is changed to the gate-off voltage level. In the period, the Q1 sync TFT (Tqbsync) is turned on, so that the connection between the Q1 node and the Q2 node is maintained, and the Q1 node and the Q2 node are synchronized to maintain a low voltage.

The operation of the output circuit units OC1 and OC2 will be described.

The first output circuit part OC1 includes a first pull-up TFT Tu1, a first capacitor Cu1, and a first pull-down TFT Td1. The first pull-up TFT Tu1 is controlled by the Q1 node, and is connected between the first clock CLK1 and the first output Vout1. The first capacitor Cu1 is connected between the gate electrode and the source electrode of the first pull-up TFT Tu1. The first pull-down TFT Td1 is controlled by the QB node and is connected between the low voltage VSS and the first output Vout1. When a high voltage is applied to the first clock CLK1 connected to the drain electrode of the first pull-up TFT Tu1 while the Q1 node is charged, an output is generated at the first output Vout1. In this case, during the period in which the first clock CLK1 is at a high voltage, bootstrapping occurs, so the voltage charged in the Q1 node rises. When a high voltage is applied to the QB node, the first pull-down TFT Td1 is turned on, and accordingly, a low voltage VSS is output to the output Vout1.

The second output circuit unit OC2 includes a second pull-up TFT (Tu2), a second capacitor (Cu2), and a second pull-down TFT (Td2). The second pull-up TFT Tu2 is controlled by the Q2 node, and is connected between the second clock CLK2 and the second output Vout2. The second capacitor Cu2 is connected between the gate electrode and the source electrode of the second pull-up TFT Tu2. The second pull-down TFT Td2 is controlled by the QB node and is connected between the low voltage VSS and the second output Vout2. When a high voltage is applied to the second clock CLK2 connected to the drain electrode of the second pull-up TFT Tu2 while the Q2 node is charged, an output is generated at the second output Vout2. In this case, during the period in which the second clock CLK2 is at a high voltage, bootstrapping occurs, so the voltage charged in the Q2 node rises. When the high voltage is applied to the QB node, the second pull-down TFT Td2 is turned on, and accordingly, the low voltage VSS is output to the second output Vout2.

9 is a view for explaining a shift register according to the present invention.

10 is a timing diagram for explaining the operation of the shift register according to the present invention.

The operation of the shift register according to the present invention will be described with reference to FIGS. 9 and 10.

The first clock CLK1 is a signal in which the signals of the gate-on voltage level and the gate-off voltage level are periodically repeated. For example, the first clock CLK1 is a gate-off voltage level in periods 1 and 2 and a gate-on voltage level in period 3. In the subsequent section, this pattern is repeated.

The second clock CLK2 is a signal in which the signals of the gate-on voltage level and the gate-off voltage level are periodically repeated. For example, the second clock CLK2 is a gate-off voltage level in periods 2 and 3 and a gate-on voltage level in period 4. In the subsequent section, this pattern is repeated.

In section 1, the start pulse Vst is a gate-on voltage level. The first start TFT Ts1 and the second start TFT Ts2 are turned on, and accordingly a start pulse Vst is applied to the Q1 node, and the third start TFT Ts3 is turned on. Also, the start sync TFT (Tssync) is turned on.

In the period 2, the start pulse Vst is applied to the Q1 node through the second start TFT Ts2 and the first start TFT Ts2. That is, the Q1 node is charged due to the application of the start pulse Vst. In addition, because the start sink TFT (Tssync) is turned on, the Q2 node connected to the Q1 node is charged in synchronization with the Q1 node.

In the period 3, the first clock CLK1 is a gate-on voltage level. In the period (2), the Q1 node is in a charged state, and since a gate-on voltage is applied to the first clock CLK1 connected to the drain electrode of the pull-up TFT (Tu1), bootstrapping occurs and the voltage charged in the Q1 node rises. An output is generated at the output Vout1.

In the period 4, the second clock CLK2 is a gate-on voltage level. In the period 3, the Q2 node is in the charged state, and since the gate-on voltage is applied to the second clock CLK12 connected to the drain electrode of the pull-up TFT Tu2, bootstrapping occurs and the voltage charged in the Q2 node rises. An output is generated at the output Vout2.

Since the Q1 node and the Q2 node are high voltages in the periods 2 to 4, the QB node becomes a low voltage by the inverter.

In section 5, the reset pulse Vrst is the gate-on voltage level. Accordingly, the first reset TFT (Tr1) and the second TFT (Tr2) are turned on, and the Q1 node is connected to the low voltage (VSS) through the first reset TFT (Tr1) and the second reset TFT (Tr2). , The voltage charged in the Q1 node is discharged. Meanwhile, a high voltage is applied to the QB node by the inverter, and accordingly, the third reset TFT (Tr3) and the fourth reset TFT (T4) are turned on, so that the Q1 node is the third TFT (Tr3) and the fourth Since it is connected to the low voltage VSS through the reset TFT Tr4, the low voltage state of the Q1 node is maintained. In addition, since the reset sink TFT (Trsync) is turned on and the Q1 node and the Q2 node are synchronized, the charged voltage of the Q2 node is also discharged.

In intervals 6 and 7, the high voltage is maintained at the QB node. The QB sink TFT (Tqbsync) is turned on and the connection between the Q1 node and the Q2 node is maintained. Accordingly, since the Q1 node and the Q2 node are connected to the low voltage VSS through the third reset TFT Tr3 and the fourth reset TFT T4, the voltage state can stably maintain the low voltage state.

The on / off operation characteristics of the start sink TFT (Tssync) are turned on in the section 1 where the start pulse Vst is the gate-on voltage level, and the section 2 where the start pulse Vst is the gate-off voltage level. In the section 7 is turned off. Since the Q1 node and the Q2 node are synchronized by the start sink TFT (Tssync) in the period 1, the Q1 node and the Q2 node are synchronized and the voltage is charged in the period 2.

The on / off operation characteristics of the reset sink TFT (Trsync) are turned on in a section 5 where the reset pulse Vrst is a gate-on voltage level, and a section 1 where the reset pulse Vrst is a gate-off voltage level. It is turned off at, (2), (3), (4), (6), (7). In the section 5, the Q1 node and the Q2 node are synchronized by the reset sink TFT (Trsync), so the Q The 1 node and the Q2 node are discharged in synchronization with the charged voltage.

The on-off operation characteristics of the QB sink TFT (Tqbsync) are turned on in sections 5, 6, and 7 where the QB node is a high voltage, and in the section 1 where the QB node is a low voltage, ( 2), (3), (4) is turned off. Since the Q1 node and the Q2 node are synchronized by the QB sink TFT (Tqbsync) in the periods 6 and 7, the Q1 node and the Q2 node are stably maintained in a discharged state with a low voltage.

11 is a view for explaining the voltage of the Q1 node and the Q2 node according to the present invention.

Referring to FIG. 11, the voltage of the Q1 node rises in the section 2 and bootstraps in the section 3. The voltage of the Q2 node rises in section 2 and bootstraps in section 4. This is the same as referring to FIGS. 9 and 10.

In some cases, the magnitude d1 of the Q1 node voltage rising by bootstrapping may be smaller than the magnitude d2 of the Q2 node voltage rising by bootstrapping. This is because, as illustrated in FIG. 9, the start circuit unit Ts, the reset circuit unit Tr, and the inverter circuit unit INV are configured around the Q1 node, and the Q2 node is connected to the Q1 node. That is, the level of bootstrapping is different because the capacitance of the Q1 node directly connected to the components and that of the Q2 node indirectly connected to the components are different.

In order to compensate for this, according to an embodiment of the present invention, the capacity of the capacitors Cu1 and Cu2 connected to the output circuit unit OC may be set differently. For example, the capacity of the first capacitor Cu1 of the output circuit unit OC1 connected to the Q1 node having a low bootstrapping level is equal to that of the second capacitor Cu2 of the output circuit unit OC2 connected to the Q2 node having a high bootstrapping level. It can be set larger than the capacity. According to this embodiment, it is possible to reduce the difference in bootstrapping levels of Q1 and Q2 occurring in FIG. 11.

To compensate for this, according to another embodiment of the present invention, a capacitor can be added to a Q2 node having a high bootstrapping level. That is, a capacitor directly connected to the Q2 node that is only indirectly connected to the components can be added. According to this embodiment, it is possible to reduce the difference in bootstrapping levels of Q1 and Q2 occurring in FIG. 11.

TC: Timing controller
DD: Data driver
GD: Gate driver
PANEL: Display panel
PXL: Pixel
Tssync: Start sync TFT
Trsync: Reset sync TFT
Tqbsync: QB sync TFT

Claims (13)

A display device comprising a shift register,
A start circuit unit that receives a start pulse;
A reset circuit unit receiving a reset pulse;
A Q1 node and a Q2 node to which a voltage is applied by the start circuit unit and a voltage is discharged by the reset circuit unit;
An inverter circuit unit for inverting voltages applied to the Q1 node and the Q2 node and outputting the QB node;
A first output circuit part outputting a first output by the Q1 node; And
Including; a second output circuit for outputting a second output by the Q2 node;
Display device including a shift register. According to claim 1,
And a start sync TFT controlled by the start pulse and connected between the Q1 node and the Q2 node,
Display device including a shift register. According to claim 2,
When the start pulse is a gate-on voltage level, the start sink TFT is turned on and the Q1 node and the Q2 node are synchronized to charge a voltage by the start circuit unit,
Display device including a shift register. According to claim 1,
Further comprising a reset sink TFT controlled by the reset pulse and connected between the Q1 node and the Q2 node,
Display device including a shift register. The method of claim 4,
When the reset pulse is at the gate-on voltage level, the reset sink TFT is turned on and the Q1 node and the Q2 node are synchronized to discharge voltage by the reset circuit portion,
Display device including a shift register. According to claim 1,
Further comprising a QB sink TFT controlled by the QB node and connected between the Q1 node and the Q2 node,
Display device including a shift register. The method of claim 6,
When a gate-on voltage level is applied to the QB node by the inverter circuit unit, the QB sink TFT is turned on and the Q1 node and the Q2 node are synchronized to maintain a low voltage state by the reset circuit unit,
Display device including a shift register. According to claim 1,
The start circuit part:
A first start TFT controlled by the start pulse and connected to the Q1 node;
A second start TFT controlled by the start pulse and connected between the start pulse and the first start TFT; And
Including a third start TFT controlled by the Q1 node and connected between the high voltage and the first start TFT;
Display device including a shift register. According to claim 1,
The reset circuit portion:
A first reset TFT controlled by the reset pulse and connected to the Q1 node;
A second reset TFT controlled by the reset pulse and connected between the first reset TFT and a low voltage;
A third reset TFT controlled by the QB node and connected to the Q1 node; And
And a fourth reset TFT controlled by the QB node and connected between the third reset TFT and the low voltage.
Display device including a shift register. According to claim 1,
The inverter circuit portion:
A first inverter TFT controlled by the high voltage and connected to the high voltage;
A second inverter TFT controlled by the Q1 node and connected between the first inverter and the Q1 node;
A third inverter TFT controlled by the output of the first inverter TFT and connected between the high voltage and the QB node; And
Including; a fourth inverter TFT controlled by the Q1 node and connected between the QB node and a low voltage;
Display device including a shift register. According to claim 1,
The first output circuit portion includes: a first pull-up TFT controlled by the Q1 node and connected between a first clock and a first output; A first capacitor connected between a gate electrode and a source electrode of the first pull-up TFT; And a first pull-down TFT controlled by the QB node and connected between a low voltage and the first output,
The second output circuit portion includes: a second pull-up TFT controlled by the Q2 node and connected between a second clock and a second output; A second capacitor connected between a gate electrode and a source electrode of the second pull-up TFT; And a second pull-down TFT controlled by the QB node and connected between the low voltage and the second output,
Display device including a shift register. The method of claim 11,
The capacity of the first capacitor is larger than the capacity of the second capacitor,
Display device including a shift register. The method of claim 11,
An additional capacitor is connected to the Q2 node,
Display device including a shift register.

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