KR102455584B1 - Organic Light Emitting Diode display panel and Organic Light Emitting Diode display device using the same - Google Patents

Abstract

The present invention relates to a display panel in which a GIP of a gate driving circuit is disposed in a pixel array and an OLED display using the same, wherein the display panel includes data lines and gate lines crossing each other and including sub-pixels disposed at the intersections area; and a plurality of GIPs dispersedly disposed in a plurality of unit pixel areas driven by each gate line in the display area to supply a scan pulse to the corresponding gate line, wherein each of the plurality of GIPs is for outputting a plurality of carry pulses A scan pulse output buffer unit for receiving one of the clock signals and one of the plurality of clock signals for outputting scan pulses and outputting a scan pulse and a carry pulse according to voltages of the first node and the second node, and a carry pulse It includes an output buffer, and a plurality of scan pulse output buffers and a plurality of carry pulse output buffers of the plurality of GIPs are irregularly arranged.

Description

Organic Light Emitting Diode display panel and Organic Light Emitting Diode display device using the same}

The present invention relates to an OLED display panel in which a GIP of a gate driving circuit is disposed in a pixel array and capable of improving image quality due to the GIP arrangement, and an OLED display device using the same.

As the information society develops and various portable electronic devices such as mobile communication terminals and notebook computers develop, the demand for a flat panel display device that can be applied thereto is gradually increasing.

As such a flat panel display, a liquid crystal display (LCD) using liquid crystal and an OLED display using an organic light emitting diode (OLED) are used.

Such flat panel displays include a display panel having a plurality of gate lines and a plurality of data lines to display an image, and a driving circuit for driving the display panel.

Among the display devices, the display panel of the liquid crystal display includes a thin film transistor array substrate on which a thin film transistor array is formed on a glass substrate, a color filter array substrate on which a color filter array is formed on the glass substrate, and the thin film transistor A liquid crystal layer filled between the array substrate and the color filter array substrate is provided.

The thin film transistor array substrate includes a plurality of gate lines GL extending in a first direction and a plurality of data lines DL extending in a second direction perpendicular to the first direction, and each gate line and one sub-pixel area Pixel (P) is defined by each data line. One thin film transistor and a pixel electrode are formed in one sub-pixel area P.

The display panel of the liquid crystal display device generates an electric field in the liquid crystal layer by applying a voltage to an electric field generating electrode (a pixel electrode and a common electrode), and adjusts an arrangement state of liquid crystal molecules in the liquid crystal layer by the electric field to generate incident light. Display an image by controlling the polarization.

In addition, in the display panel of the OLED display among the above display devices, the plurality of gate lines and the plurality of data lines cross to define sub-pixels, and each sub-pixel includes an anode and a cathode and the anode and the cathode An OLED composed of an organic light emitting layer therebetween, and a pixel circuit independently driving the OLED are provided.

The pixel circuit may be configured in various ways, but includes at least one switching TFT, a capacitor, and a driving TFT.

The at least one switching TFT charges the capacitor with a data voltage in response to a scan pulse. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the capacitor.

The display panel for a display device is defined as an active area (AA) providing an image to a user and a non-active area (NA) surrounding the display area (AA).

The driving circuit for driving the display panel includes a gate driving circuit that sequentially supplies a gate pulse (or scan pulse) to the plurality of gate lines of the display panel, and the plurality of data lines of the display panel. and a data driving circuit for supplying data voltages to the data, and a timing controller for supplying image data and various control signals to the gate driving circuit and the data driving circuit.

The gate driving circuit may include at least one gate driving IC, but the display panel is not displayed in the process of forming the plurality of signal lines (gate lines and data lines) and sub-pixels of the display panel. may be formed simultaneously on the region.

That is, a gate-in-panel (hereinafter also referred to as "GIP") method in which the gate driving circuit is directly integrated into the display panel is applied.

The gate driving circuit as described above is configured to include a plurality of stages (hereinafter referred to as "GIP") greater than the number of gate lines in order to sequentially supply scan pulses to each gate line, and improve driving characteristics To do this, oxide semiconductor thin film transistors are used.

That is, the gate driving circuit includes a plurality of stages GIP connected to each other. In addition, each stage GIP is connected to each gate line and receives a clock signal, a gate start signal, a gate high voltage, and a gate low voltage applied from the timing controller, and generates one carry pulse and one scan pulse. It contains an output that generates.

As described above, since the conventional gate driving circuit is directly integrated into the non-display area of the display panel, it is difficult to design a narrow bezel of the flat panel display.

The present invention is intended to solve the above problems in the prior art. It is possible to minimize the bezel, to arrange the GIP in the display area of the display panel regardless of the bezel shape, and to improve the image quality due to the GIP being placed in the display area. An object of the present invention is to provide an OLED display panel that can be used and an OLED display device using the same.

Another object of the present invention is to prevent a block dim or a diagonal dim from being recognized when the GIP is disposed in a display area of a display panel.

According to an aspect of the present invention, an OLED display panel includes: a display area in which data lines and gate lines intersect, and including sub-pixels disposed at the intersections; and a plurality of GIPs dispersedly disposed in a plurality of unit pixel areas driven by each gate line in the display area to supply a scan pulse to the corresponding gate line, wherein each of the plurality of GIPs is for outputting a plurality of carry pulses A scan pulse output buffer unit for receiving one of the clock signals and one of the plurality of clock signals for outputting scan pulses and outputting a scan pulse and a carry pulse according to voltages of the first node and the second node, and a carry pulse An output buffer is provided, and a plurality of scan pulse output buffers and a plurality of carry pulse output buffers of the plurality of GIPs are irregularly arranged.

Here, the GIP selectively stores a set signal according to a line selection signal, and charges the first node to the first constant voltage and discharges the second node to the second constant voltage according to the real-time compensation signal in the blank section of the corresponding stage. The first and second node controllers of the blank section, and the driving section of the corresponding stage, charging the first node with the carry pulse voltage of the previous stage according to the carry pulse of the previous stage, and charging the first node and the first node according to the carry pulse of the rear stage The first to third node controllers for discharging the third node to a second constant voltage and charging the third node to the first constant voltage according to the voltage of the first node, and inverting the voltage of the first node Further comprising: an inverter unit applied to a second node; and a reset unit discharging the first node to a second constant voltage according to a reset signal output from the timing controller during the blank period, the elements of the inverter unit and the blank Elements of the first and second node controllers in the first and second sections, elements of the first to third node controllers in the driving period, and elements of the reset unit are arranged in order, and a plurality of scan pulse output buffers of the plurality of GIPs; A plurality of carry pulse output buffer units are irregularly arranged between the elements of the inverter unit, the elements of the first and second node controllers in the blank section, the elements of the first to third node controllers in the driving period, and the elements of the reset unit. It is characterized in that it is placed as

Each of the plurality of scan pulse output buffers includes a pull-up transistor configured to receive one of the plurality of scan pulse output clock signals and output a scan pulse according to voltages of the first node and the second node, It is characterized in that the pull-up transistor is arranged irregularly.

Each of the plurality of carry pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a carry pulse according to voltages of the first node and the second node, It is characterized in that the pull-up transistor is arranged irregularly.

Each of the plurality of scan pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a scan pulse according to voltages of the first node and the second node, The pull-up transistor may be divided and disposed in parallel in a plurality of unit pixel areas along a corresponding gate line direction.

The first node and the second node, and an output terminal of each scan pulse output buffer unit are sequentially arranged in a first direction of the panel.

In addition, an OLED display device according to the present invention for achieving the above object includes: a display area in which a plurality of data lines and a plurality of gate lines intersect, and including sub-pixels disposed at the intersections; a plurality of source drive ICs dividing the plurality of data lines into a plurality of groups to drive the data lines of each group; and the plurality of display regions are divided into groups driven by each source drive IC, and are dispersedly disposed in unit pixel regions driven by each gate line in each divided display region group to supply scan pulses to the corresponding gate lines. GIPs, each of the plurality of GIPs receives one clock signal from among a plurality of clock signals for outputting carry pulses and one clock signal from among clock signals for outputting a plurality of scan pulses to receive voltages of a first node and a second node A scan pulse output buffer and a carry pulse output buffer for outputting a scan pulse and a carry pulse according to There is this.

In addition, an OLED display device according to the present invention for achieving the above object includes: a display area in which a plurality of data lines and a plurality of gate lines intersect, and including sub-pixels disposed at the intersections; a plurality of source drive ICs dividing the plurality of data lines into a plurality of groups to drive the data lines of each group; and the display area is divided into groups driven by two or more adjacent source drive ICs, and the display area is distributed in unit pixel areas driven by each gate line in each divided display area group, and a scan pulse is applied to the corresponding gate line. and a plurality of GIPs for supplying A scan pulse output buffer unit and a carry pulse output buffer unit outputting a scan pulse and a carry pulse according to the voltage of two nodes, wherein the plurality of scan pulse output buffer units and a plurality of carry pulse output buffer units of the plurality of GIPs are irregularly There is another feature of being placed.

The OLED display panel according to the present invention having the above characteristics and the OLED display device using the same have the following effects.

First, since the GIPs are distributed in the display area, the left and right bezels of the display panel can be minimized compared to the conventional display panel in which the GIPs are configured in the non-display area on the left and right sides of the display area.

Second, when placing one GIP on one gate line (scan line) while arranging the GIP within the display area, it is efficient for uniformity of image quality, etc. .

Third, since the scan pulse output buffer part and the carry pulse output buffer part are irregularly arranged among the components of the GIP, the block dim and the diagonal dim may not be recognized.

Fourth, the elements constituting the GIP can be sufficiently dispersed in the display area because the elements having a relatively large size among the elements of the GIP can be divided and arranged and connected in parallel.

Fifth, since at least three sub-pixel units and the GIP unit are separately arranged in the unit pixel area in the display area, the signal interference phenomenon between the pixel and the GIP can be minimized.

Sixth, since the display area is divided into groups driven by each source drive IC, and elements constituting the GIP are distributed in unit pixel areas driven by each gate line in each divided display area group, each source Signals for driving the GIP can be supplied through the drive IC.

1 is a block diagram schematically showing an OLED display device according to an embodiment of the present invention;
FIG. 2 is a circuit configuration diagram of one sub-pixel in the OLED display device of FIG. 3 ;
3 is a circuit diagram of the (n)th GIP according to the present invention
4 is a configuration diagram of a display area of a display panel according to a first exemplary embodiment of the present invention;
FIG. 5 is a configuration diagram illustrating in more detail two adjacent unit pixels disposed in a display area of the display panel of FIG. 4 ;
6 is an explanatory view showing the arrangement state of the GIP elements according to the first embodiment of the present invention;
7 is an explanatory diagram schematically illustrating an arrangement state of the GIP elements according to the first embodiment of the present invention;
8 is an explanatory diagram schematically illustrating an arrangement state of GIP elements according to a second embodiment of the present invention;
9 is a configuration diagram of a display area of a display panel according to a second exemplary embodiment of the present invention;

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains It is provided to fully understand the scope of the invention, and the invention is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiment of the present invention are exemplary, the present invention is not limited to the matters shown in the drawings. Like reference numerals refer to substantially like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

When "includes", "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, it may be interpreted as the plural unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship between the two components is described as 'on One or more other elements may be interposed between those elements in which 'directly' or 'directly' are not used.

The first, second, etc. may be used to distinguish the components, but the functions or structures of these components are not limited to the ordinal number or component name attached to the front of the component.

The following embodiments can be partially or wholly combined or combined with each other, and technically various interlocking and driving are possible. Each of the embodiments may be implemented independently of each other or may be implemented together in a related relationship.

The circuit of the GIP and the circuit of the sub-pixel according to the present invention may be implemented as a TFT having an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. It should be noted that although the n-type TFT is exemplified in the following embodiments, the present invention is not limited thereto. A TFT is a three-electrode device including a gate, a source and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since carriers are electrons, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type TFT (PMOS), since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed according to the applied voltage. Although transistors constituting the GIP circuit and the pixel circuit are exemplified as n-type TFTs in the following embodiments, the present invention is not limited thereto. Therefore, the invention should not be limited by the source and drain of the TFT in the following description.

A gate pulse output from the GIP circuit swings between a gate-on voltage (Gate High Voltage, VGH) and a gate-off voltage (Gate Low Voltage, VGL). The gate-on voltage VGH is set to a voltage higher than the threshold voltage of the TFT, and the gate-off voltage VGH is set to a voltage lower than the threshold voltage of the TFT. In the case of the n-type TFT, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In the case of the p-type TFT, the gate-on voltage may be a gate low voltage VGL, and the gate-off voltage may be a gate high voltage VGH.

1 is a block diagram schematically showing an OLED display device according to an embodiment of the present invention.

Referring to FIG. 1 , an OLED display device according to the present invention includes a display panel PNL and a driving circuit for providing image data to the display panel PNL.

The display area AA of the display panel PNL includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn that are cross-arranged, and the plurality of data lines DL1 to DLm. and a plurality of sub-pixels arranged in a matrix form by the plurality of gate lines GL1 to GLn. Touch sensors may be further disposed in the display area AA of the display panel PNL.

The plurality of sub-pixels include red (R), green (G), and blue (B) sub-pixels for color implementation, and the red (R), green (G), and blue (B) sub-pixels In addition to the pixels, a white (W) sub-pixel may be further included.

The red (R), green (G), and blue (B) sub-pixels constitute one unit pixel, or the red (R), green (G), blue (B), and white (W) sub-pixels constitute one unit pixel.

In addition, devices (TFTs, capacitors, etc.) constituting the GIP of the gate driving circuit are dispersedly disposed in the unit pixel areas.

That is, devices (TFTs, capacitors, etc.) constituting at least one GIP of the gate driving circuit are dispersedly disposed in a plurality of unit pixel areas disposed on each gate line. Of course, devices (TFTs, capacitors, etc.) constituting a plurality of GIPs may be dispersedly disposed in a plurality of unit pixel areas disposed on each gate line. The specific arrangement method of the GIP will be described later.

The driving circuit includes a data driving circuit for supplying an image data voltage to the data lines DL1 to DLm of the display panel PNL, and a scan pulse synchronized with the image data voltage to the gate lines of the display panel PNL. and a gate driving circuit supplied to GL1 to GLn, and a timing controller (T-CON) for controlling operation timings of the data driving circuit and the gate driving circuit.

The data driving circuit may include one or more source drive ICs (SICs). The source drive IC (SIC) generates a data voltage by converting digital video data of an input image into an analog gamma compensation voltage under the control of the timing controller T-CON, and applies the data voltage to the data lines DL1 to DLm. output as The source drive IC (SIC) may be mounted on a bendable flexible circuit board, for example, on a chip on film (COF) or may be directly attached to a substrate in the non-display area of the display panel PNL through a COG process. .

The COFs are adhered to the pad area of the lower substrate SUBS1 of the display panel PNL and the source PCB SPCB through an anisotropic conductive film (ACF). Input pins of the COFs are electrically connected to output terminals (pads) of the source PCB (SPCB). Output pins of the source COFs COF are electrically connected to data pads formed on the substrate of the display panel PNL through the ACF.

The gate driving circuit receives a start pulse (VST), clock signals (CRCLK, SCCLK), a gate high voltage (VGH), a gate low voltage (VGL), etc. from the timing controller (T-CON) to each gate line ( It includes a plurality of GIPs sequentially outputting scan pulses to GL1 to GLn). The plurality of GIPs sequentially supply scan pulses synchronized with the data voltage to each of the gate lines GL1 to GLn under the control of the timing controller T-CON to generate pixels in one line to which the image data voltage is applied. choose

The timing controller T-CON is mounted on a control PCB CPCB, and the control PCB CPCB and the source PCB SPCB are connected by a flexible flat cable (FFC).

The circuit configuration of one sub-pixel and the circuit of one GIP according to the present invention in the OLED display device according to the present invention are as shown in FIGS. 2 and 3 .

FIG. 2 is a circuit configuration diagram of one sub-pixel in the OLED display device of FIG. 1 , and FIG. 3 is a circuit configuration diagram of the (n)th GIP according to the present invention.

As shown in FIG. 2 , each sub-pixel of the OLED display according to the present invention includes an organic light emitting diode (OLED) and a pixel circuit driving the organic light emitting diode.

The pixel circuit includes first and second switching TFTs T1 and T2, a storage capacitor Cst, and a driving TFT DT.

The first switching TFT T1 charges a data voltage to the storage capacitor Cst in response to a scan pulse Scan. The driving TFT DT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the data voltage charged in the storage capacitor Cst. The second switching TFT T2 senses a threshold voltage and mobility of the driving TFT DT in response to a sensing signal.

The organic light emitting diode OLED may include a first electrode (eg, an anode electrode or a cathode electrode), an organic light emitting layer, and a second electrode (eg, a cathode electrode or an anode electrode).

The storage capacitor Cst is electrically connected between a gate electrode and a source electrode of the driving TFT DT, and applies a data voltage corresponding to the image signal voltage or a voltage corresponding thereto for one frame time. can keep you

2 illustrates the configuration of a 3T1C pixel circuit including three TFTs (T1, T2, DT) and one storage capacitor (Cst), but the present invention is not limited thereto. The pixel circuit is 4T1C (consisting of 4 TFTs and 1 storage capacitor), 4T2C (consisting of 4 TFTs and 2 storage capacitors), 5T1C (consisting of 5 TFTs and 1 storage capacitor), 5T2C (5 TFTs) and two storage capacitors).

On the other hand, the circuit of the (k)-th GIP according to the present invention, as shown in FIG. 3, comprises transistors TA, TB, T3qA, T1B, T1C, T5A, T5B and a capacitor C1, The set signal CP(k) is selectively stored according to the line select pulse (LSP), and the corresponding stage is stored in the blank time according to the real-time compensation signal (VRT; vertical real time). The first and second node (Q, Qb) controllers 21 and 26 in the blank section for charging the first node Q to the first constant voltage GVDD and discharging the second node Qb to the second constant voltage GVSS2 ; Transistors (T1, T1A, T3n, T3nA, T3q, T3, T3A, T5) are configured to drive the corresponding stage according to the carry pulse (CP(k-3)) of the third front stage in the driving section of the first node ( Q) is charged with the carry pulse voltage CP(k-3), and the first node Q and the third node Qh are removed according to the carry pulse CP(k+3) of the third subsequent stage. The first to third node controllers 23 and 25 in the driving period for discharging to the second constant voltage GVSS2 and charging the third node Qh to the first constant voltage GVDD according to the voltage of the first node Q ); an inverter unit 24 including transistors T4, T41, T4q, and T5q and a capacitor C2 to invert the voltage of the first node Q and apply it to the second node Qb; The pull-up transistors T6cr and T6 and the pull-down transistors T7cr and T7 and the bootstrap capacitor C3 are configured to include one clock signal CRCLK(k)) and a plurality of scan signals for outputting a plurality of carry pulses. Receives one of the clock signals for pulse output SCCLK(k), and receives a carry pulse CP(k) and a scan pulse SP according to the voltages of the first node Q and the second node Qb. an output buffer unit 27 for outputting (k)); In addition, the transistors T3nB and T3nC are provided to convert the first node Q to a second constant voltage GVSS2 according to the reset signal RST output from the timing controller during the blank time. and a reset unit 22 for discharging.

In the blank section, the first and second nodes Q and Qb controllers 21 and 26 turn on the transistors TA, TB, and T3q when the line select signal LSP is at a high level to turn on a set signal ( CP(k)) is stored in the capacitor C1.

In the blank section, when the real-time compensation signal VRT is at a high level, the transistors T1C and T5B are turned on to charge the first node Q with a first constant voltage GVDD, and The second node Qb is discharged to the second constant voltage GVSS2.

In the driving period, the first to third node controllers 23 and 25 turn on the transistors T1, T1A, and T5 when the carry pulse CP(k-3) of the third previous stage is at a high level during the driving period. -on, the first node Q is charged with the voltage of the carry pulse CP(k-3) of the third previous stage, and the second node Qb is discharged with a second constant voltage GVSS2. As described above, when the first node Q is charged and the second node Qb is discharged, the transistor T3q is turned on to charge the third node Qh to the first constant voltage GVDD. .

And when the carry pulse CP(k+3) of the third rear stage is at a high level, the transistors T3n and T3nA are turned on to connect the first node Q and the third node Qh to the second Discharge with a constant voltage (GVSS2).

The inverter unit 24 inverts the voltage of the first node Q and applies it to the second node Qb.

In the output buffer unit 27, when the first node Q is at a high level and the second node Qb is at a low level, the pull-up transistor T6cr is turned on and the pull-down transistor T7cr is turned on. -off, one clock signal CRCLK(k) among the plurality of clock signals for outputting carry pulses is output as a carry pulse CP(k). Also, when the first node Q is at a high level and the second node Qb is at a low level, the pull-up transistor T6 is turned on and the pull-down transistor T7 is turned off to turn off the plurality of scans. One clock signal SCCLK(k) among the clock signals for pulse output is output as a scan pulse SP(k).

At this time, when the scan pulse output clock signal SCCLK(k) is applied at a high level, the first node Q is bootstrapped by the bootstrapping capacitor C3 of the output buffer unit 27 . (or coupled) to have a higher potential.

In the state in which the first node Q is bootstrapped as described above, the output buffer unit 27 receives the clock signal for outputting the carry pulse CRCLK(k) and the clock signal for outputting the scan pulse SCCLK(k), respectively. ) as carry pulses CP(k) and scan pulses SP(k), output loss can be prevented.

The reset unit 22 is configured to turn on the transistors T3nB and T3nC when the reset signal RST output from the timing controller 4 is at a high level during the blank time. The first node Q is discharged to the second constant voltage GVSS2.

Although FIG. 3 shows a GIP driven by six phases, the present invention is not limited thereto, and the GIP according to the present invention may be variously configured with four phases, eight phases, or 12 phases.

As shown in FIG. 3 , the GIP includes 25 transistors and 3 capacitors.

Therefore, when one unit element (transistor or capacitor) constituting the circuit of the GIP is distributed in one unit pixel area, the circuit of one GIP for driving one gate line (scan line) is connected to the corresponding gate line. may be disposed in unit pixels driven by

4 is a block diagram of a display area of a display panel according to a first exemplary embodiment of the present invention, and FIG. 5 is a block diagram illustrating in more detail two adjacent unit pixels disposed in the display area of the display panel of FIG. 4 .

4 and 5 illustrate that the unit pixel is composed of red (R), green (G), blue (B), and white (W) sub-pixels, but the present invention is not limited thereto. G) and blue (B) sub-pixels.

The unit pixel area of the display area of the display panel according to the present invention includes at least three sub-pixel portions (R, G, B, W) 33 , a GIP portion 31 , and a GIP internal connection wiring portion 32 , etc. are separated

The at least three sub-pixel units R, G, B, and W 33 include a plurality of data lines DL1 to DLm, a plurality of reference voltage lines Vref, and first and second constant voltage lines EVDD and EVSS. ) are arranged in a vertical direction, and a plurality of gate lines (scan lines) are arranged in a horizontal direction.

The GIP unit 31 corresponds to one unit element (transistor or capacitor) constituting the circuit of the GIP. That is, in a unit pixel region composed of red (R), green (G), blue (B), and white (W) sub-pixels, one unit element (transistor) constituting the circuit of the GIP shown in FIG. 3 . or capacitors) are distributed.

That is, one GIP for driving one gate line (scan line) is dispersedly disposed in a plurality of unit pixel areas driven by the corresponding gate line (scan line).

Of course, two or more GIPs for driving one gate line (scan line) may be distributed in a plurality of unit pixel areas driven by the corresponding gate line (scan line).

If one GIP is disposed, the elements (transistors or capacitors) constituting the GIP are distributed in a plurality of unit pixel areas in the middle among a plurality of unit pixel areas driven by a corresponding gate line (scan line). It is preferable to place

If two GIPs for driving one gate line (scan line) are disposed, each of the plurality of unit pixel areas on both edges of the plurality of unit pixels driven by the corresponding gate line (scan line) It is preferable to distribute the elements (transistors or capacitors) constituting the GIP.

In addition, although it is illustrated that the GIP unit 31 is disposed in all unit pixel areas in FIGS. 4 and 5 , the present invention is not limited thereto, and the GIP unit 31 may not be disposed in some unit pixel areas.

As shown in FIG. 3 , the GIP internal connection wiring unit 32 is an area in which connection wirings (Q node, QB node, device and device connection line, etc.) connecting each device of the GIP are disposed.

In addition, the arrangement positions of the at least three sub-pixel units 33 , the GIP unit 31 , and the GIP internal connection wiring unit 32 may be varied.

6 is an explanatory diagram illustrating an arrangement state of the GIP elements according to the first embodiment of the present invention, and FIG. 7 is an explanatory diagram schematically illustrating the arrangement state of the GIP elements according to the first embodiment of the present invention. .

First, as described in FIG. 3 , the circuit of the GIP according to the present invention includes the first and second node (Q, Qb) controllers 21 and 26 in the blank section, and the first to third node controllers 23 in the driving section. , 25 , an inverter unit 24 , an output buffer unit 27 , and a reset unit 22 .

Here, the output buffer unit 27 includes a carry pulse output buffer unit CRCLK composed of the pull-up transistor T6cr and the pull-down transistor T7cr for outputting a carry pulse CP(k), and the pull-up transistor It is divided into a scan pulse output buffer unit composed of T6, the pull-down transistor T7, and the bootstrapping capacitor C3 and outputting a scan pulse SP(k).

Accordingly, in disposing each element of the GIP in the display area, as shown in FIG. 6 , the elements T6 , T7 , and C3 of the scan pulse output buffer unit SCCLK of the output buffer unit 27 . first, then the elements of the inverter unit 24, the elements of the first and second nodes Q and Qb of the blank section, the elements of the controllers 21 and 26, and the output buffer unit 27. When the elements T6cr and T7cr of the carry pulse output buffer unit CRCLK are arranged in the order of the first to third node controllers 23 and 25 and the reset unit 22 in the driving period, the GIP internal connection wiring unit ( 32) can be simplified.

7 illustrates a circuit configuration in which one unit element (transistor or capacitor) constituting the circuit of the GIP is distributed in one unit pixel area.

Accordingly, one GIP circuit for driving the corresponding gate line is disposed in unit pixel areas of one horizontal line driven by one gate line (scan line), and a plurality of GIPs are illustrated.

For the sake of simplicity, it shows that the gate driving circuit is driven in 6 phases, and 6 GIPs are shown.

That is, the clock signal SCCLK1 for the first scan pulse is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the first GIP, and the pull-up of the carry pulse output buffer unit CRCLK of the first GIP is applied. The clock signal CRCLK1 for the first carry pulse is applied to the source electrode of the transistor T6cr.

The second scan pulse clock signal SCCLK2 is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the second GIP, and the pull-up transistor (CRCLK) of the carry pulse output buffer unit CRCLK of the second GIP is applied. T6cr), the clock signal CRCLK2 for the second carry pulse is applied to the source electrode.

The third scan pulse clock signal SCCLK3 is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the third GIP, and the pull-up transistor (CRCLK) of the carry pulse output buffer unit CRCLK of the third GIP is applied. T6cr), the clock signal CRCLK3 for the third carry pulse is applied to the source electrode.

The fourth scan pulse clock signal SCCLK4 is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the fourth GIP, and the pull-up transistor ( T6cr), the clock signal CRCLK4 for the fourth carry pulse is applied to the source electrode.

The clock signal SCCLK5 for the fifth scan pulse is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the fifth GIP, and the pull-up of the carry pulse output buffer unit CRCLK of the fifth GIP is applied. The clock signal CRCLK5 for the fifth carry pulse is applied to the source electrode of the transistor T6cr.

The clock signal SCCLK6 for the sixth scan pulse is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the sixth GIP, and the pull-up of the carry pulse output buffer unit CRCLK of the sixth GIP is applied. The clock signal CRCLK6 for the sixth carry pulse is applied to the source electrode of the transistor T6cr.

In addition, the blank section first and second node (Q, Qb) control section (21, 26), the driving section first to third node control section (23, 25), the inverter section 24, the reset Signal lines for supplying constant voltages GVDD and GVSS and various control signals VRT, RST, and LSP are also connected to each element of the unit 22 .

That is, in the horizontal direction of the display panel, not only the gate line (not shown), but also the first node Q and the second node Qb of the GIP and the output terminal Scout of the scan pulse output buffer unit SCCLK (k)) is arranged consecutively.

In addition, in the vertical direction of the display panel, the scan pulse clock signal lines SCCLK1 to SCCLK6, the carry pulse clock signal lines CRCLK1 to CRCLK6, constant voltage signal lines GVDD, GVSS0 to GVSS2, and various Control signal (VRT, RST, LSP) supply lines and the like are arranged.

7, the bootstrapping capacitor (C3 of FIG. 3) of the scan pulse output buffer unit SCCLK of each GIP is not shown. However, as shown in FIG. 3 , the bootstrapping capacitor C3 of the scan pulse output buffer unit SCCLK is connected to the first node Q and the output terminal SP(k) of the scan pulse output buffer unit SCCLK. ) are placed between

Accordingly, in FIG. 7 , the bootstrapping capacitor (C3 in FIG. 3 ) of the scan pulse output buffer unit SCCLK of each GIP is connected to the first node Q of the corresponding GIP and the scan pulse output buffer unit SCCLK of the corresponding GIP. It may be disposed between the output terminals SCout.

However, as shown in FIGS. 6 and 7 , when each element of the GIP is disposed in the display area, a block dim phenomenon in which a dim phenomenon is recognized for each block or a dim phenomenon in an oblique direction This perceived oblique dim phenomenon occurred.

As a result of analyzing the cause, the elements constituting the scan pulse output buffer unit SCCLK and the carry pulse output buffer unit CRCLK to which the clock signals SCCLK1 to SCCLK6 and CRCLK1 to CRCLK6 having relatively high high frequency and voltage are applied It could be recognized that they were caused by being concentrated in a certain area.

Accordingly, the elements constituting the scan pulse output buffer unit and the carry pulse output buffer unit may be irregularly disposed on the front surface of the panel to prevent block dims and diagonal dims from being recognized.

8 is an explanatory diagram schematically illustrating an arrangement state of GIP elements according to a second embodiment of the present invention.

As shown in FIG. 8 , the arrangement state of the GIP elements according to the second embodiment of the present invention is basically the elements of the inverter unit 24 and the first and second nodes Q and Qb in the blank section. ) elements of the control unit 21 and 26 , the elements of the first to third node controllers 23 and 25 d of the driving section, and the elements of the reset unit 22 are arranged in this order.

Then, the elements of the scan pulse output buffer unit SCCLK and the elements of the carry pulse output buffer unit CRCLK are combined with the elements of the inverter unit 24 and the first and second nodes Q and Qb of the blank section. ) elements of the controllers 21 and 26 , elements of the first to third node controllers 23 and 25 of the driving period, and elements of the reset unit 22 are arranged irregularly.

That is, as described in FIG. 7 , the clock signal SCCLK1 for the first scan pulse is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the first GIP, and the scan pulse of the second GIP The clock signal SCCLK2 for the second scan pulse is applied to the source electrode of the pull-up transistor T6 of the output buffer unit SCCLK, and the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the third GIP is applied. A clock signal SCCLK3 for a third scan pulse is applied to the , and a clock signal SCCLK4 for a fourth scan pulse is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the fourth GIP, The clock signal SCCLK5 for the fifth scan pulse is applied to the source electrode of the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the fifth GIP, and the pull-up of the scan pulse output buffer unit SCCLK of the sixth GIP is applied. It is assumed that the clock signal SCCLK6 for the sixth scan pulse is applied to the source electrode of the transistor T6.

In addition, the clock signal CRCLK1 for the first carry pulse is applied to the source electrode of the pull-up transistor T6cr of the carry pulse output buffer unit CRCLK of the first GIP, and the pull-up of the carry pulse output buffer unit CRCLK of the second GIP is applied. The clock signal CRCLK2 for the second carry pulse is applied to the source electrode of the transistor T6cr, and the clock signal for the third carry pulse is applied to the source electrode of the pull-up transistor T6cr of the carry pulse output buffer CRCLK of the third GIP. (CRCLK3) is applied, the fourth carry pulse clock signal CRCLK4 is applied to the source electrode of the pull-up transistor T6cr of the carry pulse output buffer unit CRCLK of the fourth GIP, and the carry pulse output buffer of the fifth GIP The clock signal CRCLK5 for the fifth carry pulse is applied to the source electrode of the pull-up transistor T6cr of the negative CRCLK, and to the source electrode of the pull-up transistor T6cr of the carry pulse output buffer CRCLK of the sixth GIP. It is assumed that the clock signal CRCLK6 for the sixth carry pulse is applied.

Under this assumption, the elements of the scan pulse output buffer unit SCCLK and the elements of the carry pulse output buffer unit CRCLK are connected to the elements of the inverter unit 24, the first and second nodes of the blank section ( Q, Qb) When disposing between the elements of the controllers 21 and 26 , the elements of the first to third node controllers 23 and 25 of the driving period and the elements of the reset unit 22 , Arrange the order irregularly.

This will be described in detail as follows.

As shown in FIG. 8 , the pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the first GIP to which the clock signal SCCLK1 for the first scan pulse is applied is formed in the first and second blank sections of the first GIP. The two nodes Q and Qb are disposed between the two transistors Ta and Tb of the control unit 21 .

The pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the second GIP to which the clock signal SCCLK2 for the second scan pulse is applied is the transistor T4 and the capacitor C2 of the inverter unit 24 of the second GIP. ) are placed between

The pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the third GIP to which the third scan pulse clock signal SCCLK3 is applied is the pull-down transistor T7 of the scan pulse output buffer unit SCCLK of the third GIP and It is disposed between the transistors T5q of the inverter unit 24 .

The pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the fourth GIP to which the fourth scan pulse clock signal SCCLK4 is applied is the first and second nodes Q and Qb of the blank section of the fourth GIP. (21) is disposed between the transistor T3qa and the capacitor C1.

The pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the fifth GIP to which the fifth scan pulse clock signal SCCLK5 is applied is connected to the transistor T4q of the inverter unit 24 of the fifth GIP and the The blank section is disposed between the first and second nodes Q and Qb and the transistor T5a of the controller 26 .

The pull-up transistor T6 of the scan pulse output buffer unit SCCLK of the sixth GIP to which the clock signal for the sixth scan pulse SCCLK6 is applied includes two transistors T5q of the inverter unit 24 of the sixth GIP; T4l).

In addition, the pull-up transistor T6cr of the carry pulse output buffer CRCLK of the first GIP to which the clock signal CRCLK1 for the first carry pulse is applied is connected to the first to third node controllers 23, 25) between the two transistors T1a and T3q.

The pull-up transistor T6cr of the carry pulse output buffer CRCLK of the second GIP to which the second carry pulse clock signal CRCLK2 is applied is a transistor of the first to third node controller 23 of the driving period of the second GIP. It is disposed between T3a and the transistor T3nb of the reset section 22 .

The pull-up transistor T6cr of the carry pulse output buffer CRCLK of the third GIP to which the third carry pulse clock signal CRCLK3 is applied is the pull-down transistor T7cr of the carry pulse output buffer CRCLK of the third GIP and It is disposed between the transistors T3n or T3na of the first to third node controllers 23 and 25 in the driving period.

The pull-up transistor T6cr of the carry pulse output buffer CRCLK of the fourth GIP to which the clock signal CRCLK4 for the fourth carry pulse is applied has two transistors T3nb and T3nc of the reset unit 22 of the fourth GIP. ) are placed between

The pull-up transistor T6cr of the carry pulse output buffer CRCLK of the fifth GIP to which the clock signal CRCLK5 for the fifth carry pulse is applied is the first to third node controller 23 of the driving period of the fifth GIP; 25) between the two transistors T3q and T3.

The pull-up transistor T6cr of the carry pulse output buffer CRCLK of the sixth GIP to which the sixth carry pulse clock signal CRCLK6 is applied is connected to the first and second nodes Q and Qb of the blank period of the sixth GIP. ) is disposed between the transistor Ta of the control unit 21 and the pull-down transistor T7cr of the carry pulse output buffer unit CRCLK.

The arrangement state of the GIP elements of FIG. 8 shows an embodiment for explaining that the elements of the scan pulse output buffer unit SCCLK and the elements of the carry pulse output buffer unit CRCLK are irregularly arranged. As such, it is not limited thereto.

That is, the elements of the inverter unit 24, the elements of the first and second node (Q, Qb) controllers 21 and 26 in the blank section, and the first to third node controllers 23 and 25 in the driving section ) d elements and the arrangement order of the elements of the reset unit 22 may be different, and the pull-up transistor T6c of the scan pulse output buffer unit SCCLK of each GIP and the carry pulse output buffer unit of each GIP ( The arrangement order of the pull-up transistor T6cr of CRCLK) can also be variously changed.

Similarly, as shown in FIG. 8 , in the horizontal direction of the display panel, the first node Q, the second node Qb, and the scan pulse output buffer of the GIP as well as the gate line (not shown) The output terminal Scout(k) of the sub SCCLK is arranged continuously.

In addition, in the vertical direction of the display panel, the scan pulse clock signal lines SCCLK1 to SCCLK6, the carry pulse clock signal lines CRCLK1 to CRCLK6, constant voltage signal lines GVDD, GVSS0 to GVSS2, and various Control signal (VRT, RST, LSP) supply lines and the like are arranged.

8, the bootstrapping capacitor (C3 of FIG. 3) of the scan pulse output buffer unit SCCLK of each GIP is not shown. However, as shown in FIG. 3 , the bootstrapping capacitor C3 of the scan pulse output buffer unit SCCLK is connected to the first node Q and the output terminal SP(k) of the scan pulse output buffer unit SCCLK. ) are placed between

Accordingly, in FIG. 8 , the bootstrapping capacitor (C3 in FIG. 3 ) of the scan pulse output buffer unit SCCLK of each GIP is not limited in its position, and the first node Q of the corresponding GIP and the scan It may be disposed between the output terminal SCout of the pulse output buffer unit SCCLK.

In addition, as described above, in disposing each element of the GIP in the display area, a pull-up transistor constituting the scan pulse output buffer unit SCCLK of the output buffer unit 27 among the elements of the GIP ( T6) requires a relatively larger width than other transistors.

That is, when the pull-up transistor T6 constituting the scan pulse output buffer unit outputs the scan pulse output clock signal SCCLK as a scan pulse, the delay should be minimized. Accordingly, the width of the transistor T6 constituting the scan pulse output buffer is relatively larger than that of the other transistors.

Also, for the same reason, the transistor T1 of the first to third node controller 23 in the driving period needs a width relatively larger than that of other transistors.

As such, the width of the transistor T6 constituting the scan pulse output buffer unit and the width of the transistor T1 of the first to third node controller 23 in the driving period should be designed to be relatively larger than the widths of other transistors. , since the unit pixel area is limited, the transistor T6 constituting the scan pulse output buffer unit cannot be disposed in one unit pixel area. Accordingly, elements requiring a relatively large width, such as the pull-up transistor T6 constituting the scan pulse output buffer unit and the transistor T1 of the first to third node control units 23 of the driving period, are divided and parallel to each other in the horizontal direction. (spreading) arrangement, a large size thin film transistor can be arranged in a limited unit pixel area.

So far, it has been described that at least one GIP is disposed on one gate line (scan line) in the display area. However, the present invention is not limited thereto.

As described with reference to FIG. 1 , the data driving circuit includes a plurality of source drive ICs (SICs). 1 shows that it is composed of six source drive ICs.

Accordingly, as another embodiment, the GIP may be disposed along each gate line (scan line) for each source drive IC (SIC).

9 is a configuration diagram of a display area of a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , an OLED display device according to an exemplary embodiment of the present invention includes a display panel PNL and a driving circuit for providing image data to the display panel PNL.

The display area AA of the display panel PNL includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn that are cross-arranged, and the plurality of data lines DL1 to DLm. and a plurality of sub-pixels arranged in a matrix form by the plurality of gate lines GL1 to GLn. Touch sensors may be further disposed in the display area AA of the display panel PNL.

The plurality of sub-pixels include red (R), green (G), and blue (B) sub-pixels for color implementation, and the red (R), green (G), and blue (B) sub-pixels In addition to the pixels, a white (W) sub-pixel may be further included.

The red (R), green (G), and blue (B) sub-pixels constitute one unit pixel, or the red (R), green (G), blue (B), and white (W) sub-pixels constitute one unit pixel.

In addition, devices (TFT, capacitor, etc.) constituting the GIP of the gate driving circuit are dispersedly disposed in the unit pixel areas.

More specifically, as follows.

The driving circuit includes a data driving circuit for supplying an image data voltage to the data lines DL1 to DLm of the display panel PNL, and a scan pulse synchronized with the image data voltage to the gate lines of the display panel PNL. and a gate driving circuit supplied to GL1 to GLn, and a timing controller (see T-CON of FIG. 1 ) for controlling operation timings of the data driving circuit and the gate driving circuit.

The data driving circuit includes a plurality of source drive ICs SIC1 to SIC6. 9 illustrates that the data driving circuit includes six source drive ICs SIC1 to SIC6.

Accordingly, the six source drive ICs SIC1 to SIC6 are respectively mounted on six COFs (Chip on Film), and each COF is connected to the pad area of the lower substrate SUBS1 of the display panel PNL through the ACF. It is bonded to the source PCB (SPCB). Input pins of each of the COFs are electrically connected to output terminals (pads) of the source PCB (SPCB), and output pins of each of the source COFs (COF) are connected to the substrate of the display panel PNL through the ACF. It is electrically connected to the formed data pads.

The gate driving circuit receives a start pulse (VST), clock signals (CRCLK, SCCLK), a gate high voltage (VGH), a gate low voltage (VGL), etc. from the timing controller, and is applied to each of the gate lines GL1 to GLn. It includes a plurality of GIPs sequentially outputting scan pulses.

The plurality of GIPs sequentially supply scan pulses synchronized with the data voltage to each of the gate lines GL1 to GLn under the control of the timing controller to select pixels of one line to which the image data voltage is applied.

Here, the plurality of GIPs are divided for each source drive IC (SIC1 to SIC6), and devices constituting at least one GIP in a plurality of unit pixel areas of each gate line for each source drive IC (SIC1 to SIC6). (TFT, Capacitor, etc.) are distributed.

That is, one GIP block having a plurality of GIPs is disposed for each display area driven by each source drive IC (SIC1, SIC2, SIC3, SIC4, SIC5, SIC6). At this time, the elements (TFT, capacitor, etc.) constituting the GIP are dispersedly disposed in the plurality of unit pixel areas of each of the plurality of gate lines (scan lines) of each block.

For example, if the display panel is a UHD (3840 * 2160) model, 2160 GIPs are arranged for each display area driven by each source drive IC (SIC1, SIC2, SIC3, SIC4, SIC5, SIC6).

In addition, as mentioned above, GIPs are arranged for each display region driven by each of the source drive ICs (SIC1 to SIC6), and in a plurality of unit pixel regions arranged on each gate line (scan line). Two or more GIPs may be deployed.

Accordingly, the configuration in which GIPs are divided for each display area driven by each of the source drive ICs (SIC1 to SIC6), and the elements (TFT, capacitor, etc.) constituting the GIP are dispersedly arranged in a plurality of unit pixel areas. As described with reference to FIGS. 4 and 5 , at least three sub-pixel units R, G, B, and W, a GIP unit 31 , and a GIP internal connection wiring unit 32 are divided.

In addition, GIPs are arranged for each display area driven by each of the source drive ICs SIC1 to SIC6 , and as described with reference to FIGS. 6 and 7 , the scan pulse output buffer of the output buffer unit 27 . The parts T6, T7, and C3 are arranged first, and then the inverter part 24, the first and second nodes Q and Qb of the blank section, the controllers 21 and 26, and the output buffer part 27 Among the carry pulse output buffer units T6cr and T7cr, the first to third node control units 23 and 25 of the driving section, and the reset unit 22 are arranged in the order of the wiring of the GIP internal connection wiring unit 32 . can be simplified.

In addition, GIPs are arranged for each display area driven by each of the source drive ICs (SIC1 to SIC6), and as described with reference to FIG. 8 , basically, the elements of the inverter unit 24 and the blank section Elements of the first and second node (Q, Qb) controllers 21 and 26 , elements of the first to third node controllers 23 and 25 d of the driving period, and elements of the reset unit 22 . placed in the order of

Then, the elements of the scan pulse output buffer unit SCCLK and the elements of the carry pulse output buffer unit CRCLK are combined with the elements of the inverter unit 24 and the first and second nodes Q and Qb of the blank section. ) elements of the controllers 21 and 26 , elements of the first to third node controllers 23 and 25 of the driving period, and elements of the reset unit 22 are arranged irregularly.

In addition, GIPs are arranged for each display area driven by each of the source drive ICs SIC1 to SIC6, and the GIPs arranged on the same gate line (scan line) for each source drive IC (SIC1 to SIC6) have the same carry It is driven by the carry pulse CRCLK for pulse output and the scan pulse SCCLK for outputting the same scan pulse to simultaneously output the carry pulse and the scan pulse.

In addition, although GIPs are arranged separately for each display area driven by each of the source drive ICs SIC1 to SIC6, each gate line (scan line) is a display area driven by each of the source drive ICs SIC1 to SIC6. Each may be electrically independent, and may be integrally formed in the display area driven by each of the source drive ICs SIC1 to SIC6.

In addition, each of the source drive ICs (SIC1 to SIC6) supplies a data voltage and various power sources for driving the pixels, and in the case of a GIP of 6 phases for each GIP group, a carry pulse output for driving the GIP Pulse (CRCLK1 to CRCLK6), scan pulse for scan pulse output (SCCLK1 to SCCLK6), power supply (GVDD, GVSS0, GVSS1, GVSS2), start signal (VST), reset signal (RESET, RST), line selection signal (LSP), etc. is supplied to the GIP unit 31 and the GIP internal connection wiring unit 32 .

In addition, although it has been described in FIG. 11 that at least one GIP block is disposed in a display area driven by one source drive IC (SIC1, SIC2, SIC3, SIC4, SIC5, or SIC6), the present invention is not limited thereto. One GIP block may be disposed in the display area driven by the source drive ICs (SIC1 and SIC2, SIC3 and SIC4, or SIC5 and SIC6), and three adjacent source drive ICs (SIC1 to SIC3, or SIC4 to SIC6) One GIP block may be disposed in the display area driven by .

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

PNL: Display panel SIC1~SIC: Source drive IC
21, 26: blank section first and second node (Q, Qb) control unit
22: reset unit 24: inverter unit
23, 25: driving section first to third node control unit
27: output buffer unit 31: GIP circuit unit
32: GIP internal connection wiring part 33: sub-pixel part

Claims (18)

a display area in which data lines and gate lines intersect, the display area including sub-pixels disposed at the intersections; and
and a plurality of GIPs dispersedly disposed in a plurality of unit pixel areas driven by each gate line in the display area and supplying scan pulses to the corresponding gate lines;
Each of the plurality of GIPs receives one of a plurality of clock signals for outputting carry pulses and one of a plurality of clock signals for outputting scan pulses, and receives scan pulses and carry signals according to voltages of first and second nodes. A scan pulse output buffer unit for outputting a pulse and a carry pulse output buffer unit are provided;
The plurality of scan pulse output buffers and the plurality of carry pulse output buffers of the plurality of GIPs are irregularly arranged. The method of claim 1,
The GIP is,
The first and the blank sections in which the set signal is selectively stored according to the line selection signal, the stage is charged to the first constant voltage according to the real-time compensation signal in the blank section, and the second node is discharged to the second constant voltage a second node control unit;
During the driving period of the corresponding stage, the first node is charged with the carry pulse voltage of the previous stage according to the carry pulse of the previous stage, and the first node and the third node are discharged with a second constant voltage according to the carry pulse of the rear stage, first to third node controllers in the driving period for charging the third node to the first constant voltage according to the voltage of the first node;
an inverter unit for inverting the voltage of the first node and applying it to the second node;
Further comprising a reset unit for discharging the first node to a second constant voltage according to a reset signal output from the timing controller in the blank section,
Elements of the inverter unit, elements of the first and second node controllers of the blank section, elements of the first to third node controllers of the driving period, and elements of the reset unit are arranged in order,
The plurality of scan pulse output buffers and the plurality of carry pulse output buffers of the plurality of GIPs are elements of the inverter, elements of the first and second node controllers in the blank period, and first to third node controllers in the driving period An OLED display panel that is irregularly disposed between the elements of the reset unit and the elements of the reset unit. The method of claim 1,
Each of the plurality of scan pulse output buffers includes a pull-up transistor configured to receive one of the plurality of scan pulse output clock signals and output a scan pulse according to voltages of the first node and the second node,
An OLED display panel in which the pull-up transistors are irregularly arranged. The method of claim 1,
Each of the plurality of carry pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a carry pulse according to voltages of the first node and the second node,
An OLED display panel in which the pull-up transistors are irregularly arranged. The method of claim 1,
Each of the plurality of scan pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a scan pulse according to voltages of the first node and the second node, The pull-up transistor is divided and disposed in parallel in a plurality of unit pixel areas along a corresponding gate line direction. The method of claim 1,
The first node and the second node, and an output terminal of each scan pulse output buffer unit are sequentially arranged in a first direction of the panel. a display area in which a plurality of data lines and a plurality of gate lines intersect, the display area including sub-pixels disposed at the intersections;
a plurality of source drive ICs dividing the plurality of data lines into a plurality of groups to drive the data lines of each group; and
The display area is divided into groups driven by each source drive IC, and a plurality of display areas are dispersedly disposed in unit pixel areas driven by each gate line in each divided display area group to supply scan pulses to the corresponding gate lines. Have a GIP,
Each of the plurality of GIPs receives one of a plurality of clock signals for outputting carry pulses and one of a plurality of clock signals for outputting scan pulses, and receives scan pulses and carry signals according to voltages of first and second nodes. A scan pulse output buffer unit for outputting a pulse and a carry pulse output buffer unit are provided;
The plurality of scan pulse output buffers and the plurality of carry pulse output buffers of the plurality of GIPs are irregularly arranged. 8. The method of claim 7,
The GIP is,
The first and the blank sections in which the set signal is selectively stored according to the line selection signal, the stage is charged to the first constant voltage according to the real-time compensation signal in the blank section, and the second node is discharged to the second constant voltage a second node control unit;
During the driving period of the corresponding stage, the first node is charged with the carry pulse voltage of the previous stage according to the carry pulse of the previous stage, and the first node and the third node are discharged with a second constant voltage according to the carry pulse of the rear stage, first to third node controllers in the driving period for charging the third node to the first constant voltage according to the voltage of the first node;
an inverter unit for inverting the voltage of the first node and applying it to the second node;
Further comprising a reset unit for discharging the first node to a second constant voltage according to a reset signal output from the timing controller in the blank section,
Elements of the inverter unit, elements of the first and second node controllers of the blank section, elements of the first to third node controllers of the driving period, and elements of the reset unit are arranged in order,
The plurality of scan pulse output buffers and the plurality of carry pulse output buffers of the plurality of GIPs are elements of the inverter, elements of the first and second node controllers in the blank period, and first to third node controllers in the driving period An OLED display device that is irregularly disposed between the elements of the reset unit and the elements of the reset unit. 8. The method of claim 7,
Each of the plurality of scan pulse output buffers includes a pull-up transistor configured to receive one of the plurality of scan pulse output clock signals and output a scan pulse according to voltages of the first node and the second node,
An OLED display in which the pull-up transistors are irregularly arranged. 8. The method of claim 7,
Each of the plurality of carry pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a carry pulse according to voltages of the first node and the second node,
An OLED display in which the pull-up transistors are irregularly arranged. 8. The method of claim 7,
Each of the plurality of scan pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a scan pulse according to voltages of the first node and the second node, , wherein the pull-up transistor is divided and disposed in parallel in a plurality of unit pixel areas along a corresponding gate line direction. 8. The method of claim 7,
The first node and the second node, and an output terminal of each scan pulse output buffer unit are sequentially arranged in a first direction of a panel. a display area in which a plurality of data lines and a plurality of gate lines intersect, the display area including sub-pixels disposed at the intersections;
a plurality of source drive ICs dividing the plurality of data lines into a plurality of groups to drive the data lines of each group; and
The display area is divided into groups driven by two or more adjacent source drive ICs, and is distributed in unit pixel areas driven by each gate line in each divided display area group to apply a scan pulse to the corresponding gate line. Equipped with a plurality of GIPs to supply,
Each of the plurality of GIPs receives one of a plurality of clock signals for outputting carry pulses and one of a plurality of clock signals for outputting scan pulses, and receives scan pulses and carry signals according to voltages of first and second nodes. A scan pulse output buffer unit for outputting a pulse and a carry pulse output buffer unit are provided;
The plurality of scan pulse output buffers and the plurality of carry pulse output buffers of the plurality of GIPs are irregularly arranged. 14. The method of claim 13,
The GIP is,
The first and the blank sections in which the set signal is selectively stored according to the line selection signal, the stage is charged to the first constant voltage according to the real-time compensation signal in the blank section, and the second node is discharged to the second constant voltage a second node control unit;
During the driving period of the corresponding stage, the first node is charged with the carry pulse voltage of the previous stage according to the carry pulse of the previous stage, and the first node and the third node are discharged with a second constant voltage according to the carry pulse of the rear stage, first to third node controllers in the driving period for charging the third node to the first constant voltage according to the voltage of the first node;
an inverter unit for inverting the voltage of the first node and applying it to the second node;
Further comprising a reset unit for discharging the first node to a second constant voltage according to a reset signal output from the timing controller in the blank section,
Elements of the inverter unit, elements of the first and second node controllers of the blank section, elements of the first to third node controllers of the driving period, and elements of the reset unit are arranged in order,
The plurality of scan pulse output buffers and the plurality of carry pulse output buffers of the plurality of GIPs are elements of the inverter, elements of the first and second node controllers in the blank period, and first to third node controllers in the driving period An OLED display device that is irregularly disposed between the elements of the reset unit and the elements of the reset unit. 14. The method of claim 13,
Each of the plurality of scan pulse output buffers includes a pull-up transistor configured to receive one of the plurality of scan pulse output clock signals and output a scan pulse according to voltages of the first node and the second node,
An OLED display in which the pull-up transistors are irregularly arranged. 14. The method of claim 13,
Each of the plurality of carry pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a carry pulse according to voltages of the first node and the second node,
An OLED display in which the pull-up transistors are irregularly arranged. 14. The method of claim 13,
Each of the plurality of scan pulse output buffers includes a pull-up transistor that receives one of the plurality of carry pulse output clock signals and outputs a scan pulse according to voltages of the first node and the second node, , wherein the pull-up transistor is divided and disposed in parallel in a plurality of unit pixel areas along a corresponding gate line direction. 14. The method of claim 13,
The first node and the second node, and an output terminal of each scan pulse output buffer unit are sequentially arranged in a first direction of a panel.

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