KR102562946B1 - Gate driving circuit and display device including the same - Google Patents

Abstract

The present invention is to provide a GIP-type gate driving circuit suitable for ultra-high resolution and a display device having the same, including a plurality of transistors, a logic unit for controlling charging and discharging of a Q node and a QB (Q bar) node; A first pull-up transistor controlled by the Q node and including first and second transistors connected in series with each other, and a third pull-up transistor including third and fourth transistors connected in series with each other and controlled by the QB node. a first output buffer including a first pull-down transistor and having a first output terminal at a first node to which a second transistor and a fourth transistor are connected; A second pull-up transistor controlled by the Q node and including fifth and sixth transistors connected in series with each other, and seventh and eighth transistors controlled by the QB node and connected in series with each other. and a second output buffer having a second output terminal at a second node to which a sixth transistor and an eighth transistor are connected, wherein the second transistor and the fourth transistor are connected in series. And, the sixth transistor and the eighth transistor are connected in series.

Description

Gate driving circuit and display device having the same

The present invention relates to a gate driving circuit and a display device including the same, and more particularly, to a gate driving circuit of the GIP (Gate In Panel) type and a display device including the same.

Flat panel displays include Liquid Crystal Display Devices (LCDs), Plasma Display Panels (PDPs), Organic Light Emitting Diode Displays (hereinafter referred to as "OLED displays"), electrical Electrophoretic Display Device (EPD) and the like.

A conventional display device will be described with reference to FIGS. 1 and 2 . 1 is a schematic block diagram of a conventional display device, and FIG. 2 is an equivalent circuit diagram showing parts of each stage of a GIP type gate driving circuit applied to a conventional display device.

Referring to FIG. 1 , the display device includes a display panel 1, a source driver IC (SDIC) for driving data lines DL of the display panel 1, and gate lines ( GL) to drive the gate driver (GD_GIP). Unlike the source driver IC (SDIC), the gate driver (GD_GIP) uses a GIP (Gate driver In Panel) type TFT (Thin Film Transistor) process to reduce the number of processes and manufacturing cost, and the non-display of the display panel (1). It is directly formed in the outer bezel area BZ of the active area AA, that is, the display area.

The GIP-type gate driving circuit (GD_GIP) includes a plurality of stages formed side by side along the Y direction corresponding to the gate lines, and each stage has a plurality of TFTs required to generate a gate pulse (scan pulse). .

2 is an equivalent circuit diagram showing a part of each stage ST of a GIP type gate driving circuit GD_GIP applied to a conventional display device.

Referring to FIG. 2, each stage ST includes a plurality of TFTs for controlling the activation and deactivation of the Q node and QB node, a first output buffer OB1 controlled by the Q node and the QB node, and a second output buffer OB1 controlled by the Q node and the QB node. An output buffer (OB) is provided.

The first output buffer OB1 is controlled by a Q node, a first pull-up transistor TU1 composed of a first transistor T1 and a second transistor T2 connected in series with each other, and a QB node, and a first pull-down transistor TD1 composed of a third transistor T3 and a fourth transistor T4 connected in series with each other.

The second output buffer OB2 is controlled by the Q node and is controlled by a second pull-up transistor TU2 composed of a fifth transistor T5 and a sixth transistor T6 connected in series with each other and a QB node, and a second pull-down transistor (TD2) composed of a seventh transistor (T7) and an eighth transistor (T8) connected in series with each other.

The Q node and QB node are charged and discharged opposite to each other. That is, when the Q node is charged to the active level, the QB node is discharged to the inactive level, and conversely, when the Q node is discharged to the inactive level, the QB node is charged to the active level.

When the Q node is activated, the first and second pull-down transistors TD1 and TD2 are turned off, and the first and second pull-up transistors TU1 and TU2 are turned on to scan the n-th and n+1-th gate lines, respectively. output a pulse. This scan pulse becomes the gate voltage (VOUT(n), VOUT(n+1)) output to the corresponding gate line, and is used as a carry signal supplied to the stage of the next stage. On the other hand, when the QB node is activated, the first and second pull-up transistors TU1 and TU2 are turned off and the first and second pull-down transistors TD1 and TD2 are turned on, so that the gate voltage of the corresponding gate line is sensed. is supplied to the gate low voltage (VGL) supply wiring.

However, a display device having a conventional GIP-type gate driving circuit (GD_GIP) including the stages ST1 to STn as described above, the first pull-up transistor TU1 of the first output buffer OB1 and Since the first pull-down transistor TD1, the second pull-up transistor TU2 of the second output buffer OB2, and the second pull-down transistor TD2 are arranged in parallel in the y-axis direction, the width in the y-axis direction (that is, the vertical width) increases. However, according to the trend of ultra-high resolution display devices, the size of each pixel area is reduced, and the vertical width occupied by one stage is also reduced, limiting the size.

For example, at a resolution of 1,500 ppi, the width that one stage can occupy in the y-axis direction is only about 32.8 μm. In contrast, the vertical width of each of the first to eighth transistors T1 to T8 constituting the first and second output buffers OB1 and OB2 is 30.5 μm, and the first pull-up transistor TU1 and the first pull-down The vertical width of the transistor TD1 or the second pull-up transistor PU2 and the second pull-down transistor PD2 must occupy at least 61.0 μm. Accordingly, in a conventional display device having a GIP-type gate driving circuit, there is a problem in that arrangement of a stage itself is completely impossible under ultra-high resolution conditions.

The present invention is to solve the above problems, and provides a GIP type gate driving circuit capable of accommodating the output buffer of each stage within a limited vertical width (y-axis width) in an ultra-high resolution display device and a display device having the same. aims to do

A GIP-type gate driving circuit according to the present invention for achieving the above object includes a plurality of transistors, and a logic unit for controlling charging and discharging of a Q node and a QB (Q bar) node; A first pull-up transistor controlled by the Q node and including first and second transistors connected in series with each other, and a third pull-up transistor including third and fourth transistors connected in series with each other and controlled by the QB node. a first output buffer including a first pull-down transistor and having a first output terminal at a first node to which a second transistor and a fourth transistor are connected; A second pull-up transistor controlled by the Q node and including fifth and sixth transistors connected in series with each other, and seventh and eighth transistors controlled by the QB node and connected in series with each other. and a second output buffer having a second output terminal at a second node to which a sixth transistor and an eighth transistor are connected, wherein the second transistor and the fourth transistor are connected in series. and the sixth transistor and the eighth transistor are connected in series.

In the above configuration, the first to eighth transistors may be disposed on the same line.

In addition, the source electrodes of the first, fifth, third, and seventh transistors and the drain electrodes of the second, sixth, fourth, and eighth transistors are alternately disposed on a horizontal first line, The gate electrodes of the first, second, fifth, and sixth transistors are disposed at positions corresponding to the source and drain electrodes of the first, second, fifth, and sixth transistors in a vertical direction, and the first line It is disposed on one side of a second line in the horizontal direction adjacent to the vertical direction, and the gate electrodes of the third, fourth, seventh, and eighth transistors are sources of the third, fourth, seventh, and eighth transistors. and drain electrodes of the first, fifth, third, and seventh transistors disposed on the other side of the second line at a position corresponding to the drain electrodes in a vertical direction, and the drain electrodes of the second, sixth, and seventh transistors, respectively. Source electrodes of the fourth and eighth transistors may be alternately disposed on a third line in a horizontal direction adjacent to the second line in a vertical direction.

A GIP type gate driving circuit according to the present invention includes a first connection portion connecting a third node to which the first transistor and the second transistor are connected and a fourth node to which the third transistor and the fourth transistor are connected; The device may further include a second connector connecting a fifth node to which the fifth and sixth transistors are connected and a sixth node to which the seventh and eighth transistors are connected.

In the above configuration, the first and second connectors may be disposed on the same line.

In addition, the source electrodes of the first and fifth transistors and the drain electrodes of the second and sixth transistors are alternately disposed on a horizontal first line, and the first, second, fifth, and sixth transistors are alternately arranged. Gate electrodes of the transistors are disposed on a second line in a horizontal direction adjacent to the first line at a position corresponding to the source and drain electrodes of the first, second, fourth, and third transistors in a vertical direction, A first connection line and a second connection line operating as a source electrode and a drain electrode adjacent to the second line are disposed on a third line in the horizontal direction at a position corresponding to the gate electrode of the second line in the vertical direction, and , The first connection line serves as drain electrodes of the first and third transistors and source electrodes of the second and fourth transistors, and the second connection line serves as drain electrodes of the fifth and seventh transistors. and source electrodes of the sixth and eighth transistors, and the gate electrodes of the third, fourth, seventh, and eighth transistors are on a fourth line in a horizontal direction vertically adjacent to the third line. The source electrodes of the third and seventh transistors and the drain electrodes of the fourth and eighth transistors may be alternately disposed on a fifth line in a horizontal direction vertically adjacent to the fourth line. .

A display device according to the present invention for achieving the above object includes a display panel including an active area including a pixel array on which an input image is displayed and a bezel area outside the active area; a data driving circuit supplying data voltages to data lines of the pixel array; and a gate output signal supplied to gate lines of the pixel array, and any one of the aforementioned GIP type gate driving circuits.

According to the display device according to the present invention, since the output buffer of each stage can be accommodated within the limited vertical width of ultra-high resolution, an effect capable of providing a GIP type gate driving circuit suitable for ultra-high resolution and a display device having the same can be obtained. can

1 is a block diagram schematically showing a conventional display device;
2 is an equivalent circuit diagram showing a part of each stage of a GIP type gate driving circuit applied to a conventional display device;
3 is a block diagram showing a display device according to an embodiment of the present invention;
Figure 4 is a diagram showing the configuration of the shift register of the GIP circuit of Figure 3
5 is an equivalent circuit diagram showing an example of each stage of the shift register of FIG. 4;
6 is a plan view showing the configuration of the first to eighth transistors shown in FIG. 5;
7 is an equivalent circuit diagram showing another example of each stage of the shift register of FIG. 4;
FIG. 8 is a plan view showing configurations of first to eighth transistors shown in FIG. 7;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numbers throughout the specification indicate substantially the same elements. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, the names of components used in the following description may be selected in consideration of the ease of writing specifications, and may be different from names of parts of actual products.

First, a display device according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4 .

3 is a block diagram showing a display device according to an embodiment of the present invention, and FIG. 4 is a diagram schematically showing the configuration of a shift register of the GIP circuit shown in FIG.

Referring to FIG. 3 , a display device according to an embodiment of the present invention includes a display panel 10, a data driving circuit, a Gate In Panel (GIP) type gate driving circuit, and a timing controller (TC).

The display panel 10 includes an active area AA and a bezel area BA. The active area AA is an area where an input image is displayed and a pixel array is disposed. The bezel area BA is an area where the shift register SR of the gate driving circuit, various signal wires, and a common voltage supply line are disposed.

The pixel array may include a thin film transistor (TFT) array formed on the first substrate and a color filter array formed on the second substrate.

The TFT array is defined by data lines DL, gate lines (or scan lines) GL crossing the data lines DL, and intersections of the data lines DL and the gate lines GL. and a pixel array made up of pixels arranged in areas where

The common voltage Vcom may be supplied from a separate power supply unit (not shown) and is supplied to the pixel array through the common line CL. As shown in FIG. 4 , the common line CL is disposed in the bezel area BA and diverged from the common line CL to form a plurality of common line branch portions CLb arranged in parallel with the gate lines GL. can include

The display panel 10 may be formed in a color filter on transistor (COT) method in which the color filter array is not formed on the second substrate and color filters are provided on the TFT array.

The data driving circuit includes a plurality of source drive ICs (Integrated Circuits) (SDa, SD) each connected to a group of data lines (DL). The source drive ICs SDa and SD receive digital video data RGB from the timing controller TC. The source drive ICs (SDa, SD) convert digital video data (RGB) into analog data voltages in response to the source timing control signal from the timing controller (TC), and then convert the data voltages into gate pulses (or scan pulses). ) is supplied to the data lines DL of the display panel 10 to be synchronized. The source drive ICs SDa and SD may be connected to the data lines DL of the display panel 10 through a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The source drive ICs SDa and SD shown in FIG. 3 show an example of being mounted on a Tape Carrier Package (TCP). In addition, a printed circuit board (PCB) 20 is connected to the first substrate of the display panel 10 via TCP.

The GIP type gate driving circuit includes a level shifter LS mounted on the PCB 20 and a shift register SR formed on the first substrate of the display panel 10 .

The level shifter LS receives signals such as a start pulse ST, gate shift clocks GLCK, and a flicker signal FLK from the timing controller TC, and also generates a gate high voltage VGH and a gate low voltage. (VGL) and the like are supplied. The start pulse ST, the gate shift clocks GCLK, and the flicker signal FLK are signals that swing between 0V and 3.3V, but are not limited thereto. The gate shift clocks GLCK1 to n are n-phase clock signals having a predetermined phase difference. The gate high voltage (VGH) is a voltage higher than or equal to the threshold voltage of the thin film transistor (TFT) formed in the thin film transistor array of the display panel 10 and is a voltage of about 28V, and the gate low voltage (VGL) is the voltage of the thin film transistor (TFT) of the display panel 10 The voltage is lower than the threshold voltage of the thin film transistor (TFT) formed in the transistor array and is approximately -5V, but the present invention is not limited thereto.

The level shifter LS is a shift clock signal obtained by level-shifting the start pulse ST and the gate shift clocks GLCK input from the timing controller TC to a gate high voltage VGH and a gate low voltage VGL, respectively. outputs (CLK). Accordingly, each of the start pulse VST and shift clock signals CLK output from the level shifter LS swings between the gate high voltage VGH and the gate low voltage VGL. The level shifter LS may reduce the flicker by lowering the kickback voltage ΔVp of the liquid crystal cell by lowering the gate high voltage according to the flicker signal FLK.

As shown in FIG. 3 , the output signals of the level shifter LS are connected to wires formed on the TCP of the first source drive IC SDa disposed on the upper left side of the display panel 10 and to the display panel 10. It may be supplied to the shift register SR through Line On Glass (LOG) lines LW formed on the first substrate. The shift register SR is directly formed on the first substrate of the display panel 10 by a GIP process.

As shown in FIG. 4 , a start pulse VST, clock signals CLK1 to CLKn, a gate low voltage VGL, and a gate high voltage VGH are input to the shift register SR. The shift register SR includes a plurality of stages ST1 to STn that are cascadedly connected. The clock signals CLK1 to n are n (n is a natural number greater than or equal to 2) phase clock signals whose phases are sequentially delayed. Clock signals CLK1 to CLKn are supplied to each of the stages ST1 to STn through clock signal supply lines SL1 to SLn.

Next, a first example of each of the stages ST1 to STn of the GIP type gate driving circuit of the display device according to an embodiment of the present invention will be described with reference to FIG. 5 .

Fig. 5 is an equivalent circuit diagram showing an example of each stage of the shift register shown in Fig. 4;

Referring to FIG. 5, each stage (ST1 to STn, hereinafter simply referred to as ST) of the shift register SR includes a logic unit Lo, a first output buffer OB1, and a second output buffer OB2. ).

The logic unit Lo includes input terminals to which the start signal VST or the carry signal and the gate high signal VGH from the previous stage are input, and the first pull-up transistor TU1 of the first output buffer OB1 and the first pull-up transistor TU1 of the first output buffer OB1. 1 Q node controlling the second pull-up transistor TU2 of the output buffer OB1, the first pull-down transistor TD1 of the first output buffer OB1 and the second pull-down transistor of the second output buffer OB2 and a controlling QB node that controls (TD2).

The logic unit Lo includes a plurality of switching transistors and controls charging and discharging operations of the Q node and the QB node in response to a gate start signal VST, a gate high voltage VGH, and a gate low voltage VGL. . The configuration of the logic unit Lo can be configured in various ways, and since the transistors constituting the logic unit have a size much smaller than the size of the transistor included in the output buffer, it is highly related to solving the technical problem of the present invention. does not exist. Accordingly, a detailed description of the logic unit Lo will be omitted.

The first output buffer OB1 is controlled by a Q node, a first pull-up transistor TU1 composed of a first transistor T1 and a second transistor T2 connected in series with each other, and a QB node, and a first pull-down transistor TD1 composed of a third transistor T3 and a fourth transistor T4 connected in series with each other.

The first transistor T1 of the first pull-up transistor TU1 includes a gate electrode controlled by the Q node, a source electrode to which the n-th clock signal CLK(n) is input, and a first pull-up transistor TU1. and a drain electrode connected to the second transistor T2. The second transistor T2 of the first pull-up transistor TU1 is connected to a gate electrode controlled by the Q node, a source electrode connected to the drain electrode of the first transistor T1, and a first output node N1. A drain electrode is included.

The third transistor T3 of the first pull-down transistor TD1 includes a gate electrode controlled by the QB node, a source electrode to which the gate low voltage VGL is input, and a fourth transistor of the first pull-down transistor TD1 ( and a drain electrode connected to T4). The fourth transistor T4 of the first pull-down transistor TD1 is connected to the gate electrode controlled by the QB node, the source electrode connected to the drain electrode of the third transistor T3, and the first output node N1. A drain electrode is included.

The second output buffer OB2 is controlled by the Q node and is controlled by a second pull-up transistor TU2 composed of a fifth transistor T5 and a sixth transistor T7 connected in series with each other and a QB node, and a second pull-down transistor (TD2) composed of a fifth transistor (T5) and a sixth transistor (T6) connected in series with each other.

The fifth transistor T1 of the second pull-up transistor TU2 includes a gate electrode controlled by the Q node, a source electrode to which the n+1th clock signal CLK(n+1) is input, and a second pull-up transistor. and a drain electrode connected to the sixth transistor T6 of (TU2). The sixth transistor T6 of the second pull-up transistor TU2 is connected to the gate electrode controlled by the Q node, the source electrode connected to the drain electrode of the fifth transistor T5, and the second output node N2. A drain electrode is included.

The seventh transistor T7 of the second pull-down transistor TD2 includes a gate electrode controlled by the QB node, a source electrode to which the gate low voltage VGL is input, and an eighth transistor of the second pull-down transistor TD2 ( and a drain electrode connected to T8). The eighth transistor T8 of the second pull-down transistor TD2 is connected to the gate electrode controlled by the QB node, the source electrode connected to the drain electrode of the seventh transistor T7, and the second output node N2. A drain electrode is included.

The Q node and the QB node are charged and discharged in opposite directions by the signal output from the logic unit Lo. That is, when the Q node is charged to the active level, the QB node is discharged to the inactive level, and conversely, when the Q node is discharged to the inactive level, the QB node is charged to the active level.

When the Q node is activated, the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8 of the first and second pull-down transistors TD1 and TD2 are turned off, and the first and second pull-down transistors TD1 and TD2 are turned off. 2 The first, second, fifth, and sixth transistors T1, T2, T5, and T6 of the pull-up transistors TU1 and TU2 are turned on to output scan pulses to the nth and n+1th gate lines, respectively. do. This scan pulse becomes the gate voltage (Vout(n), Vout(n+1)) output to the corresponding gate line, and is used as a carry signal supplied to the stage of the next stage. On the other hand, when the QB node is activated, the first, second, fifth, and sixth transistors T1, T2, T5, and T6 of the first and second pull-up transistors TU1 and TU2 are turned off, and Since the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8 of the first and second pull-down transistors TD1 and TD2 are turned on, the gate voltage of the corresponding gate line is sensed and the gate is low. It is supplied to the voltage (VGL) supply wiring.

The first pull-up transistor TU1 and the first pull-down transistor TD1, the second pull-up transistor PU2 and the second pull-down transistor ( As shown in FIG. 5 , the first to eighth transistors T1 to T8 constituting the PD2) are disposed in the same row.

As such, the first to eighth transistors T1 to T8 included in the shift register of the GIP type gate driving circuit according to the present invention are all arranged in the same row.

Therefore, the stage included in the shift register of the GIP-type gate driving circuit according to the present invention can significantly narrow the vertical width (i.e., the width in the y-axis direction) compared to the stage included in the shift register of the conventional GIP-type gate driving circuit. Since a certain effect can be obtained, it can be used for an ultra-high resolution display device.

Hereinafter, referring to FIG. 6 , the transistors T1 to T8 included in the first and second output buffers OB1 and OB2 will be described.

FIG. 6 is a plan view specifically illustrating configurations of the first to eighth transistors shown in FIG. 5 .

In FIG. 6 , the upper side shows the arrangement state of the first to eighth transistors T1 to T8 , and the lower side shows the current flow path of the first to eighth transistors T1 to T8 on the upper side. In Fig. 6, x indicates the source electrode (or drain electrode) and drain electrode (or source electrode) of each transistor.

Referring to FIG. 6 , the source electrodes of the first, fifth, third, and seventh transistors T1, T5, T3, and T7 and the second, sixth, fourth, and eighth transistors T2, The drain electrodes of T6, T4 and T8) are alternately disposed on the first horizontal line.

The gate electrodes G1 of the first, second, fifth, and sixth transistors T1, T2, T5, and T6 are the first, second, fifth, and sixth transistors T1, T2, and T5. , T6) is disposed on a second line in a horizontal direction vertically adjacent to the first line at a position corresponding vertically downward to the source and drain electrodes of T6).

Gate electrodes G2 of the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8 are connected to the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8. T8) is disposed on a second line in a horizontal direction vertically adjacent to the first line at a position corresponding vertically downward to the source and drain electrodes.

The gate electrode G1 and the gate electrode G2 are disposed adjacent to each other in the horizontal direction. That is, the gate electrode G1 and the gate electrode G2 are disposed on the same horizontal line.

Drain electrodes of the first, fifth, third, and seventh transistors T1, T5, T3, and T7, and the second, sixth, fourth, and eighth transistors T2, T6, T4, and T8 The source electrodes of are alternately disposed on the third line in the horizontal direction adjacent to the second line.

5 and 6, according to the stage of the GIP type gate driving circuit according to the first example of the present invention, the first output buffer OB1 and the second output buffer OB2 are disposed on the same line. The first transistor T1 and the second transistor T2, the fifth transistor T5 and the sixth transistor T6, the third transistor T3 and the fourth transistor T4, and the seventh transistor T7 and the eighth transistor T8 are arranged in one row along the x-axis direction. Therefore, since the width of the first output buffer OB1 and the second output buffer OB2 in the y-axis direction (ie, the vertical axis direction) is sufficient as the area occupied by one transistor, the width in the y-axis direction (ie, the vertical axis direction) direction) can achieve the effect of significantly reducing the width.

Next, a second example of each of the stages ST1 to STn of the GIP type gate driving circuit of the display device according to an embodiment of the present invention will be described with reference to FIG. 7 .

Fig. 7 is an equivalent circuit diagram showing a second example of each stage of the shift register shown in Fig. 4;

Referring to FIG. 7, each stage (ST1 to STn, hereinafter simply referred to as ST) of the shift register SR includes a logic unit Lo, a first output buffer OB1, and a second output buffer OB2. ).

The logic unit Lo includes input terminals to which the start signal VST or the carry signal and the gate high signal VGH from the previous stage are input, and the first pull-up transistor TU1 of the first output buffer OB1 and the first pull-up transistor TU1 of the first output buffer OB1. 1 Q node controlling the second pull-up transistor TU2 of the output buffer OB1, the first pull-down transistor TD1 of the first output buffer OB1 and the second pull-down transistor of the second output buffer OB2 and a controlling QB node that controls (TD2).

The logic unit Lo includes a plurality of switching transistors and controls charging and discharging operations of the Q node and the QB node in response to a gate start signal VST, a gate high voltage VGH, and a gate low voltage VGL. . The configuration of the logic unit Lo can be configured in various ways, and since the transistors constituting the logic unit have a size much smaller than the size of the transistor included in the output buffer, it is highly related to solving the technical problem of the present invention. does not exist. Accordingly, a detailed description of the logic unit Lo will be omitted.

The first output buffer OB1 is controlled by a Q node, a first pull-up transistor TU1 composed of a first transistor T1 and a second transistor T2 connected in series with each other, and a QB node, and a first pull-down transistor TD1 composed of a third transistor T3 and a fourth transistor T4 connected in series with each other.

The first transistor T1 of the first pull-up transistor TU1 includes a gate electrode controlled by the Q node, a source electrode to which the n-th clock signal CLK(n) is input, and a first pull-up transistor TU1. and a drain electrode connected to the second transistor T2. The second transistor T2 of the first pull-up transistor TU1 is connected to a gate electrode controlled by the Q node, a source electrode connected to the drain electrode of the first transistor T1, and a first output node N1. A drain electrode is included.

The third transistor T3 of the first pull-down transistor TD1 includes a gate electrode controlled by the QB node, a source electrode to which the gate low voltage VGL is input, and a fourth transistor of the first pull-down transistor TD1 ( and a drain electrode connected to T4). The fourth transistor T4 of the first pull-down transistor TD1 is connected to the gate electrode controlled by the QB node, the source electrode connected to the drain electrode of the third transistor T3, and the first output node N1. A drain electrode is included.

A third node N3 to which the drain electrode of the first transistor T1 and the source electrode of the second transistor T2 are connected, and the drain electrode of the third transistor T3 and the source electrode of the fourth transistor T4 are connected. The connected fourth node N4 is connected by a first connection wire C1.

The second output buffer OB2 is controlled by the Q node and is controlled by a second pull-up transistor TU2 composed of a fifth transistor T5 and a sixth transistor T7 connected in series with each other and a QB node, and a second pull-down transistor (TD2) composed of a fifth transistor (T5) and a sixth transistor (T6) connected in series with each other.

The fifth transistor T1 of the second pull-up transistor TU2 includes a gate electrode controlled by the Q node, a source electrode to which the n+1th clock signal CLK(n+1) is input, and a second pull-up transistor. and a drain electrode connected to the sixth transistor T6 of (TU2). The sixth transistor T6 of the second pull-up transistor TU2 is connected to the gate electrode controlled by the Q node, the source electrode connected to the drain electrode of the fifth transistor T5, and the second output node N2. A drain electrode is included.

The seventh transistor T7 of the second pull-down transistor TD2 includes a gate electrode controlled by the QB node, a source electrode to which the gate low voltage VGL is input, and an eighth transistor of the second pull-down transistor TD2 ( and a drain electrode connected to T8). The eighth transistor T8 of the second pull-down transistor TD2 is connected to the gate electrode controlled by the QB node, the source electrode connected to the drain electrode of the seventh transistor T7, and the second output node N2. A drain electrode is included.

A fifth node N5 to which the drain electrode of the fifth transistor T5 and the source electrode of the sixth transistor T6 are connected, the drain electrode of the seventh transistor T7 and the source electrode of the eighth transistor T8 are The connected sixth node N6 is connected by a second connection wire C2.

The Q node and the QB node are charged and discharged in opposite directions by the signal output from the logic unit Lo. That is, when the Q node is charged to the active level, the QB node is discharged to the inactive level, and conversely, when the Q node is discharged to the inactive level, the QB node is charged to the active level.

When the Q node is activated, the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8 of the first and second pull-down transistors TD1 and TD2 are turned off, and the first and second pull-down transistors TD1 and TD2 are turned off. 2 The first, second, fifth, and sixth transistors T1, T2, T5, and T6 of the pull-up transistors TU1 and TU2 are turned on to output scan pulses to the nth and n+1th gate lines, respectively. do. This scan pulse becomes the gate voltage (Vout(n), Vout(n+1)) output to the corresponding gate line, and is used as a carry signal supplied to the stage of the next stage. On the other hand, when the QB node is activated, the first, second, fifth, and sixth transistors T1, T2, T5, and T6 of the first and second pull-up transistors TU1 and TU2 are turned off, and Since the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8 of the first and second pull-down transistors TD1 and TD2 are turned on, the gate voltage of the corresponding gate line is sensed and the gate is low. It is supplied to the voltage (VGL) supply wiring.

Hereinafter, referring to FIG. 8 , the transistors T1 to T8 included in the first and second output buffers OB1 and OB2 will be described.

FIG. 8 is a plan view specifically showing configurations of the first to eighth transistors shown in FIG. 7 .

In FIG. 8 , the upper side shows the arrangement state of the first to eighth transistors T1 to T8 , and the lower side shows the current flow path of the upper side transistors T1 to T8 . In addition, x marks in FIG. 8 represent source electrodes (or drain electrodes) and drain electrodes (or source electrodes) of the first, second, fifth, and sixth transistors T1, T2, T5, and T6, respectively. , Δ indicates the source electrode (or drain electrode) and drain electrode (or source electrode) of each of the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8.

Referring to FIG. 8 , the source electrodes of the first and fifth transistors T1 and T5 and the drain electrodes of the second and sixth transistors T2 and T6 are alternately disposed on a first horizontal line. do.

The gate electrodes G1 of the first, second, fifth, and sixth transistors T1, T2, T5, and T6 are connected to the first, second, fourth, and third transistors T1, T2, T5, and T5. T6) is disposed on a second line in a horizontal direction adjacent to the first line at a position corresponding to the source and drain electrodes in the vertical direction.

At positions corresponding to the gate electrode G1 of the second line in the vertical direction, the first connection line C1 and the second connection line C2 operating as source and drain electrodes adjacent to the second line are provided in the horizontal direction. placed on the third line. The first connection line C1 serves as drain electrodes of the first and third transistors T1 and T3 and as source electrodes of the second and fourth transistors. The second connection line C2 serves as drain electrodes of the fifth and seventh transistors T5 and T7 and as source electrodes of the sixth and eighth transistors T6 and T8.

The gate electrodes G2 of the third, fourth, seventh, and eighth transistors T3, T4, T7, and T8 are disposed on a fourth line in a horizontal direction vertically adjacent to the third line.

The source electrodes of the third and seventh transistors T3 and T7 and the drain electrodes of the fourth and eighth transistors T3 and T8 are connected to each other on the fifth line in the horizontal direction vertically adjacent to the fourth line. placed alternately.

As shown in FIGS. 7 and 8 , a third node N3 to which the first transistor T1 and the second transistors T2 are connected, and the third transistor T3 and the fourth transistor T4 are connected. The connected fourth nodes N4 are connected to each other by the first connection pattern C1. In addition, the fifth node N5 to which the fifth transistor T5 and the sixth transistors T6 are connected and the sixth node N6 to which the seventh transistor T7 and the eighth transistor T8 are connected are They are connected to each other by the second connection pattern C2.

Since the first connection pattern C1 connects the third node N3 and the fourth node N4, the drain electrode D of the first transistor T1 connected to the third node N3 and the third node N3 are connected to each other. The drain electrode D of the transistor T3 is shared, and the source electrode S of the second transistor T2 connected to the fourth node N4 and the source electrode S of the fourth transistor T4 are shared. You can do it. Also, since the second connection pattern C2 connects the fifth node N5 and the sixth node N6, the drain electrode D of the fifth transistor T5 connected to the fifth node N3 and The source electrode S of the sixth transistor T6 and the source electrode S of the eighth transistor T6 share the drain electrode D of the seventh transistor T7 and are connected to the sixth node N6. will be able to share

Therefore, according to the configuration of the first and second output buffers included in the stage of the GIP-type gate driving circuit according to the second example of the present invention, while reducing the vertical width compared to the stage configuration of the conventional GIP-type gate driving circuit, Compared to the first example of the present invention, the effect of narrowing the left and right widths can be obtained. Accordingly, an effect of obtaining a display device suitable for an ultra-high resolution display device can be obtained.

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

10: display panel 20: PCB
SDa, SD: source drive IC LS: level shifter
SR: shift register ST1 to STn: stage
TC: Timing Controller OB1, OB2: Output Buffer
TU1, TU2: Pull-up transistor TD1, TD2: Pull-down transistor

Claims (7)

a logic unit including a plurality of transistors and controlling charging and discharging of a Q node and a QB (Q bar) node;
A first pull-up transistor controlled by the Q node and including first and second transistors connected in series with each other, and a third pull-up transistor including third and fourth transistors controlled by the QB node and connected in series with each other. a first output buffer including a first pull-down transistor and having a first output terminal at a first node to which a second transistor and a fourth transistor are connected;
A second pull-up transistor controlled by the Q node and including fifth and sixth transistors connected in series with each other, and controlled by the QB node and including seventh and eighth transistors connected in series with each other A second output buffer including a second pull-down transistor and having a second output terminal at a second node to which a sixth transistor and an eighth transistor are connected;
The second transistor and the fourth transistor are connected in series, and the sixth transistor and the eighth transistor are connected in series;
The first to the eighth transistors are disposed on the same line as a GIP (Gate In Panel) type gate driving circuit. delete According to claim 1,
The source electrodes of the first, fifth, third, and seventh transistors and the drain electrodes of the second, sixth, fourth, and eighth transistors are alternately disposed on a horizontal first line,
The gate electrodes of the first, second, fifth, and sixth transistors are disposed at positions corresponding to the source and drain electrodes of the first, second, fifth, and sixth transistors in a vertical direction, and the first line It is disposed on one side on the second line in the horizontal direction adjacent to the vertical direction,
The gate electrodes of the third, fourth, seventh, and eighth transistors correspond to the source and drain electrodes of the third, fourth, seventh, and eighth transistors in a vertical direction, and the second line It is placed on the other side of the top,
The drain electrodes of the first, fifth, third, and seventh transistors and the source electrodes of the second, sixth, fourth, and eighth transistors are formed on a horizontal third line vertically adjacent to the second line. GIP-type gate driving circuits arranged alternately on top of each other. a logic unit including a plurality of transistors and controlling charging and discharging of a Q node and a Q bar (QB) node;
A first pull-up transistor controlled by the Q node and including first and second transistors connected in series with each other, and a third pull-up transistor including third and fourth transistors connected in series with each other and controlled by the QB node. a first output buffer including a first pull-down transistor and having a first output terminal at a first node to which a second transistor and a fourth transistor are connected;
A second pull-up transistor controlled by the Q node and including fifth and sixth transistors connected in series with each other, and controlled by the QB node and including seventh and eighth transistors connected in series with each other A second output buffer including a second pull-down transistor and having a second output terminal at a second node to which a sixth transistor and an eighth transistor are connected;
The second transistor and the fourth transistor are connected in series, and the sixth transistor and the eighth transistor are connected in series;
a first connection portion connecting a third node to which the first and second transistors are connected and a fourth node to which the third and fourth transistors are connected;
a second connection portion connecting a fifth node to which the fifth and sixth transistors are connected and a sixth node to which the seventh and eighth transistors are connected;
The first and second connection parts are disposed on the same line as the GIP type gate driving circuit. delete According to claim 4,
The source electrodes of the first and fifth transistors and the drain electrodes of the second and sixth transistors are alternately disposed on a horizontal first line;
The gate electrodes of the first, second, fifth, and sixth transistors are on the first line at positions corresponding to the source and drain electrodes of the first, second, fourth, and third transistors in a vertical direction. It is disposed on a second line in the horizontal direction adjacent to the vertical direction,
At a position corresponding to the gate electrode of the second line in the vertical direction, a first connection portion and a second connection portion operating as a source electrode and a drain electrode adjacent to the second line and a second connection portion in a horizontal direction vertically adjacent to the second line placed on line 3,
The first connection portion serves as drain electrodes of the first and third transistors and source electrodes of the second and fourth transistors, and the second connection portion serves as drain electrodes of the fifth and seventh transistors and the source electrodes of the second and fourth transistors. Acting as source electrodes of the sixth and eighth transistors;
Gate electrodes of the third, fourth, seventh, and eighth transistors are disposed on a fourth line in a horizontal direction vertically adjacent to the third line,
The source electrodes of the third and seventh transistors and the drain electrodes of the fourth and eighth transistors are alternately disposed on a fifth line in a horizontal direction vertically adjacent to the fourth line. a display panel including an active area including a pixel array on which an input image is displayed and a bezel area outside the active area;
a data driving circuit supplying data voltages to data lines of the pixel array; and
A display device comprising the GIP type gate driving circuit according to any one of claims 1, 3, 4, and 6 for supplying gate output signals to gate lines of the pixel array.

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