KR20130067989A - Gate shift register and display device using the same - Google Patents

Abstract

PURPOSE: A gage shift register and a display device using the same are provided to remove lines for supplying a gate low voltage, thereby reducing wirings. CONSTITUTION: A first TFT(T1) applies a carry signal of a k-1 stage(VOUTk-1) that is inputted though a first input terminal to a Q node in response a A-1 gate shift clolck(CLKA-1). A second TFT(T2) applies a gate high voltage(VGH) to the Q node in response to a carry signal of a k+2 stage that is inputted through a second input terminal(IN2). A pull-up switching element(TU) applies an A gate shift clock to an output node according to a voltage level of the Q node. The pull-up switching element applies the gate high voltage to the output node in response to an A+2 gate shift clock. A capacitor is provided between and connected to the Q node and the output node.

Description

GATE SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a gate shift register and a display device using the same, which can reduce the number of TFTs and facilitate a narrow bezel design.

Recently, a GIP (Gate In Panel) type display device, in which a gate driving circuit is embedded in a panel, reduces the volume and weight of a display device and reduces manufacturing costs. In the GIP type display device, the gate driving circuit is embedded in the non-display area of the panel by using an amorphous silicon thin film transistor (hereinafter TFT). The gate driving circuit includes a gate shift register for sequentially supplying scan pulses to a plurality of gate lines.

On the other hand, display devices of recent years are in the trend of high resolution, narrow bezel (narrow bezel). Therefore, efforts to reduce the design area of the panel-embedded gate shift resistor are continuously required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a gate shift register and a display device using the same, which can reduce the number of TFTs to facilitate narrow bezel design.

In order to achieve the above object, a gate shift register according to an embodiment of the present invention includes a plurality of stages that receive a plurality of gate shift clocks and sequentially output scan pulses; A kth stage of the plurality of stages includes: a first switching element configured to apply a carry signal of a k-1 stage input through a first input terminal to a Q node in response to an A-1 th gate shift clock; A second switching element configured to apply a gate high voltage to the Q node in response to a carry signal of a k + 2 stage input through a second input terminal; A pull-up switching element configured to apply an A-th gate shift clock to an output node according to the voltage level of the Q node; A pull-down switching device configured to apply the gate high voltage to an output node in response to an A + 2th gate shift clock; And a capacitor provided between the Q node and the output node and connected thereto.

The scan pulse may be supplied to the front or rear stage as the carry signal.

The plurality of gate shift clocks are shifted by one horizontal period each with a pulse width of two horizontal periods; It is characterized by a four-phase cyclic clock which is sequentially delayed from the first gate shift clock to the fourth gate shift clock.

The first and second switching elements and the pull-up and pull-down switching elements may be thin film transistors having a P type.

The gate shift register according to the present invention can reduce the number of TFTs provided in each stage to four, thereby reducing the design area of the embedded gate driver. In addition, the gate low voltage supply line applied to the stages can be eliminated, thereby reducing wiring.

1 is a block diagram of a gate shift register according to an exemplary embodiment of the present invention.
2 is a circuit diagram of a k-th stage STk according to the embodiment.
3 shows the input and output signals of the kth stage STk.
4 is a block diagram of a display device according to an exemplary embodiment.

Hereinafter, a gate shift register according to an exemplary embodiment of the present invention and a display device using the same will be described in detail with reference to the accompanying drawings.

For reference, although the TFT described above in the embodiment may be configured as P type or N type, hereinafter, the TFT is configured as P type. Thus, in the embodiment, the gate-on voltage is the gate-low voltage (VGL) and the gate-off voltage is the gate-high voltage (VGH).

1 is a block diagram of a gate shift register according to an exemplary embodiment of the present invention.

The gate shift register shown in FIG. 1 includes a plurality of stages ST1 to STn that are cascaded and at least two dummy stages (not shown).

In the following description, the "shear stage" is located above the reference stage. For example, the shear stage based on the k th (1 <k <n) stage STk is the "th k-1 stage ST (k -1)) to 1st stage ST1 ". In addition, the "back stage" is located below the reference stage. For example, the rear stage based on the k-th stage STk is the "k + 1th stage STk + 1 to nth stage STn". It indicates either one.

Each stage ST1 to STn includes two input terminals and one output terminal, and outputs a scan pulse through the output terminal. The scan pulse is applied to the gate lines of the flat panel display and serves as a carry signal transmitted to the front stage and the rear stage.

Each of the stages ST1 to STn operates in response to a carry signal of a front stage applied to the first input terminal IN1 and a carry signal of a rear stage applied to the second input terminal IN2. These stages ST1 to STn output scan pulses VOUT1 to VOUTn in the order of “first stage ST1 to kth stage STk to nth stage STn”. However, a gate start pulse of an external (timing control unit) is applied to the first input terminal IN1 of the first stage ST1, and a carry signal of the dummy stage is applied to the second input terminal IN2 of the nth stage STn. Can be applied.

The gate shift register according to the embodiment outputs scan pulses VOUT1 to VOUTn superimposed on each other by a predetermined time. To this end, three gate shift clocks are input to each of the stages ST1 to STn among the gate shift clocks on i (i is a positive even number) that are overlapped for a predetermined time and sequentially delayed. Hereinafter, the four-phase clock pulses CLK1 to CLK4 will be described.

The four-phase clock pulses CLK1 to CLK4 swing between the gate high voltage VGH and the gate low voltage VGL. Each of them is shifted by one horizontal period with a pulse width of two horizontal periods 2H, and adjacent clocks overlap each other by one horizontal period.

2 is a circuit diagram of a k-th stage STk according to the embodiment. The circuit configuration of the kth stage STk is the same as the remaining stages.

Referring to FIG. 2, three gate shift clocks CLKA, CLKA-1, and CLKA + 2 among the four-phase clocks CLK1 to CLK4 are input to the clock terminal of the k-th stage STk. Here, the A-1 th gate shift clock CLKA-1 is a clock output just before the A th gate shift clock CLKA, and the A + 2 th gate shift clock CLKA + 2 is the A th gate shift clock ( CLKA) is the next clock output.

The kth stage STk includes four TFTs and one capacitor. Specifically, the k-th stage STk includes the first and second TFTs T1 and T2, the pull-up TFT TU, and the pull-down TFT TD, and includes a capacitor C.

The first TFT T1 carries the carry signal VOUTk-1 of the k-1 stage STk-1 input through the first input terminal IN1 in response to the A-1 th gate shift clock CLKA-1. ) Is applied to the Q node.

The second TFT T2 applies the gate high voltage VGH to the Q node in response to the carry signal VOUTk + 2 of the k + 2th stage STk + 2 input through the second input terminal IN2. do.

The pull-up TFT TU applies the A-th gate shift clock CLKA to the output node NO according to the voltage level of the Q node.

The pull-down TFT TD applies the gate high voltage VGH to the output node NO in response to the A + 2th gate shift clock CLKA + 2.

The capacitor C is provided between the Q node and the output node NO and connected to them.

As described above, each stage ST1 to STn according to the embodiment includes four TFTs and one capacitor. That is, in the conventional gate shift register, each stage has at least six TFTs, but the gate shift register according to the embodiment can reduce the design area of the embedded gate driver by reducing the TFTs of each stage to four.

3 shows the input and output signals of the kth stage STk. The operation of the k-th stage STk will be described in detail with reference to FIGS. 2 and 3 as follows.

The gate shift clocks CLK1 to CLK4 on the four phases are cyclic clocks sequentially delayed from the first gate shift clock CLK1 to the fourth gate shift clock CLK4. Assume that "CLKA" input to the kth stage STk is "CLK1", "CLKA-1" is assumed to be "CLKA-1" to "CLK4", and "CLKA + 2" is assumed to be "CLK3". do.

In the T1 period, the fourth gate shift clock CLK4 at the gate low voltage VGL level is input as the start signal. In response to this start signal, the first TFT T1 is turned on. As a result, the Q node is pre-charged to the gate low voltage VGL by applying the carry signal VOUTk-1 of the k-th stage STk-1.

In the T2 period, the first gate shift clock CLK1 applied to the drain electrode of the pull-up TFT TU is input at the gate low voltage VGL level. The voltage of the Q node is bootstrapped by the parasitic capacitance between the gate and drain electrodes of the pull-up TFT (TU) to be lowered to a voltage level lower than the gate low voltage VGL to turn on the pull-up TFT (TU). Accordingly, the k th stage STk outputs the k th scan pulse VOUTk having the gate low voltage VGL level.

In the T3 period, the carry signal VOUTk + 2 of the k + 2th stage STk + 2 is input as a reset signal through the second input terminal IN2. In response to this reset signal, the second TFT T2 is turned on. As a result, the Q node is discharged to the gate high voltage VGH, and the pull-up TFT TU is turned off by the discharge of the Q node. At the same time, the third gate shift clock CLK3 having the gate low voltage VGL level is applied to the gate electrode of the pull-down TFT TD to turn on the pull-down TFT TD. Accordingly, the k th stage STk outputs the k th scan pulse VOUTk having the gate high voltage VGH level. At this time, the k th scan pulse VOUTk maintains the gate high voltage VGH level until the start signal of the next frame is applied due to the capacitor C provided between the Q node and the output node NO.

As described above, the embodiment can reduce the number of TFTs provided in each of the stages ST1 to STn to four, thereby reducing the design area of the embedded gate driver. In addition, the embodiment does not need to separately apply the gate low voltage VGL to drive each of the stages ST1 to STn. Accordingly, the gate low voltage VGL supply line applied to each of the stages ST1 to STn can be deleted, thereby reducing the wiring.

4 is a block diagram of a display device according to an exemplary embodiment.

The display device shown in FIG. 4 includes a display panel 2, a data driver 4, a gate driver 6, and a timing controller 8.

The display panel 2 includes a plurality of data lines DL and a plurality of gate lines GL that cross each other, and pixels P arranged in a matrix form. The display panel 2 may be implemented by any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).

The data driver 4 includes at least one source drive IC (not shown). The source drive IC receives the digital video data RGB from the timing controller 8. The source drive IC 120 converts the digital video data RGB into a gamma compensation voltage in response to the source timing control signal DCS from the timing controller 8 to generate a data voltage, and scans the data voltage. The data lines DL of the display panel 2 are supplied to be synchronized with the pulses. The source drive ICs may be connected to the data lines DL of the display panel 2 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The gate driver 6 includes a gate shift register. The gate shift register is composed of stages which sequentially output the carry signal and the scan pulse by shifting the gate start pulse VST provided from the timing controller 8 according to the gate shift clocks CLK1 to CLK4. The gate driver 6 may be formed directly on the lower substrate of the display panel 2 in a GIP (Gate In Panel) manner or may be formed on the gate lines GL of the display panel 2 and the timing controller 8, Respectively.

The timing controller 8 receives digital video data RGB from an external host computer through an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 8 transmits digital video data RGB input from the host computer to the source drive ICs.

The timing controller 8 controls the timing of the vertical synchronizing signal Vsync, the horizontal synchronizing signal Hsync, the data enable signal DE, and the dot clock DCLK from the host computer through the LVDS or TMDS interface receiving circuit. Receive a signal. The timing controller 2 generates timing control signals DCS and GCS for controlling the operation timing of the data and gate drivers 4 and 6 based on the timing signal from the host computer.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

IN1: first input terminal IN2: second input terminal

Claims (9)

A plurality of stages that receive a plurality of gate shift clocks and sequentially output scan pulses; Kth stage of the plurality of stages
A first switching element configured to apply a carry signal of a k-1 stage input to the Q node in response to the A-1 th gate shift clock to the Q node;
A second switching element configured to apply a gate high voltage to the Q node in response to a carry signal of a k + 2 stage input through a second input terminal;
A pull-up switching element configured to apply an A-th gate shift clock to an output node according to the voltage level of the Q node;
A pull-down switching device configured to apply the gate high voltage to an output node in response to an A + 2th gate shift clock;
And a capacitor provided between the Q node and the output node and connected to the Q node. The method of claim 1,
And the scan pulse is supplied to the front or rear stage as the carry signal. The method of claim 1,
The plurality of gate shift clocks are shifted by one horizontal period each with a pulse width of two horizontal periods;
And a four-phase cyclic clock sequentially delayed from the first gate shift clock to the fourth gate shift clock. The method of claim 1,
And the first and second switching elements and the pull-up and pull-down switching elements are thin film transistors of P type. A display panel including a plurality of pixels in which a plurality of gate lines and a plurality of data lines cross each other and are arranged in a matrix;
A gate driver sequentially supplying scan pulses to the plurality of gate lines;
A data driver supplying data voltages to the plurality of data lines;
A timing controller which controls driving timing of the gate driver and the data driver;
The gate driver includes a plurality of stages that receive a plurality of gate shift clocks and sequentially output scan pulses; Kth stage of the plurality of stages
A first switching element configured to apply a carry signal of a k-1 stage input to the Q node in response to the A-1 th gate shift clock to the Q node;
A second switching element configured to apply a gate high voltage to the Q node in response to a carry signal of a k + 2 stage input through a second input terminal;
A pull-up switching element configured to apply an A-th gate shift clock to an output node according to the voltage level of the Q node;
A pull-down switching device configured to apply the gate high voltage to an output node in response to an A + 2th gate shift clock;
And a capacitor provided between the Q node and the output node and connected to the Q node. The method of claim 5, wherein
And the scan pulse is supplied to the front or rear stage as the carry signal. The method of claim 5, wherein
The plurality of gate shift clocks are shifted by one horizontal period each with a pulse width of two horizontal periods;
And a four-phase cyclic clock sequentially delayed from the first gate shift clock to the fourth gate shift clock. The method of claim 5, wherein
And the first and second switching elements and the pull up and pull down switching elements are thin film transistors formed of a P type. The method of claim 5, wherein
And the gate driver is directly formed on a lower substrate of the display panel using a gate in panel (GIP) method.

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