KR102634769B1 - Shift register and display device using the same - Google Patents

Abstract

A shift register according to an embodiment of the present invention is provided with a plurality of stages that are dependently connected to each other. Each stage includes first to third set transistors (Ts1 to Ts3) that control the Q node (Q) with a precharging voltage (Vpc) and a precharging set transistor that applies a precharging voltage (Vpc) to the Q node (Q). It is controlled by the set unit equipped with (Tsp) and the Q node (Q), and scans the nth clock (CLK(N)) supplied to the clock terminal (CK) through the output terminal (OUT) and outputs (Gout ( a first pull-up transistor (Tpu1) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) through the carry terminal (CR), and a second pull-up transistor (Tpu2) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) ) includes a pull-up unit provided with a.

Description

Shift register and display device using the same {SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a shift register and a display device using the same, and more specifically, to a shift register including a circuit unit for controlling the reduction of the output signal of a precharging transistor (Tpc) and a display device using the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Various electronic devices such as mobile phones, tablets, navigation, laptops, televisions, monitors, and public displays (PDs) are deeply embedded in our daily lives. As these electronic devices are basically equipped with display devices, the demand for display devices is also increasing day by day. Display devices include Liquid Crystal Display Device (hereinafter referred to as 'LCD') and Organic Light Emitting Diode Display (hereinafter referred to as 'OLED').

Such a display device includes a plurality of pixels that display an image and a driving circuit that controls light to be transmitted or emitted from each of the plurality of pixels.

The driving circuit of the display device is a data driving circuit that supplies data signals to the data lines of the pixel array, and sequentially supplies gate signals (or scan signals) synchronized with the data signals to the gate lines (or scan lines) of the pixel array. It includes a gate driving circuit (or scan driving circuit) and a timing controller that controls the data driving circuit and the gate driving circuit.

Each of the plurality of pixels may include a thin film transistor that supplies the voltage of the data line to the pixel electrode in response to the gate signal supplied through the gate line. The gate signal swings between Gate High Voltage (VGH) and Gate Low Voltage (VGL). In other words, the gate signal appears in the form of a pulse.

The gate high voltage (VGH) is set to a voltage higher than the threshold voltage of the thin film transistor formed in the display panel, and the gate low voltage (VGL) is set to a voltage lower than the threshold voltage of the thin film transistor. The thin film transistors of the pixels are turned on in response to the gate high voltage.

The gate signal consists of a gate high voltage (VGH) and a gate low voltage (VGL). When the gate signal outputs the gate high voltage (VGH) through the output terminal, the gate line (GL) of the display panel receives the gate high voltage (VGH) and causes the pixel to emit light. After a pixel emits light, the gate signal of the stage output terminal connected to the emitted pixel outputs a gate low voltage (VGL) to prevent the data signal to be transmitted to the next pixel from flowing in. Additionally, it is desirable to prevent ripple signals from flowing in during the time the stage output terminal is maintained at the gate low voltage (VGL).

Recently, as display devices have become thinner, technology for embedding a gate driving circuit in a display panel along with a pixel array is being developed. The gate driving circuit built into the display panel like this is known as the “GIP (Gate-In-Panel) driving circuit”. Here, the GIP driving circuit includes a shift register for generating a gate signal. Shift A register (shift register) includes a plurality of stages that are dependently connected. The plurality of stages generate output in response to a start signal and move the output to the next stage according to the shift signal. Accordingly, the GIP driving circuit generates a gate signal by sequentially driving a plurality of stages in the shift register.

Meanwhile, the GIP driving circuit is composed of a shift register, and the shift register includes a plurality of transistors. While the shift register operates when power and clock signals are applied, a plurality of transistors included in the shift register are exposed to various stresses. Stress occurs not only in the section where the transistor turns on, but also in the section where it turns off. In particular, during the period when the transistor is turned off, junction stress may occur due to the voltage difference between the drain electrode and the source electrode. Transistors exposed to junction stress for a certain period of time may undergo degradation, and deteriorated transistors and shift registers may output unintended signals.

The above-mentioned shift register includes a transistor (hereinafter referred to as a pre-charging transistor (Tpc)) that receives a set signal and pre-charges the Q node (Q). When the pre-charging time of the pre-charging transistor (Tpc) becomes longer, stress occurs in the pull-up transistor (Tpu) among the transistors that make up the plurality of stages, causing stress in the GIP driving circuit. It may affect the output signal of the furnace.

Additionally, the precharging transistor (Tpc) has a diode structure in which a gate electrode and a drain electrode are connected. In this structure, as the threshold voltage (Vth) of the precharging transistor (Tpc) increases, the pre-charging voltage of the Q node (Q) decreases, which reduces the Reduce the bootstrap voltage (Vbc).

As a result, the turn-on rising and turn-off falling times of the pull-up transistor (Tpu) may change, thereby reducing the output signal of the GIP driving circuit. This may lead to problems that weaken the reliability level of the display device.

Therefore, the GIP driving circuit needs to improve the reduction of the output signal of the precharging transistor (Tpc), and various research and development for this purpose are in progress.

As described above, the inventors of the present invention have improved the reduction of the output signal of the precharging transistor (Tpc) of the GIP driving circuit and a shift register including a circuit to increase the precharging voltage (Vpc) of the Q node (Q), and A new structure for a display device including this was invented.

Accordingly, the problem to be solved by the present invention is a circuit unit that controls precharging of the Q node (Q), which can improve the output signal reduction of the GIP driving circuit by increasing the precharging voltage (Vpc) of the Q node (Q). To provide a shift register including and a display device including the same.

In addition, another problem to be solved by the present invention is a shift register including a circuit unit capable of improving the stress of the pull-up transistor (Tpu) among the transistors constituting a plurality of stages, and the same. The purpose is to provide a display device including.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to an embodiment of the present specification, a shift register having a plurality of stages dependently connected to each other is provided. The gate driving circuit includes a plurality of stages. Each stage includes first to third set transistors (Ts1 to Ts3) that control the Q node (Q) with a precharging voltage (Vpc) and a precharging set transistor that applies a precharging voltage (Vpc) to the Q node (Q). It is controlled by the set unit equipped with (Tsp) and the Q node (Q), and scans the nth clock (CLK (N)) supplied to the clock terminal (CK) through the output terminal (OUT) and outputs (Gout ( a first pull-up transistor (Tpu1) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) through the carry terminal (CR), and a second pull-up transistor (Tpu2) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) ) Includes a pull-up unit provided.

A display device according to an embodiment of the present specification is provided. A display device includes a substrate, a display unit with a plurality of pixels defined on the substrate, a non-display unit disposed on at least one side of the display unit, and a Gate In Panel (GIP) circuit located on the non-display unit and corresponding to the plurality of pixels. The GIP circuit includes first to third set transistors (Ts1 to Ts3) that control the Q node (Q) with the precharging voltage (Vpc) and a precharging set transistor that applies the precharging voltage (Vpc) to the Q node (Q). It is controlled by the set unit equipped with (Tsp) and the Q node (Q), and scans the nth clock (CLK(N)) supplied to the clock terminal (CK) through the output terminal (OUT) and outputs (Gout ( a first pull-up transistor (Tpu1) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) through the carry terminal (CR), and a second pull-up transistor (Tpu2) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) ) includes a pull-up unit provided with a.

Specific details of other embodiments are included in the detailed description and drawings.

The present invention relates to first to third set transistors (Ts1 to Ts3) that control the Q node (Q) with a precharging voltage (Vpc) and a precharging set transistor that applies a precharging voltage (Vpc) to the Q node (Q). By providing a set unit with (Tsp), there is an effect of charging the Q node (Q) with a gate high voltage (VGH) with a precharging voltage (Vpc) as low as the threshold voltage (Vth) of the precharging set transistor (Tsp). there is.

In the present invention, the precharging set transistor (Tsp) is composed of three transistors that share one gate electrode connected to the set terminal (S), which has the effect of minimizing high junction stress (HJS).

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

Since the content of the invention described above in the problem to be solved, the means for solving the problem, and the effect do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the invention.

Figure 1 is a block diagram schematically showing the configuration of a display device with a built-in shift register according to an embodiment of the present invention.
Figure 2 is a block diagram showing the configuration of a shift register according to an embodiment of the present invention.
Figure 3 is a circuit diagram showing the configuration of the Nth stage in a shift register according to an embodiment of the present invention.
FIG. 4 is a driving waveform diagram of the Nth stage shown in FIG. 3.
Figure 5 is a graph showing that the precharging section of the Nth stage is 2H according to an embodiment of the present invention.
Figure 6 is a graph showing the voltage applied to the Q node (Q) of the Nth stage according to an embodiment of the present invention.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise. When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as '~ on top', '~ at the top', '~ at the bottom', '~ next to', etc., '~ right away' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

The size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the components shown.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a schematic block diagram of a display device according to an embodiment of the present invention.

Referring to FIG. 1, the display device includes a display panel 110, a timing controller 150, a data driver 120, and scan drivers 130 and 140.

The display panel 110 is divided by data lines (DL) and scan lines (GL) that intersect each other, and includes pixels (PXL) connected to the data lines (DL) and scan lines (GL). . The display panel 110 includes a display area 110A defined by pixels PXL and a non-display area 110B where various signal lines, pads, etc. are formed. The display panel 110 may be implemented as a display panel used in various display devices, such as a liquid crystal display (LCD), an organic light emitting display (OLED), and an electrophoretic display (EPD).

One pixel (PXL) includes a transistor connected to the scan line (GL) or data line (DL) and a pixel circuit that operates in response to the scan signal and the data signal supplied by the transistor. A pixel (PXL) is implemented as a liquid crystal display panel containing a liquid crystal element or an organic light emitting display panel containing an organic light emitting element, depending on the configuration of the pixel circuit.

For example, when the display panel 110 is composed of a liquid crystal display panel, the display panel 110 can be configured in TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, and FFS (Fringe Field Switching) mode. ) mode or ECB (Electrically Controlled Birefringence) mode. When the display panel 110 is composed of an organic light emitting display panel, the display panel 110 may be implemented in a top-emission method, a bottom-emission method, or a dual-emission method, etc. You can.

The timing controller 150 receives timing signals such as a vertical synchronization signal, horizontal synchronization signal, data enable signal, and dot clock through a receiving circuit such as an LVDS or TMDS interface connected to the video board. The timing controller 150 generates timing control signals for controlling the operation timing of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive integrated circuits (ICs). Source drive ICs receive digital video data (RGB) and source timing control signal (DDC) from the timing controller 150. The source drive ICs generate a data voltage by converting digital video data (RGB) into a gamma voltage in response to the source timing control signal (DDC), and generate the data voltage through the data lines (DL) of the display panel 110. supply. The source drive ICs are connected to the data lines DL of the display panel 110 through a Chip On Glass (COG) process or a Tape Automated Bonding (TAB) process. The source drive ICs may be formed on the display panel 110, or may be formed on a separate PCB board and connected to the display panel 110.

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 shifts the level of the clock signals (CLK) input from the timing controller 150 to a TTL (Transistor-Transistor-Logic) level of 0V to 3.3V and then supplies the levels to the shift register 140. . The shift register 140 may be formed in the form of a thin film transistor (TFT) in the non-display area 110B of the display panel 110 using a gate-in-panel (GIP) method. The shift register 140 is composed of stages that shift and output scan signals in response to clock signals (CLK) and start signals (Vst). Stages included in the shift register 140 sequentially output scan signals through a plurality of output terminals.

The scan signal consists of a gate high voltage (VGH) and a gate low voltage (VGL). When the scan signal outputs the gate high voltage (VGH) through the output terminal, the scan line (GL) of the display panel 110 receives the gate high voltage (VGH) and causes the pixel to emit light. After a pixel emits light, the scan signal at the stage output connected to the emitted pixel outputs a gate low voltage (VGL) to prevent the data signal to be transmitted to the next pixel from flowing in. While the pixel (PXL) emits light, the output signal of the stage output is preferably maintained at the gate high voltage (VGH) for a sufficient period of time.

Figure 2 is a block diagram briefly explaining a shift register according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing the configuration of the Nth (N is a natural number) stage (STn) in the shift register according to an embodiment of the present invention shown in FIG. 2. FIG. 4 is a driving waveform diagram of the stage shown in FIG. 3. The shift register 140 includes a plurality of transistors.

The shift register has a plurality of stages (ST1 to STn; n is the number of stages) that are dependently connected to each other and generate individual scan outputs (Gout). For convenience, only the first to fifth stages (ST1 to ST5) are shown in FIG. 2. It is showing. Hereinafter, “front stage” means any one of at least one stage located before (upper) of the corresponding stage, and “backward stage” refers to at least one of the stages located after (lower) of the corresponding stage. It means either one.

Referring to FIG. 2, each of the stages ST1 to STn has a set terminal (S), a reset terminal (R), a clock terminal (CK), a power terminal (PT), an output terminal (OUT), and a carry terminal (CR). etc. are provided.

Referring to FIG. 4, the N-th stage (STn) receives one clock signal (CLK(N)) among clock signals of the i phase (i is a positive integer) with different phases. For example, the clock signal (CLK(N)) of any one of the 8-phase clock signals (CLK1 to CLK8) whose high logic sections partially overlap each other with sequential phase delays can be supplied to the Nth stage (STn). You can.

For the 8-phase clock signals (CLK1 to CLK8), the high logic sections are sequentially phase-delayed by 1H periods, and each clock signal has 3H periods, 2H periods, and 1H periods among the high logic sections with the high logic sections of each of the other adjacent clocks. Overlap is possible. These 8-phase clock signals (CLK1 to CLK8) are sequentially output as scan outputs (Gout), and each scan output (Gout) also has a high section of 4H period, thereby providing sufficient charging time in high-speed driving. In the 8-phase clock signals (CLK1 to CLK8), a clock (CLK(N)) having an N-th phase and a clock (CLK(N+4)) having an N+4-th phase, for example, the first clock (CLK) and the fifth clock (CLK) have phases inverted from each other.

Referring to FIG. 4, the clock signal (CLK(N)) with the Nth phase output as the scan output (Gout(N)) and the carry signal (CRY(N)) in the Nth stage is a high logic (4H period) The gate-on voltage) section and the low logic (gate-off voltage) section of the 4H period are alternately repeated.

In addition, the clock signal (CLK(N)) having the N-th phase is the N-2th front-end carry signal (CRY(N-2)) and the N+2-th front-end carry signal (CRY(N+), which are used as set signals. 2)) and the high section overlap by 2H each, and the high section does not overlap with the N+4th rear carry signal (CRY(N+4)) used as a reset signal.

The Nth stage (STn) shown in FIG. 3 includes a pull-up period including the first and second periods (t1, t2) shown in FIG. 4 for each frame, and a third period (t3) and thereafter. It can be driven with a pull-down period.

Referring to FIG. 4, the first section (t1) is a section in which the N-2nd front-end carry signal (CRY(N-2)) is maintained at a high voltage for a period of 2H. Additionally, the first section (t1) is a section (PC) in which the Q node (Q) is precharged.

The second section (t2) is a section in which the carry signal (CRY(N)) is maintained at a high voltage for a period of 4H, and is a section (BS) in which the Q node (Q) is bootstrapped.

The third section (t3) is a section in which the N+4th rear carry signal (CRY(N+4)) is maintained at a high voltage for a period of 2H.

Referring to FIG. 2, the terminals of each stage will be described in detail.

The set terminal (S) can receive the start signal (Vst) supplied through the start signal line or the front-end carry signal (CRY(N-2)) supplied from the front-end stage (STn-2) as a set signal.

Additionally, in response to the set signal, the Q node (Qn) of each stage (ST) may be sequentially pre-charged and pulled up.

Additionally, the reset terminal (R) can receive the rear-stage carry signal (CRY(N+4)) supplied from the carry terminal (CR) of the rear-stage stage as a reset signal.

The clock terminal (CK) receives one or more clock signals (CLK(N)) among clock signals of different phases. Subsequently, the clock signal CLK(N) having the N-th phase may be output as a scan output Gout(N) through the output terminal OUT.

The power terminal (PT) may be supplied with a low potential voltage (VSS) and a gate low voltage (VGL) used as a low voltage of the carry signal (CRY(N)) or the output voltage (Gout(N)).

Therefore, each stage (ST) is set by the start signal (Vst) or the previous carry signal (CRY (N-2)) supplied from one of the previous stages and sends the corresponding clock (CLK (N)) to the scan output (Gout (N)) or a carry signal (CRY(N)).

In addition, each stage (ST) is reset by the rear carry signal (CRY(N+4)) supplied from one of the rear stage and turns the gate low voltage (VGL) into the scan output (Gout(N)). output, and the low potential voltage (VSS) is output as a carry signal (CRY(N)).

Additionally, the Q node (Q) of each stage (ST) may be pulled down by the low potential voltage (VSS) supplied through the power terminal (PT) in response to the reset signal.

Referring to FIG. 3, the operation of the Nth stage (STn) will be described in detail. The Nth stage (STn) has a SLC (Simple Logic Circuit) structure.

The SLC structure of the Nth stage (STn) shown in FIG. 3 includes a set unit 210, a pull-up unit 220, a pull-down unit 230, a reset unit 240, a noise removal unit 250, and a stabilization unit 260. ) and an inverter 270.

The Nth stage (STn) adds a bootstrap capacitor (CB) between the scan output (Gout (N)) and the Q node (Q) in the transistor of the pull-up unit 220 involved in the scan output (Gout (N)). By doing this, the Q node (Q) can be bootstrapped. As a result, the voltage of the Q node (Q) connected to the gate electrode of the pull-up transistor is significantly bootstrapped.

The set unit 210 connected to the Q node (Q) is involved in precharging the Q node (Q), and the noise removal unit 250 connected to the Q node (Q) generates ripples in the Q node (Q). can be prevented. Additionally, the reset unit 240 connected to the Q node (Q) may discharge the voltage of the Q node (Q) to a low voltage after the scan output (Gout (N)).

Referring to FIGS. 3 and 4, the set unit 210 according to an embodiment of the present invention uses the N-2th front-end carry signal (CRY(N-2)) and the N+2-th front-end carry signal (CRY(N) +2)) is supplied as a set signal to precharge the Q node (Q) with the high voltage of the set signal (hereinafter expressed as precharging voltage (Vpc)). Here, the precharging voltage (Vpc) may be the gate high voltage (VGH).

Below, the configuration and connection relationship of the set unit 210 will be described.

The set unit 210 is configured to apply a precharging voltage (Vpc) to the first to third set transistors (Ts1 to Ts3) that control the precharging voltage (Vpc) of the Q node (Q) and the Q node (Q). A charging set transistor (Tsp) is provided.

The gate electrode and drain electrode of the first set transistor Ts1 have a diode structure, and the N-2nd front carry signal CRY(N-2) is supplied as the gate high voltage VGH. The source electrode of the first set transistor (Ts1) is connected to the gate electrode of the precharging set transistor (Tsp). As a result, the gate electrode of the precharging set transistor (Tsp) is charged with a voltage equal to the difference between the gate high voltage (VGH) and the threshold voltage (Vth).

The precharging set transistor (Tsp) consists of three transistors that share one gate electrode connected to the set terminal (S), and is connected in series between the set terminal (S) and the Q node (Q). In other words, the high junction stress (HJS) of three precharging set transistors (Tsp) connected in series can be distributed. Additionally, the precharging set transistor (Tsp) can improve the driving current (Ion) drop phenomenon caused by high junction stress (HJS).

The gate electrode of the precharging set transistor (Tsp) is connected to the set terminal (S), and the drain electrode of the precharging set transistor (Tsp) is connected to the N-2th front carry signal (CRY(N-2)) terminal. Additionally, the Q node (Q) is connected to the source electrode of the precharging set transistor (Tsp). When the N-2nd front-end carry signal (CRY(N-2)) becomes the gate high voltage (VGH), the gate electrode of the precharging set transistor (Tsp) is the difference between the gate high voltage (VGH) and the threshold voltage (Vth). As the voltage rises, the precharging set transistor (Tsp) turns on.

Subsequently, the source electrode of the precharging set transistor (Tsp) rises from the gate low voltage (VGL) to the gate high voltage (VGH). At this time, a coupling effect occurs due to the parasitic capacitance (Cgs) of the precharging set transistor (Tsp), causing the voltage of the gate electrode to rise above the gate high voltage (VGH).

Accordingly, the output voltage of the precharging set transistor (Tsp) increases. This may result in increasing the precharging voltage (Vpc) of the Q node (Q). That is, the voltage charged at the Q node (Q) can be charged at the gate high voltage (VGH) without being lowered by the threshold voltage (Vth) of the precharging set transistor (Tsp).

The gate electrode and source electrode of the second set transistor Ts2 are connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharging set transistor Tsp. As a result, the second set transistor Ts2 is turned on by receiving a voltage equal to the gate electrode minus the threshold voltage (Vth) from the gate high voltage (VGH) charged at the source electrode of the first set transistor (Ts1). do.

Additionally, the gate high voltage (VGH) of the N-2nd front carry signal (CRY(N-2)) is applied to the drain electrode of the second set transistor (Ts2). The source electrode of the second set transistor Ts2 is charged with a voltage higher than the gate high voltage VGH applied to the gate electrode of the precharging set transistor Tsp. Subsequently, the second set transistor (Ts2) discharges a voltage higher than the gate high voltage (VGH) applied to the source electrode to the drain electrode so that the voltage drops by the gate high voltage (VGH).

The gate electrode of the third set transistor (Ts3) is supplied with the N+2th front carry signal (CRY(N+2)), and the drain electrode of the third set transistor (Ts3) is the gate electrode of the precharging set transistor (Tsp). It is connected to the electrode. The source electrode of the third set transistor (Ts3) is connected to the low potential voltage (Vss). As a result, the third set transistor (Ts3) is turned on in response to the high voltage of the N+2th front-end carry signal (CRY(N+2)), and the voltage applied to the gate electrode of the pre-charging set transistor (Tsp) is discharged to low potential voltage (VSS).

Therefore, during the first period t1, the set unit 210 including the first to third set transistors Ts1 to Ts3 prevents the voltage of the Q node Q from falling below the gate high voltage VGH. do. That is, during the first period t1, the set unit 210 controls the voltage of the Q node Q to maintain the gate high voltage VGH.

Referring to FIGS. 3 and 4, the pull-up unit 220 is pulled up under the control of the Q node (Q) and scans the clock signal (CLK(N)) having the Nth phase supplied to the clock terminal (CK). It is output as an output (Gout(N)) and also as a carry signal (CRY(N)).

The pull-up unit 220 includes first and second pull-up transistors (Tpu1 and Tpu2). The first pull-up transistor Tpu1 has a gate electrode connected to the Q node (Q), a drain electrode connected to the clock terminal (CK), and a source electrode connected to the output terminal (OUT). The second pull-up transistor Tpu2 has a gate electrode connected to the Q node (Q), a drain electrode connected to the clock terminal (CK), and a source electrode connected to the carry terminal (CR).

The first pull-up transistor Tpu1 of the pull-up unit 220 is turned on by the precharging voltage Vpc, which is a high voltage of the Q node Q. Subsequently, the clock signal (CLK(N)) having the N-th phase is output as the scan output (Gout(N)) through the output terminal (OUT).

The second pull-up transistor Tpu2 is turned on by the precharging voltage (Vpc) of the Q node (Q). Subsequently, the clock signal CLK(N) having the N-th phase is output as the carry signal CRY(N) through the carry terminal CR.

Therefore, during the second period t2, the scan output Gout(N) and the carry signal CRY(N) are output using the first and second pull-up transistors Tpu1 and Tpu2 of the pull-up unit 220. It can be printed.

Referring to FIGS. 3 and 4, in the first period (t1), the low voltage of the clock signal (CLK(N)) having the Nth phase is connected to the scan output (Gout(N)) and the carry signal (CRY(N)). is output as a low voltage, and in the second period (t2), the high voltage of the clock signal (CLK(N)) having the Nth phase is the high voltage of the scan output (Gout (N)) and the carry signal (CRY (N)). It is output as voltage.

Specifically, the first period (t1) is a precharging period (PC), and the second period (t2) is a bootstrap period (BS). During the precharging period (PC), the Q node (Q) is precharged with the precharging voltage (Vpc). In addition, during the second period (t2), the Q node (Q) generates a precharging voltage (Vpc) due to the coupling phenomenon of the bootstrap capacitor (CB) located between the gate electrode and the source electrode of the first pull-up transistor (Tpu1). ) rises significantly.

As a result, during the pre-charging period (PC), the first and second pull-up transistors (Tpu1, Tpu2) are turned on by the pre-charging voltage (Vpc) of the charged Q node (Q), and the N-th stage output terminal ( A scan output (Gout(N)) and a carry signal (CRY(N)) corresponding to the clock signal (CLK(N)) having the Nth phase are output through OUT). At this time, the clock signal (CLK(N)) is in a low state, so the output terminal of the Nth stage (STn) outputs the gate low voltage (VGL).

Subsequently, during the bootstrap section BS, when the clock signal CLK(N) is in a high state, the output terminal of the Nth stage STn outputs the gate high voltage VGH.

Additionally, the potential change during the bootstrap section (BS) of the Q node (Q) can be explained in relation to the law of charge conservation.

In this way, the law of charge conservation is as follows [Equation 1].

[Equation 1]

Q = CV, Q1 = Q2

C1(ΔVa - ΔVb) = C2(ΔVb - ΔVc), ΔVc=0

C1(ΔVa - ΔVb) = C2ΔVb

∴ΔV2= C1/C1+C2* ΔV1

Here, C1 is the capacitance of the bootstrap capacitor (CB), ㅿVa is the potential change of the Q node (Q), ㅿVb is the potential change of the N-th stage output stage, C2 is the parasitic capacitance of the first pull-up transistor (Tpu1), ㅿVc is the potential change amount of the clock signal (CLK(N)).

Specifically, when the high voltage of the scan output (Gout(N)) is applied to the source electrode of the first pull-up transistor (Tpu1), a voltage change occurs at the source electrode. Next, the voltage applied to the floating gate electrode, Q node (Q), is bootstrapped.

Accordingly, in the bootstrap section BS, the Q node Q rises to a voltage greater than the precharging (hereinafter referred to as bootstrap voltage Vbs), as shown in FIG. 4.

In addition, the bootstrap section (BS) of the present invention is a section in which the Q node (Q) charged with a certain precharging voltage (Vpc) is bootstrapped and maintained at a bootstrap voltage (Vbs) higher than the high voltage (VGH), This is a section in which the gate-source voltage (Vgs) of the first pull-up transistor (Tpu1) is greater than the threshold voltage (Vth). Accordingly, the first pull-up transistor Tpu1 can be turned on for a sufficiently long time, so that the scan output (Gout(N)) of the Nth stage (STn) can be stably controlled. Additionally, this can increase the reliability of the GIP driving circuit.

In addition, the bootstrap capacitor (CB) connected between the gate electrode and the source electrode of the first pull-up TFT (Tpu1) pulls up the first pull-up transistor (Tpu1) to output a high voltage of the corresponding clock signal (CLK(N)). The rising time of the scan output (Gout(N)) can be reduced by bootstrapping and amplifying the precharging voltage (Vpc) of the Q node (Q).

The role of the pull-up unit 220 is to transfer the clock signal CLK(N) input from the drain electrode to the source electrode while the first pull-up transistor Tpu1 is turned on. At this time, the condition for turning on the first pull-up transistor (Tpu1) is when the gate-source voltage (Vgs) is greater than the threshold voltage (Vth). Additionally, in the section where the gate-source voltage (Vgs) is smaller than the threshold voltage (Vth), the Q node (Q) is not bootstrapped and can be maintained at the pre-charging voltage (Vpc).

Referring to FIGS. 2 to 4, the reset unit 240 uses the reset pulse or the N+4th carry signal (CRY(N+4)) supplied from the N+4th rear stage as a reset signal to the reset terminal (R). ) is supplied to. The reset signal input to the reset unit 240 resets (discharges) the Q node (Q) and the output terminal (OUT) that outputs the scan output (Gout (N)). For convenience, the following will describe a case where the N+4th carry signal (CRY(N+4)) is supplied as a reset signal to the reset terminal (R).

The reset unit 240 is controlled by a reset signal (CRY(N+4)) and includes first and second reset transistors (Trs1 and Trs2) that reset the Q node (Q) and the output terminal (OUT), respectively. do. Additionally, the first and second reset transistors Trs1 and Trs2 are simultaneously turned on when the reset signal CRY(N+4) is a high voltage.

The first reset transistor (Trs1) discharges the Q node (Q) to a low potential voltage (VSS). The second reset transistor (Trs2) discharges the output terminal (OUT) to the gate low voltage (VGL).

The first reset transistor (Trs1) has a structure in which two transistors sharing a gate electrode connected to the reset terminal (R) are connected in series between the Q node (Q) and a supply terminal of the low potential voltage (VSS).

Therefore, during the third period (t3), the reset unit 240 uses the first and second reset transistors (Trs1 and Trs2) to set the Q node (Q) to the low potential voltage (VSS) and the output terminal (OUT). is discharged to the gate low voltage (VGL).

Referring to FIGS. 3 and 4 , the inverter 270 includes first to fourth inverter TFTs (Ti1 to Ti4).

The first inverter transistor Ti1 has a diode structure in which a gate electrode and a drain electrode are connected to a clock terminal (CK) to which a clock signal (CLK(N)) having the N-th phase is supplied, and a source electrode is connected to the control node (CN). Electrodes are connected.

The second inverter transistor Ti2 has a gate electrode connected to the control node CN, a drain electrode connected to the clock terminal CK, and a source electrode connected to the inverter output node VN.

The third inverter transistor Ti3 has a gate electrode connected to the carry terminal CR, a drain electrode connected to the control node CN, and a source electrode connected to a supply terminal of the low potential voltage VSS.

The fourth inverter transistor Ti4 has a gate electrode connected to the carry terminal CR, a drain electrode connected to the inverter output node VN, and a source electrode connected to a supply terminal of the low potential voltage VSS.

The first inverter TFT (Ti1) is turned on by the high voltage of the clock signal (CLK(N)) having the Nth phase, and the high voltage of the clock signal (CLK(N)) is applied to the control node (CN). It is charged. Subsequently, the second inverter TFT (Ti2) is turned on by the charged control node (CN) and outputs the clock signal (CLK(N)) having the Nth phase as the inverter output (Vinv(N)).

The third and fourth inverter TFTs (Ti3, Ti4) are turned on by the Nth carry signal (CRY(N)) to set the control node (CN) and the inverter output node (VN) to the low potential voltage (VSS). Discharge.

Therefore, even if the first and second inverter transistors Ti1 and Ti2 of the inverter unit 270 are turned on during the second period t2 for outputting the clock signal CLK(N) having the N-th phase, , the inverter output (Vinv(N)) outputs a low potential voltage (VSS) by the turned-on third and fourth inverter TFTs (Ti3, Ti4). Additionally, each of the first to fourth inverter TFTs (Ti1 to Ti4) has a structure in which two TFTs sharing a gate electrode are connected in series.

3 and 4, the pull-down unit 230 connects the carry terminal (CR) and the output terminal (OUT) in response to the control of the inverter output node (VN) to which the Nth inverter output (Vinv(N)) is supplied. discharges.

The pull-down unit 230 includes a first pull-down transistor (Tpd1) that is controlled by the N-th inverter output (Vinv(N)) to discharge the carry terminal (CR) to a low potential voltage (VSS), and an N-th inverter output (Vinv). (N)) and has a second pull-down transistor (Tpd2) that discharges the output terminal to the gate low voltage (VGL).

Accordingly, whenever the high voltage of the N-th inverter output (Vinv(N)) is supplied in synchronization with the clock signal (CLK(N)) having the N-th phase, the first pull-down transistor (Tpd1) and the second pull-down transistor (Tpd2) is turned on to prevent multi-output of the carry signal (CRY(N)) and scan output (Gout(N)).

Referring to Figures 3 and 4, the noise removal unit 250 of the present invention discharges the Q node (Q) to a low potential voltage (VSS) in response to control of the Nth inverter output (Vinv(N)). The noise removal unit 250 includes a noise removal transistor (Tnp) having a structure in which two transistors sharing a gate electrode are connected in series.

The gate electrode of the noise removal transistor (Tnp) is supplied with the Nth inverter output (Vinv(N)), the drain electrode is connected to the Q node (Q), and the source electrode is connected to the low potential voltage (VSS) supply terminal.

Accordingly, the noise removal transistor Tnp is turned on by the high voltage of the Nth inverter output Vinv(N), thereby discharging the Q node Q to the low potential voltage VSS.

As a result, the ripple of the Q node (Q) caused by coupling of the clock signal (CLK(N)) having the Nth phase can be removed.

3 and 4, the stabilization unit 260 of the present invention resets the inverter control node (CN), the inverter output node (VN), and the output terminal (OUT) in response to the stabilization signal (Vstable), respectively. It is provided with first to third stabilization transistors (Tst1 to Tst3). The first to third stabilization transistors Tst1 to Tst3 are simultaneously turned on by the stabilization signal Vstable during each vertical blank period of the vertical synchronization signal.

The first stabilization TFT (Tst1) discharges the inverter control node (CN) to a low voltage (VSS), and the second stabilization TFT (Tst2) discharges the inverter output node (VN) to a low voltage (VSS), The third stabilization TFT (Tst3) initializes all major nodes of the stage by discharging the output terminal to the gate low voltage (VGL). In addition, referring to FIG. 3, the gate low voltage (VGL) and the low potential voltage (VSS) supplied to the Nth stage (STn) are low potential voltages of negative polarity that can turn off the transistor, and are the first and second low potential voltages that can turn off the transistor. 2 Each can be expressed as a gate-off voltage. The low potential voltage (VSS) is the second gate-off voltage and is lower than the gate low voltage (VGL) used for scan output, that is, the first gate-off voltage. Accordingly, the low potential voltage (VSS) can reduce leakage current by stably turning off the transistor.

Figure 5 is a graph showing that the precharging section of the Nth stage is 2H according to an embodiment of the present invention.

Referring to FIG. 5, the set unit 210 supplies the N-2nd front-end carry signal (CRY(N-2)) as a set signal to set the Q node (Q) at the high voltage (hereinafter referred to as pre-charging voltage) of the set signal. Precharge (expressed as (Vpc)).

The clock signal (CLK(N)) with the Nth phase output from the Nth stage (STn) to the scan output (Gout(N)) and carry signal (CRY(N)) is a high logic (gate-on voltage) with a period of 4H. ) section and the low logic (gate-off voltage) section of the 4H period are alternately repeated. The Q node (Q) is precharged in response to the N-2nd front-end carry signal (CRY(N-2)), and the precharging section is maintained for a 2H period.

The Nth stage (STn) according to an embodiment of the present invention uses the front-end carry signal (CRY(N-2)) as a set signal. This can reduce the precharging time of the Q node (Q).

Specifically, by using the front-end carry signal (CRY(N-2)), the precharging time of the Q node (Q) is reduced, so that the first pull-up transistor ( The stress time experienced by Tpu1) is reduced. As a result, the pull-up unit 220 involved in outputting the clock (CLK(N)) from the Nth (N is a natural number) stage (STn) as a scan output (Gout (N)) or a carry signal (CRY (N)) ) can minimize stress and deterioration of the first pull-up transistor (Tpu1).

Figure 6 is a graph showing the voltage applied to the Q node (Q) of the Nth stage according to an embodiment of the present invention. That is, it is a graph showing the voltage applied to the Q node (Q), which is the gate electrode of the first pull-up transistor (Tpu1) constituting the pull-up unit.

Referring to FIG. 6, during the pre-charging period, the graph of the comparative example shows that the Q node (Q) is charged with a pre-charging voltage (Vpc) as low as the threshold voltage (Vth) of the transistor involved in pre-charging.

The set unit 210 of the present invention applies the precharging voltage (Vpc) to the first to third set transistors (Ts1 to Ts3) and the Q node (Q), which controls the precharging voltage (Vpc) of the Q node (Q). A precharging set transistor (Tsp) is provided.

During the precharging period (PC), the graph of the embodiment shows that the precharging set transistor (Tsp) involved in precharging outputs the gate high voltage (VGH), so that the precharging voltage (Vpc) charged to the Q node (Q) increases. It shows what has been done.

Additionally, during the bootstrap section (BS), the graph of the embodiment shows that the Q node (Q) is precharged with the high voltage (VGH) and then bootstrapped with the bootstrap voltage (Vbs).

Accordingly, the Q node (Q) significantly increases to the bootstrap voltage (Vbs) due to the coupling phenomenon of the bootstrap capacitor (CB) located between the gate electrode and the source electrode of the first pull-up transistor (Tpu1).

Referring to FIG. 6, it can be seen that the bootstrap voltage (Vbs) of the embodiment is higher than the bootstrap voltage (Vbs) of the comparative example. This means that the gate electrode voltage of the first pull-up transistor (Tpu1) increases. As a result, the rising and falling times of the first pull-up transistor Tpu1 can be improved. This can improve the lifespan of the GIP circuit.

Below, a circuit unit that controls precharging of the Q node (Q), which increases the precharging voltage (Vpc) of the Q node (Q) and improves the output signal reduction of the GIP driving circuit according to an embodiment of the present invention. Various features of the shift register and the display device including the shift register will be described.

In a shift register having a plurality of stages dependently connected to each other, each stage includes first to third set transistors (Ts1 to Ts3) and Q node (Q) that control the Q node (Q) with a precharging voltage (Vpc). ) a set unit including a precharging set transistor (Tsp) for applying a precharging voltage (Vpc) to; and a first signal that is controlled by the Q node (Q) and outputs the nth clock (CLK(N)) supplied to the clock terminal (CK) as a scan output (Gout(N)) through the output terminal (OUT). It includes a pull-up transistor (Tpu1) and a second pull-up transistor (Tpu2) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) through the carry terminal (CR). .

According to another feature of the present invention, the set unit sets the N-2th front-end carry signal (CRY(N-2)) and the N+2-th front-end carry signal (CRY(N+2)), which are the gate high voltage (VGH). By receiving the signal, the Q node (Q) can be charged with the precharging voltage (Vpc).

According to another feature of the present invention, the gate electrode and drain electrode of the first set transistor (Ts1) have a diode structure, and the N-2th front carry signal (CRY(N-2)) is converted to the gate high voltage (VGH). can be supplied.

According to another feature of the present invention, the source electrode of the first set transistor (Ts1) may be connected to the precharging set transistor (Tsp).

According to another feature of the present invention, the precharging set transistor (Tsp) is composed of three transistors sharing one gate electrode connected to the set terminal (S), thereby minimizing high junction stress (HJS). can do.

According to another feature of the present invention, the gate electrode of the precharging set transistor (Tsp) is connected to the first set transistor (Ts1) and the second set transistor (Ts2), and the drain electrode of the precharging set transistor (Tsp) is connected to the first set transistor (Ts1) and the second set transistor (Ts2). The N-2nd front-end carry signal (CRY(N-2)) can be supplied.

According to another feature of the present invention, the source electrode of the precharging set transistor (Tsp) may be connected to the Q node (Q).

According to another feature of the present invention, the gate electrode and source electrode of the second set transistor (Ts2) are connected to the source electrode of the first set transistor (Ts1) and the gate electrode of the precharging set transistor (Tsp), and the second The drain electrode of the set transistor (Ts2) may be supplied with the N-2nd front carry signal (CRY(N-2)).

According to another feature of the present invention, the gate electrode of the third set transistor (Ts3) is supplied with the N+2th front-end carry signal (CRY(N-2)), and the drain electrode of the third set transistor (Ts3) is supplied with It is connected to the precharging set transistor (Tsp), and the source electrode of the third set transistor (Ts3) may be connected to the low potential voltage (Vss).

According to another feature of the present invention, the third set transistor (Ts3) is turned on by the high voltage of the N+2th front-end carry signal (CRY(N+2)), and the gate of the precharging set transistor (Tsp) is turned on. The voltage applied to the electrode can be discharged to low potential voltage (VSS).

According to another feature of the present invention, the set unit can charge the Q node (Q) with the gate high voltage (VGH) so that the voltage of the Q node (Q) does not become lower than the gate high voltage (VGH).

According to another feature of the present invention, the first pull-up transistor Tpu1 is turned on by the precharging voltage Vpc, which is the high voltage of the Q node Q, during the first period, and the high voltage Vpc is turned on during the second period. The clock signal (CLK(N)) can be scanned and output (Gout(N)) through the output terminal (OUT).

According to another feature of the present invention, the second pull-up transistor Tpu2 is turned on by the precharging voltage Vpc, which is the high voltage of the Q node Q, during the first period, and the high voltage Vpc is turned on during the second period. A carry signal (CRY(N)) can be output from the clock signal (CLK(N)) through the carry terminal (CR).

According to another feature of the present invention, the Q node (Q) is charged with the precharging voltage (Vpc) during the precharging section (PC) and by coupling of the bootstrap capacitor (BC) during the bootstrap section (BS). It can rise to a voltage higher than the precharging voltage (Vpc).

According to another feature of the present invention, the shift register is controlled by a reset terminal and may further include a reset unit that resets the output terminal (OUT) that outputs the Q node (Q) and the scan output (Gout (N)). You can.

According to another feature of the present invention, the shift register includes a first inverter transistor (Ti1) whose gate electrode and drain electrode are connected to the clock terminal (CK) in a diode structure and whose source electrode is connected to the control node (CN); A second inverter transistor (Ti2) with a gate electrode connected to the control node (CN), a drain electrode connected to the clock terminal (CK), and a source electrode connected to the inverter output node (VN), and a carry terminal (CR) The gate electrode is connected to the third inverter transistor (Ti3), the drain electrode is connected to the control node (CN), the source electrode is connected to the supply terminal of the low potential voltage (VSS), and the gate is connected to the carry terminal (CR). It may further include an inverter having a fourth inverter transistor (Ti4) to which an electrode is connected, a drain electrode is connected to the inverter output node (VN), and a source electrode is connected to a supply terminal of the low potential voltage (VSS). .

According to another feature of the present invention, the inverter output ( Vinv(N)) can be output as low potential voltage (VSS).

According to another feature of the present invention, the shift register is a pull-down register that discharges the carry terminal (CR) and the output terminal (OUT) in response to the control of the inverter output node (VN) to which the inverter output (Vinv(N)) is supplied. It can include more wealth.

According to another feature of the present invention, the shift register may further include a noise removal unit that discharges the Q node (Q) to the low potential voltage (VSS) in response to control of the inverter output (Vinv(N)).

According to another feature of the present invention, the shift register is the first to the first to reset the inverter control node (CN), the inverter output node (VN), and the output terminal (OUT) in response to the stabilization signal (Vstable). It may further include a stabilization unit including three stabilization transistors (Tst1 to Tst3).

A display device includes a display unit in which a plurality of pixels are defined on a substrate; a non-display portion disposed on at least one side of the display portion; and a GIP (Gate In Panel) circuit located on the non-display portion and corresponding to a plurality of pixels, wherein the GIP circuit portion includes first to third set transistors that control the Q node (Q) with a precharging voltage (Vpc). (Ts1 to Ts3) and a set unit including a precharging set transistor (Tsp) for applying a precharging voltage (Vpc) to the Q node (Q); And it is controlled by the Q node (Q), and outputs the nth clock (CLK(N)) supplied to the clock terminal (CK) as a scan output (Gout(N)) through the output terminal (OUT). It includes a pull-up transistor (Tpu1) and a pull-up transistor (Tpu2) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) through the carry terminal (CR). .

The set unit can charge the Q node (Q) with the precharging voltage (Vpc) by receiving the N-2nd front carry signal (CRY(N-2)), which is the gate high voltage (VGH), in the precharging section (PC). there is.

The gate electrode and drain electrode of the first set transistor (Ts1) form a diode structure and receive the N-2nd front carry signal (CRY(N-2)) with the gate high voltage (VGH), and the first set transistor (Ts1) ) The source electrode may be connected to the precharging set transistor (Tsp).

The gate electrode of the precharging set transistor (Tsp) is connected to the first set transistor (Ts1) and the second set transistor (Ts2), and the drain electrode of the precharging set transistor (Tsp) is connected to the N-2th front carry signal (CRY). (N-2)), and the source electrode of the precharging set transistor (Tsp) may be connected to the Q node (Q).

The gate electrode and source electrode of the second set transistor Ts2 are connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharging set transistor Tsp, and the drain electrode of the second set transistor Ts2 is connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharging set transistor Tsp. The N-2nd front-end carry signal (CRY(N-2)) can be supplied.

The gate electrode of the third set transistor (Ts3) is supplied with the N+2th front-end carry signal (CRY(N-2)), and the drain electrode of the third set transistor (Ts3) is connected to the precharging set transistor (Tsp). The source electrode of the third set transistor Ts3 may be connected to the low potential voltage Vss.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100: Organic light emitting display device 110: Display panel
110A: Display area 110B: Non-display area
120: data driver 130: level shifter
140: shift register 150: timing controller
210: set part 220: pull-up part
230: pull-down unit 240: reset unit
250: noise removal unit 260: stabilization unit
270: inverter

Claims (26)

In a shift register having a plurality of stages dependently connected to each other,
Each stage,
First to third set transistors (Ts1 to Ts3) that control the Q node (Q) with the precharging voltage (Vpc) and a precharging set transistor (Tsp) that applies the precharging voltage (Vpc) to the Q node (Q) A set unit provided with; and
It is controlled by the Q node (Q) and outputs the nth clock (CLK(N)) supplied to the clock terminal (CK) as a scan output (Gout(N)) through the output terminal (OUT). A pull-up unit including a pull-up transistor (Tpu1) and a second pull-up transistor (Tpu2) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) through the carry terminal (CR). And
The precharging set transistor (Tsp) is a shift register including three transistors sharing one gate electrode connected to at least one of the first to third set transistors (Ts1 to Ts3). According to paragraph 1,
The set unit receives the N-2th front-end carry signal (CRY(N-2)) and the N+2-th front-end carry signal (CRY(N+2)), which are the gate high voltage (VGH), as set signals and connects the Q node to the Q node. A shift register that charges (Q) to the precharging voltage (Vpc). According to paragraph 2,
A shift register in which the gate electrode and drain electrode of the first set transistor (Ts1) have a diode structure, and the N-2th front-end carry signal (CRY(N-2)) is supplied as a gate high voltage (VGH). According to paragraph 2,
A shift register where the source electrode of the first set transistor (Ts1) is connected to the precharging set transistor (Tsp). delete According to paragraph 2,
The gate electrode of the precharging set transistor (Tsp) is connected to the first set transistor (Ts1) and the second set transistor (Ts2), and the drain electrode of the precharging set transistor (Tsp) is connected to the N-2th set transistor (Tsp). Shift register supplied with front-end carry signal (CRY(N-2)). According to paragraph 2,
The source electrode of the precharging set transistor (Tsp) is a shift register connected to the Q node (Q). According to any one of claims 2 to 4,
The gate electrode and source electrode of the second set transistor (Ts2) are connected to the source electrode of the first set transistor (Ts1) and the gate electrode of the precharging set transistor (Tsp), and the second set transistor (Ts2) The drain electrode of is a shift register that receives the N-2nd front carry signal (CRY(N-2)). According to paragraph 2,
The gate electrode of the third set transistor (Ts3) receives the N+2th front-end carry signal (CRY(N+2)), and the drain electrode of the third set transistor (Ts3) receives the pre-charging set transistor ( A shift register connected to Tsp), and the source electrode of the third set transistor (Ts3) is connected to a low potential voltage (Vss). According to clause 9,
The third set transistor (Ts3) is turned on by the high voltage of the N+2th front-end carry signal (CRY(N+2)), and the voltage applied to the gate electrode of the precharging set transistor (Tsp) is A shift register that discharges to low potential voltage (VSS). According to clause 7,
The set unit connects the Q node (Q) to the precharging voltage (Vpc) having a voltage level of the gate high voltage (VGH) so that the voltage of the Q node (Q) does not become lower than the gate high voltage (VGH). A shift register that is charged with . According to paragraph 1,
The first pull-up transistor (Tpu1) is turned on by the precharging voltage (Vpc), which is the high voltage of the Q node (Q) during the first period, and the nth clock (which is high voltage) during the second period. A shift register that scans CLK(N)) and outputs (Gout(N)) through the output terminal (OUT). According to paragraph 1,
The second pull-up transistor (Tpu2) is turned on by the precharging voltage (Vpc), which is the high voltage of the Q node (Q) during the first period, and the nth clock (which is high voltage) during the second period. A shift register that outputs a carry signal (CRY(N)) through CLK(N)) through the carry terminal (CR). According to claim 1,
The pull-up unit further includes a bootstrap capacitor (CB) connected between the Q node (Q) and the output terminal (OUT),
The Q node (Q) is charged with the precharging voltage (Vpc) during the precharging section (PC), and the precharging voltage (Vpc) is charged by coupling the bootstrap capacitor (CB) during the bootstrap section (BS). ), a shift register that is boosted to a voltage higher than that. According to paragraph 1,
Controlled by the reset terminal,
A shift register further comprising a reset unit that resets the output terminal (OUT) that outputs the Q node (Q) and scan output (Gout (N)) According to paragraph 1,
a first inverter transistor (Ti1) whose gate electrode and drain electrode are connected to the clock terminal (CK) in a diode structure and whose source electrode is connected to the control node (CN);
a second inverter transistor (Ti2) having a gate electrode connected to the control node (CN), a drain electrode connected to the clock terminal (CK), and a source electrode connected to the inverter output node (VN);
a third inverter transistor (Ti3) having a gate electrode connected to the carry terminal (CR), a drain electrode connected to the control node (CN), and a source electrode connected to a supply terminal of a low potential voltage (VSS); and
A fourth inverter transistor (Ti4) having a gate electrode connected to the carry terminal (CR), a drain electrode connected to the inverter output node (VN), and a source electrode connected to the supply terminal of the low potential voltage (VSS). A shift register further comprising an inverter having. According to clause 16,
During the second period (t2) during which the n-th clock (CLK(N)) is output at a high voltage, the output (Vinv ( N)) is a shift register that outputs low potential voltage (VSS). According to clause 16,
A shift register further comprising a pull-down unit that discharges the carry terminal (CR) and the output terminal (OUT) in response to control of the inverter output node (VN) to which the output (Vinv(N)) of the inverter is supplied. According to clause 16,
A shift register further comprising a noise removal unit that discharges the Q node (Q) to the low potential voltage (VSS) in response to control of the output (Vinv(N)) of the inverter. According to clause 16,
Stabilization comprising first to third stabilization transistors (Tst1 to Tst3) that reset the control node (CN), the inverter output node (VN), and the output terminal (OUT) in response to a stabilization signal (Vstable), respectively. A shift register containing more parts. A display unit with a plurality of pixels defined on a substrate;
a non-display portion disposed on at least one side of the display portion; and
It is located on the non-display portion and includes a GIP (Gate In Panel) circuit corresponding to the plurality of pixels,
The GIP circuit part,
First to third set transistors (Ts1 to Ts3) that control the Q node (Q) with the precharging voltage (Vpc) and a precharging set transistor (Tsp) that applies the precharging voltage (Vpc) to the Q node (Q) A set unit provided with; and
It is controlled by the Q node (Q) and outputs the nth clock (CLK(N)) supplied to the clock terminal (CK) as a scan output (Gout(N)) through the output terminal (OUT). A pull-up unit including a pull-up transistor (Tpu1) and a second pull-up transistor (Tpu2) that outputs the n-th clock (CLK(N)) as a carry signal (CRY(N)) through the carry terminal (CR). And
The precharging set transistor (Tsp) includes three transistors sharing one gate electrode connected to at least one of the first to third set transistors (Ts1 to Ts3). According to clause 21,
The set unit receives the N-2nd front-end carry signal (CRY(N-2)), which is the gate high voltage (VGH), in the precharging section (PC) and converts the Q node (Q) to the precharging voltage (Vpc). Charging display device. According to clause 22,
The gate electrode and drain electrode of the first set transistor (Ts1) form a diode structure and receive the gate high voltage (VGH) for the N-2th front-end carry signal (CRY(N-2)), and the first set transistor (Ts1) has a diode structure. A display device in which the source electrode of the transistor (Ts1) is connected to the precharging set transistor (Tsp). According to clause 23,
The gate electrode of the precharging set transistor (Tsp) is connected to the first set transistor (Ts1) and the second set transistor (Ts2), and the drain electrode of the precharging set transistor (Tsp) is connected to the N-2th set transistor (Tsp). A display device that receives a front-end carry signal (CRY(N-2)), and the source electrode of the precharging set transistor (Tsp) is connected to the Q node (Q). According to clause 22,
The gate electrode and source electrode of the second set transistor (Ts2) are connected to the source electrode of the first set transistor (Ts1) and the gate electrode of the precharging set transistor (Tsp), and the second set transistor (Ts2) The drain electrode of a display device receives the N-2th front-end carry signal (CRY(N-2)). According to clause 22,
The gate electrode of the third set transistor (Ts3) receives the N+2th front carry signal (CRY(N-2)), and the drain electrode of the third set transistor (Ts3) receives the pre-charging set transistor (Tsp). ), and the source electrode of the third set transistor (Ts3) is connected to a low potential voltage (Vss).

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