KR20120060298A

KR20120060298A - Gate driving circuit and display device having the same

Info

Publication number: KR20120060298A
Application number: KR1020100121728A
Authority: KR
Inventors: 이재훈
Original assignee: 삼성전자주식회사
Priority date: 2010-12-02
Filing date: 2010-12-02
Publication date: 2012-06-12

Abstract

PURPOSE: A gate driving circuit and a display device including the same are provided to omit transistors for eliminating noise of a pull-up part, thereby reducing integrated area of the gate driving circuit. CONSTITUTION: A plurality of stages is dependently connected. A pull-up part(230) outputs high voltage of a clock signal as high voltage of an n-th gate signal in response to high voltage of a first node. A pull-down part(260) reduces the high voltage of the n-th gate signal into first low voltage. A discharge part(250) discharges the high voltage of the first node as second low voltage. A carry part(240) outputs the high voltage of the clock signal as an n-th carry signal. A first maintaining part(280) maintains the carry signal with the second low voltage.

Description

GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME}

The present invention relates to a gate driving circuit and a display device including the same, and more particularly, to a gate driving circuit having a reduced integrated area of a circuit and a display device including the same.

In general, the liquid crystal display includes a liquid crystal display panel displaying an image using a light transmittance of the liquid crystal, and a backlight assembly disposed under the liquid crystal display panel to provide light to the liquid crystal display panel.

The liquid crystal display includes a display panel in which a plurality of pixel parts are formed by a plurality of gate lines and data lines crossing the gate lines, a gate driving circuit outputting a gate signal to the gate lines, and the data lines. And a data driving circuit for outputting a data signal. The gate driving circuit and the data driving circuit have a chip shape and are typically mounted on a display panel.

Recently, a method of integrating the gate driving circuit in the form of an amorphous silicon gate (ASG) on a display substrate in order to increase productivity while reducing the overall size has been attracting attention.

However, the ASG circuit may generate noise when the gate driver rises to a high temperature due to driving for a long time. Therefore, a structure including various holders has been proposed to minimize the noise. However, when the holders are added, an integrated area is increased.

Therefore, while maintaining the high temperature margin of the ASG circuit, it is required to reduce the integrated area of the ASG circuit.

Accordingly, the technical problem of the present invention was conceived in this respect, and an object of the present invention is to provide a gate driving circuit which improves driving reliability and reduces the integrated area of the circuit.

Another object of the present invention is to provide a display device including the gate driving circuit.

In the gate driving circuit according to an embodiment for realizing the object of the present invention, a plurality of stages are cascaded to output a plurality of gate signals, and the nth (n is a natural number) stage includes a pull-up unit, a pull-down unit, And a discharge part, a carry part, and a first holding part. The pull-up part outputs the high voltage of the clock signal as the high voltage of the n-th gate signal in response to the high voltage of the first node. The pull-down unit pulls down the high voltage of the n-th gate signal to a first low voltage in response to an n + 1 th carry signal. The discharge unit discharges the high voltage of the first node to a second low voltage at a level lower than the first low voltage in response to a carry signal of at least one of the subsequent stages of the nth stage. The carry unit outputs a high voltage of the clock signal as an nth carry signal in response to a high voltage of the first node. The first holding part maintains the carry signal at the second low voltage in response to the clock signal.

In an embodiment of the present invention, after the high voltage of the n-th gate signal is output, the voltage between the control electrode and the output electrode of the pull-up part may maintain a negative voltage.

In an exemplary embodiment of the present disclosure, the electronic device may further include a second holding part configured to maintain the voltage of the first node discharged to the second low voltage at the second low voltage in response to the clock signal.

In an embodiment of the present disclosure, the discharge unit may be configured in response to the first discharge unit and the n + 2 carry signal to discharge the high voltage of the first node to the first low voltage in response to the n + 1 carry signal. And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage.

In an exemplary embodiment of the present disclosure, the semiconductor device may further include a third holding part which maintains the n-th gate signal at the first low voltage in response to the clock signal.

In an embodiment of the present disclosure, the discharge unit may be configured to respond to the first discharge unit and the n + 2 carry signal which discharge the high voltage of the first node to the second low voltage in response to the n + 1 carry signal. And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage.

In an embodiment of the present disclosure, the discharge unit may include a first discharge unit outputting a high voltage of the first node in response to the n + 1 carry signal, and a high voltage of the first node output from the first discharge unit; And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to an n + 2 carry signal.

In an embodiment of the present disclosure, the discharge unit may discharge the high voltage of the first node to the second low voltage in response to the n + 1 carry signal.

In an embodiment of the present invention, the gate driving circuit may include 11 or more and 15 or less transistors.

In an embodiment of the present disclosure, the apparatus may further include a buffer unit including a control electrode and an input electrode connected to the first input terminal receiving the n−1 th carry signal, and an output electrode connected to the first node.

In an embodiment of the present disclosure, the apparatus may further include a charging unit including one end connected to the first node and the other end connected to an output node at which the n-th gate signal is output.

In one embodiment of the present invention, the switching unit for outputting a signal synchronized with the clock signal for a period other than the output period of the n-th carry signal may further include.

According to another aspect of the present invention, there is provided a display device including a display area in which gate wires and source wires that cross each other are formed to display an image, and a peripheral area surrounding the display area. And a gate driving circuit including a panel, a source driving circuit outputting data signals to the source wiring lines, and a plurality of stages integrated in the peripheral area and outputting gate signals to the gate wiring lines. The nth (n is a natural number) stage includes a pull-up part, a pull-down part, a discharge part, a carry part, and a first holding part. The pull-up part outputs the high voltage of the clock signal as the high voltage of the n-th gate signal in response to the high voltage of the first node. The pull-down unit pulls down the high voltage of the n-th gate signal to a first low voltage in response to an n + 1 th carry signal. The discharge unit discharges the high voltage of the first node to a second low voltage at a level lower than the first low voltage in response to a carry signal of at least one of the subsequent stages of the nth stage. The carry unit outputs a high voltage of the clock signal as an nth carry signal in response to a high voltage of the first node. The first holding part maintains the carry signal at the second low voltage in response to the clock signal.

According to embodiments of the present invention, since the voltage between the control electrode and the output electrode of the pull-up part maintains a negative voltage after the gate signal is output, transistors for controlling noise of the pull-up part may be omitted. Therefore, the integrated area of the gate driving circuit can be reduced, and power consumption can also be reduced.

1 is a plan view of a display device according to a first exemplary embodiment of the present invention.
FIG. 2 is a block diagram of the gate driving circuit shown in FIG. 1.
3 is a circuit diagram of the stage shown in FIG.
4 is a waveform diagram illustrating input and output signals of the stage illustrated in FIG. 3.
FIG. 5 is a circuit diagram of the first dummy stage shown in FIG. 2.
FIG. 6 is a circuit diagram of the second dummy stage shown in FIG. 2.
7 is a simulation result of measuring the output of the gate driving circuit shown in FIG. 2 under a high temperature condition.
FIG. 8 is a simulation result of measuring the output of the gate driving circuit shown in FIG. 2 in a low temperature condition.
FIG. 9 is a simulation result of measuring voltages of a Q node and an output node of the gate driving circuit shown in FIG. 2.
10 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 2 of the present invention.
FIG. 11 is a circuit diagram of the first dummy stage illustrated in FIG. 10.
FIG. 12 is a circuit diagram of the second dummy stage shown in FIG. 10.
13 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 3 of the present invention.
14 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 4 of the present invention.
FIG. 15 is a simulation result of measuring voltages of a Q node and an output node of the gate driving circuit shown in FIG. 14.
16 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 5 of the present invention.
17 is a block diagram of a gate driving circuit according to Embodiment 6 of the present invention.
FIG. 18 is a circuit diagram for the stage shown in FIG. 17.
FIG. 19 is a simulation result of measuring voltages of a Q node and an output node of the gate driving circuit shown in FIG. 18.
20 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 7 of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example 1

1 is a plan view of a display device according to a first exemplary embodiment of the present invention.

Referring to FIG. 1, the display device includes a display panel 100, a gate driving circuit 200, a source driving circuit 400, and a printed circuit board 500.

The display panel 100 includes a display area DA and a peripheral area PA surrounding the display area DA. The display area DA includes gate lines, source lines, and a plurality of pixel units that cross each other. Each pixel portion P includes a switching element TR electrically connected to a gate line GL and a source line DL, a liquid crystal capacitor CLC electrically connected to the switching element TR, and the liquid crystal capacitor CLC. And a storage capacitor (CST) connected in parallel.

The gate driving circuit 200 includes a shift register for sequentially outputting high level gate signals to the gate lines. The shift register includes a plurality of stages SRCn-1, SRCn, SRCn + 1 (n is a natural number). The gate driving circuit 200 is integrated in the peripheral area PA corresponding to one end of the gate lines. In the present exemplary embodiment, the gate driving circuit 200 is integrated to correspond to one end of the gate lines, but the gate driving circuit 200 may be integrated to correspond to both ends of the gate lines.

The source driving circuit 400 includes a source driving chip 410 for outputting data signals to the source wirings, and the source driving chip 410 is mounted to the printed circuit board 500 and the display panel 100. It includes a flexible circuit board 430 for electrically connecting the. In the present exemplary embodiment, the source driving chip 410 is described as being mounted on the flexible circuit board 430. However, the source driving chip 410 may be directly mounted on the display panel 100. The driving chip 410 may be directly integrated in the peripheral area PA of the display panel 100.

FIG. 2 is a block diagram of the gate driving circuit shown in FIG. 1.

Referring to FIG. 2, the gate driving circuit 200 may include first to mth stages SRC1 to SRCm, a first dummy stage SRCd1, and a second dummy stage SRCd2 connected to each other. Contains registers

The first to m th stages SRC1 to SRCm are connected to m gate lines, respectively, and sequentially output m gate signals to the gate lines. The first dummy stage SRCd1 controls the driving of the m-th and m-th stages SRCm-1 and SRCm, and the second dummy stage SRCd2 controls the m-th stage SRCm and the The driving of the first dummy stage SRCd1 is controlled. The first and second dummy stages SRCd1 and SRCd2 are not connected to the gate lines.

Each stage includes a first clock terminal CT1, a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a first voltage terminal VT1, and a second voltage terminal VT2. ), A first output terminal OT1 and a second output terminal OT2.

The first clock terminal CT1 receives a clock signal CK or an inverted clock signal CKB in which the phase of the clock signal CK is inverted. For example, the first clock terminal CT1 of the odd-numbered stages SRC1, SRC3,..., SRCd1 receives the clock signal CK and the even-numbered stages SRC2, SRC4 ... The first clock terminal CT1 of SRCd2 receives the inverted clock signal CKB. The clock signal CK and the inverted clock signal CKB include a high voltage VDD and a first low voltage VSS1.

The first input terminal IN1 receives a vertical start signal STV or an n-1th carry signal CRn-1. For example, the first input terminal IN1 of the first stage SRC1 receives the vertical start signal STV, and the first to second dummy stages SRC2 to SRCd2. The input terminal IN1 receives the n-th carry signal CRn-1, respectively.

The second input terminal IN2 receives the n + 1 th carry signal CRn + 1 or the vertical start signal STV. The second input terminal IN2 of the first to first dummy stages SRC1 to SRCd1 receives the n + 1 carry signal CRn + 1, respectively, and the second dummy stage SRCd2. The second input terminal IN2 receives the vertical start signal STV. The vertical start signal STV received at the second input terminal IN2 of the second dummy stage SRCd2 may be a vertical start signal corresponding to the next frame.

The third input terminal IN3 receives the n + 2th carry signal CRn + 2 or the vertical start signal STV. The third input terminal IN3 of the first to mth stages SRC1 to SRCm receives the n + 2th carry signal CRn + 2, respectively, and of the first dummy stage SRCd1. The third input terminal IN3 receives the vertical start signal STV.

The first voltage terminal VT1 receives the first low voltage VSS1. The first low voltage VSS1 has a first low level, and the first low level corresponds to a discharge level of the gate signal. For example, the first low level is about −6 volts.

The second voltage terminal VT2 receives a second low voltage VSS2 having a second low level lower than the first low level VSS1. The second low level corresponds to the discharge level of the first node Q (hereinafter, Q node) included in the stage. For example, the second low level is about −10 volts.

The first output terminal OT1 is electrically connected to the corresponding gate line to output the gate signal. The first output terminals OT1 of the first to m th stages SRC1 to SRCm respectively output first to m th gate signals. The first output terminals OT1 of the first and second dummy stages SRCd1 and SRCd2 do not output a gate signal.

The second output terminal OT2 outputs the carry signal. The second output terminal OT2 is electrically connected to the first input terminal IN1 of the (n + 1) th stage SRCn + 1. In addition, the second output terminal OT2 includes the second input terminal IN2 of the (n-1) th stage SRCn-1 and the third input terminal of the (n-2) th stage SRCn-2 ( Electrically connected to IN3).

3 is a circuit diagram of the stage shown in FIG. 4 is a waveform diagram illustrating input and output signals of the stage illustrated in FIG. 3.

3 and 4, the n th stage SRCn includes a buffer unit 210, a charging unit 220, a pull-up unit 230, a carry unit 240, a discharge unit 250, and a pull-down unit 260. And a switching unit 270, a first holding unit 280, and a second holding unit 290.

The buffer unit 210 transmits the n-1th carry signal CRn-1 to the pullup unit 230. The buffer unit 210 may include a fourth transistor TFT4. The fourth transistor TFT4 includes a control electrode and an input electrode connected to the first input terminal IN1, and an output electrode connected to the Q node Q.

The charging unit 220 is charged in response to the n-1th carry signal CRn-1 provided by the buffer unit 210. One end of the charging unit 220 is connected to the Q node Q, and the other end is connected to the output node O of the gate signal. When the high voltage VDD of the n-th carry signal CRn-1 is received by the buffer unit 210, the charging unit 220 may include a first voltage V1 corresponding to the high voltage VDD. To charge.

The pull-up unit 230 outputs the gate signal. The pull-up unit 230 may include a first transistor TFT1. The first transistor TFT1 includes a control electrode connected to the Q node Q, an input electrode connected to the first clock terminal CT1, and an output electrode connected to the output node O. The output node O is connected to the first output terminal OT1.

The high voltage of the clock signal CK is applied to the first clock terminal CT1 while the first voltage V1 charged by the charging unit 220 is applied to the control electrode of the pull-up unit 230. When the VDD) is received, the pull-up unit 230 bootstrap. In this case, the Q node Q connected to the control electrode of the pull-up unit 230 is boosted from the first voltage V1 to the boosting voltage VBT. That is, the Q node Q has the first voltage V1 in the n-1 th section Tn-1 and the boosting voltage VBT in the n th section Tn.

During the nth period Tn where the boosting voltage VBT is applied to the control electrode of the pullup unit 230, the pullup unit 230 applies the nth high voltage VDD of the clock signal CK. The high voltage VDD of the gate signal Gn is output. The nth gate signal Gn is output through the first output terminal OT1 connected to the output node O.

The pull-down unit 260 pulls down the n-th gate signal Gn. The pull-down unit 260 may include a second transistor TFT2. The second transistor TFT2 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the output node O, and an output electrode connected to the first voltage terminal VT1. When the n + 1 gate signal Gn + 1 is received at the second input terminal IN2, the pull-down unit 260 applies the voltage of the output node O to the first voltage terminal VT1. It pulls down to the first low voltage VSS1.

The carry unit 240 outputs the carry signal. The carry part 240 may include a fifth transistor TFT5. The fifth transistor TFT5 includes a control electrode connected to the Q node Q, an input electrode connected to the first clock terminal CT1, and an output electrode connected to the R node R. The R node R is connected to the second output terminal OT2.

The carry part 240 may further include a capacitor C connecting the control electrode and the output electrode. When the high voltage is applied to the Q node Q, the carry unit 240 receives the high voltage VDD of the clock signal CK received at the first clock terminal CT1 to the nth carry signal CRn. Will output The n-th carry signal CRn is output through the second output terminal OT2 connected to the R node R.

The first holding part 280 maintains the voltage of the R node R. The first holding part 280 may include an eleventh transistor TFT11. The eleventh transistor TFT11 includes a control electrode connected to the node N, an input electrode connected to the R node R, and an output electrode connected to the second voltage terminal VT2. The first holding part 280 maintains the voltage of the R node R as the second low voltage VSS2 in response to the signal of the N node N for the remaining period of the frame.

The switching unit 270 is in phase with the clock signal CK received at the first clock terminal CT1 at the N node N during a period other than an output period of the n-th carry signal CRn. Apply a signal. The switching unit 270 may include a twelfth transistor TFT12, a seventh transistor TFT7, a thirteenth transistor TFT13, and an eighth transistor TFT8.

The twelfth transistor TFT12 includes a control electrode and an input electrode connected to the first clock terminal CT1, an input electrode of the thirteenth transistor TFT13, and an output electrode connected to the seventh transistor TFT7. The seventh transistor TFT7 includes a control electrode connected to the thirteenth transistor TFT13, an input electrode connected to the first clock terminal CT1, and an output electrode connected to an input electrode of the eighth transistor TFT8. . The output electrode of the seventh transistor TFT7 is connected to the N node N.

The thirteenth transistor TFT13 includes a control electrode connected to the R node R, an input electrode connected to the twelfth transistor TFT12, and an output electrode connected to the first voltage terminal VT1. The eighth transistor TFT8 includes a control electrode connected to the R node R, an input electrode connected to the N node N, and an output electrode connected to the first voltage terminal VT1.

The switching unit 270 receives the clock signal CK received at the first clock terminal CT1 during the nth period Tn of the frame where the high voltage is applied to the R node R. Discharges to the first low voltage VSS1 applied to the voltage terminal VT1. That is, the eighth and thirteenth transistors TFT8 and TFT13 are turned on in response to the high voltage of the R node R, and thus the clock signal CK is turned into the first low voltage VSS1. Discharged.

The discharge unit 250 discharges the high voltage of the Q node Q to a second low voltage VSS2 at a level lower than the first low voltage VSS1 in response to at least one carry signal of the stage. . In the present embodiment, the discharge unit 250 discharges the high voltage of the Q node Q in response to the n + 1th carry signal Gn + 1 and the n + 2th carry signal Gn + 2. do.

The discharge part 250 includes a first discharge part 251 and a second discharge part 252.

The first discharge part 251 may include a ninth transistor TFT9. The ninth transistor TFT9 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the Q node Q, and an output electrode connected to the first voltage terminal VT1. When the n + 1th carry signal Gn + 1 is applied to the second input terminal IN2, the first discharge unit 251 may apply the voltage of the Q node Q to the first voltage terminal VT1. Is discharged to the first low voltage VSS1 applied to.

The second discharge part 252 may include a sixth transistor TFT6. The sixth transistor TFT6 includes a control electrode connected to the third input terminal IN3, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. When the n + 2th carry signal Gn + 2 is applied to the third input terminal IN3, the second discharge unit 252 applies the voltage of the Q node Q to the second voltage terminal VT2. Is discharged to the second low voltage VSS2 applied to.

Accordingly, the voltage of the Q node Q has the boosting voltage VBT in the n th section Tn of the frame, and discharges to the first low voltage VSS1 in the n + 1 th section Tn + 1. The second low voltage VSS2 is discharged in the n + 2 th section Tn + 2.

The second holding part 290 maintains the voltage of the Q node Q. The second holding part 290 may include a tenth transistor TFT10. The tenth transistor TFT10 includes a control electrode connected to the N node N, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. The second holding unit 290 maintains the voltage of the Q node Q as the second low voltage VSS2 in response to the signal of the N node N for the remaining period of the frame.

The gate-source voltage VGS of the first transistor TFT1 included in the pull-up unit 230 may be defined as a difference between the voltage Qnode_V of the Q node and the voltage of the output node Onode_V (VGS = Qnode_V). -Onode_V). In general, the gate driving circuit may cause noise at a high temperature. For example, at room temperature, the operating temperature of the actual display panel increases to about 35 ° C. to about 40 ° C. rather than room temperature due to the backlight. When the temperature rises, the drain current of the first transistor TFT1 increases (Vth decreases), thereby increasing the leakage current.

The increased leakage current flows into the Q node Q of the next stage through the fifth transistor TFT5 of the carry unit 240, whereby the first stage of the next stage is not a section in which the next stage should be driven. The transistor TFT1 may be boosted to generate high temperature noise.

In the present embodiment, the gate-source voltage VGS may be designed as a negative voltage while the first transistor TFT1 is turned off, thereby reducing leakage current. Thus, for example, the problem of noise caused by an increase in the drain current at a high temperature may be solved. In addition, since the number of transistors is smaller than that of the conventional gate driving circuit, the integrated area of the circuit can be reduced.

FIG. 5 is a circuit diagram of the first dummy stage shown in FIG. 2. FIG. 6 is a circuit diagram of the second dummy stage shown in FIG. 2.

Referring to FIG. 5, the first dummy stage SRCd1 is substantially the same as the nth stage SRCn of FIG. 3 except for the discharge unit 350. Therefore, the same components as those of the n-th stage SRCn of FIG. 3 are assigned the same reference numerals, and repeated descriptions are omitted.

The discharge part 350 lowers the high voltage of the Q node Q lower than the first low voltage VSS1 in response to the n + 1th carry signal CRn + 1 or the vertical start signal STV. The discharge is performed at the second low voltage VSS2 of the level. The discharge part 350 includes a first discharge part 351 and a second discharge part 352.

The first discharge part 351 may include a ninth transistor TFT9. The ninth transistor TFT9 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. The first discharge unit 351 receives the voltage of the Q node Q when the n + 1 carry signal Gn + 1 is received at the second input terminal IN2, and transmits the voltage of the Q node Q to the second voltage terminal VT2. The second low voltage VSS2 is applied to the discharge.

The second discharge part 352 may include a sixth transistor TFT6. The sixth transistor TFT6 includes a control electrode connected to the third input terminal IN3, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. The second discharge part 352 applies the voltage of the Q node Q to the second voltage terminal VT2 when the vertical start signal STV is received at the third input terminal IN3. 2 is discharged to the low voltage (VSS2).

In the first dummy stage SRCd1, the vertical start signal STV is input instead of the n + 2 carry signal Gn + 2 input to the third input terminal IN3 at the n stage SRCn. do. The first dummy stage SRCd1 does not output a gate signal.

Referring to FIG. 6, the second dummy stage SRCd2 is substantially the same as the nth stage SRCn of FIG. 3 except for the discharge unit 360 and the reset unit 370. Therefore, the same components as those of the n-th stage SRCn of FIG. 3 are assigned the same reference numerals, and repeated descriptions are omitted.

The discharge unit 360 discharges the high voltage of the Q node Q to a second low voltage VSS2 at a level lower than the first low voltage VSS1 in response to the vertical start signal STV.

The discharge part 360 may include a ninth transistor TFT9. The ninth transistor TFT9 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. The discharge part 360 applies the voltage of the Q node Q to the second voltage terminal VT2 when the vertical start signal STV is received at the second input terminal IN2. Discharge at voltage VSS2.

In the second dummy stage SRCd2, the vertical start signal STV is input instead of the n + 1 carry signal Gn + 1 input to the second input terminal IN2 at the n stage SRCn. do. The vertical start signal STV received at the second input terminal IN2 of the second dummy stage SRCd2 may be a vertical start signal corresponding to the next frame. The second dummy stage SRCd2 does not receive the n + 2th carry signal Gn + 2 and does not output a gate signal.

The reset unit 370 resets the R node R and the Q node Q. The reset unit 370 may include a fourteenth transistor TFT14 and a fifteenth transistor TFT15.

The fourteenth transistor TFT14 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the R node R, and an output electrode connected to the second voltage terminal VT2. The fourteenth transistor TFT14 pulls down the voltage of the R node R to the second low voltage VSS2 in response to the vertical start signal STV.

The fifteenth transistor TFT15 includes a control electrode connected to the R node R, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. The fifteenth transistor TFT15 pulls down the voltage of the Q node Q to the second low voltage VSS2 in response to the voltage of the R node R.

7 is a simulation result of measuring the output of the gate driving circuit shown in FIG. 2 under a high temperature condition. FIG. 8 is a simulation result of measuring the output of the gate driving circuit shown in FIG. 2 in a low temperature condition.

FIG. 7 shows gate signals output from each stage under conditions of an image of about 80 ° C., and FIG. 8 measures gate signals output from each stage under conditions of about 40 ° C ..

7 and 8, since the output of the gate signals is constant, it can be seen that the gate driving circuit 200 according to the present embodiment operates normally even though it has fewer transistors than the conventional gate driving circuit.

FIG. 9 is a simulation result of measuring voltages of a Q node and an output node of the gate driving circuit shown in FIG. 2.

9, waveforms of signals measured at the Q node and the output node O when the gate-source voltage VGS of the first transistor TFT1 is designed to be about −4 V are illustrated. That is, in order to design the gate-source voltage VGS to about −4 V, the low voltage of the Q node is maintained at about −10 V and the low voltage of the output node O is maintained at about −6 V. shall. Thus, the gate-source voltage VGS is -10-(-6) =-4V.

According to the present embodiment, it can be seen that the signal of the output node O outputs a high voltage in the 1H section and is maintained at the first low voltage (VSS1 = -6V) in the remaining sections. The signal of the Q node Q outputs the boosted voltage in the 1H section in which the signal of the output node O outputs a high voltage, and then, in the next section, the signal of the Q node Q becomes the first low voltage (VSS1 = -6 V). It can be seen that it is pulled down and maintained at the second low voltage (VSS2 = -10 V) in the remaining period.

After the 1H period, the signal of the Q node Q includes the ripple Rp, and the ripple Rp was about -2 V at maximum. The ripple Rp becomes the gate-source voltage VGS of the first transistor TFT1 while the first transistor TFT1 is turned off.

As a result, the drain current caused by the ripple Rp becomes smaller than when the gate-source voltage VGS of the first transistor TFT1 is designed to be 0V. Therefore, by designing the gate-source voltage VGS of the first transistor TFT1 as a negative voltage, it is possible to improve high temperature noise of the gate driving circuit.

In addition, the falling time (falling time) of the output voltage is about 2.403 s, it can be confirmed that the level is almost the same as the conventional gate driving circuit.

Example 2

10 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 2 of the present invention.

Referring to FIG. 10, the nth stage SRCn according to the present exemplary embodiment is substantially the same as the nth stage SRCn of FIG. 3 except for the third holding part 262. Therefore, the same components as those of the n-th stage SRCn of FIG. 3 are assigned the same reference numerals, and repeated descriptions are omitted.

The third holding part 262 maintains the voltage of the output node O. The third holding part 262 may include a third transistor TFT3. The third transistor TFT3 includes a control electrode connected to the node N, an input electrode connected to the output node O, and an output electrode connected to the first voltage terminal VT1. The third holding part 262 applies the voltage of the output node O to the first voltage terminal VT1 in response to a signal of the N node N for the remaining period of the frame. It is maintained at the voltage VSS1.

In the present embodiment, since the n-th stage SRCn further includes the third holding part 262, the output node pulled down to the first low voltage VSS1 by the pull-down part 260 ( The voltage of O) can be kept more stable.

FIG. 11 is a circuit diagram of the first dummy stage illustrated in FIG. 10. FIG. 12 is a circuit diagram of the second dummy stage shown in FIG. 10.

Referring to FIG. 11, the first dummy stage SRCd1 is substantially the same as the first dummy stage SRCd1 of FIG. 5 except for further including a third holding part 262. 12, the second dummy stage SRCd2 is also substantially the same as the second dummy stage SRCd2 of FIG. 6, except that the second dummy stage SRCd2 further includes a third holding part 262.

Therefore, the same components as those of the nth stage SRCn of FIG. 5 and the second dummy stage SRCd2 of FIG. 6 are denoted by the same reference numerals, and repeated descriptions are omitted.

Example 3

13 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 3 of the present invention.

Referring to FIG. 13, the nth stage SRCn according to the present exemplary embodiment is substantially the same as the nth stage SRCn of FIG. 10 except for the discharge unit 255. Therefore, the same components as those of the nth stage SRCn of FIG. 10 are assigned the same reference numerals, and repeated descriptions thereof will be omitted.

The discharge unit 255 then discharges the high voltage of the Q node Q to a second low voltage VSS2 at a level lower than the first low voltage VSS1 in response to the carry signal of at least one of the stages. . In the present embodiment, the discharge unit 255 discharges the high voltage of the Q node Q in response to the n + 1th carry signal Gn + 1 and the n + 2th carry signal Gn + 2. do.

The discharge part 255 includes a first discharge part 253 and a second discharge part 252.

The first discharge part 253 may include a ninth transistor TFT9. The ninth transistor TFT9 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. When the n + 1th carry signal Gn + 1 is applied to the second input terminal IN2, the first discharge unit 253 may apply the voltage of the Q node Q to the second voltage terminal VT2. Is discharged to the second low voltage VSS2 applied to.

In the present embodiment, the voltage of the Q node Q has the boosting voltage VBT in the n th section Tn of the frame, and the second low voltage VSS2 in the n + 1 th section Tn + 1. Discharge, the discharge time can be reduced.

Example 4

14 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 4 of the present invention. FIG. 15 is a simulation result of measuring voltages of a Q node and an output node of the gate driving circuit shown in FIG. 14.

Referring to FIG. 14, the nth stage SRCn according to the present exemplary embodiment is substantially the same as the nth stage SRCn of FIG. 3 except for the discharge unit 450. Therefore, the same components as those of the n-th stage SRCn of FIG. 3 are assigned the same reference numerals, and repeated descriptions are omitted.

The discharge part 450 includes a first discharge part 451, an auxiliary discharge part 453, and a second discharge part 452.

The first discharge part 451 may include a ninth transistor TFT9. The ninth transistor TFT9 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the Q node Q, and an output electrode connected to the auxiliary discharge unit 453. When the n + 1th carry signal Gn + 1 is applied to the second input terminal IN2, the first discharge unit 451 applies the voltage of the Q node Q to the auxiliary discharge unit 453. Will output

The auxiliary discharge unit 453 may include a sixteenth transistor TFT16. The sixteenth transistor TFT16 includes a control electrode and an input electrode connected to the output electrode of the first discharge unit 451, and an output electrode connected to the second voltage terminal VT2. The auxiliary discharge unit 453 discharges the voltage of the Q node Q applied from the auxiliary discharge unit 453 to the second low voltage VSS2.

The second discharge part 452 may include a sixth transistor TFT6. The sixth transistor TFT6 includes a control electrode connected to the third input terminal IN3, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2. When the n + 2th carry signal Gn + 2 is applied to the third input terminal IN3, the second discharge unit 452 receives the voltage of the Q node Q from the second voltage terminal VT2. Is discharged to the second low voltage VSS2 applied to.

In the present embodiment, since the n-th stage SRCn further includes the auxiliary discharge unit 453, the fall time of the output voltage may be shortened by delaying the discharge of the Q node Q. FIG.

FIG. 15 measures gate signals output from each stage when the gate driving circuit of FIG. 14 is operated for 5000 hours under the condition of an image of about 80 ° C. FIG. Referring to FIG. 15, it can be seen that the fall time of the output voltage is faster than the fall time of the output voltage of FIG. 3. Therefore, even when the gate driving circuit is driven for a long time, driving reliability can be ensured.

Example 5

16 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 5 of the present invention.

Referring to FIG. 16, the nth stage SRCn according to the present exemplary embodiment is substantially the same as the nth stage SRCn of FIG. 14 except for the third holding part 262. Therefore, the same components as those of the nth stage SRCn of FIG. 14 are assigned the same reference numerals, and repeated descriptions are omitted.

Example 6

17 is a block diagram of a gate driving circuit according to Embodiment 6 of the present invention.

Referring to FIG. 17, the gate driving circuit 300 includes a shift register including first to mth stages SRC1 to SRCm and a first dummy stage SRCd1 that are connected to each other dependently.

The first to m th stages SRC1 to SRCm are connected to m gate lines, respectively, and sequentially output m gate signals to the gate lines. The first dummy stage SRCd1 controls the driving of the m th stage SRCm. The first dummy stage SRCd1 is not connected to the gate line.

Each stage includes a first clock terminal CT1, a first input terminal IN1, a second input terminal IN2, a first voltage terminal VT1, a second voltage terminal VT2, and a first output terminal OT1. ) And a second output terminal OT2.

Each stage is substantially the same as the nth stage SRCn of FIG. 2 except that the stage does not include the third input terminal IN3 that receives the n + 2th carry signal CRn + 2. Therefore, the same components as those of the n-th stage SRCn in FIG. 2 are assigned the same reference numerals, and repeated descriptions are omitted.

The first input terminal IN1 receives a vertical start signal STV or an n-1th carry signal CRn-1. For example, the first input terminal IN1 of the first stage SRC1 receives the vertical start signal STV, and the first to second dummy stages SRC2 to SRCd1. The input terminal IN1 receives the n-th carry signal CRn-1, respectively.

The second input terminal IN2 receives the n + 1 th carry signal CRn + 1 or the vertical start signal STV. The second input terminal IN2 of the first to mth dummy stages SRC1 to SRCm receives the n + 1th carry signal CRn + 1, respectively, and the first dummy stage SRCd1. The second input terminal IN2 receives the vertical start signal STV. The vertical start signal STV received at the second input terminal IN2 of the first dummy stage SRCd1 may be a vertical start signal corresponding to the next frame.

The first dummy stage SRCd1 may be substantially the same as the second dummy stage SRCd2 of FIG. 6.

FIG. 18 is a circuit diagram for the stage shown in FIG. 17. FIG. 19 is a simulation result of measuring voltages of a Q node and an output node of the gate driving circuit shown in FIG. 18.

Referring to FIG. 18, the nth stage SRCn according to the present exemplary embodiment is substantially the same as the nth stage SRCn of FIG. 3 except for the discharge unit 550. Therefore, the same components as those of the n-th stage SRCn of FIG. 3 are assigned the same reference numerals, and repeated descriptions are omitted.

The discharge unit 550 discharges the voltage of the Q node Q to the second low voltage VSS2 in response to the n + 1th carry signal Gn + 1. The discharge part 550 may include a ninth transistor TFT9. The ninth transistor TFT9 includes a control electrode connected to the second input terminal IN2, an input electrode connected to the Q node Q, and an output electrode connected to the second voltage terminal VT2.

In the present embodiment, the discharge unit 550 discharges the voltage of the Q node Q by using only the n + 1th carry signal Gn + 1, and thus includes only one transistor. Therefore, the integrated area of the gate driving circuit can be further reduced.

Referring to FIG. 19, it can be seen that the fall time of the output voltage is delayed from the fall time of the output voltage of FIG. 3. However, the delay of the fall time of the output voltage may be compensated by increasing the size of a transistor (not shown) formed at the other end of the peripheral area PA in which the gate driving circuit 200 is formed to discharge the gate signal. In addition, since the size of the transistor formed at the other end of the peripheral area PA is not included in the integrated area of the gate driving circuit, the integrated area of the gate driving circuit can be further reduced in this embodiment.

Example 7

20 is a circuit diagram of a stage of a gate driving circuit according to Embodiment 7 of the present invention.

Referring to FIG. 20, the nth stage SRCn according to the present exemplary embodiment is substantially the same as the nth stage SRCn of FIG. 18 except for the third holding part 262. Therefore, the same components as those of the nth stage SRCn of FIG. 18 are assigned the same reference numerals, and repeated descriptions are omitted.

As described above, since the voltage between the control electrode and the output electrode of the pull-up part has a negative voltage after the gate signal is output, noise can be improved by reducing the leakage current of the pull-up part. In addition, since the transistors for controlling the noise can be omitted, the integrated area and power consumption of the gate driving circuit can be reduced.

Although described above with reference to preferred embodiments of the present invention, those skilled in the art or those skilled in the art without departing from the spirit and scope of the invention described in the claims to be described later It will be understood that various modifications and variations can be made within the scope of the invention.

100: display panel 200, 300: gate driving circuit
400: source driving circuit 500: printed circuit board
SRCn: nth stage 210: buffer portion
220: charging unit 230: pull-up unit
240: carry part
250, 255, 350, 360, 450, 550: discharge part
251, 253, 351, 451: first discharge part 252, 352, 452: second discharge part
280: first holding part 290: second holding part
453: auxiliary discharge unit 370: reset unit
260: pull-down portion 262: third holding portion
270: switching unit

Claims

In a gate driving circuit in which a plurality of stages are cascaded and output a plurality of gate signals, the nth (n is a natural number) stage is
A pull-up unit configured to output the high voltage of the clock signal as the high voltage of the n-th gate signal in response to the high voltage of the first node;
A pull-down unit configured to pull down the high voltage of the n-th gate signal to a first low voltage in response to an n + 1 th carry signal;
A discharge unit configured to discharge the high voltage of the first node to a second low voltage at a level lower than the first low voltage in response to a carry signal of at least one of subsequent stages of the nth stage;
A carry unit configured to output a high voltage of the clock signal as an nth carry signal in response to a high voltage of the first node; And
And a first holding part configured to hold the carry signal at the second low voltage in response to the clock signal.

The gate driving circuit of claim 1, wherein a voltage between the control electrode and the output electrode of the pull-up part maintains a negative voltage after the high voltage of the n-th gate signal is output.

The gate driving circuit of claim 1, further comprising a second holding part configured to hold the voltage of the first node discharged to the second low voltage at the second low voltage in response to the clock signal.

The method of claim 1, wherein the discharge unit,
A first discharge unit configured to discharge the high voltage of the first node to the first low voltage in response to the n + 1 carry signal; And
And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to an n + 2 carry signal.

The gate driving circuit of claim 4, further comprising a third holding part configured to hold the n-th gate signal at the first low voltage in response to the clock signal.

The method of claim 1, wherein the discharge unit,
A first discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to the n + 1 carry signal; And
And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to an n + 2 carry signal.

The gate driving circuit of claim 6, further comprising a third holding part configured to hold the n-th gate signal at the first low voltage in response to the clock signal.

The method of claim 1, wherein the discharge unit,
A first discharge unit configured to output a high voltage of the first node in response to the n + 1th carry signal;
An auxiliary discharge unit configured to discharge the high voltage of the first node output from the first discharge unit to the second low voltage; And
And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to an n + 2 carry signal.

The gate driving circuit of claim 8, further comprising a third holding part configured to hold the n-th gate signal at the first low voltage in response to the clock signal.

The gate driving circuit of claim 1, wherein the discharge unit discharges the high voltage of the first node to the second low voltage in response to the n + 1 carry signal.

The gate driving circuit of claim 10, further comprising a third holding part configured to hold the n-th gate signal at the first low voltage in response to the clock signal.

2. The gate driving circuit according to claim 1, comprising 11 or more and 15 or less transistors.

The gate driving circuit of claim 1, further comprising a buffer unit including a control electrode and an input electrode connected to a first input terminal receiving the n−1 th carry signal, and an output electrode connected to the first node. .

The gate driving circuit of claim 1, further comprising a charging unit including one end connected to the first node and the other end connected to an output node to which the n-th gate signal is output.

The gate driving circuit of claim 1, further comprising a switching unit configured to output a signal synchronized with the clock signal during a section other than an output section of the n-th carry signal.

A display panel including a display area in which gate lines and source lines intersecting each other are formed to display an image, and a peripheral area surrounding the display area;
A source driving circuit which outputs data signals to the source wirings; And
In a display device including a gate driving circuit integrated in the peripheral area and including a plurality of stages for outputting gate signals to the gate lines,
The nth (n is a natural number) stage of the plurality of stages
A pull-up unit configured to output the high voltage of the clock signal as the high voltage of the n-th gate signal in response to the high voltage of the first node;
A pull-down unit configured to pull down the high voltage of the n-th gate signal to a first low voltage in response to an n + 1 th carry signal;
A discharge unit configured to discharge the high voltage of the first node to a second low voltage at a level lower than the first low voltage in response to a carry signal of at least one of the subsequent stages of the nth stage;
A carry unit configured to output a high voltage of the clock signal as an nth carry signal in response to a high voltage of the first node; And
And a first holding part configured to hold the carry signal at the second low voltage in response to the clock signal.

The display device of claim 16, wherein a voltage between the control electrode and the output electrode of the pull-up part maintains a negative voltage after the high voltage of the n-th gate signal is output.

The display device of claim 16, further comprising a second holding part configured to hold the voltage of the first node discharged to the second low voltage at the second low voltage in response to the clock signal.

The display device of claim 16, further comprising a third holding part configured to hold the nth gate signal at the first low voltage in response to the clock signal.

The method of claim 16, wherein the discharge unit,
A first discharge unit configured to discharge the high voltage of the first node to the first low voltage in response to the n + 1 carry signal; And
And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to an n + 2 carry signal.

The method of claim 16, wherein the discharge unit,
A first discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to the n + 1 carry signal; And
And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to an n + 2 carry signal.

The method of claim 16, wherein the discharge unit,
A first discharge unit configured to output a high voltage of the first node in response to the n + 1th carry signal;
An auxiliary discharge unit configured to discharge the high voltage of the first node output from the first discharge unit to the second low voltage; And
And a second discharge unit configured to discharge the high voltage of the first node to the second low voltage in response to an n + 2 carry signal.

The display device of claim 16, wherein the discharge unit discharges the high voltage of the first node to the second low voltage in response to the n + 1 carry signal.