KR20180062185A - Shift register and display device using the same - Google Patents

Abstract

According to an embodiment of the present invention, a shift register is provided with multiple stages which are connected to each other in a dependent manner. Each of the stages includes: a set unit including first to third set transistors (Ts1 to Ts3) for controlling Q nodes (Q) by using a pre-charging voltage (Vpc) and a pre-charging set transistor (Tsp) for applying the pre-charging voltage (Vpc) to the Q nodes (Q); and a pull-up unit including a first pull-up transistor (Tpu1) which is controlled by the Q nodes (Q) and outputs an n^th clock (CLK(N)) being supplied to a clock terminal (CK) through an output terminal (OUT) as a scan output (Gout(N)); and a second pull-up transistor (Tpu2) which outputs the n^th clock (CLK(N)) through a carry terminal (CR) as a carry signal (CRY(N)).

Description

Technical Field [0001] The present invention relates to a shift register and a display device using the shift register.

The present invention relates to a shift register and a display device using the shift register. More particularly, the present invention relates to a shift register including a circuit portion for controlling reduction of an output signal of a precharging transistor (Tpc) and a display using the shift register.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Various electronic devices such as mobile phones, tablets, navigation, notebooks, televisions, monitors and public displays (PDs) are deeply embedded in everyday life And the demand for display devices is also increasing day by day because display devices are basically installed in such electronic devices. A display device includes a liquid crystal display (LCD) device and an organic light emitting diode (OLED) display device.

Such a display device includes a plurality of pixels for displaying an image and a driving circuit for controlling light to be transmitted or emitted in each of the plurality of pixels.

The driving circuit of the display device includes a data driving circuit for supplying a data signal to the data lines of the pixel array, a gate signal (or a scanning signal) synchronized with the data signal to the gate lines (or scan lines) And a timing controller for controlling the gate driver circuit (or scan driving circuit) and the data driving circuit and the gate driving circuit.

Each of the plurality of pixels may include a thin film transistor that supplies a voltage of the data line to the pixel electrode in response to a gate signal supplied through the gate line. The gate signal swings between the gate high voltage (VGH) and the gate low voltage (VGL). That is, the gate signal appears in the form of a pulse.

The gate high voltage VGH is set to a voltage higher than the threshold voltage of the thin film transistor formed on the display panel and the gate low voltage VGL is set to a voltage lower than the threshold voltage of the thin film transistor. The thin film transistors of the pixels are turned on in response to the gate high voltage.

The gate signal consists of a gate high voltage (VGH) and a gate low voltage (VGL). When the gate signal outputs the gate high voltage VGH through the output terminal, the gate line GL of the display panel receives the gate high voltage VGH and emits the pixel. The gate signal of the stage output stage connected to the light emitting pixel outputs the gate low voltage VGL so that the data signal to be transmitted to the next pixel can not be inputted after the pixel is lighted. It is preferable that the ripple signal is not supplied during the time when the output stage of the stage is held at the gate low voltage VGL.

BACKGROUND ART [0002] Recently, as a display device has become thinner, a technique of embedding a gate drive circuit together with a pixel array in a display panel has been developed. The gate driving circuit built in the display panel is known as a " GIP (Gate-In-Panel) driving circuit ". Here, the GIP driving circuit includes a shift register for generating a gate signal. The shift register includes a plurality of stages connected in a dependent manner. The plurality of stages generates an output in response to the start signal and shifts the output to the next stage according to the shift signal The GIP driving circuit sequentially drives a plurality of stages in a shift register to generate a gate signal.

On the other hand, the GIP driving circuit is composed of a shift register, and the shift register includes a plurality of transistors. While the power source and the clock signal are applied and the shift register is operated, the plurality of transistors included in the shift register are exposed to various stresses. Stress occurs not only in the turn-on period of the transistor but also in the turn-off period. Particularly, during a period during which the transistor is turned off, a junction stress may occur due to a voltage difference between the drain electrode and the source electrode. Transistors exposed to a junction stress for a certain period of time may undergo degradation, and deteriorated transistors and shift registers may output unintended signals.

The above-mentioned shift register includes a transistor (hereinafter referred to as a precharging transistor Tpc) that receives a set signal and precharges the Q node Q. When the precharging time of the precharging transistor Tpc becomes long, the pull-up transistor Tpu among the transistors constituting the plurality of stages generates stress, Lt; / RTI > can be influenced by the output signal.

Also, the pre-charging transistor Tpc has a diode structure in which a gate electrode and a drain electrode are connected to each other. In this structure, as the threshold voltage Vth of the precharging transistor Tpc increases, the precharging voltage of the Q node Q decreases, which occurs in the Q node Q during the bootstrap period Thereby reducing the bootstrap voltage Vbc.

As a result, the turn-on rising and turning off times of the pull-up transistor Tpu are changed, so that the output signal of the GIP driving circuit can be reduced. This may lead to a problem of weakening the reliability level of the display device.

Therefore, it is necessary to improve the output signal reduction of the precharging transistor Tpc in the GIP driving circuit, and various researches and developments thereof are under way.

The inventors of the present invention have proposed a shift register including a circuit for improving the output signal reduction of the precharging transistor Tpc of the GIP driving circuit and for increasing the precharged voltage Vpc of the Q node Q, And invented a new structure of a display device including the same.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit for controlling precharging of a Q node (Q) capable of improving the output signal reduction of a GIP driving circuit by increasing a precharging voltage (Vpc) And a display device including the shift register.

Another object of the present invention is to provide a shift register including a circuit section capable of improving the stress of a pull-up transistor Tpu among the transistors constituting a plurality of stages, And a display device including the display device.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

There is provided a shift register having a plurality of stages which are connected to each other in dependence on one another according to an embodiment of the present invention. The gate drive circuit includes a plurality of stages. Each stage includes first to third set transistors Ts1 to Ts3 for controlling the Q node Q to a precharging voltage Vpc and a precharged set transistor Q1 to Q3 for applying a precharging voltage Vpc to the Q node Q. [ (N), which is controlled by the Q node Q and supplied to the clock terminal CK, is connected to the scan output Gout (N) via the output terminal OUT, And a second pull-up transistor Tpu2 for outputting the n-th clock CLK (N) through a carry terminal CRY (N) via a carry terminal CR And a pull-up unit including the pull-up unit.

A display device according to an embodiment of the present invention is provided. The display device includes a substrate, a display portion on which a plurality of pixels are defined, a non-display portion disposed on at least one side of the display portion, and a GIP (Gate In Panel) portion positioned on the non-display portion and corresponding to the plurality of pixels. The GIP circuit section includes first to third set transistors Ts1 to Ts3 for controlling the Q node Q to a precharging voltage Vpc and a precharging set transistor Q1 to Ts3 for applying a precharging voltage Vpc to the Q node Q. [ (N), which is controlled by the Q node Q and supplied to the clock terminal CK, is connected to the scan output Gout (N) via the output terminal OUT, And a second pull-up transistor Tpu2 for outputting the n-th clock CLK (N) through a carry terminal CRY (N) via a carry terminal CR And a pull-up unit including the pull-up unit.

The details of other embodiments are included in the detailed description and drawings.

The present invention is characterized in that the first to third set transistors Ts1 to Ts3 for controlling the Q node Q to the precharging voltage Vpc and the precharging set transistor Q1 to Q3 for applying the precharging voltage Vpc to the Q node Q, The effect of charging the Q node Q with the precharging voltage Vpc as low as the threshold voltage Vth of the precharging set transistor Tsp to the gate high voltage VGH is obtained have.

In the present invention, the precharging set transistor Tsp is composed of three transistors sharing one gate electrode connected to the set terminal S, which has an effect of minimizing High Junction Stress (HJS).

The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by those skilled in the art from the following description.

The scope of the claims is not limited by the matters described in the contents of the invention, as the contents of the invention described in the problems, the solutions to the problems and the effects to be solved do not specify essential features of the claims.

FIG. 1 is a block diagram schematically showing a configuration of a display device incorporating a shift register according to an embodiment of the present invention. Referring to FIG.
2 is a block diagram showing the structure of a shift register according to an embodiment of the present invention.
3 is a circuit diagram showing a configuration of an Nth stage in a shift register according to an embodiment of the present invention.
4 is a driving waveform diagram of the N-th stage shown in Fig.
5 is a graph showing a precharging interval of the N-th stage of 2H according to an embodiment of the present invention.
6 is a graph showing a voltage applied to a Q node Q of an Nth stage according to an embodiment of the present invention.

Brief Description of the Drawings The advantages and features of the present disclosure, and how to accomplish them, will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise. In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a display device according to an embodiment of the present invention.

1, a display device includes a display panel 110, a timing controller 150, a data driver 120, and a scan driver 130 and 140.

The display panel 110 includes pixels PXL connected to the data lines DL and the scan lines GL by the data lines DL and the scan lines GL intersecting with each other . The display panel 110 includes a display region 110A defined by the pixels PXL and a non-display region 110B where various signal lines, pads, and the like are formed. The display panel 110 may be implemented as a display panel used in various display devices such as a liquid crystal display (LCD), an organic light emitting display (OLED), and an electrophoretic display (EPD).

One pixel PXL includes a transistor connected to the scan line GL or the data line DL and a pixel circuit operating in response to the scan signal and the data signal supplied by the transistor. The pixel PXL is implemented by a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of a pixel circuit.

For example, when the display panel 110 is composed of a liquid crystal display panel, the display panel 110 may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an In Plane Switching Mode or an ECB (Electrically Controlled Birefringence) mode. When the display panel 110 is an organic light emitting display panel, the display panel 110 may be a top emission type, a bottom emission type, or a dual emission type. .

The timing controller 150 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through a receiving circuit such as an LVDS or TMDS interface connected to an image board. The timing controller 150 generates timing control signals for controlling the operation timings of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs are supplied with digital video data RGB and a source timing control signal DDC from the timing controller 150. The source driver ICs convert the digital video data RGB to a gamma voltage in response to the source timing control signal DDC to generate a data voltage and apply the data voltage to the data lines DL of the display panel 110 Supply. The source drive ICs are connected to the data lines DL of the display panel 110 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The source drive ICs may be formed on the display panel 110 or may be formed on a separate PCB substrate and connected to the display panel 110. [

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 shifts the level of the clock signals CLK input from the timing controller 150 to the TTL (Transistor-Transistor-Logic) level of 0V to 3.3V and supplies the shifted level to the shift register 140 . The shift register 140 may be formed in the form of a thin film transistor (hereinafter referred to as TFT) in a non-display region 110B of the display panel 110 by a gate-in-panel (GIP) method. The shift register 140 is composed of stages for shifting and outputting a scan signal corresponding to the clock signals CLK and the start signal Vst. The stages included in the shift register 140 sequentially output scan signals through a plurality of output stages.

The scan signal consists of a gate high voltage (VGH) and a gate low voltage (VGL). When the scan signal outputs the gate high voltage VGH through the output terminal, the scan line GL of the display panel 110 receives the gate high voltage VGH and emits the pixel. The scan signal of the stage output stage connected to the light emitting pixel outputs the gate low voltage VGL so that the data signal to be transmitted to the next pixel can not be inputted after the pixel is emitted. While the pixel PXL is emitting light, the output signal of the stage output stage is preferably maintained at the gate high voltage VGH for a sufficient time.

2 is a block diagram briefly explaining a shift register according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration of an Nth (N is a natural number) stage STn in a shift register according to an embodiment of the present invention shown in FIG. 4 is a driving waveform diagram of the stage shown in Fig. The shift register 140 includes a plurality of transistors.

The shift registers have a plurality of stages ST1 to STn (n is the number of stages) that are connected to each other in a dependent manner and generate a separate scan output Gout. For convenience, only the first to fifth stages ST1 to ST5 Respectively. Hereinafter, "front stage" means any one of at least one stage located at a previous (upper) position of the stage, and "rear stage" means at least one stage Which means either.

2, each of the stages ST1 to STn includes a set terminal S, a reset terminal R, a clock terminal CK, a power terminal PT, an output terminal OUT, and a carry terminal CR. And the like.

Referring to FIG. 4, the N-th stage STn is supplied with one of the clock signals CLK (N) of i-phase (i is a positive integer) phase having a different phase. For example, any one of the eight-phase clock signals CLK1 to CLK8, which are sequentially delayed in phase and whose high logic sections partially overlap each other, is supplied to the N-th stage STn .

The 8-phase clock signals CLK1 to CLK8 are sequentially phase delayed by 1H periods in the high logic period, and each of the 3H, 2H, and 1H periods of the high logic period is synchronized with the high logic period of each of the adjacent clocks Overlapping can be performed. Since the 8-phase clock signals CLK1 to CLK8 are sequentially output to the scan output Gout and each scan output Gout has a high period of the 4H period, a sufficient charge time can be provided in the high-speed drive. A clock CLK (N + 4) having an Nth phase and an N + 4th phase in the 8-phase clock signals CLK1 through CLK8, for example, a first clock CLK, And the fifth clock (CLK) have a phase-inverted form with respect to each other

Referring to FIG. 4, the clock signal CLK (N) having the Nth phase output from the scan output (Gout (N)) and the carry signal (CRY (N) Gate-on voltage) interval and the low logic (gate-off voltage) interval of the 4H period are alternately repeated.

(N + 2) th previous carry signal CRY (N-2) and N + 2th previous carry signal CRY (N + 2) used as a set signal, 2) and the high period are overlapped with each other for 2H periods, and the high section is not overlapped with the (N + 4) th rear stage carry signal CRY (N + 4) used as the reset signal.

The Nth stage STn shown in FIG. 3 includes a pull-up period including the first and second periods t1 and t2 shown in FIG. 4, a third period t3 and thereafter Down period during which the < / RTI >

Referring to FIG. 4, the first period t1 is a period during which the N-2.sup.th forward carry signal CRY (N-2) is maintained at a high voltage for the 2H period. The first period t1 is a period (PC) in which the Q node Q is precharged.

The second period t2 is a period during which the carry signal CRY (N) is maintained at the high voltage for the 4H period and is the period (BS) during which the Q node Q is bootstrapped.

The third period t3 is a period during which the (N + 4) th rear carry signal CRY (N + 4) is maintained at a high voltage for the 2H period.

The terminals of each stage will be described in detail with reference to Fig.

The set terminal S may be supplied with the set signal as the start signal Vst supplied through the start signal line or the preceding carry signal CRY (N-2) supplied from the front stage STn-2.

Also, in response to the set signal, the Q node Qn of each stage ST may be precharged sequentially and pulled up sequentially.

The reset terminal R may be supplied with a reset signal as the next carry signal CRY (N + 4) supplied from the carry terminal CR of the subsequent stage.

The clock terminal CK is supplied with one or more clock signals CLK (N) of clock signals having different phases. Then, the clock signal CLK (N) having the Nth phase can be output to the scan output Gout (N) through the output terminal OUT.

The power supply terminal PT can be supplied with the low potential voltage VSS and the gate low voltage VGL used as the low voltage of the carry signal CRY (N) or the output voltage Gout (N).

Therefore, each stage ST is set by the start signal Vst or the preceding carry signal CRY (N-2) supplied from any one of the preceding stages and supplies the clock CLK (N) to the scan output Gout (N) or the carry signal CRY (N).

Each stage ST is reset by a subsequent carry signal CRY (N + 4) supplied from one of the succeeding stage stages to turn the gate low voltage VGL to the scan output Gout (N) And outputs the low potential voltage VSS as the carry signal CRY (N).

In addition, the Q-node Q of each stage ST may be pulled-down to the low potential voltage VSS supplied through the power supply terminal PT in response to the reset signal.

The operation of the N-th stage STn will be described in detail with reference to FIG. The N-th stage STn has a SLC (Simple Logic Circuit) structure

The SLC structure of the N-th stage STn shown in FIG. 3 includes a set unit 210, a pull-up unit 220, a pull-down unit 230, a reset unit 240, a noise removing unit 250, And an inverter 270. As shown in FIG.

The Nth stage STn adds a bootstrap capacitor CB between the scan output Gout (N) and the Q node Q in the transistor of the pull-up unit 220 involved in the scan output Gout (N) So that the Q node Q can be bootstrapped. As a result, the voltage of the Q node (Q) connected to the gate electrode of the pull-up transistor is largely bootstrapped.

The setter 210 connected to the Q node Q participates in the precharging of the Q node Q. The noise removing unit 250 connected to the Q node Q generates a ripple of the Q node Q, Can be prevented. Also, the reset unit 240 connected to the Q node Q may discharge the voltage of the Q node Q to a low voltage after the scan output Gout (N).

3 and 4, the set unit 210 according to an embodiment of the present invention includes an N-2th forward carry signal CRY (N-2) and an N + 2 & +2) is supplied as a set signal to pre-charge the Q node Q to a high voltage of the set signal (hereinafter referred to as a precharging voltage Vpc). Here, the precharging voltage Vpc may be the gate high voltage VGH.

The configuration and connection relationship of the set unit 210 will be described below.

The set unit 210 includes first to third set transistors Ts1 to Ts3 for controlling the precharging voltage Vpc of the Q node Q and a precharge voltage applying unit for applying a precharging voltage Vpc to the Q node Q, And a charging set transistor Tsp.

The gate electrode and the drain electrode of the first set transistor Ts1 have a diode structure and are supplied with the gate high voltage VGH as the (N-2) th previous carry signal CRY (N-2). The source electrode of the first set transistor Ts1 is connected to the gate electrode of the precharging set transistor Tsp. As a result, the gate electrode of the precharging set transistor Tsp is charged with a voltage equal to the difference between the gate high voltage VGH and the threshold voltage Vth.

The precharging set transistor Tsp is composed of three transistors sharing one gate electrode connected to the set terminal S and the set terminal S and the Q node Q are connected in series. That is, the high junction stress (HJS) can be dispersed in the three precharging set transistors Tsp connected in series. Also, the precharging set transistor Tsp can be improved in the drop of the driving current Ion caused by the high junction stress (HJS).

The gate electrode of the precharging set transistor Tsp is connected to the set terminal S and the drain electrode of the precharging set transistor Tsp is connected to the (N-2) th previous carry signal CRY (N-2). In addition, the Q node Q is connected to the source electrode of the precharging set transistor Tsp. When the (N-2) th previous carry signal CRY (N-2) becomes the gate high voltage VGH, the gate electrode of the precharging set transistor Tsp is set to the difference between the gate high voltage VGH and the threshold voltage Vth So that the precharging set transistor Tsp is turned on.

Then, the source electrode of the precharging set transistor Tsp rises from the gate low voltage VGL to the gate high voltage VGH. At this time, a coupling effect occurs due to the parasitic capacitance Cgs of the precharging set transistor Tsp, so that the voltage of the gate electrode rises above the gate high voltage VGH.

Thus, the output voltage of the precharging set transistor Tsp rises. This may result in raising the precharging voltage Vpc of the Q node Q. That is, the gate high voltage VGH can be charged as it is without the voltage charged in the Q node Q dropping by the threshold voltage Vth of the precharging set transistor Tsp.

The gate electrode and the source electrode of the second set transistor Ts2 are connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharged set transistor Tsp. As a result, the second set transistor Ts2 supplies the gate electrode with a voltage equal to the gate high voltage VGH charged in the source electrode of the first set transistor Ts1 minus the threshold voltage Vth, do.

 The gate high voltage VGH of the (N-2) th previous carry signal CRY (N-2) is applied to the drain electrode of the second set transistor Ts2. The source electrode of the second set transistor Ts2 is charged with a voltage higher than the gate high voltage VGH applied to the gate electrode of the precharging set transistor Tsp. Then, the second set transistor Ts2 discharges to the drain electrode a voltage higher than the gate high voltage VGH applied to the source electrode by the gate high voltage VGH.

The gate electrode of the third set transistor Ts3 receives the (N + 2) th previous carry signal CRY (N + 2), and the drain electrode of the third set transistor Ts3 receives the gate of the precharged set transistor Tsp Electrode. And the source electrode of the third set transistor Ts3 is connected to the low potential voltage Vss. As a result, the third set transistor Ts3 is turned on in response to the high voltage of the (N + 2) th previous carry signal (CRY (N + 2) To the low potential voltage VSS.

Therefore, during the first period t1, the set portion 210 including the first to third set transistors Ts1 to Ts3 prevents the voltage of the Q node Q from becoming lower than the gate high voltage VGH do. That is, during the first period t1, the set unit 210 controls the voltage of the Q node Q to maintain the gate high voltage VGH.

3 and 4, the pull-up unit 220 is pulled up under the control of the Q node Q to scan the clock signal CLK (N) having the Nth phase supplied to the clock terminal CK (Gout (N)) and outputs it as a carry signal (CRY (N)).

The pull-up unit 220 includes first and second pull-up transistors Tpu1 and Tpu2. In the first pull-up transistor Tpu1, a gate electrode is connected to the Q node Q, a drain electrode is connected to the clock terminal CK, and a source electrode is connected to the output terminal OUT. The second pull-up transistor Tpu2 has a gate electrode connected to the Q node Q, a drain electrode connected to the clock terminal CK, and a source electrode connected to the carry terminal CR.

The first pull-up transistor Tpu1 of the pull-up unit 220 is turned on by the precharging voltage Vpc which is a high voltage of the Q node Q. Then, the clock signal CLK (N) having the Nth phase is output to the scan output Gout (N) through the output terminal OUT.

The second pull-up transistor Tpu2 is turned on by the precharged voltage Vpc of the Q node Q. Then, the clock signal CLK (N) having the Nth phase is output as the carry signal CRY (N) through the carry terminal CR.

Therefore, during the second period t2, the scan output Gout (N) and the carry signal (CRY (N)) are supplied to the pull-up unit 220 using the first and second pull-up transistors Tpu1 and Tpu2 Can be output.

3 and 4, in the first period t1, the low voltage of the clock signal CLK (N) having the N-th phase is supplied to the scan output Gout (N) and the carry signal (CRY (N) And the high voltage of the clock signal CLK (N) having the Nth phase in the second period t2 is output as the low voltage of the scan signal Gout (N) and the carry signal CRY (N) Voltage.

More specifically, the first period t1 is the precharging interval PC and the second period t2 is the bootstrap interval BS. During the precharging interval PC, the Q node Q is precharged to the precharging voltage Vpc. During the second period t2, the Q node Q is activated by the coupling phenomenon of the bootstrap capacitor CB located between the gate electrode and the source electrode of the first pull-up transistor Tpu1, ).

As a result, during the precharging interval PC, the first and second pull-up transistors Tpu1 and Tpu2 are turned on by the precharging voltage Vpc of the charged Q node Q, and the Nth stage output terminal The scan output Gout (N) and the carry signal (CRY (N)) corresponding to the clock signal CLK (N) having the Nth phase are output through the output terminal OUT. Since the clock signal CLK (N) at this time is in the low state, the output terminal of the Nth stage STn outputs the gate low voltage VGL.

Then, during the bootstrap interval BS, when the clock signal CLK (N) goes high, the output terminal of the Nth stage STn outputs the gate high voltage VGH.

In addition, the potential change during the bootstrap section (BS) of the Q node (Q) can be explained in connection with the law of conservation of the amount of charge.

The law of conservation of the amount of charge is expressed by the following equation (1).

[Equation 1]

Q = CV, Q1 = Q2

C1 (? Va -? Vb) = C2 (? Vb -? Vc),? Vc = 0

C1 (? Va -? Vb) = C2? Vb

∴ΔV2 = C1 / C1 + C2 * ΔV1

Vb is the potential change amount of the output stage of the N stage, C2 is the parasitic capacitance of the first pull-up transistor Tpu1, Vc is the potential variation of the clock signal CLK (N).

More specifically, when a high voltage of the scan output (Gout (N)) is applied to the source electrode of the first pull-up transistor Tpu1, a voltage change occurs in the source electrode. Then, the voltage across the floating gate electrode, Q node Q, is bootstrapped.

 Therefore, in the bootstrap section BS, the Q node Q rises to a voltage (hereinafter referred to as a bootstrap voltage Vbs) larger than pre-charging as shown in FIG.

The bootstrap interval BS of the present invention is a period in which the Q node Q charged with the predetermined precharging voltage Vpc is bootstrapped and held at the bootstrap voltage Vbs higher than the high voltage VGH, The gate-source voltage Vgs of the first pull-up transistor Tpu1 is greater than the threshold voltage Vth. Therefore, the first pull-up transistor Tpu1 can be turned on for a sufficiently long time, so that the scan output Gout (N) of the Nth stage STn can be stably controlled. In addition, this can increase the reliability of the GIP driving circuit.

Also, The bootstrap capacitor CB connected between the gate electrode and the source electrode of the first pull-up TFT Tpu1 is turned on when the first pull-up transistor Tpu1 is pulled up and outputs a high voltage of the corresponding clock signal CLK (N) The Rising time of the scan output Gout (N) can be reduced by bootstrapping and amplifying the precharging voltage Vpc of the Q node Q. [

The role of the pull-up unit 220 is to transfer the input clock signal CLK (N) of the drain electrode to the source electrode during the time that the first pull-up transistor Tpu1 is turned on. At this time, the condition in which the first pull-up transistor Tpu1 is turned on is when the gate-source voltage Vgs is larger than the threshold voltage Vth. Also, the Q node Q can be maintained at the precharging voltage Vpc without bootstrapping during a period in which the gate-source voltage Vgs becomes smaller than the threshold voltage Vth.

2 to 4, the reset unit 240 receives a reset pulse or an N + 4th carry signal CRY (N + 4) supplied from the (N + 4) . The reset signal input to the reset unit 240 causes the Q node Q and the output terminal OUT for outputting the scan output Gout (N) to be reset (discharged). For convenience sake, the case where the N + 4th carry signal (CRY (N + 4)) is supplied as the reset signal to the reset terminal R will be described.

The reset unit 240 is controlled by the reset signal CRY (N + 4) and includes first and second reset transistors Trs1 and Trs2 for resetting the Q node Q and the output terminal OUT, respectively do. Also, the first and second reset transistors Trs1 and Trs2 are simultaneously turned on when the reset signal CRY (N + 4) is at a high voltage.

The first reset transistor Trs1 discharges the Q node Q to the low potential voltage VSS. The second reset transistor Trs2 discharges the output terminal OUT to the gate low voltage VGL.

The first reset transistor Trs1 has a structure in which two transistors sharing the gate electrode connected to the reset terminal R are connected in series between the Q node Q and the supply terminal of the low potential voltage VSS.

Therefore, during the third period t3, the reset unit 240 uses the first and second reset transistors Trs1 and Trs2 to drive the Q node Q to the low potential voltage VSS and the output terminal OUT, To the gate low voltage (VGL).

Referring to Figs. 3 and 4, the inverter 270 includes first to fourth inverter TFTs Ti1 to Ti4.

The first inverter transistor Ti1 has a diode structure in which a gate electrode and a drain electrode are connected to a clock terminal CK to which a clock signal CLK (N) having an Nth phase is supplied, Electrode is connected.

The second inverter transistor Ti2 has a gate electrode connected to the control node CN, a drain electrode connected to the clock terminal CK, and a source electrode connected to the inverter output node VN.

In the third inverter transistor Ti3, a gate electrode is connected to the carry terminal CR, a drain electrode is connected to the control node CN, and a source electrode is connected to the supply terminal of the low potential voltage VSS.

The fourth inverter transistor Ti4 has the gate electrode connected to the carry terminal CR, the drain electrode connected to the inverter output node VN, and the source electrode connected to the supply terminal of the low potential voltage VSS.

The first inverter TFT Ti1 is turned on by the high voltage of the clock signal CLK (N) having the Nth phase and the high voltage of the clock signal CLK (N) is turned on by the control node CN Is charged. Then, the second inverter TFT Ti2 is turned on by the charged control node CN to output the clock signal CLK (N) having the Nth phase to the inverter output Vinv (N).

The third and fourth inverter TFTs Ti3 and Ti4 are turned on by the Nth carry signal CRY (N) to turn the control node CN and the inverter output node VN to the low potential voltage VSS Discharge.

Therefore, even if the first and second inverter transistors Ti1 and Ti2 of the inverter section 270 are turned on during the second period t2 for outputting the clock signal CLK (N) having the Nth phase And the inverter output Vinv (N) outputs the low potential voltage VSS by the turned-on third and fourth inverter TFTs Ti3 and Ti4. In addition, each of the first to fourth inverter TFTs (Ti1 to Ti4) has a structure in which two TFTs sharing a gate electrode are connected in series.

3 and 4, the pull-down unit 230 includes a carry terminal CR and an output terminal OUT in response to control of an inverter output node VN to which an N-th inverter output Vinv (N) .

Down section 230 includes a first pull-down transistor Tpd1 controlled by the Nth inverter output Vinv (N) to discharge the carry terminal CR to the low voltage VSS, (N)) for discharging the output terminal to the gate low voltage (VGL).

Thus, every time a high voltage of the Nth inverter output Vinv (N) is supplied in synchronization with the clock signal CLK (N) having the Nth phase, the first pull-down transistor Tpd1 and the second pull- It is possible to prevent the multi-output of the carry signal (CRY (N)) and the scan output (Gout (N)).

3 and 4, the noise eliminator 250 of the present invention discharges the Q node Q to the low potential voltage VSS in response to the control of the Nth inverter output Vinv (N). The noise removing unit 250 includes a noise removing transistor Tnp having a structure in which two transistors sharing a gate electrode are connected in series.

The gate electrode of the noise elimination transistor Tnp is supplied with the Nth inverter output Vinv (N), the drain electrode thereof is connected to the Q node Q, and the source electrode thereof is connected to the low potential voltage (VSS) supply terminal.

 Therefore, the noise elimination transistor Tnp can be turned on by the high voltage of the Nth inverter output Vinv (N) to discharge the Q node Q to the low potential voltage VSS.

As a result, it is possible to remove the ripple of the Q node Q by coupling the clock signal CLK (N) having the Nth phase.

3 and 4, the stabilizing unit 260 of the present invention resets the inverter control node CN, the inverter output node VN, and the output terminal OUT, respectively, in response to the stabilization signal Vstable And first to third stabilization transistors Tst1 to Tst3. The first to third stabilization transistors Tst1 to Tst3 are simultaneously turned on by the stabilization signal Vstable every vertical blanking period of the vertical synchronization signal.

The first stabilization TFT Tst1 discharges the inverter control node CN to the low potential voltage VSS and the second stabilization TFT Tst2 discharges the inverter output node VN to the low potential voltage VSS, The third stabilization TFT (Tst3) initializes all the main nodes of the stage by discharging the output terminal to the gate low voltage (VGL). 3, the gate-low voltage VGL and the low-potential voltage VSS supplied to the N-th stage STn are a low-potential voltage having a negative polarity capable of turning off the transistor, 2 gate off voltage, respectively. The low-potential voltage VSS is a second gate-off voltage, and a gate-low voltage VGL used for the scan output, that is, a voltage lower than the first gate-off voltage is used. Accordingly, the low-potential voltage VSS can reduce the leakage current by stably turning off the transistor.

5 is a graph showing a precharging interval of the N-th stage of 2H according to an embodiment of the present invention.

5, the set unit 210 receives the N-2 < th > previous carry signal CRY (N-2) as a set signal to set the Q node Q to a high voltage (Expressed as voltage Vpc).

The clock signal CLK (N) having the Nth phase output from the scan output (Gout (N)) and the carry signal (CRY (N)) in the Nth stage STn is a high logic ) Period and the low logic (gate-off voltage) period of the 4H period are alternately repeated. The Q node Q is precharged corresponding to the (N-2) th previous carry signal CRY (N-2), and the precharging period is maintained for the 2H period.

The Nth stage STn according to an embodiment of the present invention uses the preceding carry signal CRY (N-2) as a set signal. This can reduce the precharging time of the Q node (Q).

More specifically, by using the front carry signal CRY (N-2), the precharging time of the Q node Q is reduced and the first pull-up transistor Tpu1) reduces the stress time. As a result, the pull-up unit 220 (N) for outputting the clock CLK (N) as the scan output Gout (N) or the carry signal CRY (N) in the Nth (N is a natural number) The pull-up transistor Tpu1 of the first pull-up transistor Tpu1 can be minimized in stress and deterioration.

6 is a graph showing a voltage applied to a Q node Q of an Nth stage according to an embodiment of the present invention. That is, it is a graph showing a voltage applied to the Q node Q which is the gate electrode of the first pull-up transistor Tpu1 constituting the pull-up unit.

Referring to FIG. 6, during the pre-magnetic sensing period, the graph of the comparative example shows that the pre-charging voltage Vpc as low as the threshold voltage Vth of the transistor involved in precharging is charged in the Q node Q.

The set portion 210 of the present invention is configured to apply the precharging voltage Vpc to the first to third set transistors Ts1 to Ts3 and the Q node Q that control the precharging voltage Vpc of the Q node Q And a precharging set transistor Tsp.

During the precharging interval PC, the graph of the embodiment shows that the precharging voltage Vpc charged in the Q node Q by outputting the gate high voltage VGH by the precharging set transistor Tsp involved in precharging increases .

Further, during the bootstrap interval BS, the graph of the embodiment shows that the Q node Q is precharged to the high voltage VGH and then bootstrapped to the bootstrap voltage Vbs.

Thus, the Q node Q rises greatly to the bootstrap voltage Vbs by the coupling phenomenon of the bootstrap capacitor CB located between the gate electrode and the source electrode of the first pull-up transistor Tpu1.

Referring to FIG. 6, it can be seen that the bootstrap voltage Vbs of the embodiment is higher than the bootstrap voltage Vbs of the comparative example. This means that the gate electrode voltage of the first pull-up transistor Tpu1 becomes high. As a result, the rising and falling times of the first pull-up transistor Tpu1 can be improved. This can improve the lifetime of the GIP circuit.

Hereinafter, a circuit section for controlling the precharging of the Q node Q which increases the precharging voltage Vpc of the Q node Q and improves the output signal reduction of the GIP driving circuit according to an embodiment of the present invention Various functions of the shift register and the display device including the shift register will be described.

In a shift register having a plurality of stages connected to each other in a dependent manner, each stage includes first to third set transistors Ts1 to Ts3 for controlling the Q node Q to a precharging voltage Vpc, A precharging set transistor Tsp for applying a precharging voltage Vpc to the precharging transistor Tsp; And a scan output Gout (N) through an output terminal OUT, the nth clock CLK (N) being controlled by a Q node Q and supplied to a clock terminal CK, And a second pull-up transistor Tpu2 for outputting the pull-up transistor Tpu1 and the n-th clock CLK (N) via a carry terminal CR as a carry signal CRY (N) .

According to another aspect of the present invention, the set unit sets the N-2 < th > the previous carry signal CRY (N-2) and the N + Signal to charge the Q node Q with the pre-charging voltage Vpc.

According to another aspect of the present invention, the gate electrode and the drain electrode of the first set transistor Ts1 have a diode structure, and the N-2 < th > Can be supplied.

According to another aspect of the present invention, the source electrode of the first set transistor Ts1 may be connected to the precharged set transistor Tsp.

According to another aspect of the present invention, the precharging set transistor Tsp is composed of three transistors sharing one gate electrode connected to the set terminal S to minimize the High Junction Stress (HJS) can do.

According to another aspect of the present invention, the gate electrode of the precharging set transistor Tsp is connected to the first set transistor Ts1 and the second set transistor Ts2, and the drain electrode of the precharging set transistor Tsp (N-2) th previous carry signal CRY (N-2).

According to another aspect of the present invention, the source electrode of the precharging set transistor Tsp may be connected to the Q node Q.

According to another aspect of the present invention, the gate electrode and the source electrode of the second set transistor Ts2 are connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharged set transistor Tsp, And the drain electrode of the set transistor Ts2 may be supplied with the (N-2) th previous carry signal CRY (N-2).

According to another aspect of the present invention, the gate electrode of the third set transistor Ts3 is supplied with the (N + 2) th preceding carry signal CRY (N-2) And the source electrode of the third set transistor Ts3 may be connected to the low potential voltage Vss.

According to still another aspect of the present invention, the third set transistor Ts3 is turned on at a high voltage of the (N + 2) th preceding carry signal CRY (N + 2) to turn on the gate of the precharging set transistor Tsp The voltage applied to the electrode can be discharged at a low potential (VSS).

According to another aspect of the present invention, the set unit may charge the Q node Q to the gate high voltage VGH such that the voltage of the Q node Q is not lower than the gate high voltage VGH.

According to another aspect of the present invention, the first pull-up transistor Tpu1 is turned on by the precharging voltage Vpc which is the high voltage of the Q node Q during the first period, The clock signal CLK (N) can be scanned (Gout (N)) through the output terminal OUT.

According to another aspect of the present invention, the second pull-up transistor Tpu2 is turned on by the pre-charging voltage Vpc which is a high voltage of the Q node Q during the first period, It is possible to output the carry signal CRY (N) via the carry terminal CR to the clock signal CLK (N).

According to another aspect of the present invention, the Q node Q is charged to the precharging voltage Vpc during the precharging interval PC and is coupled to the bootstrap capacitor BC during the bootstrap interval BS by coupling the bootstrap capacitor BC It can rise to a voltage higher than the precharging voltage Vpc.

According to another aspect of the present invention, the shift register is controlled by a reset terminal, and further includes a reset unit for resetting an output terminal (OUT) for outputting the Q node (Q) and the scan output (Gout .

According to another aspect of the present invention, the shift register includes a first inverter transistor Ti1 having a gate electrode and a drain electrode connected in a diode structure to a clock terminal CK, and a source electrode connected to the control node CN, A second inverter transistor Ti2 having a gate electrode connected to the control node CN, a drain electrode connected to the clock terminal CK and a source electrode connected to the inverter output node VN, a carry terminal CR, A third inverter transistor Ti3 and a carry terminal CR to which the gate electrode is connected, the drain electrode is connected to the control node CN, and the source electrode is connected to the supply terminal of the low potential voltage VSS, And an inverter including a fourth inverter transistor (Ti4) to which an electrode is connected, a drain electrode is connected to the inverter output node (VN), and a source electrode is connected to a supply terminal of the low potential voltage (VSS) .

The third and fourth inverter transistors Ti3 and Ti4 of the inverter section during the second period t2 for outputting the clock signal CLK (N) to the high voltage, Vinv (N) can output the low potential voltage VSS.

According to another aspect of the present invention, the shift register is a pull-down resistor for discharging the carry terminal CR and the output terminal OUT in response to the control of the inverter output node VN to which the inverter output Vinv (N) And the like.

According to another aspect of the present invention, the shift register may further include a noise canceling unit for discharging the Q node (Q) to the low potential voltage (VSS) in response to the control of the inverter output (Vinv (N)).

According to another aspect of the present invention, the shift register includes first to seventh shift registers for resetting the inverter control node CN, the inverter output node VN, and the output terminal OUT respectively in response to the stabilization signal Vstable. 3 stabilization transistors Tst1 to Tst3.

A display device includes: a display having a plurality of pixels defined on a substrate; A non-display portion disposed on at least one side of the display portion; And a GIP (Gate In Panel) circuit portion located on the non-display portion and corresponding to a plurality of pixels, wherein the GIP circuit portion includes a first to a third set transistor for controlling the Q node (Q) A set portion having a precharging set transistor Tsp for applying a precharging voltage Vpc to the Q node Q1 and Ts1 to Ts3; And a scan output Gout (N) through an output terminal OUT, the nth clock CLK (N) being controlled by a Q node Q and supplied to a clock terminal CK, And a second pull-up transistor Tpu2 for outputting the pull-up transistor Tpu1 and the n-th clock CLK (N) via a carry terminal CR as a carry signal CRY (N) .

The set unit can supply the Q node Q with the precharging voltage Vpc by supplying the N-2th preceding carry signal CRY (N-2) which is the gate high voltage VGH to the precharging interval PC have.

The gate electrode and the drain electrode of the first set transistor Ts1 have a diode structure and receive the gate high voltage VGH as the N-2th previous carry signal CRY (N-2) May be connected to the precharging set transistor Tsp.

The gate electrode of the precharging set transistor Tsp is connected to the first set transistor Ts1 and the second set transistor Ts2 and the drain electrode of the precharging set transistor Tsp is connected to the N- (N-2)), and the source electrode of the precharging set transistor Tsp may be connected to the Q node (Q).

The gate electrode and the source electrode of the second set transistor Ts2 are connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharged set transistor Tsp and the drain electrode of the second set transistor Ts2 (N-2) th previous carry signal CRY (N-2).

The gate electrode of the third set transistor Ts3 is supplied with the (N + 2) th previous carry signal CRY (N-2), and the drain electrode of the third set transistor Ts3 is connected to the precharged set transistor Tsp And the source electrode of the third set transistor Ts3 may be connected to the low potential voltage Vss.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: organic light emitting display device 110: display panel
110A: display area 110B: non-display area
120: Data driver 130: Level shifter
140: Shift register 150: Timing controller
210: set section 220: pull-up section
230: pull down section 240: reset section
250: noise removing unit 260: stabilizing unit
270: Inverter

Claims (26)

In a shift register having a plurality of stages connected to each other in a dependent manner,
In each stage,
The first to third set transistors Ts1 to Ts3 for controlling the Q node Q to the precharging voltage Vpc and the precharging set transistor Tsp for applying the precharging voltage Vpc to the Q node Q, ; And
(N), which is controlled by the Q-node (Q) and outputs the n-th clock CLK (N) supplied to the clock terminal CK through the output terminal OUT to the scan output Gout Up transistor Tpu1 and a second pull-up transistor Tpu2 for outputting the n-th clock CLK (N) as a carry signal CRY (N) through a carry terminal CR Shift register. The method according to claim 1,
The set unit receives the N-2th previous carry signal CRY (N-2) and the N + 2th previous carry signal CRY (N + 2) which are the gate high voltage VGH as a set signal, (Qp) with the precharging voltage (Vpc). 3. The method of claim 2,
The gate electrode and the drain electrode of the first set transistor Ts1 have a diode structure, and the (N-2) th previous carry signal CRY (N-2) is supplied to the gate high voltage VGH. 3. The method of claim 2,
And a source electrode of the first set transistor Ts1 is connected to the precharged set transistor Tsp. The method according to claim 1,
The precharging set transistor Tsp is composed of three transistors sharing one gate electrode connected to the set terminal S, thereby minimizing a high junction stress (HJS). 3. The method of claim 2,
The gate electrode of the precharging set transistor Tsp is connected to the first set transistor Ts1 and the second set transistor Ts2 and the drain electrode of the precharging set transistor Tsp is connected to the N- A shift register supplied with the preceding carry signal CRY (N-2). 3. The method of claim 2,
And a source electrode of the precharging set transistor (Tsp) is connected to the Q node (Q). 6. The method according to any one of claims 2 to 5,
The gate electrode and the source electrode of the second set transistor Ts2 are connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharged set transistor Tsp, And the drain electrode of the shift register receives the (N-2) th previous carry signal (CRY (N-2)). 3. The method of claim 2,
The gate electrode of the third set transistor Ts3 is supplied with the (N + 2) th previous carry signal CRY (N-2), and the drain electrode of the third set transistor Ts3 is connected to the precharged set transistor Tsp), and the source electrode of the third set transistor Ts3 is connected to the low potential voltage (Vss). 10. The method of claim 9,
The third set transistor Ts3 is turned on at a high voltage of the (N + 2) th previous carry signal (CRY (N + 2)) to change the voltage applied to the gate electrode of the pre- A shift register for discharging to a low potential voltage (VSS). 8. The method of claim 7,
Wherein the set portion charges the Q node (Q) to the gate high voltage (VGH) so that the voltage of the Q node (Q) is not lower than the gate high voltage (VGH). The method according to claim 1,
The first pull-up transistor Tpu1 is turned on by the precharging voltage Vpc which is a high voltage of the Q node Q during a first period and the high voltage of the clock signal CLK N) through the output terminal OUT (Gout (N)). The method according to claim 1,
The second pull-up transistor Tpu2 is turned on by the precharging voltage Vpc which is a high voltage of the Q node Q during a first period and the clock signal CLK N) outputting a carry signal (CRY (N)) via the carry terminal (CR). The method according to claim 1,
The Q node Q is charged with the precharging voltage Vpc during the precharging interval PC and the precharging voltage Vpc by coupling of the bootstrap capacitor BC during the bootstrap interval BS. A shift register that is raised to a higher voltage. The method according to claim 1,
Controlled by a reset terminal,
Further comprising a reset section for resetting an output terminal (OUT) for outputting the Q node (Q) and the scan output (Gout (N) The method according to claim 1,
A first inverter transistor (Ti1) having a gate electrode and a drain electrode connected to the clock terminal (CK) through a diode structure, and a source electrode connected to the control node (CN);
A second inverter transistor (Ti2) having a gate electrode connected to the control node (CN), a drain electrode connected to the clock terminal (CK), and a source electrode connected to the inverter output node (VN);
A third inverter transistor (Ti3) having a gate electrode connected to the carry terminal (CR), a drain electrode connected to the control node (CN), and a source electrode connected to a supply terminal of the low potential voltage (VSS); And
A fourth inverter transistor (Ti4) having a gate electrode connected to the carry terminal (CR), a drain electrode connected to the inverter output node (VN), and a source electrode connected to a supply terminal of the low potential voltage (VSS) The shift register comprising: an inverter; 17. The method of claim 16,
The inverter output Vinv (N) is turned on by the third and fourth inverter transistors Ti3 and Ti4 of the inverter during a second period t2 during which the clock signal CLK (N) Is output as a low potential voltage (VSS). 17. The method of claim 16,
And a pull-down section for discharging the carry terminal (CR) and the output terminal (OUT) in response to control of the inverter output node (VN) to which the inverter output (Vinv (N)) is supplied. 17. The method of claim 16,
And a noise eliminator for discharging said Q node (Q) to said low potential voltage (VSS) in response to control of said inverter output (Vinv (N)). 17. The method of claim 16,
And first to third stabilization transistors Tst1 to Tst3 for resetting the inverter control node CN, the inverter output node VN and the output terminal OUT respectively in response to the stabilization signal Vstable And a stabilization unit. A display unit having a plurality of pixels defined on a substrate;
A non-display portion disposed on at least one side of the display portion; And
And a GIP (Gate In Panel) circuit unit located on the non-display unit and corresponding to the plurality of pixels,
The GIP circuit unit includes:
The first to third set transistors Ts1 to Ts3 for controlling the Q node Q to the precharging voltage Vpc and the precharging set transistor Tsp for applying the precharging voltage Vpc to the Q node Q, ; And
(N), which is controlled by the Q-node (Q) and outputs the n-th clock CLK (N) supplied to the clock terminal CK through the output terminal OUT to the scan output Gout Up transistor Tpu1 and a second pull-up transistor Tpu2 for outputting the n-th clock CLK (N) as a carry signal CRY (N) through a carry terminal CR / RTI > 22. The method of claim 21,
The set unit supplies the N-2.sup.th forward carry signal CRY (N-2) which is the gate high voltage VGH to the precharging interval PC and converts the Q node Q to the precharging voltage Vpc Display device to charge. 23. The method of claim 22,
The gate electrode and the drain electrode of the first set transistor Ts1 have a diode structure and receive the gate high voltage VGH at the N-2 < nd > the previous carry signal CRY (N-2) And the source electrode of the transistor Ts1 is connected to the precharging set transistor Tsp. 24. The method of claim 23,
The gate electrode of the precharging set transistor Tsp is connected to the first set transistor Ts1 and the second set transistor Ts2 and the drain electrode of the precharging set transistor Tsp is connected to the N- And a source electrode of the precharging set transistor Tsp is connected to the Q node (Q). 23. The method of claim 22,
The gate electrode and the source electrode of the second set transistor Ts2 are connected to the source electrode of the first set transistor Ts1 and the gate electrode of the precharged set transistor Tsp, (N-2) th previous carry signal (CRY (N-2)). 23. The method of claim 22,
The gate electrode of the third set transistor Ts3 is supplied with the (N + 2) th previous carry signal CRY (N-2), and the drain electrode of the third set transistor Ts3 is connected to the precharge set transistor Tsp And the source electrode of the third set transistor Ts3 is connected to the low potential voltage Vss.

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